Memory device
By using inverters, transistors and auxiliary circuits to provide negative voltages and pull down the power supply voltage in static random read memory, the problem of using negative bit line method to increase energy consumption in SRAM is solved, and the writing capacity is improved. Reduces energy consumption.
Patent Information
- Application Number
- CN202310678305.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-08
- Publication Date
- 2024-12-10
AI Technical Summary
In static random read memory (SRAM), the negative bit line (NBL) method is used to maintain write capability, energy consumption is increased.
A memory device is designed, including an inverter, transistor and auxiliary circuit, by providing a negative voltage on the bit line and pulling down the power supply voltage to improve write capability while saving energy.
By improving the discharge capability of the bit line, the writing capability is improved and energy consumption is reduced during the write operation, effectively reducing the energy consumption of the memory device.
Smart Images
Figure CN119107996A_ABST
Abstract
Description
Technical Field
[0001] An embodiment of the present disclosure relates to a memory device, and more particularly to a memory device with an auxiliary circuit. Background Art
[0002] Static random access memory (SRAM) with high-density bit cells needs to use a negative bit-line (NBL) method to maintain write capability. However, using the NBL method in SRAM increases the power consumption of the SRAM. Summary of the invention
[0003] In some embodiments, a memory device is provided. The memory device includes at least one inverter, a transistor, and an auxiliary circuit. The transistor is coupled between the at least one inverter and a bit line. The auxiliary circuit is coupled to the bit line and provides a negative voltage to the bit line, and pulls down a power supply voltage provided to the at least one inverter.
[0004] In some embodiments, a memory device is provided. The memory device includes a pull-up transistor, a pull-down transistor, a pass-gate transistor, and an auxiliary circuit. The pull-up transistor receives a power supply voltage. The pull-down transistor is coupled to the pull-up transistor at a node. The pass-gate transistor is coupled between the node and a bit line. The auxiliary circuit includes at least one first rail, at least one second rail, and at least one third rail. The at least one first rail is coupled to the bit line. The at least one second rail couples a negative voltage to the at least one first rail. The at least one third rail adjusts the power supply voltage in response to the negative voltage provided by the at least one second rail.
[0005] In some embodiments, a memory device is provided. The memory device includes a first inverter, a second inverter, and a pull-down circuit. The second inverter is coupled to the first inverter at a node. The pull-down circuit pulls down a first voltage of the node and pulls down a second voltage provided to the first inverter and the second inverter. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The aspects of one embodiment of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or reduced for clarity of discussion.
[0007] Figure 1 is a schematic diagram of a memory device according to some embodiments;
[0008] Figure 2 is a schematic diagram of a portion of a memory device having an auxiliary circuit structure according to some embodiments;
[0009] Figure 3 According to some embodiments, Figure 1 and Figure 2 A waveform diagram of a signal of a memory device;
[0010] Figure 4 is a schematic diagram of a portion of an auxiliary circuit of a memory device according to some embodiments.
[0011]
Explanation of symbols
[0012] 100:Memory device
[0013] 101: Bit Line
[0014] 103: Bit line
[0015] 105: Word Line
[0016] 110: Memory unit
[0017] 111: Inverter
[0018] 113: Inverter
[0019] 120: Auxiliary circuit
[0020] 1211-1214: Track 1
[0021] 1221-1226: Second track
[0022] 1231-1232: The Third Track
[0023] BL: Bit line signal
[0024] BLB: Bit Line Signal
[0025] NVSS: Negative voltage
[0026] P1: Current path
[0027] P2: Current path
[0028] PD1: Pull-down transistor
[0029] PD2: Pull-down transistor
[0030] PG1: transfer gate transistor
[0031] PG2: transfer gate transistor
[0032] PU1: Pull-up transistor
[0033] PU2: Pull-up transistor
[0034] Q: Node
[0035] QB:Node
[0036] T7: Control transistor
[0037] T8: Control transistor
[0038] VDD: power supply voltage
[0039] VNBL: Negative Bit Line Signal
[0040] VQ:Data
[0041] VQB: Data
[0042] WC: Control signal
[0043] WL(1)-WL(n): word line signal
[0044] WT: control signal
[0045] X: Direction
[0046] Y: direction DETAILED DESCRIPTION
[0047] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify an embodiment of the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in each example. This repetition is for simplification and clarity purposes, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.
[0048] The terms used in an embodiment of the present disclosure generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in the present disclosure, including examples of any term discussed herein, is illustrative only and in no way limits the scope and meaning of an embodiment of the present disclosure or any exemplary term. Likewise, an embodiment of the present disclosure is not limited to the various embodiments given in the present disclosure.
[0049] The terms "including", "having" and the like used herein should be understood as open-ended, in other words, meaning including but not limited to.
[0050] All references to "one embodiment" or "some embodiments" in this disclosure indicate that a particular feature, structure, or implementation associated with the embodiment is included in at least one embodiment of this disclosure. Therefore, the use of the phrases "in one embodiment" or "in some embodiments" throughout this document does not necessarily refer to the same embodiment. In addition, particular features, structures, or implementations may be combined in any suitable manner in one or more embodiments.
[0051] Further, for ease of description, spatially relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0052] As used herein, "approximately", "about", "approximately" or "substantially" shall generally refer to any approximation of a given value or range, wherein it varies depending on the various fields involved, and its scope shall be consistent with the broadest interpretation understood by those skilled in the art to cover all of the multiple modifications and similar structures. In some embodiments, it shall generally refer to within 20 percent of a given value or range, preferably within 10 percent, and more preferably within 5 percent. The numerical values given herein are approximate, meaning that if not explicitly stated, the term "approximately", "about", "approximately" or "substantially" can be inferred, or other approximate values are meant.
[0053] Reference Figure 1 According to some embodiments of the present disclosure, Figure 1 is a schematic diagram of a memory device 100 . To illustrate, the memory device 100 includes a plurality of memory cells 110 and an auxiliary circuit 120 . The auxiliary circuit 120 is coupled to the memory cells 110 .
[0054] In some embodiments, the memory cells 110 are arranged in a plurality of rows and a plurality of columns in a memory cell array (not shown). Figure 1 Only two memory cells 110 are shown, which are coupled to the bit lines 101 and 103 to receive the bit line signals BL and BLB. Configurations with different numbers of memory cells 110 also fall within the scope of the disclosed embodiments.
[0055] In some embodiments, memory cell 110 includes inverter 111 and inverter 113. Inverter 111 and inverter 113 are cross-coupled. In fact, inverter 111 and inverter 113 operate as a data latch. For illustration, Figure 1 As shown, an output node of the inverter 111 and an input node of the inverter 113 are connected to each other at a node Q. Figure 1 As shown, an input node of the inverter 111 and an output node of the inverter 113 are connected to each other at a node QB.
[0056] For the purpose of explaining the operation, the data latch (including the inverter 111 and the inverter 113) can store one bit of data at the node Q. For the purpose of explanation, the voltage level at the node Q represents the logic value "1" or the logic value "0" corresponding to the logic data stored in the memory cell 110. The node QB has a logic level opposite to the logic level of the node Q. For the convenience of explanation, the logic value "0" is indicated by a low level and the logic value "1" is indicated by a high level. This indication is for the purpose of explanation only. Different indication methods also fall within the scope of the embodiments disclosed herein.
[0057] In some embodiments, Figure 1 The illustrated memory cell 110 is a static random-access memory (SRAM) cell, illustratively comprising six transistors: a pull-up transistor PU1, a pull-up transistor PU2, a pull-down transistor PD1, a pull-down transistor PD2, a pass-gate transistor PG1, and a pass-gate transistor PG2. The pull-up transistor PU1 and the pull-down transistor PD1 are configured and operated as an inverter 111. The pull-up transistor PU2 and the pull-down transistor PD2 are configured and operated as an inverter 113. In some embodiments, the pull-down transistors PD1-PD2 and the pass-gate transistors PG1-PG2 are N-type transistors, and the pull-up transistors PU1-PU2 are P-type transistors.
[0058] In some embodiments, the pass-gate transistor PG1 is configured as a first pass-gate transistor and the pass-gate transistor PG2 is configured as a second pass-gate transistor. For illustration, the gate of the pass-gate transistor PG1 and the gate of the pass-gate transistor PG2 are coupled to the word line 105 and controlled by the word line signals WL(1)-WL(n). The output node of the inverter 111 and the input node of the inverter 113 (in other words, the node Q) are coupled to the bit line 101 of the transmission bit line signal BL through the pass-gate transistor PG1. The input node of the inverter 111 and the output node of the inverter 113 (in other words, the node QB) are coupled to the bit line 103 of the transmission bit line signal BLB through the pass-gate transistor PG2.
[0059] In some embodiments, the memory device 100 includes a plurality of memory cells 110, and word line signals (e.g., WL(1)-WL(n)) are used to select and trigger at least one of the plurality of memory cells 110 for a write / read operation of the memory device 100. When the memory cell 110 is not selected in response to the corresponding word line signal, the memory cell 110 maintains the voltage levels on the nodes Q and QB unchanged.
[0060] To illustrate the operation, the assist circuit 120 is used to provide a negative voltage to the bit lines 101 and 103 in order to assist the write operation of the memory device 100. For example, during a write operation of the memory device 100, the voltage stored at the node QB is pulled low through the current path P1, and the node QB is thus written to have a logic value of "0".
[0061] In order to improve the write capability of the memory device 100 during a write operation, the auxiliary circuit 120 is used to provide a negative voltage to the bit line 103 to increase the voltage difference between the node QB and the bit line 103, and thus enhance the ability to discharge through the current path P1. In this way, the node QB is effectively written to have a logic value of "0". As described above, because the discharge capability from the node QB to the bit line 103 is enhanced in response to the negative voltage provided to the bit line 103, the write capability of the memory device 100 is improved.
[0062] In some embodiments, the memory cell 110 includes a control transistor T7 and a control transistor T8. The control transistor T7 is coupled between the auxiliary circuit 120 and the bit line 101, and the control transistor T8 is coupled between the auxiliary circuit 120 and the bit line 103. To illustrate the operation, the control transistor T7 is used to transmit a negative voltage provided by the auxiliary circuit 120 to the bit line 101 in response to the control signal WC. The control transistor T8 is used to transmit a negative voltage provided by the auxiliary circuit 120 to the bit line 103 in response to the control signal WT.
[0063] To illustrate the operation, the auxiliary circuit 120 is used to pull down the power supply voltage VDD provided to the inverter 111 and the inverter 113. For example, during the write operation of the memory device 100, the auxiliary circuit 120 is used to pull down the power supply voltage VDD provided to the inverter 111 and the inverter 113, and the charging capacity through the current path P2 is reduced. Since the charging capacity through the current path P2 is reduced, the memory device saves energy during the write operation to reduce the energy consumption of the memory device 100.
[0064] In some embodiments, the auxiliary circuit 120 is coupled to the upper side of the inverter 111 and the upper side of the inverter 113. During a write operation of the memory device 100, the auxiliary circuit 120 is used to pull down the power supply voltage VDD provided to the inverter 111 and the inverter 113.
[0065] In some embodiments, Figure 1 The auxiliary circuit 120 is a pull-down circuit. To illustrate the operation, the auxiliary circuit 120 is used to pull down the voltage stored at the node QB, and the auxiliary circuit 120 is used to pull down the voltage provided to the inverter 111 and the inverter 113. For example, the auxiliary circuit 120 is used to pull down the power supply voltage VDD provided to the inverter 111 and the inverter 113.
[0066] To illustrate the operation, the auxiliary circuit 120 is used to pull down the voltage stored at the node QB and the voltage provided to the inverters 111 and 113. In various embodiments, the auxiliary circuit 120 is used to pull down the voltage stored at the node QB and the voltage provided to the inverters 111 and 113 simultaneously.
[0067] In some embodiments, the auxiliary circuit 120 is used to pull down the voltage stored at the node QB and the voltage provided to the inverter 111 and the inverter 113 respectively or simultaneously according to the actual operation of the embodiments of the present disclosure.
[0068] In some embodiments, in response to the voltage stored at the node QB being pulled down by the auxiliary circuit 120, the current output from the node QB through the current path P1 increases. In different embodiments, in response to the voltage provided to the inverter 111 and the inverter 113 being pulled down by the auxiliary circuit 120, the current input to the node QB through the current path P2 decreases.
[0069] Figure 1 The configuration is provided for illustrative purposes. Different implementations also belong to embodiments of the present disclosure. For example, in some embodiments, the auxiliary circuit 120 is used to sequentially pull down the voltage stored at the node QB and provide it to the voltage of the inverter 111 and the inverter 113. For example, in some embodiments, the auxiliary circuit 120 is used to first pull down the voltage stored at the node QB, and the auxiliary circuit 120 is used to then pull down the voltage provided to the inverter 111 and the inverter 113. For example, in some embodiments, the auxiliary circuit 120 is used to first pull down the voltage provided to the inverter 111 and the inverter 113 according to the actual operation of the embodiments of the present disclosure, and the auxiliary circuit 120 is used to then pull down the voltage stored at the node QB.
[0070] Reference Figure 2 According to some embodiments of the present disclosure, Figure 2 The structure having the auxiliary circuit 120 Figure 1 A schematic diagram of a portion of a memory device 100 in FIG. Figure 1 For ease of understanding, Figure 2 Similar components in the present invention are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted in this article unless there is a need to introduce the same Figure 2 The collaborative relationship of the components shown in .
[0071] In some embodiments, the auxiliary circuit 120 includes a plurality of first rails 1211-1214 and a plurality of second rails 1221-1227. The plurality of first rails 1211-1214 are respectively coupled to the bit lines 101 and 103 through the control transistors T7 and T8. The plurality of second rails 1221-1227 are disposed adjacent to the plurality of second rails 1211-1214 and are used to couple negative voltages to the plurality of first rails 1211-1214.
[0072] In some embodiments, a portion of the plurality of second rails 1221-1227 is disposed directly adjacent to the plurality of first rails 1211-1214. For example, the plurality of second rails 1222-1226 is disposed directly adjacent to the plurality of first rails 1211-1214. In different embodiments, the second rail 1222 of the plurality of second rails 1221-1227 is directly disposed adjacent to the first rail 1211 of the plurality of first rails 1211-1214, the second rail 1223 of the plurality of second rails 1221-1227 is directly disposed adjacent to the first rails 1211 and 1212 of the plurality of first rails 1211-1214, the second rail 1224 of the plurality of second rails 1221-1227 is directly disposed adjacent to the first rails 1212 and 1213 of the plurality of first rails 1211-1214, the second rail 1225 of the plurality of second rails 1221-1227 is directly disposed adjacent to the first rails 1213 and 1214 of the plurality of first rails 1211-1214, and the second rail 1226 of the plurality of second rails 1221-1227 is directly disposed adjacent to the first rail 1214 of the plurality of first rails 1211-1214.
[0073] For the operation of the memory device 100, please refer to Figure 3 According to some embodiments of the present disclosure, Figure 3 Draw the correspondence Figure 1 to Figure 2 The waveform of the signal of the memory device 100.
[0074] To illustrate the operation, when the auxiliary circuit 120 is used to provide a negative voltage NVSS to the bit lines 101 and 103 for writing to the auxiliary memory cell 110, the plurality of second rails 1221-1227 respond to the negative voltage NVSS. Figure 3The negative bit line signal VNBL shown couples the negative voltage NVSS to the plurality of first rails 1211-1214, so that the plurality of first rails 1211-1214 provide the negative voltage NVSS to the bit lines 101 and 103. Figure 3 As shown in the embodiment of FIG. 1 , at time point t1, the voltage level of the negative bit line signal VNBL provided to the plurality of second rails 1221-1227 changes from a high voltage level to a low voltage level, and the plurality of second rails 1221-1227 thus couples the negative voltage associated with the voltage level change to the plurality of first rails 1211-1214. The plurality of first rails 1211-1214 then provide the negative voltage NVSS to the bit lines 101 and 103 transmitting the bit line signals BL and BLB. Figure 3 As described in the embodiment of FIG. 1 , the bit line signal BL or BLB is therefore pulled low in response to the negative voltage NVSS provided by the plurality of first rails 1211 - 1214 .
[0075] In various embodiments, when the auxiliary circuit 120 is used to provide a negative voltage NVSS to the bit lines 101 and 103 for a write operation of the auxiliary memory cell 110, a portion of the plurality of second rails 1221-1227 responds to Figure 3 The negative bit line signal VNBL is shown coupling the negative voltage NVSS to the plurality of first rails 1211-1214, and the plurality of first rails 1211-1214 provide the negative voltage NVSS to the bit lines 101 and 103. For example, the second rails 1222-1226 of the plurality of second rails 1221-1227 couple the negative voltage NVSS to the plurality of first rails 1211-1214 because the second rails 1222-1226 of the plurality of second rails 1221-1227 are directly adjacent to the plurality of first rails 1211-1214.
[0076] In some embodiments, the auxiliary circuit 120 further includes a plurality of third rails 1231 and 1232. The plurality of third rails 1231 and 1232 are disposed adjacent to the plurality of second rails 1221-1227. In various embodiments, the plurality of third rails 1231 and 1232 are disposed directly adjacent to portions of the plurality of second rails 1221-1227. For example, the plurality of third rails 1231 and 1232 are disposed directly adjacent to the second rails 1221, 1222, 1226, and 1227 of the plurality of second rails 1221-1227.
[0077] In some embodiments, each of the plurality of third rails 1231 and 1232 is disposed directly adjacent to a portion of the plurality of second rails 1221-1227. For example, the third rail 1231 of the plurality of third rails 1231 and 1232 is disposed directly adjacent to the second rails 1221 and 1222 of the plurality of second rails 1221-1227, and the third rail 1232 of the plurality of third rails 1231 and 1232 is disposed directly adjacent to the second rails 1226 and 1227 of the plurality of second rails 1221-1227.
[0078] To illustrate the operation, when the auxiliary circuit 120 is used to pull down the power supply voltage VDD provided to the inverter 111 and the inverter 113, the plurality of second rails 1221-1227 are used to couple the negative voltage to the plurality of third rails 1231 and 1232, and the plurality of third rails 1231 and 1232 pull down the power supply voltage VDD provided to the inverter 111 and the inverter 113. For example, the plurality of second rails 1221-1227 are used to couple the negative voltage to the plurality of third rails 1231 and 1232 in response to the negative bit line signal VNBL. The plurality of third rails 1231 and 1232 then pull down the power supply voltage VDD provided to the inverter 111 and the inverter 113.
[0079] like Figure 3 As shown in the embodiment of FIG. 1 , at time point t1, the voltage level of the negative bit line signal VNBL provided to the plurality of second rails 1221-1227 changes from a high voltage level to a low voltage level, and the second rails 1221 and 1227 of the plurality of second rails 1221-1227 thus couple the negative voltage associated with the voltage level change to the third rails 1231 and 1232, respectively (because the second rails 1221 and 1227 are directly disposed adjacent to the third rails 1231 and 1232). The plurality of third rails 1231 and 1232 then pull down the power supply voltage VDD provided to the inverters 111 and 113. As shown in FIG. Figure 3 As shown in the embodiment of FIG. 1 , the power supply voltage VDD provided to the inverter 111 and the inverter 113 is therefore pulled down.
[0080] To illustrate the operation, when the auxiliary circuit 120 is used to pull down the power supply voltage VDD provided to the inverter 111 and the inverter 113, a portion of the plurality of second rails 1221-1227 couples a negative voltage to the third rails 1231 and 1232, and the third rails 1231 and 1232 pull down the power supply voltage VDD provided to the inverter 111 and the inverter 113. For example, the second rail 1221 of the plurality of second rails 1221-1227 is used to couple a negative voltage to the third rail 1231 of the plurality of third rails 1231 and 1232 in response to the negative bit line signal VNBL (because the second rail 1221 is disposed directly adjacent to the third rail 1231). The second rail 1227 of the plurality of second rails 1221-1227 is used to couple a negative voltage to the third rail 1232 of the plurality of third rails 1231 and 1232 in response to the negative bit line signal VNBL (because the second rail 1227 is directly disposed adjacent to the third rail 1232). Subsequently, the plurality of third rails 1231 and 1232 pull down the power supply voltage VDD provided to the inverters 111 and 113.
[0081] like Figure 3 As shown in the embodiment of FIG. 1 , at time point t1, the voltage level of the negative bit line signal VNBL provided to the plurality of second rails 1221-1227 changes from a high voltage level to a low voltage level, and the second rails 1221 and 1227 of the plurality of second rails 1221-1227 thus couple the negative voltage associated with the voltage level change to the plurality of third rails 1231 and 1232, respectively (because the second rails 1221 and 1227 are directly disposed adjacent to the third rails 1231 and 1232). Subsequently, the plurality of third rails 1231 and 1232 pull down the power supply voltage VDD provided to the inverters 111 and 113. As shown in FIG. Figure 3 As shown in the embodiment of FIG. 1 , the power supply voltage VDD provided to the inverter 111 and the inverter 113 is therefore pulled down.
[0082] In some embodiments, the third rails 1231 and 1232 of the auxiliary circuit 120 are coupled to the upper sides of the inverters 111 and 113. During a write operation of the memory device 100, when the auxiliary circuit 120 is used to pull down the power supply voltage VDD provided to the upper sides of the inverters 111 and 113, the plurality of second rails 1221-1227 are used to couple a negative voltage to the plurality of third rails 1231 and 1232, and the plurality of third rails 1231 and 1232 pull down the power supply voltage VDD provided to the upper sides of the inverters 111 and 113.
[0083] In some embodiments, Figure 3 As shown in the embodiment, the logic levels of the data VQ and VQB stored at the nodes Q and QB are changed after the write operation of the memory device 100 is performed.
[0084] Figure 2 and Figure 3 The configuration is provided for the purpose of illustration. Different implementations also belong to the embodiments of the present disclosure. A person skilled in the art can adjust the structure of the auxiliary circuit 120 according to the actual operation of the embodiments of the present disclosure.
[0085] Reference Figure 4 According to some embodiments, Figure 4 yes Figure 2 A schematic diagram of a portion of the auxiliary circuit 120 of the memory device 100. Figure 2 For ease of understanding, Figure 4 Similar components in the present invention are denoted by the same reference numerals. For the sake of brevity, the specific operations of similar components that have been discussed in detail in the above paragraphs are omitted in this article unless there is a need to introduce the same Figure 4 The collaborative relationship of the components shown in .
[0086] In some embodiments, one of the plurality of first rails 1211-1214, one of the plurality of second rails 1221-1227, another of the plurality of first rails 1211-1214, and another of the plurality of second rails 1221-1227 are sequentially arranged. For example, the first rail 1211 of the plurality of first rails 1211-1214, the second rail 1223 of the plurality of second rails 1221-1227, the first rail 1212 of the plurality of first rails 1211-1214, and the second rail 1224 of the plurality of second rails 1221-1227 are sequentially arranged. In different embodiments, the first rail 1211, the second rail 1223, the first rail 1213, the second rail 1225, the first rail 1214, and the second rail 1226 are sequentially arranged.
[0087] In some embodiments, each of the plurality of first rails 1211-1214 is disposed between two of the plurality of second rails 1221-1227. For example, the first rail 1211 of the plurality of first rails 1211-1214 is disposed between the second rails 1222 and 1223 of the plurality of second rails 1221-1227. The first rail 1212 of the plurality of first rails 1211-1214 is disposed between the second rails 1223 and 1224 of the plurality of second rails 1221-1227. The first rail 1213 of the plurality of first rails 1211-1214 is disposed between the second rails 1224 and 1225 of the plurality of second rails 1221-1227. The first rail 1214 of the plurality of first rails 1211-1214 is disposed between the second rails 1225 and 1226 of the plurality of second rails 1221-1227.
[0088] In some embodiments, one of the plurality of third rails 1231 and 1232 is disposed between two of the plurality of second rails 1221-1227. For example, the third rail 1231 of the plurality of third rails 1231 and 1232 is disposed between the second rails 1221 and 1222 of the plurality of second rails 1221-1227. The third rail 1232 of the plurality of third rails 1231 and 1232 is disposed between the second rails 1226 and 1227 of the plurality of second rails 1221-1227.
[0089] In some embodiments, one of the plurality of second rails 1221-1227 is disposed at the outermost side of the auxiliary circuit 120. For example, the second rail 1221 of the plurality of second rails 1221-1227 is disposed at the outermost side of the auxiliary circuit 120. For example, the second rail 1221 of the plurality of second rails 1221-1227 is disposed at the top of the auxiliary circuit 120. The second rail 1227 of the plurality of second rails 1221-1227 is disposed at the outermost side of the auxiliary circuit 120. For example, the second rail 1227 of the plurality of second rails 1221-1227 is disposed at the bottom of the auxiliary circuit 120.
[0090] In some embodiments, the plurality of first rails 1211-1214 are disposed between the plurality of third rails 1231 and 1232. For example, the plurality of first rails 1211-1214 are disposed between the plurality of third rails 1231 and 1232.
[0091] In some embodiments, one of the plurality of first rails 1211-1214, one of the plurality of second rails 1221-1227, and one of the plurality of third rails 1231 and 1232 are sequentially arranged. For example, the first rail 1214 of the plurality of first rails 1211-1214, the first rail 1226 of the plurality of second rails 1221-1227, and the third rail 1232 of the plurality of third rails 1231 and 1232 are sequentially arranged. In different embodiments, one of the plurality of third rails 1231 and 1232, one of the plurality of second rails 1221-1227, and one of the plurality of first rails 1211-1214 are sequentially arranged. For example, the third rail 1231 of the plurality of third rails 1231 and 1232, the first rail 1222 of the plurality of second rails 1221-1227, and the first rail 1211 of the plurality of first rails 1211-1214 are sequentially arranged.
[0092] In some embodiments, a portion of the plurality of second rails 1221-1227 and all of the plurality of first rails 1211-1214 are arranged in reverse order. For example, the second rails 1222-1226 of the plurality of second rails 1221-1227 and all of the plurality of first rails 1211-1214 are arranged in reverse order. In other words, the second rail 1222, the first rail 1211, the second rail 1223, the first rail 1212, the second rail 1224, the first rail 1213, the second rail 1225, the first rail 1214, and the second rail 1226 are arranged in sequence.
[0093] In some embodiments, second rail 1221, third rail 1231, second rail 1222, first rail 1211, second rail 1223, first rail 1212, second rail 1224, first rail 1213 and second rail 1225, first rail 1214 and second rail 1226, third rail 1232, and second rail 1227 are arranged in sequence.
[0094] In some embodiments, the plurality of first rails 1211-1214 are disposed in even columns of the auxiliary circuit 120. For example, the first rail 1211 of the plurality of first rails 1211-1214 is disposed in the fourth column of the auxiliary circuit 120, the first rail 1211 of the plurality of first rails 1211-1214 is disposed in the fourth column of the auxiliary circuit 120, the first rail 1212 of the plurality of first rails 1211-1214 is disposed in the sixth column of the auxiliary circuit 120, the first rail 1213 of the plurality of first rails 1211-1214 is disposed in the eighth column of the auxiliary circuit 120, and the first rail 1214 of the plurality of first rails 1211-1214 is disposed in the tenth column of the auxiliary circuit 120.
[0095] In some embodiments, the plurality of second rails 1221-1227 are disposed in odd columns of the auxiliary circuit 120. For example, the second rail 1221 of the plurality of second rails 1221-1227 is disposed in the first column of the auxiliary circuit 120, the second rail 1222 of the plurality of second rails 1221-1227 is disposed in the third column of the auxiliary circuit 120, the second rail 1223 of the plurality of second rails 1221-1227 is disposed in the fifth column of the auxiliary circuit 120, the second rail 1224 of the plurality of second rails 1221-1227 is disposed in the seventh column of the auxiliary circuit 120, the second rail 1225 of the plurality of second rails 1221-1227 is disposed in the ninth column of the auxiliary circuit 120, the second rail 1226 of the plurality of second rails 1221-1227 is disposed in the eleventh column of the auxiliary circuit 120, and the second rail 1227 of the plurality of second rails 1221-1227 is disposed in the thirteenth column of the auxiliary circuit 120.
[0096] In some embodiments, the plurality of third rails 1231 and 1232 are disposed in even-numbered columns of the auxiliary circuit 120. For example, the third rail 1231 of the plurality of third rails 1231 and 1232 is disposed in the second column of the auxiliary circuit 120, and the third rail 1232 of the plurality of third rails 1231 and 1232 is disposed in the twelfth column of the auxiliary circuit 120.
[0097] In some embodiments, a plurality of first rails 1211-1214 are disposed along the X direction. A plurality of second rails 1221-1227 are disposed along the X direction. A plurality of third rails 1231-1232 are disposed along the X direction.
[0098] In some embodiments, the plurality of first rails 1211-1214 are coupled to each other. The plurality of second rails 1221-1227 are coupled to each other. The plurality of third rails 1231 and 1232 are coupled to each other. In different embodiments, the plurality of first rails 1211-1214 are not coupled to the plurality of second rails 1221-1227. The plurality of first rails 1211-1214 are not coupled to the plurality of third rails 1231-1232. The plurality of second rails 1221-1227 are not coupled to the plurality of third rails 1231 and 1232.
[0099] In some embodiments, the plurality of first rails 1211 - 1214 , the plurality of second rails 1221 - 1227 , and the plurality of third rails 1231 and 1232 are located on the same layer.
[0100] In some embodiments, the plurality of first rails 1211-1214, the plurality of second rails 1221-1227, and the plurality of third rails 1231 and 1232 are made of metal. In different embodiments, the plurality of first rails 1211-1214, the plurality of second rails 1221-1227, and the plurality of third rails 1231 and 1232 are made of copper.
[0101] In some embodiments, the plurality of first rails 1211-1214, the plurality of second rails 1221-1227, and the plurality of third rails 1231 and 1232 are metal capacitors. Compared to using MOS capacitors, the memory device 100 can effectively save area by using metal capacitors for the plurality of rails.
[0102] Figure 4 The configuration is provided for the purpose of illustration. Different implementations also belong to the embodiments of the present disclosure. A person skilled in the art can adjust the structure of the auxiliary circuit 120 according to the actual operation of the embodiments of the present disclosure.
[0103] According to the above content, the present disclosure provides a memory device. By improving the discharge capacity from the storage node of the memory device to the bit line in response to the negative voltage provided to the bit line, the write capacity of the memory device is improved. In addition, since the charging capacity of the storage node of the memory device is reduced, the memory device saves energy during the write operation to reduce the energy consumption of the memory device. In addition, by using a circuit with multiple rails to assist the write capacity of the memory device, the memory device effectively saves area compared to other methods.
[0104] According to some embodiments of the present disclosure, a memory device is provided. The memory device includes at least one inverter, a transistor, and an auxiliary circuit. The transistor is coupled between the at least one inverter and a bit line. The auxiliary circuit is coupled to the bit line and provides a negative voltage to the bit line, and pulls down a power supply voltage provided to the at least one inverter.
[0105] In some embodiments, the auxiliary circuit includes a plurality of first rails and a plurality of second rails. The plurality of first rails are coupled to the bit lines. The plurality of second rails are disposed adjacent to the first rails and couple negative voltages to the first rails.
[0106] In some embodiments, one of the first tracks, one of the second tracks, another of the first tracks, and another of the second tracks are sequentially arranged.
[0107] In some embodiments, each of the first rails is disposed between two of the second rails.
[0108] In some embodiments, the auxiliary circuit includes a plurality of first rails and at least two second rails. The plurality of first rails couple negative voltages to the bit lines. At least two second rails are disposed adjacent to the first rails, wherein the first rails couple negative voltages to the at least two second rails, and the at least two second rails pull down a power supply voltage provided to at least one inverter.
[0109] In some embodiments, one of the at least two second rails is disposed between two of the first rails.
[0110] In some embodiments, the auxiliary circuit includes a plurality of first rails, a plurality of second rails, and at least two third rails. The plurality of first rails are coupled to the bit lines. The plurality of second rails are disposed adjacent to the first rails and couple negative voltages to the first rails. At least two third rails are disposed adjacent to the second rails. The first rails are disposed inside the at least two third rails.
[0111] In some embodiments, one of these second rails is disposed at the outermost side of the auxiliary circuit.
[0112] In some embodiments, one of the first rails, one of the second rails, and one of the at least two third rails are disposed in sequence.
[0113] According to some embodiments of the present disclosure, a memory device is provided. The memory device includes a pull-up transistor, a pull-down transistor, a pass-gate transistor, and an auxiliary circuit. The pull-up transistor receives a power supply voltage. The pull-down transistor is coupled to the pull-up transistor at a node. The pass-gate transistor is coupled between the node and a bit line. The auxiliary circuit includes at least one first rail, at least one second rail, and at least one third rail. The at least one first rail is coupled to the bit line. The at least one second rail couples a negative voltage to the at least one first rail. The at least one third rail adjusts the power supply voltage in response to the negative voltage provided by the at least one second rail.
[0114] In some embodiments, the at least one second rail further couples a negative voltage to the at least one third rail, and the at least one third rail reduces the power supply voltage in response to the negative voltage provided by the at least one second rail.
[0115] In some embodiments, at least one second rail is disposed between at least one first rail and at least one third rail.
[0116] In some embodiments, at least one first rail, at least one second rail, and at least one third rail are disposed in sequence.
[0117] In some embodiments, the at least one second rail includes a plurality of second rails, and one of the second rails is disposed at the outermost side of the auxiliary circuit.
[0118] In some embodiments, at least one first rail is disposed between two of the second rails.
[0119] In some embodiments, at least one third rail is disposed between two of the second rails.
[0120] According to some embodiments of the present disclosure, a memory device is provided. The memory device includes a first inverter, a second inverter, and a pull-down circuit. The second inverter is coupled to the first inverter at a node. The pull-down circuit pulls down a first voltage of the node and pulls down a second voltage provided to the first inverter and the second inverter.
[0121] In some embodiments, the pull-down circuit pulls down the first voltage and the second voltage respectively.
[0122] In some embodiments, the pull-down circuit pulls down the first voltage and the second voltage simultaneously.
[0123] In some embodiments, in response to the first voltage of the node being pulled low, the first current output from the node increases. In response to the second voltage provided to the first inverter and the second inverter being pulled low, the second current of the input node decreases.
[0124] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of an embodiment of the present disclosure. Those skilled in the art will understand that they can easily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced in this specification. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment of the present disclosure, and various changes, substitutions and modifications may be made to this document without departing from the spirit and scope of an embodiment of the present disclosure.
Claims
1. A memory device, characterized in that: Include: at least one inverter; a transistor coupled between the at least one inverter and a bit line; and An auxiliary circuit is coupled to the bit line and used to provide a negative voltage to the bit line and to pull down a power supply voltage provided to the at least one inverter.
2. The memory device according to claim 1, wherein: The auxiliary circuit includes: a plurality of first rails coupled to the bit line; and A plurality of second rails are disposed adjacent to the plurality of first rails and are used to couple the negative voltage to the plurality of first rails.
3. The memory device according to claim 2, wherein: One of the plurality of first rails, one of the plurality of second rails, another one of the plurality of first rails, and another one of the plurality of second rails are sequentially disposed.
4. The memory device according to claim 1, wherein: The auxiliary circuit includes: a plurality of first rails for coupling the negative voltage to the bit line; as well as At least two second rails are disposed adjacent to the plurality of first rails, wherein the plurality of first rails are used to couple the negative voltage to the at least two second rails, and the at least two second rails pull down the power supply voltage provided to the at least one inverter, One of the at least two second rails is disposed between two of the plurality of first rails.
5. The memory device according to claim 1, wherein: The auxiliary circuit includes: a plurality of first rails coupled to the bit line; a plurality of second rails disposed adjacent to the plurality of first rails and configured to couple the negative voltage to the plurality of first rails; as well as At least two third rails are disposed adjacent to the plurality of second rails, wherein the plurality of first rails are disposed inside the at least two third rails.
6. The memory device according to claim 5, wherein: One of the plurality of second rails is disposed at an outermost side of the auxiliary circuit.
7. The memory device according to claim 5, wherein: One of the plurality of first rails, one of the plurality of second rails, and one of the at least two third rails are disposed in sequence.
8. A memory device, characterized in that: Include: a pull-up transistor for receiving a power supply voltage; a pull-down transistor coupled to the pull-up transistor at a node; a transmission gate transistor coupled between the node and a bit line; and An auxiliary circuit comprising: at least one first rail coupled to the bit line; at least one second rail for coupling a negative voltage to the at least one first rail; as well as At least one third rail is used to adjust the power supply voltage in response to the negative voltage provided by the at least one second rail.
9. The memory device according to claim 8, wherein: The at least one second rail is further used to couple the negative voltage to the at least one third rail, and the at least one third rail is used to reduce the power supply voltage in response to the negative voltage provided by the at least one second rail.
10. A memory device, characterized in that: Include: a first inverter; a second inverter coupled to the first inverter at a node; and A pull-down circuit is used to pull down a first voltage of the node and to pull down a second voltage provided to the first inverter and the second inverter.