Memory device and forming method thereof

Abstract

Embodiments of the present application provide a memory device and a method of forming a memory device, the memory device including an array including a plurality of one-time programmable (OTP) memory cells; a plurality of word lines (WL); a plurality of bit lines (BL); and a plurality of control gate (CG) lines. Each OTP memory cell includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first and second fuse resistors are coupled to corresponding ones of the BLs, and the first and second transistors are gated by first and second ones of the CG lines, respectively.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming the same. Background Art

[0002] A one-time programmable (OTP) memory device is a type of nonvolatile memory device used in integrated circuits to adjust the circuit after the integrated circuit is manufactured. For example, an OTP memory device is used to provide repair information that controls the use of redundant cells when replacing defective cells of a memory array. Another use is to tune analog circuits by adjusting the capacitance or resistance values ​​of analog circuits or enabling and disabling parts of the system. A recent trend is that the same product may be manufactured in different manufacturing facilities but using a common process technology. Despite the best engineering efforts, the process may be slightly different at each facility. The use of OTP memory devices allows the product functionality of each manufacturing facility to be independently optimized. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: an array including a plurality of one-time programmable (OTP) memory cells; a plurality of word lines (WL); a plurality of bit lines (BL); and a plurality of control gate (CG) lines; wherein each OTP memory cell comprises a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor; and wherein the first fuse resistor and the second fuse resistor are coupled to a corresponding one of the BLs, and the first transistor and the second transistor are respectively selected by a first CG line and a second CG line of the CG lines.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a memory cell, the memory cell comprising: a first fuse resistor; a second fuse resistor; a first transistor, connected in series to the first fuse resistor; and a second transistor, connected in series to the second fuse resistor; wherein the memory cell is configured to randomly present a first logic state when the first fuse resistor is blown, or to randomly present a second logic state when the second fuse resistor is blown.

[0005] According to another aspect of an embodiment of the present application, a method for forming a memory device is provided, comprising: forming at least a first transistor, a second transistor, and a third transistor on a first side of a substrate; forming a first fuse resistor and a second fuse resistor in one of a plurality of first metallization layers, the plurality of first metallization layers being arranged above the first transistor to the third transistor on the first side; and forming a power rail in one of a plurality of second metallization layers, the plurality of second metallization layers being arranged on a second side of the substrate opposite to the first side. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an example memory system including a memory array is shown in accordance with some embodiments.

[0008] Figure 2 A schematic diagram showing a plurality of memory cells according to some embodiments Figure 1 An example schematic diagram of a portion of a memory array of FIG.

[0009] Figure 3 A schematic diagram showing a plurality of memory cells according to some embodiments Figure 1 Another example schematic diagram of a portion of a memory array of FIG.

[0010] Figure 4 and Figure 5 shows the respective programming according to some embodiments Figure 2 An example of two memory cells shown in .

[0011] Figure 6 shows how to read the Figure 2 An example of two memory cells shown in .

[0012] Figure 7 shows a device configured to form a Figure 2 The layout of a memory cell is shown in FIG.

[0013] Figure 8 shows a device configured to form a Figure 2 The layout of the two memory cells shown in .

[0014] Fig. 9 shows a device configured to form a Figure 2 The layout of the four memory cells shown in .

[0015] Fig.10 The configuration according to some embodiments is shown as being based on Figure 2 A schematic diagram forms the layout of a memory cell.

[0016] Fig.11 shows a device configured to form a Figure 3 The layout of a memory cell is shown.

[0017] Fig.12The configuration according to some embodiments is shown as being based on Figure 3 A schematic diagram forms the layout of a memory cell.

[0018] Fig.13 According to some embodiments, the Figure 7 A cross-sectional view of a semiconductor device forming a memory cell by a layout.

[0019] Fig.14 The configuration according to some embodiments is shown as being based on Figure 2 A schematic diagram forms the layout of a memory cell.

[0020] Fig.15 According to some embodiments, the Fig.14 A cross-sectional view of a semiconductor device forming a memory cell by a layout.

[0021] Fig.16 , Fig.17 and Fig.18 sectional views of other semiconductor devices according to some embodiments are shown respectively, each semiconductor device comprising Figure 2 A memory cell is shown in FIG.

[0022] Fig.19 According to some embodiments, the Fig.11 A cross-sectional view of a semiconductor device forming a memory cell by a layout.

[0023] Fig. 20 According to some embodiments, a method for Figure 1 Flowchart of an example method for generating PUF bits for a memory array.

[0024] Fig.21 According to some embodiments Figure 1 Another example schematic diagram of a portion of a memory array including a plurality of memory cells.

[0025] Fig. 22 A flowchart of an example method for fabricating a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0028] Physically Unclonable Functions (PUFs) are commonly used for authentication and key storage without the need for secure Electrically Erasable Programmable Read-Only Memory (EEPROM) and / or other expensive hardware (e.g., battery-backed static random access memory). Instead of storing secrets in digital memory, PUFs derive secrets from the physical properties of an integrated circuit (IC). PUFs are based on the idea that even if the same manufacturing process is used to manufacture multiple ICs, each IC may be slightly different from each other due to manufacturing variability. PUFs exploit this variability to derive "secret" information (e.g., silicon biometrics) that is unique to each IC. Typically, this secret information is referred to as the "PUF signature" of the IC. Furthermore, due to the manufacturing variability that defines the PUF signature, no two identical ICs can be manufactured, even if the design of the IC is fully known. Various types of variability in the IC can be used to define such a signature, for example, gate delays, the power-on state of memory devices, and / or any of a variety of physical characteristics of the IC.

[0029] Embodiments of the present disclosure provide various systems and methods for generating at least one bit (sometimes referred to as a PUF bit) of a PUF signature for a memory device including a plurality of memory cells. In one aspect of the present disclosure, each memory cell is implemented as an electrical fuse cell (sometimes referred to as an "mT2R structure") including a plurality of transistors and two fuse resistors. The two fuse resistors each have one end commonly connected to a bit line, through which a programming voltage is applied. According to various embodiments, even if the pair of fuse resistors are formed with the same size and the same material, and have the same level of programming voltage, one of the fuse resistors may be blown (or burned) by the programming voltage before the other. Therefore, one of the two fuse resistors may be randomly (and in advance) programmed to equivalently form an open circuit, while the other remains shorted. Depending on which fuse resistor is broken down first, the disclosed system (e.g., integrated with the memory device) may generate a PUF bit for the memory device / generate a PUF bit from the memory device. Applying the same principle on all memory cells, the disclosed system may generate a unique PUF signature from such a memory device.

[0030] Figure 1 1 shows a block diagram of a memory system 100 according to various embodiments. Figure 1 In the illustrated embodiment, memory system 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuit 108, authentication circuit 110, and control logic circuit 112. Although not shown in FIG. Figure 1 1, all components of memory system 100 may be coupled to each other and to control logic circuit 112. Figure 1 In the illustrated embodiment, for the purpose of clarity, each component is shown as a separate block, but in some other embodiments, Figure 1 Some or all of the components shown in the figure may be integrated together. For example, the memory array 102 may include an embedded authentication circuit (eg, 110).

[0031] The memory array 102 is a hardware component for storing data. In various embodiments, the memory array 102 is embodied as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other memory cells) 103. The memory array 102 includes a plurality of rows R1, R2, R3 ... RM, each row extending in a first direction (e.g., X direction), and a plurality of columns C1, C2, C3 ... CN, each column extending in a second direction (e.g., Y direction). Each of the rows and columns may include one or more conductive (e.g., metal) structures used as access lines. Each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and may be operated according to a voltage or current through a corresponding conductive structure of the column and row. For example, each row may include a corresponding word line (WL), and each column may include a corresponding bit line (BL) and a plurality of corresponding control gate (CG) lines.

[0032] In some embodiments, each memory cell 103 is implemented as an electric fuse memory cell, which may include a first fuse resistor, a second fuse resistor, a first control / cascade gate (CG) selector / transistor, a second CG selector / transistor, and one or more WL selectors / transistors. The first fuse resistor, at least one of the first CG transistor, and the WL transistor are coupled in series with each other, and the second fuse resistor, at least one of the second CG transistor, and the WL transistor are coupled in series with each other. In addition, the corresponding WL can be connected to the corresponding gate of the one or more WL transistors, the corresponding BL can be connected to the corresponding ends of the first and second fuse resistors, the corresponding first CG line can be connected to the gate of the first CG transistor, and the corresponding second CG line can be connected to the gate of the second CG transistor, which will refer to Figure 2 and Figure 3 Further detailed discussion.

[0033] Although in various embodiments of the present disclosure, the memory cell 103 is implemented as an electric fuse memory cell, which includes a plurality of fuse resistors, each of which is formed as a metal track in a corresponding metallization layer, the fuse resistor of the memory cell 103 can be implemented based on other resistor-based memory configurations. For example, the memory cell 103 can be formed as a resistive random access memory (RRAM) configuration, a phase change random access memory (PCRAM or PRAM) configuration, or a magnetoresistive random access memory (MRAM) configuration. In some other embodiments, the fuse resistor of the memory cell 103 can be implemented based on a through-hole structure or a polysilicon structure. In addition, in some other embodiments, the memory cell 103 can be implemented as an electric fuse memory cell including a plurality of fuse capacitors, wherein the fuse capacitors can each be formed as a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor.

[0034] In brief overview, one or more WL transistors and first and second CG transistors may be turned on to program corresponding first and second fuse resistors. For example, the two fuse resistors may be programmed simultaneously by applying the same programming voltage on BL when the corresponding WL lines, first CG lines, and second CG lines are turned on. Randomly, one of the first and second fuse resistors may blow faster than the other, and thus, the logic state of the memory cell may be determined based on which of the two fuse resistors has blown. Such randomly programmed logic states of the memory cell may form the basis of a PUF signature. A detailed description of the configuration and operation of the memory cell 103 and its application to generating a PUF signature will be described below with reference to Figure 4 , Figure 5 and Figure 6 Have a discussion.

[0035] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., WL) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert multiple conductive structures (e.g., BL and one or more CG lines) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each of the memory cells 103 asserted by the row decoder 104 and the column decoder 106. The authentication circuit 110 is a hardware component that can generate a PUF signature based on the respective logic states of the memory cells read by the I / O circuit 108. The control logic circuit 112 is a hardware component that can control the coupled components (e.g., 102 to 110). The following references Fig. 20 The flowchart of FIG. 1 provides a detailed description of the configuration and operation of the memory system 100 .

[0036] Figure 2 and Figure 3 Schematic diagrams 200 and 300 respectively illustrate example portions of a memory device 100 (eg, some memory cells 103) according to some embodiments. Figure 2-Figure 3 In the illustrated example, e-fuse memory cells 103A, 103B, 103C, and 103D of the memory array 102 are shown, and each of the e-fuse memory cells 103A-103D includes at least two fuse resistors. Although four e-fuse memory cells 103A-103D are shown, it should be understood that the memory array 102 can have any number of similar e-fuse memory cells while remaining within the scope of the present disclosure.

[0037] The memory cells 103 may be arranged in an array (as shown above). Figure 1 ). Figure 2-Figure 3, memory cells 103A and 103B may be arranged in the same row but in different columns; and memory cells 103C and 103D may be arranged in the same row but in different columns. For example, memory cells 103A and 103B are arranged in row R0, but in columns C0 and C1, respectively; and memory cells 103C and 103D are arranged in row R1, but in columns C0 and C1, respectively. With such a configuration, each memory cell may be operably coupled to access lines in corresponding rows and columns, respectively. In various embodiments, along each row, a plurality of electric fuse memory cells 103 are coupled to corresponding WLs; and along each column, a plurality of electric fuse memory cells 103 are coupled to corresponding BLs and a plurality of corresponding CG lines. For example, the electric fuse memory cells 103A and 103B are respectively coupled to WL0 arranged in row R0, and coupled to BL0, CG0, CG1 arranged in column C0 and BL1, CG2, CG3 arranged in column C1; and the electric fuse memory cells 103C and 103D are respectively coupled to WL1 arranged in row R1, and coupled to BL0, CG0, CG1 arranged in column C0 and BL1, CG2, CG3 arranged in column C1.

[0038] In some embodiments, the electric fuse memory cell 103 may include a first fuse resistor, a second fuse resistor, a first CG transistor, a second CG transistor, a first WL transistor, and a second WL transistor, wherein source / drain terminals of the first CG transistor and the second CG transistor are coupled to ground through the first WL transistor and the second WL transistor, respectively. Figure 2 In some other embodiments, the electric fuse memory cell 103 may include a first fuse resistor, a second fuse resistor, a first CG transistor, a second CG transistor, and a common WL transistor, wherein the source / drain terminals of the first CG transistor and the second CG transistor are coupled to ground through the common WL transistor, such as Figure 3 as shown in the illustrative example.

[0039] First reference Figure 2 200 , each of the electric fuse memory cells 103A to 103D includes a first fuse resistor 210 , a second fuse resistor 220 , a first CG transistor 230 , a second CG transistor 240 , a first WL transistor 250 , and a second WL transistor 260 . Figure 2This schematic design in is sometimes referred to as a 4-transistor-2-resistor (4T2R) configuration. The first CG transistor 230, the second CG transistor 240, the first WL transistor 250, and the second WL transistor 260 are each implemented as an n-type transistor. However, it should be understood that each of these transistors can be implemented as a p-type transistor while remaining within the scope of the present disclosure. The first fuse resistor 210, the first CG transistor 230, and the first WL transistor 250 are connected in series with each other between BL0 and ground; and the second fuse resistor 220, the second CG transistor 240, and the second WL transistor 260 are also connected in series with each other between BL0 and ground.

[0040] Using the electric fuse memory cell 103A as a representative example, the first fuse resistor 210 has a first end (or terminal) connected to BL0 and a second end (or terminal) connected to the first source / drain terminal of the first CG transistor 230; the second fuse resistor 220 has a first end (or terminal) also connected to BL0 and a second end (or terminal) connected to the first source / drain terminal of the second CG transistor 240; the first CG transistor 230 has a second source / drain terminal connected to the first source / drain terminal of the first WL transistor 250, and the second source / drain terminal of the first WL transistor 250 is connected to ground; and the second CG transistor 240 has a second source / drain terminal connected to the first source / drain terminal of the second WL transistor 260, and the second source / drain terminal of the second WL transistor 260 is connected to ground. In addition, the first WL transistor 250 and the second WL transistor 260 have their respective gate terminals, which are commonly connected to WL0 (i.e., commonly selected by WL0); the gate terminal of the first CG transistor 230 is connected to CG0 (i.e., selected by CG0); and the gate terminal of the second CG transistor 240 is connected to CG1 (i.e., selected by CG1).

[0041] Next reference Figure 3 300 , each of the e-fuse memory cells 103A to 103D includes a first fuse resistor 310 , a second fuse resistor 320 , a first CG transistor 330 , a second CG transistor 340 , and a common WL transistor 350 . Figure 3This schematic design in is sometimes referred to as a 3-transistor-2-resistor (3T2R) configuration. The first CG transistor 330, the second CG transistor 340, and the WL transistor 350 are each implemented as an n-type transistor. However, it should be understood that each of these transistors can be implemented as a p-type transistor while remaining within the scope of the present disclosure. The first fuse resistor 310, the first CG transistor 330, and the WL transistor 350 are connected in series with each other between BL0 and ground; and the second fuse resistor 320, the second CG transistor 340, and the WL transistor 350 are also connected in series with each other between BL0 and ground.

[0042] Using the electric fuse memory cell 103A as a representative example, the first fuse resistor 310 has a first end (or terminal) connected to BL0 and a second end (or terminal) connected to the first source / drain terminal of the first CG transistor 330; the second fuse resistor 320 has a first end (or terminal) also connected to BL0 and a second end (or terminal) connected to the first source / drain terminal of the second CG transistor 340; and each of the first CG transistor 330 and the second CG transistor 340 has a second source / drain terminal connected to the first source / drain terminal of the WL transistor 350, wherein the second source / drain terminal of the WL transistor is connected to ground. In addition, the gate terminal of the WL transistor 350 is connected to WL0 (i.e., commonly selected by WL0); the gate terminal of the first CG transistor 330 is connected to CG0 (i.e., selected by CG0); and the gate terminal of the second CG transistor 340 is connected to CG1 (i.e., selected by CG1).

[0043] In order to program the electric fuse memory cell 103, the corresponding WL transistor and the first and second CG transistors are first enabled. In an example where these transistors are each implemented as an n-type transistor, the WL transistor and the first and second CG transistors are enabled (e.g., turned on) by applying a signal of a logic high state to each of the WL and CG lines. Next, a programming signal (e.g., a voltage) is applied to BL. In the case where the WL transistor and the first and second CG transistors (and the corresponding WL transistors) are all turned on, a programming voltage can be applied to each of the first and second fuse resistors. Alternatively, two conduction paths are available through at least the first fuse resistor and the second fuse resistor, respectively.

[0044] Due to process variability, one of the two fuse resistors may blow faster than the other, even if the two fuse resistors are made of the same material and have the same size. For example, once one of the fuse resistors blows (e.g., one of the fuse resistors becomes open while the other remains short), a sudden drop in voltage may occur on the BL, which may automatically stop the programming process on the e-fuse memory cell 103. As a result, the e-fuse memory cell 103 may be "randomly" programmed to the first logic state or the second logic state. Whether the first logic state or the second logic state is programmed into the memory cell may correspond to which fuse resistor is blown (blown earlier than the other), which may be determined based on the read process.

[0045] In order to read the electric fuse memory cell 103, the corresponding WL transistor and only one of the first or second CG transistors are first enabled (e.g., turned on). In some embodiments, which of the CG transistors is selected to be enabled is fixed across the entire memory array. For example, across all columns of the memory array, one of the even CG lines (e.g., CG0) or the odd CG lines (e.g., CG1) is enabled during the read process. Next, a read signal (e.g., voltage) is applied to the BL. Since one of the fuse resistors has been randomly programmed (blown), only one conduction path can be established from the BL through the unblown fuse resistor and the selected (enabled) CG transistor to the ground. On the other hand, a conduction path from the BL through the blown fuse resistor and the selected (enabled) CG transistor to the ground cannot be established. For example, if the selected CG transistor is connected to a blown fuse resistor, a conduction path will not be established; and if the selected CG transistor is connected to a fuse resistor that has not yet been blown, a conduction path will be established.

[0046] In some embodiments, when a conduction path is not established (i.e., the fuse resistor connected to the selected CG transistor has been blown), the e-fuse memory cell 103 is determined to be in a first logic state (e.g., logic 1); and when a conduction path is established (i.e., the fuse resistor connected to the selected CG transistor has not been blown), the e-fuse memory cell 103 is determined to be in a second logic state (e.g., logic 0). In other words, each of the e-fuse memory cells 103 can be randomly programmed to logic 1 or 0. Based on such randomly programmed logic states on each e-fuse memory cell, a PUF signature (formed by the individual PUF bits of the e-fuse memory cell) can be generated.

[0047] Figure 4 and Figure 5An example of the e-fuse memory cells 103A and 103D being sequentially programmed according to some embodiments is shown. Following the principles discussed above, each of the e-fuse memory cells 103A and 103D can be randomly programmed to a first logic state (e.g., a logic 1 with a blown fuse resistor) or a second logic state (e.g., a logic 0 with an intact fuse resistor). The numerical values ​​of the signals discussed below are provided for illustration purposes only, and therefore, other values ​​may be considered while remaining within the scope of the present disclosure.

[0048] First reference Figure 4 , to program the e-fuse memory cell 103A, WL0 is asserted by applying a voltage signal corresponding to a logic high state (e.g., about 0.75V), while each of the other word lines (e.g., WL1) is applied with a voltage signal corresponding to a logic low state (e.g., about 0V). Simultaneously or subsequently, CG0 and CG1 are also asserted by applying a voltage signal also of about 0.75V, while each of the other control gate lines (e.g., CG2 and CG3) is applied with a voltage signal of about 0V. In this way, the WL transistors 250 and 260 and the CG transistors 230 and 240 of the e-fuse memory cell 103A can be turned on, and the WL transistors and CG transistors of the other e-fuse memory cells remain de-enabled. Next, a programming voltage (e.g., about 1.2-1.5V) is applied to BL0, while each of the other bit lines (e.g., BL1) is applied with a voltage signal of about 0V. Thus, two conduction paths 401 and 403 can be used to conduct current from BL0 to ground. As described above, one of the fuse resistors (eg, 210) will blow earlier than the other (eg, 220). As a result, the voltage present on BL0 may suddenly drop, causing the programming process (eg, on the still intact fuse resistor 220) to stop.

[0049] Next reference Figure 5, to program the e-fuse memory cell 103D, WL1 is asserted by applying a voltage signal corresponding to a logic high state (e.g., about 0.75V), while each of the other word lines (e.g., WL0) is applied with a voltage signal corresponding to a logic low state (e.g., about 0V). Simultaneously or subsequently, CG2 and CG3 are also asserted by applying a voltage signal also of about 0.75V, while each of the other control gate lines (e.g., CG0 and CG1) is applied with a voltage signal of about 0V. In this way, the WL transistors 250 and 260 and the CG transistors 230 and 240 of the e-fuse memory cell 103D can be turned on, and the WL transistors and CG transistors of the other e-fuse memory cells remain disabled. Next, a programming voltage (e.g., about 1.2-1.5V) is applied to BL1, while each of the other bit lines (e.g., BL0) is applied with a voltage signal of about 0V. Therefore, two conduction paths 501 and 503 can be used to conduct current from BL1 to ground. As described above, one of the fuse resistors (eg, 220) will blow earlier than the other (eg, 210). As a result, the voltage present on BL1 may suddenly drop, which causes the programming process (eg, on the still intact fuse resistor 210) to stop.

[0050] Figure 6 An example is shown where the e-fuse memory cells 103A and 103D (after being programmed) are read sequentially in accordance with some embodiments. Figure 4-Figure 5 In the example discussed in , the e-fuse memory cell 103A may have its fuse resistor 210 blown, and the e-fuse memory cell 103A may have its fuse resistor 220 blown. The values ​​of the signals discussed below are provided for illustration purposes only, and thus, other values ​​may be considered while remaining within the scope of the present disclosure.

[0051] To program the e-fuse memory cell 103A, WL0 is asserted by applying a voltage signal corresponding to a logic high state (e.g., about 0.75V), while each of the other word lines (e.g., WL1) is applied with a voltage signal corresponding to a logic low state (e.g., about 0V). Simultaneously or subsequently, one of CG0 or CG1 (e.g., CG0) is asserted by applying a voltage signal also about 0.75V, while each of the other control gate lines (e.g., CG1, CG2, and CG3) is applied with a voltage signal of about 0V. In this way, the WL transistors 250 and 260 and the CG transistor 230 of the e-fuse memory cell 103A can be turned on, and the CG transistor 240 of the e-fuse memory cell 103A, the WL transistor, and the CG transistors of the other e-fuse memory cells remain de-enabled. Next, a read voltage (e.g., less than 1.2-1.5V) is applied to BL0, while each of the other bit lines (e.g., BL1) is applied with a voltage signal of about 0V. One conduction path 601 can be used to conduct current from BL0 to ground through the fuse resistor 210, the CG transistor 230, and the WL transistor 250. Since the fuse resistor 210 has been blown (i.e., programmed to an open circuit), no current can flow through such a conduction path 601. Therefore, there is no current (or a current level less than a predetermined threshold) on BL0, and therefore, the e-fuse memory cell 103A can be determined to be permanently programmed to a logic 1 (e.g., having a blown fuse resistor connected to an enabled CG transistor).

[0052] Similarly, to read the e-fuse memory cell 103D, WL1 is asserted by applying a voltage signal corresponding to a logic high state (e.g., about 0.75V), while each of the other word lines (e.g., WL0) is applied with a voltage signal corresponding to a logic low state (e.g., about 0V). At the same time or subsequently, one of CG2 or CG3 (e.g., CG2) is asserted by applying a voltage signal also of about 0.75V, while each of the other control gate lines (e.g., CG3, CG0, and CG1) is applied with a voltage signal of about 0V. In this way, the WL transistors 250 and 260 and the CG transistor 230 of the e-fuse memory cell 103D can be turned on, and the CG transistor 240 of the e-fuse memory cell 103D, the WL transistor, and the CG transistors of the other e-fuse memory cells remain de-enabled. Next, a read voltage (e.g., less than 1.2 to 1.5V) is applied to BL1, while each of the other bit lines (e.g., BL0) is applied with a voltage signal of about 0V. One conduction path 603 may be used to conduct current from BL1 to ground through the fuse resistor 210, the CG transistor 230, and the WL transistor 250. Since the fuse resistor 210 is not blown (i.e., programmed to an open circuit), current may flow through such a conduction path 603. Therefore, there is current (or a current level above a predetermined threshold) on BL1, and therefore, the e-fuse memory cell 103D may be determined to be permanently programmed to a logic 0 (e.g., with an intact fuse resistor connected to an enabled CG transistor).

[0053] Figure 7 According to some embodiments, Figure 2 Schematic diagram of an e-fuse memory cell 103 implemented by the schematic design 200 (4T2R configuration) of FIG. 1 , and an example layout 700 configured to form the same. For example, the layout 700 is configured to form Figure 2 The electrical fuse memory cell 103C in FIG. Figure 2 Some of the references will be reused.

[0054] As shown, layout 700 includes patterns 702 and 704, each of which is configured to form an active area (hereinafter, "active area 702" and "active area 704", respectively); and patterns 706, 708, 710, 712, 714, 716, 718, 720, 722, 724, 726, and 728, each of which is configured to form a gate structure (hereinafter, "gate structure 706", "active area 708", "gate structure 710", "gate structure 712", "gate structure 714", "gate structure 716", "gate structure 718", "gate structure 720", "gate structure 722", "gate structure 724", "gate structure 726", and "gate structure 728", respectively). In some embodiments, such active areas and gate structures are formed along a major front side surface of a substrate (sometimes referred to as part of a "front end of line (FEOL) process / network"). On the front side surface of the substrate, multiple front side metallization layers (sometimes referred to as part of the "back end of line (BEOL) processing / network") can be formed; and on the back side surface of the substrate, multiple back side metallization layers can be formed, which will be discussed below.

[0055] The active regions 702-704 may each extend along a first lateral direction (e.g., X direction), and the gate structures 706-728 may each extend along a different second lateral direction (e.g., Y direction). In some embodiments, the active regions 702-704 are each formed in a stacked structure protruding from the main surface of the substrate. The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending along the X direction and vertically separated from each other. The portion of the semiconductor structure in the stack covered by the gate structure 706-728 is retained, while the other portion is replaced by a plurality of epitaxial structures. The remaining portion of the semiconductor structure may be configured as a channel of a corresponding transistor, the epitaxial structure coupled to both sides (or ends) of the remaining portion of the semiconductor structure may be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure covering (e.g., crossing) the other portion of the semiconductor structure may be configured as a gate structure (or terminal) of the transistor.

[0056] As Figure 7 , a portion of the active area portion 702 covered by the gate structure 714 may include a plurality of nanostructures vertically separated from each other, which may serve as a channel for a first portion of the WL transistor 250. Portions of the active area portion 702 disposed on opposite sides of the gate structure 714 are replaced by epitaxial structures. Such epitaxial structures may serve as source / drain terminals of the first portion of the WL transistor 250, respectively. The gate structure 714 may serve as a gate terminal of the first portion of the WL transistor 250. A second portion of the WL transistor 250 may be formed by the active area 704 and the gate structure 716. The first portion and the second portion of the WL transistor 250 may be connected in parallel.

[0057] As another representative example, the portion of the active area portion 702 covered by the gate structure 710 may include a plurality of nanostructures vertically separated from each other, which may serve as a channel for a first portion of the CG transistor 230. The portion of the active area portion 702 disposed on the opposite side of the gate structure 710 is replaced by an epitaxial structure. Such epitaxial structures may be respectively used as source / drain terminals of the first portion of the CG transistor 230. The gate structure 710 may serve as a gate terminal of the first portion of the CG transistor 230. The second portion of the CG transistor 230 may be formed by the active area 704 and the gate structure 712. The first portion and the second portion of the CG transistor 230 may be connected in parallel. The other transistors 240 and 260 may be similarly formed, and therefore, the description is not repeated.

[0058] When active regions 702 to 704 and gate structures 706 to 728 are formed, at least transistors 230 to 260 may be defined. Thus, each of gate structures 710-712 may be operable to function as a portion of CG0 (which gates CG transistor 230), each of gate structures 714-716 may be operable to function as a portion of WL1 (which gates WL transistor 250), each of gate structures 722-724 may be operable to function as a portion of CG1 (which gates CG transistor 240), and gate structures 718-720 may be operable to function as another portion of WL1 (which gates WL transistor 260), as shown. Figure 7 shown.

[0059] Layout 700 also includes patterns 730, 732, 734, 736, 738, 740, 742, 744, 746, 748, 750, 752, 754, 756, 758, and 760, which are configured to form a middle-end interconnect structure, sometimes referred to as MD (hereinafter referred to as "MD730", "MD732", "MD734", "MD736", "MD738", "MD740", "MD742", "MD744", "MD746", "MD748", "MD750", "MD752", "MD754", "MD756", "MD758", and "MD760"). Each MD can connect the corresponding source / drain terminal to the upper interconnect structure through a middle-end via structure (sometimes referred to as VD). In addition, each gate structure can be coupled to the upper interconnect structure through another middle-end via structure (sometimes referred to as VG).

[0060] A plurality of metallization layers, such as M0, M1, M2, M3, etc., may be formed on top of these intermediate end structures on the front side of the substrate, each of which includes a plurality of metal tracks or lines embedded in a corresponding dielectric material (e.g., an intermetallic dielectric (IMD) / interlayer dielectric (ILD)). For example, the layout 700 further includes patterns 762, 763, 764, 765, 766, 767, 768, 769, 770, and 771, each of which is configured to form a metal track in the M0 layer (hereinafter referred to as "M0 track 762", "M0 track 763", "M0 track 764", "M0 track 765", "M0 track 766", "M0 track 767", "M0 track 768", "M0 track 769", "M0 track 770", and "M0 track 771" respectively). " and "M0 track 771"; patterns 770 and 772, each of which is configured to form a metal track in the M1 layer (hereinafter referred to as "M1 track 770" and "M1 track 772", respectively); patterns 774 and 776, each of which is configured to form a metal track in the M2 layer (hereinafter referred to as "M2 track 774" and "M2 track 776", respectively); and pattern 780, which is configured to form a metal track in the M3 layer (hereinafter referred to as "M3 track 780").

[0061] In some embodiments, gate structures 714 and 718 are connected to each other through at least M0 rail 770, gate structures 716 and 720 are connected to each other through at least M0 rail 771, and each of M0 rails 770 and 771 is configured to connect all portions of portions of WL1. One of the source / drain terminals of CG transistor 230 is electrically connected to a first end of M2 rail 774 through at least MD 736, M0 rail 762, and M1 rail 770 and through at least MD 738, M0 rail 766, and M1 rail 770. The gate terminal of CG transistor 230 (e.g., gate structures 710 and 712) is connected to M0 rails 763 and 767, respectively. As shown, MD 736, M0 rail 762, and M0 rail 763 are symmetrical to MD 738, M0 rail 766, and M0 rail 767, respectively. The other source / drain terminal of CG transistor 230 is connected to one of the source / drain terminals of WL transistor 250. The M2 rail 774 is operable to function as a fuse resistor 210. Similarly, one of the source / drain terminals of the CG transistor 240 is electrically connected to a first end of the M2 rail 776 through at least the MD 752, the M0 rail 764, and the M1 rail 772 and through at least the MD 754, the M0 rail 768, and the M1 rail 770. The gate terminal (e.g., gate structures 722 and 724) of the CG transistor 240 is connected to the M0 rails 765 and 769, respectively. As shown, the MD 752, the M0 rail 764, and the M0 rail 765 are symmetrical to the MD 754, the M0 rail 768, and the M0 rail 769, respectively. The other source / drain terminal of the CG transistor 240 is connected to one of the source / drain terminals of the WL transistor 260. The M2 rail 776 is operable to function as a fuse resistor 220. A second end of the M2 rail 774 and a second end of the M2 rail 776 are coupled to each other through the M3 rail 780, and the M3 rail 780 is operable to serve as a part of BLO.

[0062] Layout 700 also includes patterns 782 and 784, each of which is configured to form a metal track (hereinafter, "BM0 track 782" and "BM0 track 784", respectively) in a first backside metallization layer. In some embodiments, the first backside metallization layer is the bottommost metallization layer relative to the backside of the substrate. In addition, on the backside of the substrate, multiple metallization layers, sometimes referred to as BM1, BM2, BM3, etc., can be formed, each metallization layer including multiple metal tracks or lines embedded in a corresponding dielectric material (e.g., intermetallic dielectric (IMD) / interlayer dielectric (ILD)).

[0063] like Figure 7As shown, when viewed from the top, the BM0 track 782 can extend through the active area 702 along the X direction, e.g., overlap the active area 702 when viewed from the top; and when viewed from the top, the BM0 track 784 can extend across the active area 704 along the X direction, e.g., overlap the active area 704 when viewed from the top. In some embodiments, each of the BM0 tracks 782 and 784 is configured to carry a power supply voltage (VSS or ground) and provide the power supply voltage to transistors formed on the front side of the substrate. For example, in the upper half of the layout 700 (the first part of the transistors 230-260), the BM0 track 782 is electrically connected to the common source / drain terminal of the WL transistors 250 and 260 through the backside via structure (sometimes referred to as "VB") formed by the pattern 786. It should be noted that the common source / drain terminal of the WL transistors 250 and 260 is also connected to the MD 744 on its front side. In the lower half of layout 700 (the second portion of transistors 230-260), BM0 track 784 is electrically connected to the common source / drain terminal of WL transistors 250 and 260 through another backside via structure (VB) formed by pattern 788. Similarly, the common source / drain terminal of WL transistors 250 and 260 is also connected to MD 746 on its front side.

[0064] Figure 8 According to some embodiments, Figure 2 Schematic diagram of two e-fuse memory cells 103 implemented by the schematic design 200 (4T2R configuration) of FIG. 1 and an example layout 800 configured to form the same. For example, the layout 800 is configured to form the e-fuse memory cells 103C and 103D, so that Figure 2 Some references will be reused. As shown, the layout 800 includes two layouts 700 adjacent to each other along the X direction, so a brief description will be provided. The layout 700 on the left may correspond to the electrical fuse memory cell 103C (which is almost identical to the layout 700 on the left). Figure 7 ), and the layout 700 on the right may correspond to the e-fuse memory cell 103D (which is again similar to Figure 7 For example, the layout 700 on the right also includes a plurality of gate structures operably configured as WL1, CG2, and CG3, respectively, and includes two M2 tracks operably configured as two fuse resistors of the electrical fuse memory cell 103D, respectively, which are connected via an M3 track operably used as BL1.

[0065] Fig. 9 According to some embodiments, Figure 2Schematic diagram of four e-fuse memory cells 103 implemented by a schematic design 200 (4T2R configuration) and an example layout 900 configured to form the same. For example, the layout 900 is configured to form e-fuse memory cells 103A, 103B, 103C, and 103D, so that Figure 2 Some references will be reused. As shown, the layout 900 includes four layouts 700 adjacent to each other along the X direction and the Y direction, respectively, and therefore, a description will be briefly provided. The layout 700 in the upper left corner may correspond to the electric fuse memory cell 103C, the layout 700 in the upper right corner may correspond to the electric fuse memory cell 103D, the layout 700 in the lower left corner may correspond to the electric fuse memory cell 103A, and the layout 700 in the lower right corner may correspond to the electric fuse memory cell 103B. Fig. 9 Each of the layouts 700 shown in FIG. 7 is substantially similar to Figure 7 The layout is 700.

[0066] For example, the layout 700 corresponding to the E-fuse memory cell 103C is Figure 7 The layout 700 corresponding to the electric fuse memory cell 103D also includes a plurality of gate structures operably configured as WL1, CG2, and CG3, respectively, and includes two M2 tracks, the M2 tracks are operably configured as two fuse resistors of the electric fuse memory cell 103D, and the two fuse resistors are connected by an M3 track operably used as BL1. The layout 700 corresponding to the electric fuse memory cell 103A also includes a plurality of gate structures operably configured as WL0, CG0, and CG1, respectively, and includes two M2 tracks, the two M2 tracks are operably configured as two fuse resistors of the electric fuse memory cell 103A, and the two fuse resistors are connected by an M3 track operably used as BL0. The layout 700 corresponding to the e-fuse memory cell 103B also includes a plurality of gate structures operably configured as WL0, CG2, and CG3, respectively, and includes two M2 tracks, which are operably configured as two fuse resistors of the e-fuse memory cell 103B, respectively, and the two fuse resistors are connected by an M3 track operably used as BL1. As shown, the M3 track configured as BL0 can extend in the Y direction to cross the layout corresponding to the e-fuse memory cells 103C and 103A, and the M3 track configured as BL1 can extend in the Y direction to cross the layout corresponding to the e-fuse memory cells 103D and 103B.

[0067] Fig.10 A schematic diagram of one e-fuse memory cell 103 implemented as three fuse resistors, three CG transistors, and three WL transistors and an example layout 1000 configured to form the same are shown. Fig.10 This schematic design in is sometimes referred to as a 6-transistor-3-resistor (6T3R) configuration. In some embodiments, layout 1000 is configured to form Figure 2 The electrical fuse memory cell 103C in FIG. Figure 2 Some of the references will be reused.

[0068] exist Fig.10 In the 6T3R configuration, in addition to the fuse resistors 210-220, the CG transistors 230-240 and the WL transistors 250-260 (as described above in Figure 2 In addition to the 4T2R configuration shown in FIG. 1 , the electric fuse memory cell 103C also includes another fuse resistor 270, another CG transistor 280, and another WL transistor 290. One end of the fuse resistor 270 is also connected to BL0, and the other end is connected to the first source / drain terminal of the CG transistor 280. The CG transistor 280 is selected by another CG line CG2. The second source / drain terminal of the CG transistor 280 is connected to the first source / drain terminal of the WL transistor 290, and the second drain terminal of the WL transistor 290 is grounded. The WL transistor 290 is also selected by WL1.

[0069] Thus, layout 1000 may include Figure 7 The layout 700 is substantially similar to a specific portion (e.g. Fig.10 Layout 700 on the left), and another portion (e.g., 1010) that can be configured to form an additional fuse resistor, a CG transistor, and a WL transistor. For example, layout portion 1010 may include active areas 702 and 704 further extending thereon in the X direction, respectively, and a plurality of patterns for forming gate structures 1012, 1014, 1016, and 1018. Such gate structures 1012 to 1018 together with active areas 702 and 704 may form CG transistor 280 and WL transistor 290. As shown, CG transistor 280 may include a first portion formed by active area 702 and gate structure 1012, and a second portion formed by active area 704 and gate structure 1014; and WL transistor 290 may include a first portion formed by active area 702 and gate structure 1016, and a second portion formed by active area 704 and gate structure 1018. In this way, gate structures 1012 and 1014 can each be configured as part of CG2, and gate structures 1016 and 1018 can each be configured as part of WL1.

[0070] Layout portion 1010 also includes patterns configured to respectively form MD 1020 and 1022, M0 rails 1024 and 1026, M1 rail 1028, M2 rail 1030, and M3 rail 1032. MD 1020, M0 rail 1024, and M1 rail 1028 may connect one of the source / drain terminals of the first portion of CG transistor 280 to one end of M2 rail 1030 (which may be operatively used as fuse resistor 270); and MD 1022, M0 rail 1026, and M1 rail 1028 may connect one of the source / drain terminals of the second portion of CG transistor 280 to the same end of M2 rail 1030 (which may be operatively used as fuse resistor 270). The other end of M2 rail 1030 may be connected to M3 rail 1032, which may be operatively used as a portion of BL0. It should be noted that M3 rail 1032 and M3 rail 780 may be coupled to each other via one or more other metal rails (not shown).

[0071] In addition, layout portion 1010 may include BM0 tracks 782 and 784, which are further extended in the X direction, respectively. Similarly, one of the source / drain terminals of the first portion of WL transistor 290 is electrically connected to BM0 track 782 through a backside via structure (VB) formed by pattern 1032, and the other source / drain terminal of the first portion of WL transistor 290 is connected to the first portion of CG transistor 280; and one of the source / drain terminals of the second portion of WL transistor 290 is electrically connected to BM0 track 784 through another backside via structure (VB) formed by pattern 1034, wherein the other source / drain terminal of the second portion of WL transistor 290 is connected to the second portion of CG transistor 280.

[0072] Fig.11 According to some embodiments, Figure 3 Schematic diagram of an e-fuse memory cell 103 implemented by a schematic design 300 (3T2R configuration) and an example layout 1100 configured to form the same. For example, the layout 1100 is configured to form Figure 3 The electrical fuse memory cell 103C in FIG. Figure 3 Some of the references will be reused.

[0073] As shown, layout 1100 includes patterns 1102 and 1104, each of which is configured to form an active area (hereinafter, "active area 1102" and "active area 1104", respectively); and patterns 1106, 1108, 1110, 1112, 1114, 1116, 1118, and 1120, each of which is configured to form a gate structure (hereinafter, "gate structure 1106", "active area 1108", "gate structure 1110", "gate structure 1112", "gate structure 1114", "gate structure 1116", "gate structure 1118", and "gate structure 1120", respectively). In some embodiments, such active areas and gate structures are formed along a major front side surface of a substrate (sometimes referred to as part of a "front end of line (FEOL) process / network"). Multiple frontside metallization layers (sometimes referred to as part of the "backend of line (BEOL) processing / network") may be formed on the frontside surface of the substrate; and multiple backside metallization layers may be formed over the backside surface of the substrate, as will be discussed below.

[0074] The active regions 1102-1104 may each extend along a first lateral direction (e.g., X direction), and the gate structures 1106-1120 may each extend along a different second lateral direction (e.g., Y direction). In some embodiments, the active regions 1102-1104 are each formed by a stacked structure protruding from the main surface of the substrate. The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending along the X direction and vertically separated from each other. The portion of the semiconductor structure in the stack covered by the gate structure 1106-1120 is retained, while the other portion is replaced by a plurality of epitaxial structures. The remaining portion of the semiconductor structure may be configured as a channel of a corresponding transistor, the epitaxial structures coupled to both sides (or ends) of the remaining portion of the semiconductor structure may be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure covering (e.g., crossing) the other portion of the semiconductor structure may be configured as a gate structure (or terminal) of the transistor.

[0075] As Fig.11, a portion of the active area portion 1102 covered by the gate structure 1110 may include a plurality of nanostructures vertically separated from each other, which may be used as a channel of a first portion of the WL transistor 350. The portion of the active area portion 1102 disposed on the opposite side of the gate structure 1110 is replaced with an epitaxial structure. Such epitaxial structures may be used as source / drain terminals of the first portion of the WL transistor 350, respectively. The gate structure 1110 may be used as a gate terminal of the first portion of the WL transistor 350. A second portion of the WL transistor 350 may be formed by the active area 1102 and the gate structure 1114. A third portion of the WL transistor 350 may be formed by the active area 1104 and the gate structure 1112. A fourth portion of the WL transistor 350 may be formed by the active area 1104 and the gate structure 1116. The first portion to the fourth portion of the WL transistor 350 may be connected in parallel.

[0076] As another representative example, the portion of the active area portion 1102 covered by the gate structure 1106 may include a plurality of nanostructures vertically separated from each other, which may be used as a channel for a first portion of the CG transistor 330. The portion of the active area portion 1102 disposed on the opposite side of the gate structure 1106 is replaced with an epitaxial structure. Such epitaxial structures may be used as source / drain terminals of the first portion of the CG transistor 330, respectively. The gate structure 1106 may be used as a gate terminal of the first portion of the CG transistor 330. The second portion of the CG transistor 330 may be formed by the active area 1104 and the gate structure 1108. The first portion and the second portion of the CG transistor 330 may be connected in parallel. Another CG transistor 340 may be formed similarly, and therefore, the description is not repeated.

[0077] When forming active regions 1102 to 1104 and gate structures 1106 to 1120, at least transistors 330 to 350 may be defined. Fig.11 As shown, each of gate structures 1106-1108 is operable to function as a portion of CG0 (which gates CG transistor 330), each of gate structures 1110-1116 is operable to function as a portion of WL1 (which gates WL transistor 350), and each of gate structures 1118-1120 is operable to function as a portion of CG1 (which gates CG transistor 340), as shown. Fig.11 shown.

[0078] Layout 1100 also includes patterns 1122, 1124, 1126, 1128, 1130, 1132, 1134, 1136, 1138, and 1140, which are configured to form a middle-end interconnect structure, sometimes referred to as MD (hereinafter referred to as "MD 1122", "MD1124", "MD1126", "MD 1128", "MD 1130", "MD 1132", "MD 1134", "MD 1136", "MD 1138", and "MD 1140", respectively). Each MD can connect the corresponding source / drain terminal to the upper interconnect structure through a middle-end via structure (sometimes referred to as VD). In addition, each gate structure can be coupled to the upper interconnect structure through another middle-end via structure (sometimes referred to as VG).

[0079] Over these intermediate end structures on the front side of the substrate, a plurality of metallization layers, such as M0, M1, M2, M3, etc., may be formed, each of the metallization layers including a plurality of metal tracks or lines embedded in a corresponding dielectric material (e.g., an intermetallic dielectric (IMD) / interlayer dielectric (ILD)). For example, the layout 1100 further includes patterns 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, and 1152, each of which is configured to form a metal track in the M0 layer (hereinafter referred to as "M0 track 1142," "M0 track 1143," "M0 track 1144," "M0 track 1145," "M0 track 1146," "M0 track 1147," "M0 track 1148," "M0 track 1149," "M0 track 1150," and "M0 track 1151," respectively). The present invention relates to a metal track 1150, "M0 track 1150" and "M0 track 1152"; patterns 1154 and 1156, each of which is configured to form a metal track in the M1 layer (hereinafter referred to as "M1 track 1154" and "M1 track 1156", respectively); patterns 1158 and 1160, each of which is configured to form a metal track in the M2 layer (hereinafter referred to as "M2 track 1158" and "M2 track 1160", respectively); and pattern 1162, which is configured to form a metal track in the M3 layer (hereinafter referred to as "M3 track 1162").

[0080] In some embodiments, one of the source / drain terminals of CG transistor 330 is electrically connected to a first end of M2 rail 1158 through at least MD 1122, M0 rail 1142, and M1 rail 1154, and through at least MD 1124, M0 rail 1144, and M1 rail 1154. The other source / drain terminal of CG transistor 330 is connected to one of the source / drain terminals of WL transistor 350. M2 rail 1158 is operable to function as fuse resistor 310. Similarly, one of the source / drain terminals of CG transistor 340 is electrically connected to a first end of M2 rail 1160 through at least MD 1138, M0 rail 1150, and M1 rail 1156, and through at least MD 1140, M0 rail 1152, and M1 rail 1156. The other source / drain terminal of CG transistor 340 is connected to one of the source / drain terminals of WL transistor 350. The M2 rail 1160 is operable to function as the fuse resistor 320. A second end of the M2 rail 1158 and a second end of the M2 rail 1160 are coupled to each other through the M3 rail 1160, and the M3 rail is operable to function as a part of BLO.

[0081] The layout 1100 also includes patterns 1182 and 1184, each of which is configured to form a metal track (hereinafter referred to as "BM0 track 1182" and "BM0 track 1184", respectively) in a first backside metallization layer. In some embodiments, the first backside metallization layer is the bottommost metallization layer relative to the backside of the substrate. In addition, on the backside of the substrate, multiple metallization layers, sometimes referred to as BM1, BM2, BM3, etc., can be formed, each metallization layer including multiple metal tracks or lines embedded in a corresponding dielectric material (e.g., intermetallic dielectric (IMD) / interlayer dielectric (ILD)).

[0082] like Fig.11As shown, when viewed from the top, BM0 track 1182 can extend across active area 1102 along the X direction, for example, overlapping active area 1101 when viewed from the top; and when viewed from the top, BM0 track 1184 can extend across active area 1104 along the X direction, for example, overlapping active area 1103 when viewed from the top. In some embodiments, each of BM0 tracks 1182 and 1184 is configured to carry a power supply voltage (VSS or ground) and provide the power supply voltage to transistors formed on the front side of the substrate. For example, in the upper half of layout 1100 (the first part of transistors 330-350), BM0 track 1182 is electrically connected to the common source / drain terminal of WL transistor 350 through a backside via structure (sometimes referred to as "VB") formed by pattern 1186. It should be noted that the common source / drain terminal of WL transistor 350 is also connected to MD1130 on its front side. In the lower half of layout 1100 (the second portion of transistors 330-350), BM0 track 1184 is electrically connected to the common source / drain terminal of WL transistor 350 through another backside via structure (VB) formed by pattern 1188. Similarly, the common source / drain terminal of WL transistor 350 is also connected to MD 1132 on its front side.

[0083] Fig.12 A schematic diagram of one e-fuse memory cell 103 implemented as three fuse resistors, three CG transistors, and one WL transistor and an example layout 1200 configured to form the same are shown. Fig.12 This schematic design in is sometimes referred to as a 4-transistor-3-resistor (4T3R) configuration. In some embodiments, layout 1200 is configured to form Figure 3 The electrical fuse memory cell 103C in FIG. Figure 3 Some of the references will be reused.

[0084] exist Fig.12 In the 4T3R configuration, in addition to the fuse resistors 310-320, the CG transistors 330-340 and the WL transistor 350 (as shown above Figure 3 In addition to the 3T2R configuration shown in FIG. 1 , the e-fuse memory cell 103C also includes another fuse resistor 370 and another CG transistor 380. One end of the fuse resistor 370 is also connected to BL0, and the other end is connected to the first source / drain terminal of the CG transistor 380. The CG transistor 380 is selected by another CG line CG2. The second source / drain terminal of the CG transistor 380 is connected to the first source / drain terminal of the WL transistor 350, which is also connected in series to each of the CG transistors 330-340.

[0085] Thus, layout 1200 may include Fig.11 The layout 1100 is substantially similar to a particular portion (e.g. Fig.12 1210 ) and another portion (e.g., 1210) that may be configured to form an additional fuse resistor and a CG transistor. For example, the layout portion 1210 may include active areas 1102 and 1104 further extending thereon in the X direction, respectively, and a plurality of patterns for forming gate structures 1212, 1214, 1216, and 1218. Such gate structures 1212 to 1218 together with the active areas 1102 and 1104 may form other portions of the CG transistor 380 and the WL transistor 350. As shown, the CG transistor 380 may include a first portion formed by the active area 1102 and the gate structure 1212, and a second portion formed by the active area 1104 and the gate structure 1214; and the WL transistor 350 may include a fifth portion formed by the active area 1102 and the gate structure 1216, and a sixth portion formed by the active area 1204 and the gate structure 1218. In this way, gate structures 1212 and 1214 can each be configured as part of CG2, and gate structures 1216 and 1218 can each be configured as part of WL1.

[0086] Layout portion 1210 also includes patterns configured to respectively form MD 1220 and 1222, M0 rails 1224 and 1226, M1 rail 1228, M2 rail 1230, and M3 rail 1232. MD 1220, M0 rail 1224, and M1 rail 1228 may connect one of the source / drain terminals of the first portion of CG transistor 380 to one end of M2 rail 1230 (which may be operatively used as fuse resistor 370); and MD 1222, M0 rail 1226, and M1 rail 1228 may connect one of the source / drain terminals of the second portion of CG transistor 380 to the same end of M2 rail 1230 (which may be operatively used as fuse resistor 370). The other end of M2 rail 1230 may be connected to M3 rail 1232, which may be operatively used as a portion of BL0. It should be noted that M3 rail 1232 and M3 rail 1162 may be coupled to each other via one or more other metal rails (not shown).

[0087] In addition, the layout portion 1210 may include BM0 tracks 1182 and 1184 further extending thereto in the X direction, respectively. Similarly, one of the source / drain terminals of the fifth portion of the WL transistor 350 is electrically connected to the BM0 track 1182 through a backside via structure (VB) formed by the pattern 1232, and the other source / drain terminal of the fifth portion of the WL transistor 350 is connected to the first portion of the CG transistor 380; and one of the source / drain terminals of the sixth portion of the WL transistor 350 is electrically connected to the BM0 track 1184 through another backside via structure (VB) formed by the pattern 1234, and the other source / drain terminal of the sixth portion of the WL transistor 350 is connected to the second portion of the CG transistor 380.

[0088] Fig.13 According to some embodiments, Figure 7 1 is a cross-sectional view of a semiconductor device 1300 formed by the layout 700. It should be noted that Fig.13 The cross-sectional view shown in FIG. 1 includes multiple cross sections of the semiconductor device 1300, each of which is cut parallel to the X direction. Fig.13 In the cross-sectional view, multiple structures parallel to each other (for example, 762 and 763, 764 and 765, etc.) can be shown simultaneously. Figure 7 Some of the reference numerals will be reused in the following discussion of the semiconductor device 1300 .

[0089] As shown, in active region 702, multiple channels and epitaxial structures may be formed. Each of the channels may be covered or wrapped by a corresponding one of the gate structures (e.g., 710, 714, 718, 722), and each two of the epitaxial structures may be covered by a corresponding one of the MDs (e.g., 736, 740, 744, 748, 752). As described above, at least some corresponding portions of CG transistors 230-240 and WL transistors 250-260 may be formed by active region 702 and gate structures 710, 714, 718, and 722. In addition, gate structure 710 may be used as part of CG0, gate structures 714 and 718 may each be used as part of WL1, and gate structure 722 may be used as part of CG1. Therefore, each of gate structures 710, 714, 718, and 722 may be coupled to one or more metal tracks formed thereon.

[0090] For example, gate structure 710 is coupled to M0 rail 763, and gate structure 722 is coupled to M0 rail 765. Similarly, MD 736, together with at least M0 rail 762 and M1 rail 770, can couple one of the source / drain terminals (e.g., epitaxial structure) of CG transistor 230 to one end of M2 rail 774 used as fuse resistor 210; and MD 752, together with at least M0 rail 764 and M1 rail 772, can couple one of the source / drain terminals (e.g., epitaxial structure) of CG transistor 240 to one end of M2 rail 776 used as fuse resistor 220. The other end of M2 rail 774 is coupled to M3 rail 780, which is used as part of BL0; and the other end of M2 rail 776 is coupled to M3 rail 780 (part of BL0).

[0091] In addition, a BM0 track 782 is formed on a second (e.g., back) side of the substrate opposite to the first (e.g., front) side of the substrate on which transistors 230 to 260 are formed. As shown, the BM0 track 782 is coupled to a common source / drain terminal (e.g., an epitaxial structure) of WL transistors 250-260 via VB 786. Such a common source / drain terminal can have its front and back sides connected to MD 744 and VB 786, respectively. On the BM0 layer (when the substrate is turned upside down), multiple additional backside metallization layers, such as BM1...BMz, can be formed. Each backside metallization layer can include one or more metal tracks similar to the BM0 track 782.

[0092] Fig.15 According to some embodiments, Fig.14 FIG. 1 is a cross-sectional view of a semiconductor device 1500 formed by the layout 1400. The layout 1400 is substantially similar to Figure 7 1400, except that the layout 1400 includes at least one pattern configured to form a feed-through via (FTV) structure. Fig.15 The cross-sectional view is cut along the Y direction, for example, along the length direction of an MD passing through adjacent active regions 702-704. Figure 7 The layout is 700, so Figure 7 Some of the reference numerals will be reused in the following discussion of the semiconductor device 1500 (and the corresponding layout 1400 ).

[0093] like Figure 14-15As shown, layout 1400 includes a pattern 1410 (referred to herein as "FTV 1410") configured to form an FTV structure. FTV 1410 may extend parallel to and between active areas 702 and 704. FTV 1410 may be different from VB 786 / 788. For example, FTV 1410 may extend completely through the substrate, while VB 786 / 788 may extend partially into the substrate to connect to the back side of the epitaxial structure, wherein the lower portion is formed in the substrate. In such an embodiment where the FTV structure is formed between the active areas, a plurality of MDs (formed by corresponding patterns 1412, 1413, 1414, 1415, 1416, 1417, and 1418) may be formed on the front side of the substrate and electrically connected to FTV 1410. Furthermore, the layout 1400 may include a pattern 1420 configured to form an MD formed on the front side of the substrate and continuously extending across the active regions 702 and 704 .

[0094] Fig.16 , Fig.17 and Fig.18 It shows that according to some embodiments, Figure 7 1 and 1800. Figure 16-18 Each of the cross-sectional views shown in includes a plurality of cross sections of the corresponding semiconductor device, each cross section being taken parallel to the X direction. Figure 16-18 In each cross-sectional view, multiple structures parallel to each other can be shown simultaneously. Figure 7 Some of the reference numerals will be reused in the following discussion of the semiconductor devices 1600 to 1800 .

[0095] exist Fig.16 In the embodiment, the semiconductor device 1600 includes an M2 track 1610 and an M4 track 1620, which are respectively operable to function as the fuse resistor 210 and the fuse resistor 220. The M2 track 1610 and the M4 track 1620 each have one end connected to each other through the M3 track 780, and the M3 track 780 is operable to function as a part of BLO. Fig.17 In the embodiment, the semiconductor device 1700 includes a first M4 track 1710 and a second M4 track 1720, which are respectively operable to function as the fuse resistor 210 and the fuse resistor 220. The M4 track 1710 and the M4 track 1720 each have one end connected to each other through the M3 track 780, and the M3 track 780 is operable to function as a part of the BLO. Fig.18, the semiconductor device 1800 includes a first BM0 track 1810 and a second BM0 track 1820, which are respectively operable to function as the fuse resistor 210 and the fuse resistor 220. The BM0 track 1810 and the BM0 track 1820 each have one end connected to each other through a BM1 track 1830, which is operable to function as a portion of BL0.

[0096] Fig.19 According to some embodiments, Fig.11 A cross-sectional view of a semiconductor device 1900 formed by the layout 1100. It should be noted that Fig.19 The cross-sectional view shown in FIG. 1 includes multiple cross sections of the semiconductor device 1900, each cross section being taken parallel to the X direction. Fig.19 In the cross-sectional view, multiple structures parallel to each other (for example, 762 and 763, 764 and 765, etc.) can be shown simultaneously. Fig.11 Some of the reference numbers will be reused in the following discussion of the semiconductor device 1900 .

[0097] As shown, in active region 1102, multiple channels and epitaxial structures may be formed. Each of the channels may be covered or wrapped by a corresponding one of the gate structures (e.g., 1106, 1110, 1110, 1118), and each of the epitaxial structures may be covered by a corresponding one of the MDs (e.g., 1122, 1126, 1130, 1134, 1138). As described above, at least some corresponding portions of CG transistors 330-340 and WL transistor 350 may be formed by active region 1102 and gate structures 1106, 1110, 1114, 1118. In addition, gate structure 1106 may be used as part of CG0, gate structures 1110 and 1114 may each be used as part of WL1, and gate structure 1118 may be used as part of CG1. Therefore, each of gate structures 1106, 1110, 1114, 1118 may be coupled to one or more metal tracks formed thereon.

[0098] For example, gate structure 1106 is coupled to M0 rail 1143, and gate structure 1118 is coupled to M0 rail 1145. Similarly, MD 1122, together with at least M0 rail 1142 and M1 rail 1154, can couple one of the source / drain terminals (e.g., an epitaxial structure) of CG transistor 330 to one end of M2 rail 1158 used as fuse resistor 310; and MD 1138, together with at least M0 rail 1150 and M1 rail 1156, can couple one of the source / drain terminals (e.g., an epitaxial structure) of CG transistor 340 to one end of M2 rail 1160 used as fuse resistor 320. Additionally, M0 rail 1146 may couple MD 1126 to MD 1134, wherein MD 1126 is commonly connected to source / drain terminals of CG transistor 330 and WL transistor 350, and MD 1134 is commonly connected to source / drain terminals of CG transistor 340 and WL transistor 350. The other end of M2 rail 1158 is coupled to M3 rail 1162, which serves as part of BL0; and the other end of M2 rail 1160 is coupled to M3 rail 1162 (part of BL0).

[0099] In addition, a BM0 track 1182 is formed on a second (e.g., back) side of the substrate opposite to the first (e.g., front) side of the substrate on which transistors 330 to 350 are formed. As shown, the BM0 track 1182 is coupled to the source / drain terminal (e.g., epitaxial structure) of the WL transistor 350 through VB 1186. Such a source / drain terminal can have its front and back sides connected to MD 1130 and VB 1186, respectively. On the BM0 layer (when the substrate is turned upside down), multiple additional backside metallization layers, such as BM1...BMz, can be formed. Each backside metallization layer can include one or more metal tracks similar to the BM0 track 1182.

[0100] Fig. 20 A flowchart of an example method 2000 for generating a physical unclonable function (PUF) signature based on an electric fuse memory cell including a fuse resistor pair and a plurality of CG / WL transistors according to various embodiments is shown. The operations of the method 2000 are at least Figure 1-Figure 6 For the purpose of discussion, we will combine Figure 1-Figure 6 The following embodiments of method 2000 are described. The illustrated embodiments of method 2000 are merely examples, such that any of the various operations may be omitted, reordered, and / or added while remaining within the scope of the present disclosure.

[0101] Method 2000 may begin with operation 2002 of a programming process. In some embodiments, operation 2002 may include operation 2004 in which a column is selected, operation 2006 in which a row is selected, and operation 2008 in which a programming voltage is applied to the BL of the selected column. It should be noted that the order of operations 2004 to 2008 may be changed while remaining within the scope of the present disclosure. For example, operations 2004 and 2006 may be switched.

[0102] Referring first to operation 2004, control logic circuit 112 may provide a column address to column decoder 106 to select one of columns C1 to CN of memory array 102. In some embodiments, the column address used during programming may not specify which CG line is to be selected. In other words, column decoder 106 may assert both the CG line and the BL of the selected column. When selecting a column, I / O circuit 108 may provide a voltage (e.g., corresponding to a logic high state when the CG transistor is an n-type transistor) to each of the CG lines arranged in the selected column, e.g., Figure 2 Thus, CG transistors 230 and 240 can be turned on.

[0103] Next, in operation 2006, control logic circuit 112 may provide a row address to row decoder 104 to select one of rows R1 to RM of memory array 102. In some embodiments, the row address may specify which WL is to be selected. When selecting a row, I / O circuit 108 may provide a WL (e.g., Figure 2 The WL0 of the selected column and row can be programmed by providing a voltage (e.g., corresponding to a logic high state when the WL transistor is an n-type transistor). In this way, the WL transistors 250 and 260 can be turned on. In this way, the memory cell (e.g., 103A) arranged at the intersection of the selected column and row can be programmed.

[0104] Next, in operation 2008, a programming voltage is applied to the BL of the selected column, for example, Figure 2 By turning on the CG transistors 230-240 and the WL transistors 250-260, two conduction paths can be formed, one of which extends from BL0, passes through the fuse resistor 210, the CG transistor 230 and the WL transistor 250 and is grounded, and the other conduction path extends from BL0, passes through the fuse resistor 220, the CG transistor 240 and the WL transistor 260 and is grounded. In this way, the programming voltage applied to BL0 can randomly blow one of the fuse resistors 210 or 220.

[0105] Next, the method 2000 may proceed to operation 2010 to determine whether one of the fuse resistors of the selected memory cell has been blown (i.e., programmed). If so, the method 2000 may proceed to operation 2012, which includes one or more read processes; if not, the method 2000 may return to operation 2002 to perform the programming process again. In various embodiments, as described above, the I / O circuit 108 may determine whether one of the fuse resistors has been blown based on detecting a voltage drop present on the selected BL (e.g., BL0).

[0106] In some embodiments, operation 2012 may include operation 2014 in which a column is selected, operation 2016 in which a row is selected, and operation 2018 in which a read voltage is applied to the BL of the selected column. It should be noted that the order of operations 2014 to 2018 may be changed while remaining within the scope of the present disclosure. For example, operations 2014 and 2016 may be switched.

[0107] Referring first to operation 2014, control logic circuit 112 may provide a column address to column decoder 106 to select one of columns C1 to CN of memory array 102. In some embodiments, the column address used during a read process may specify which CG lines are to be selected. In other words, column decoder 106 may assert only one of the CG line and BL of the selected column. When selecting a column, I / O circuit 108 may assert the CG lines (e.g., Figure 2 The CG0 of the CG transistor 230 can provide a voltage (for example, corresponding to a logic high state when the CG transistor is an n-type transistor). In this way, the CG transistor 230 can be turned on, while the other CG transistor 240 can be turned off.

[0108] Next, in operation 2016, control logic circuit 112 may provide a row address to row decoder 104 to select one of rows R1 to RM of memory array 102. In some embodiments, the row address may specify which WL to select. When selecting a row, I / O circuit 108 may provide a row address to the WLs (e.g., Figure 2 The WL0 of the selected column and row can be provided with a voltage (e.g., corresponding to a logic high state when the WL transistor is an n-type transistor). In this way, the WL transistors 250 and 260 can be turned on. In this way, the memory cell (e.g., 103A) arranged at the intersection of the selected column and row can be read.

[0109] Next, in operation 2018, a read voltage is applied to the BL of the selected column, for example, Figure 2BL0. By turning on CG transistor 230 and WL transistors 250-260, a conduction path extending from BL0, through fuse resistor 210, CG transistor 230, WL transistor 250 and to ground may become available, depending on whether fuse resistor 210 has been randomly blown. For example, if fuse resistor 210 remains intact (unblown), a read voltage applied to BL0 may generate a current flowing through the conduction path. In other words, a short circuit is formed (or maintained) from BL0 through fuse resistor 210, CG transistor 230 and WL transistor 250 to ground. On the other hand, if fuse resistor 210 has been blown, no current is generated. In other words, an open circuit is formed between BL0 and ground.

[0110] The method 2000 may continue to operation 2020, where a logic state programmed into the memory cell is determined, and a bit of a PUF signature is generated based on the determined logic state. For example, the control logic circuit 112 may determine the logic state programmed into the memory cell 103A based on the read process 2012, for example, whether a current is present on BL0. If a current or a sufficiently high current level is detected (e.g., by the I / O circuit 108), the control logic circuit 112 may determine that the memory cell 103A (or, specifically, the fuse resistor connected to the selected CG transistor) is not blown, and thus the programming logic state is determined to be a logic 0. If no current is detected or a sufficiently low current level is detected (e.g., by the I / O circuit 108), the control logic circuit 112 may determine that the memory cell 103A (or, specifically, the fuse resistor connected to the selected CG transistor) has been blown, and thus the programming logic state is determined to be a logic 1. Next, the control logic circuit 112 may provide the determined logic state to the authentication circuit 110 to generate a PUF bit. Since the logic state is randomly determined based on the process variation of a pair of fuse resistors, the logic state (ie, PUF bit) can be randomly generated, which advantageously increases the security of the memory system 100 .

[0111] Fig.21 An example schematic diagram 2100 of a portion of a memory device 100 (eg, some memory cells 103) according to some embodiments is shown. Fig.21 In the example shown, electrical fuse memory cells 103A, 103B, 103C, and 103D of the memory array 102 are shown. Figure 2 ) and 300( Figure 3), each of the e-fuse memory cells 103A-103D includes two fuse capacitors. Although four e-fuse memory cells 103A-103D are shown, it should be understood that the memory array 102 can have any number of similar e-fuse memory cells while remaining within the scope of the present disclosure.

[0112] Since schematic 2100 is similar to schematic 300 except for the fuse assembly, the following discussion will focus on the differences. Fig.21 In the illustrative embodiment of the present invention, the electric fuse memory cells 103 (e.g., 103A) may each include a first fuse capacitor 2110, a second fuse capacitor 2120, a first CG transistor 2130, a second CG transistor 2140, and a common WL transistor 2150. First source / drain terminals of the first CG transistor 2130 and the second CG transistor 2140 are coupled to ground through the WL transistor 2150. Second source / drain terminals of the first CG transistor 2130 and the second CG transistor 2140 are coupled to BLO through the fuse capacitor 2110 and the fuse capacitor 2120, respectively.

[0113] Fig. 22 The semiconductor device (eg, Fig.13 1300 Fig.19 1900). For example, method 2200 may be performed to form a semiconductor device according to layout 700 or 1100. In one aspect, method 2200 includes operations for fabricating an electrical fuse memory cell composed of a plurality of CG transistors, one or more WL transistors, and a plurality of fuse resistors. It should be noted that method 2200 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 2200 may be performed in the embodiment of the present invention. Fig. 22 Additional operations are provided before, during, and after method 2200, and some other operations may be only briefly described herein.

[0114] According to various embodiments, method 2200 starts from operation 2202, in which a substrate is provided. The substrate includes a semiconductor material substrate, such as silicon. Alternatively, the substrate may include other elemental semiconductor materials, such as germanium. The substrate may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate includes an epitaxial layer. For example, the substrate may have an epitaxial layer covering a bulk semiconductor. In addition, the substrate may include a semiconductor on insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implantation of oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0115] Method 2200 proceeds to operation 2204, in which a stack comprising an alternating series of first and second nanostructures is formed according to various embodiments. Such a stack may be formed based on one of the (active region) patterns discussed above. The stack may be formed in the front side of the substrate. In some embodiments, the first nanostructure may include a SiGe sacrificial nanostructure, and the second nanostructure may include a Si channel nanostructure. Such a stack may sometimes be referred to as a superlattice. In a non-limiting example, the SiGe sacrificial nanostructure may be 25% SiGe. The symbol "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge. It should be understood that the percentage of Ge in each SiGe sacrificial nanostructure may be any value between 0 and 100 (excluding 0 and 100) while still within the scope of the present disclosure. In some other embodiments, the second nanostructure may include a first semiconductor material other than Si, and the first nanostructure may include a second semiconductor material other than SiGe, as long as the first and second semiconductor materials have different etching characteristics (e.g., etching rates), respectively.

[0116] The alternating series of nanostructures can be formed by epitaxially growing one layer and then the next layer until the desired number and desired thickness of nanostructures are obtained. The epitaxial material can be grown from gaseous or liquid precursors. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Epitaxial silicon, silicon germanium and / or carbon-doped silicon (Si:C) can be doped (in-situ doping) during deposition by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.

[0117] According to various embodiments, method 2200 proceeds to operation 2206, in which a plurality of dummy gate structures are formed. Such dummy gate structures may be formed based on one of the above-mentioned (gate structure) patterns. The dummy gate structures may extend in a direction perpendicular to the length direction of the dielectric fin structure (and stack). In addition, in one of the various embodiments, the dummy gate structure may be formed shorter than the dielectric fin structure, so that the formed dummy gate structure is cut (or otherwise separated) by the dielectric fin structure.

[0118] A pseudo gate structure can be formed by depositing amorphous silicon (a-Si) on the stack. Other materials suitable for forming a pseudo gate (e.g., polysilicon) can be used while remaining within the scope of the present disclosure. The a-Si is then flattened to a desired level. A hard mask is deposited on the flattened a-Si and patterned. The hard mask can be formed by a nitride layer or an oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form a pseudo gate structure. After forming the pseudo gate structure, a gate spacer can be formed to extend along the sidewall of the pseudo gate structure. The gate spacer can be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any appropriate combination of these materials) followed by directional etching (e.g., RIE).

[0119] Method 2200 proceeds to operation 2208, in which, according to various embodiments, internal spacers are formed by replacing the ends of each SiGe sacrificial nanostructure with a dielectric material. When forming a pseudo gate structure that covers certain portions of the stack (e.g., portions of the stack separated by a dielectric fin structure), the uncovered portions of the stack are removed. Next, the corresponding ends of each SiGe sacrificial nanostructure covering the stack are removed. The internal spacers are formed by filling these recesses of each SiGe sacrificial nanostructure with a dielectric material by chemical vapor deposition (CVD), or by single-layer doping (MLD) of nitride followed by spacer RIE. The material of the internal spacer can be formed of the same or different material as the gate spacer described above. For example, the internal spacer can be formed of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxycarbonitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5).

[0120] According to various embodiments, method 2200 proceeds to operation 2210, in which a plurality of epitaxial structures are formed. When forming the internal spacers, an epitaxial structure is formed on the exposed end of the Si nanostructure using an epitaxial layer growth process. In-situ doping (ISD) can be applied to form the doped epitaxial structure to create the necessary junctions for the corresponding transistors (or sub-transistors). N-type and P-type FETs are formed by injecting different types of dopants into selected areas of the device to form the necessary junctions. N-type devices can be formed by injecting arsenic (As) or phosphorus (P), and P-type devices can be formed by injecting boron (B). After the epitaxial structure is formed, an interlayer dielectric (e.g., silicon dioxide) is deposited to cover the epitaxial structure.

[0121] According to various embodiments, method 2200 proceeds to operation 2212, where the dummy gate structure and the remaining SiGe sacrificial nanostructure are replaced with a corresponding active gate structure. After forming the interlayer dielectric, the dummy gate structure is removed by an etching process (e.g., RIE or chemical oxide removal (COR)). Next, the remaining SiGe sacrificial nanostructure is removed while keeping the Si channel nanostructure substantially intact by applying selective etching (e.g., hydrochloric acid (HCl)). After removing the SiGe sacrificial nanostructure, the top surface, bottom surface, and sidewalls of each Si channel nanostructure can be exposed, except for the sidewalls that contact the dielectric fin structure. Next, multiple active gate structures can be formed to wrap each Si channel nanostructure, except for the sidewalls that contact the dielectric fin structure. Each active gate structure includes at least a gate dielectric layer (e.g., a high-k dielectric layer) and a gate metal layer (e.g., a work function metal layer). After forming the active gate structure, at least two CG transistors (eg, 230 and 240, 330 and 340) and one WL transistor (250 and 260, 350) of the disclosed e-fuse memory cell may be formed.

[0122] The method 2200 proceeds to operation 2214, in which a plurality of front-side interconnect structures are formed to implement an electric fuse memory cell capable of generating a PUF bit according to various embodiments. When forming the CG / WL transistor, a plurality of intermediate-end interconnect structures (e.g., VG, VD, MD) are formed above the transistor. For example, a plurality of VGs may be formed to be connected to the gate terminals of the CG transistor and the WL transistor, respectively, and a plurality of MDs may be formed to be connected to the source / drain terminals of the CG transistor and the WL transistor, respectively. In addition, a plurality of back-end metal tracks (e.g., M0 tracks, M1 tracks, M2 tracks, etc.) may be formed above the intermediate-end interconnect structures. In some embodiments, the fuse resistors (e.g., 210 and 220, 310 and 320) of the disclosed electric fuse memory cell may each be formed as one of these back-end metal tracks.

[0123] The front-side interconnect structure is formed of a metal material. The metal material may be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front-side interconnect structure may be formed by covering the front side of the substrate with the above metal material, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating, or a combination thereof.

[0124] In some embodiments, the components formed by operations 2202 to 2214 may be formed according to layout 700 ( Figure 7) are arranged to form one of the disclosed electric fuse memory cells, which can be operative to generate a PUF bit. For example, through operation 2204, two stacks corresponding to active areas 702 and 704, respectively, can be formed; through operations 2206 and 2212, multiple gate structures corresponding to gate structures 706 to 728, respectively, can be formed; and through operation 2210, multiple source / drain structures can be formed. In this way, transistors 230 to 260 (e.g., of the electric fuse memory cell 103C) can be formed. After forming the transistors, through operation 2214, fuse resistors 210 and 220 corresponding to metal tracks 774 and 776, respectively, and other metal tracks (e.g., 780) connecting transistors 230 to 260 to each other can be formed. For example, the respective gate terminals of transistors 250 and 260 are commonly connected to the same WL1. In another example, the gate terminals of transistors 230 and 240 are connected to CG0 and CG1, respectively. In yet another example, respective ends of the metal tracks 774 and 776 are connected to each other by a metal track 780 corresponding to BL0.

[0125] In some embodiments, the components formed by operations 2202 to 2214 may be formed according to layout 1100 ( Fig.11 ) are arranged to form one of the disclosed electric fuse memory cells, which can be operative to generate a PUF bit. For example, through operation 2204, two stacks corresponding to active areas 1102 and 1104, respectively, can be formed; through operations 2206 and 2212, multiple gate structures corresponding to gate structures 1106 to 1120, respectively, can be formed; and through operation 2210, multiple source / drain structures can be formed. In this way, transistors 330 to 350 (e.g., of the electric fuse memory cell 103C) can be formed. After forming the transistors, through operation 2214, fuse resistors 310 and 320 corresponding to metal tracks 1158 and 1160, respectively, and other metal tracks (e.g., 1162) connecting transistors 330 to 350 to each other can be formed. For example, the gate terminal of transistor 350 is connected to WL1. In another example, the gate terminals of transistors 330 and 340 are connected to CG0 and CG1, respectively. In yet another example, respective ends of the metal tracks 1158 and 1160 are connected to each other through a metal track 1162 corresponding to BL0.

[0126] The method 2200 proceeds to operation 2216, in which a plurality of backside interconnect structures are formed to implement power rails of the e-fuse memory cell according to various embodiments. After forming the frontside interconnect structures, the substrate may be flipped, and a plurality of backside interconnect structures (e.g., BM0 rail, BM1 rail, VB, FTV, etc.) may be formed. In some embodiments, the disclosed e-fuse memory cell may include at least one power rail (e.g., 782, 1182) formed as one of these backside interconnect structures.

[0127] The backside interconnect structure is formed of a metal material. The metal material can be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and combinations thereof. Other metal materials are also within the scope of the present disclosure. The backside interconnect structure can be formed by covering the back side of the substrate with the above metal material by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating or a combination thereof.

[0128] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes an array, the array including a plurality of one-time programmable (OTP) memory cells; a plurality of word lines (WL); a plurality of bit lines (BL); and a plurality of control gate (CG) lines. Each OTP memory cell includes a first fuse resistor, a second fuse resistor, a first transistor, and a second transistor. The first fuse resistor and the second fuse resistor are coupled to corresponding ones of the BLs, and the first transistor and the second transistor are respectively selected by the first CG line and the second CG line of the CG lines.

[0129] In some embodiments, the OTP memory cells are arranged over a plurality of columns and a plurality of rows, each row including a corresponding WL, and each column including a corresponding BL and a pair of corresponding CG lines.

[0130] In some embodiments, each OTP memory cell further includes a third transistor and a fourth transistor, and wherein the third transistor and the fourth transistor are commonly gated by a corresponding one WL.

[0131] In some embodiments, the first fuse resistor, the first transistor and the third transistor are connected in series between the corresponding BL and a power rail carrying a power supply voltage, and wherein the second fuse resistor, the second transistor and the fourth transistor are connected in series between the corresponding BL and the power rail.

[0132] In some embodiments, the first to fourth transistors are formed along a front side surface of the substrate, the first and second fuse resistors are formed in one of a plurality of metallization layers above the front side surface, and a power rail is formed above a back side surface of the substrate.

[0133] In some embodiments, each OTP memory cell further includes a third transistor, and wherein the third transistor is gated by a corresponding one of the WLs.

[0134] In some embodiments, the first fuse resistor, the first transistor and the third transistor are connected in series between the corresponding BL and a power rail carrying a power supply voltage, and wherein the second fuse resistor, the second transistor and the third transistor are also connected in series between the corresponding BL and the power rail.

[0135] In some embodiments, the first to third transistors are formed along a front side surface of the substrate, the first and second fuse resistors are formed in one of a plurality of metallization layers above the front side surface, and a power rail is formed above a back side surface of the substrate.

[0136] In some embodiments, each OTP memory cell is configured to permanently assume a logic state based on whether the first fuse resistor or the second fuse resistor is randomly blown.

[0137] In some embodiments, the logic state is identified based on enabling one of the first transistor or the second transistor.

[0138] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell, the memory cell including: a first fuse resistor; a second fuse resistor; a first transistor connected in series to the first fuse resistor; and a second transistor connected in series to the second fuse resistor. The memory cell is configured to randomly present a first logic state when the first fuse resistor is blown, or to randomly present a second logic state when the second fuse resistor is blown.

[0139] In some embodiments, the first logic state or the second logic state is used as a bit of a Physical Unclonable Function (PUF) signature.

[0140] In some embodiments, the memory cell further includes: a third transistor serially connected to the first transistor; and a fourth transistor serially connected to the second transistor.

[0141] In some embodiments, when programming the memory cell to randomly blow the first fuse resistor or the second fuse resistor, the third transistor and the fourth transistor are enabled simultaneously, and the first transistor and the second transistor are enabled simultaneously.

[0142] In some embodiments, when the memory cell is read to identify the first logic state or the second logic state, the third transistor and the fourth transistor are enabled simultaneously, and only one of the first transistor or the second transistor is enabled.

[0143] In some embodiments, the memory cell further includes a third transistor connected in series to each of the first transistor and the second transistor.

[0144] In some embodiments, when programming the memory cell to randomly blow the first fuse resistor or the second fuse resistor, the third transistor is enabled and the first transistor and the second transistor are enabled at the same time.

[0145] In some embodiments, when the memory cell is read to identify the first logic state or the second logic state, the third transistor is enabled and only one of the first transistor or the second transistor is enabled.

[0146] In yet another aspect of the present disclosure, a method for forming a memory device is disclosed. The method includes forming at least a first transistor, a second transistor, and a third transistor on a first side of a substrate. The method includes forming a first fuse resistor and a second fuse resistor in one of a plurality of first metallization layers, the plurality of first metallization layers being disposed above the first transistor to the third transistor on the first side. The method includes forming a power rail in one of a plurality of second metallization layers, the plurality of second metallization layers being disposed on a second side of the substrate opposite to the first side.

[0147] In some embodiments, the first to third transistors, the first to second fuse resistors, and the power rail together form an electric fuse memory cell, which is configured to generate bits of a physical unclonable function (PUF) signature based on whether the first fuse resistor or the second fuse resistor has been blown.

[0148] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0149] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: an array comprising a plurality of one-time programmable memory cells; multiple word lines; a plurality of bit lines; as well as a plurality of control gate lines; Each of the one-time programmable memory cells comprises a first fuse resistor, a second fuse resistor, a first transistor and a second transistor; and The first fuse resistor and the second fuse resistor are coupled to a corresponding one of the bit lines, and the first transistor and the second transistor are respectively selected by a first control gate line and a second control gate line of the control gate lines.

2. The memory device according to claim 1, wherein: The one-time programmable memory cells are arranged over a plurality of columns and a plurality of rows, each of the rows includes a corresponding one of the word lines, and each of the columns includes a pair of a corresponding one of the bit lines and a corresponding one of the control gate lines.

3. The memory device according to claim 1, wherein: Each of the one-time programmable memory cells further includes a third transistor and a fourth transistor, and wherein the third transistor and the fourth transistor are commonly gated by a corresponding one of the word lines.

4. The memory device according to claim 3, wherein: The first fuse resistor, the first transistor and the third transistor are connected in series between a corresponding bit line and a power rail carrying a power supply voltage, and wherein the second fuse resistor, the second transistor and the fourth transistor are connected in series between the corresponding bit line and the power rail.

5. The memory device according to claim 4, wherein: The first to fourth transistors are formed along a front side surface of a substrate, the first and second fuse resistors are formed in one of a plurality of metallization layers over the front side surface, and the power rail is formed over a back side surface of the substrate.

6. The memory device according to claim 1, wherein: Each of the one-time programmable memory cells further includes a third transistor, and wherein the third transistor is gated by a corresponding one of the word lines.

7. A memory device comprising: A memory unit, the memory unit comprising: a first fuse resistor; a second fuse resistor; a first transistor connected in series to the first fuse resistor; and a second transistor connected in series to the second fuse resistor; The memory cell is configured to randomly present a first logic state when the first fuse resistor is blown, or to randomly present a second logic state when the second fuse resistor is blown.

8. The memory device according to claim 7, wherein: The memory unit further comprises: a third transistor connected in series to the first transistor; and A fourth transistor is serially connected to the second transistor.

9. The memory device according to claim 8, wherein: When the memory cell is programmed to randomly blow the first fuse resistor or the second fuse resistor, the third transistor and the fourth transistor are enabled at the same time, and the first transistor and the second transistor are enabled at the same time.

10. A method of forming a memory device, comprising: forming at least a first transistor, a second transistor, and a third transistor on a first side of a substrate; forming a first fuse resistor and a second fuse resistor in one of a plurality of first metallization layers disposed over the first to third transistors on the first side; as well as A power rail is formed in a second metallization layer of a plurality of second metallization layers disposed on a second side of the substrate opposite the first side.

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