Antifuse unit, antifuse array structure, programming method and reading method

Abstract

The present application relates to an antifuse unit, an antifuse array structure, a programming method, and a reading method. The antifuse unit includes: a select transistor having a gate connected to a word line and one of a source and a drain connected to a bit line; a first antifuse device having one end connected to the other of the source and drain of the select transistor and the other end connected to a programming conductor; and a second antifuse device having one end connected to the same bit line as the select transistor and the other end connected to the same programming conductor as the first antifuse device. Embodiments of the present application facilitate effectively improving storage density.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an anti-fuse unit, an anti-fuse array structure, a programming method, and a reading method. Background Art

[0002] With the development of semiconductor technology, antifuse memory technology has emerged. Traditional antifuse cells typically consist of a select transistor and an antifuse transistor. The select transistor and the antifuse transistor share a common doped region (source or drain), allowing programming by breaking down the gate oxide beneath the antifuse transistor's gate when the select transistor is turned on.

[0003] However, this conventional anti-fuse unit has a problem of low storage density. Summary of the Invention

[0004] Based on this, embodiments of the present application provide an anti-fuse unit, an anti-fuse array structure, a programming method, and a reading method.

[0005] An antifuse unit, comprising:

[0006] A selection transistor, wherein the gate is connected to a word line, and one of the source and the drain is connected to a bit line;

[0007] a first anti-fuse device, one end of which is connected to the other of the source and the drain of the selection transistor, and the other end of which is used to connect to the programming wire;

[0008] The second anti-fuse device has one end connected to the same bit line as the selection transistor, and the other end connected to the same programming conductor as the first anti-fuse device.

[0009] In one embodiment,

[0010] The selection transistor includes a first doping region and a second doping region, one of the first doping region and the second doping region serves as a source of the selection transistor, and the other serves as a drain of the selection transistor, and the first doping region is used to connect to a bit line;

[0011] The first anti-fuse device is a transistor-type anti-fuse device, and the first anti-fuse device and the selection transistor are formed based on the same active region and share the second doped region with the selection transistor, and the gate of the first anti-fuse device is connected to the programming wire;

[0012] The second anti-fuse device includes a first capacitor electrode and a second capacitor electrode that are arranged opposite to each other. The first capacitor electrode is used to connect to the bit line, and the second capacitor electrode is used to connect to the programming wire.

[0013] In one embodiment, the first capacitor electrode and the second capacitor electrode are disposed in the same layer.

[0014] An antifuse array structure includes a plurality of antifuse unit groups, word lines, programming conductors, and bit lines. The plurality of antifuse unit groups are arranged in an array, and each antifuse unit group includes at least one antifuse unit.

[0015] Wherein, the anti-fuse unit includes:

[0016] A selection transistor having a gate connected to a word line and one of a source and a drain connected to a bit line;

[0017] A first anti-fuse device has one end connected to the other of the source and the drain of the selection transistor and the other end connected to the programming wire.

[0018] A second anti-fuse device has one end connected to the same bit line as the selection transistor, and the other end connected to the same programming conductive line as the first anti-fuse device.

[0019] In one embodiment,

[0020] The antifuse array structure includes a substrate, the substrate includes a substrate and a shallow trench isolation structure, the shallow trench isolation structure separates the substrate into a plurality of active areas,

[0021] The plurality of antifuse unit groups are arranged in an array on the substrate, and the antifuse units in the same antifuse unit group are formed based on the same active region.

[0022] In the anti-fuse unit, the selection transistor includes a first doped region and a second doped region, one of the first doped region and the second doped region serves as a source of the selection transistor, and the other serves as a drain of the selection transistor, and the first doped region is connected to the bit line through a first conductive plug;

[0023] The first anti-fuse device is a transistor-type anti-fuse device, and the first anti-fuse device and the selection transistor are formed based on the same active region and share the second doped region with the selection transistor, and the gate of the first anti-fuse device is connected to the programming wire;

[0024] The second anti-fuse device includes a first capacitor electrode and a second capacitor electrode that are oppositely arranged. The first capacitor electrode is connected to the bit line, and the second capacitor electrode is connected to the programming wire of the first anti-fuse device.

[0025] In one embodiment, the first capacitor electrode and the second capacitor electrode are disposed in the same layer.

[0026] In one embodiment,

[0027] The antifuse array structure includes a first conductive layer and a second conductive layer, the first conductive layer includes the word line and the programming wire, and the second conductive layer includes the bit line;

[0028] The first capacitor electrode and the second capacitor electrode are located in the second conductive layer, and the second capacitor electrode is connected to the programming wire through a second conductive plug.

[0029] In one embodiment, the bit line is multiplexed as the first capacitor electrode.

[0030] In one embodiment,

[0031] The antifuse array structure includes a second conductive layer, wherein the second conductive layer includes a bit line,

[0032] The bit line and the active area are at least partially staggered. The second conductive layer further includes a bit line connecting portion connected to the bit line and opposite to the first doped area.

[0033] In one embodiment, the anti-fuse unit group includes at least two anti-fuse units, and the same anti-fuse unit group includes adjacent anti-fuse units that share the same first conductive plug.

[0034] In one embodiment,

[0035] In the arrangement array of the antifuse unit group, the row direction is a first direction, the column direction is a second direction, and the second direction intersects the first direction.

[0036] The bit line and the active area both extend along the first direction,

[0037] The anti-fuse units in the same row are connected to the same bit line.

[0038] In one embodiment, in the antifuse array structure, every two rows of antifuse units form an antifuse row group, and two bit lines connected to each antifuse row group are located on opposite sides of the antifuse row group in the second direction.

[0039] In one embodiment,

[0040] In the arrangement array of the antifuse unit group, the row direction is a first direction, the column direction is a second direction, and the second direction intersects the first direction.

[0041] The bit line and the active area both extend along the first direction, and the bit line and the active area are staggered.

[0042] In the anti-fuse units located in the same row, the anti-fuse units formed on adjacent active regions are respectively connected to different bit lines located on both sides of the anti-fuse unit.

[0043] In one embodiment,

[0044] In the arrangement array of the antifuse unit group, the row direction is a first direction, the column direction is a second direction, and the second direction intersects the first direction.

[0045] The word lines and the programming wires both extend along the second direction,

[0046] The anti-fuse units in the same column are connected to the same word line, and the anti-fuse units in the same column are connected to the same programming wire. In the first direction, the word line and the programming wire connected to the anti-fuse units in the same column are respectively located on both sides of the anti-fuse units.

[0047] A programming method, applied to the antifuse array structure as described in any one of the above, comprising:

[0048] Obtaining a target anti-fuse unit to be programmed in the anti-fuse array structure, and obtaining a target word line, a target programming conductor, and a target bit line corresponding to the target anti-fuse unit;

[0049] Applying an on voltage to the target word line and an off voltage to the other word lines, applying a first programming voltage to the target programming conductor and a zero voltage to the other programming conductors, and applying a zero voltage to the target bit line and a first intermediate voltage to the other bit lines, wherein the first intermediate voltage is equal to half of the first programming voltage, so as to write to the first anti-fuse device of the target anti-fuse cell;

[0050] A turn-off voltage is applied to the target word line and other word lines, and a second programming voltage is applied to the target programming wire, while a zero voltage is applied to other programming wires, and a zero voltage is applied to the target bit line, while a second intermediate voltage is applied to other bit lines, and the second intermediate voltage is equal to half of the second programming voltage, so as to program and write the second anti-fuse device of the target anti-fuse unit.

[0051] A reading method, applied to the antifuse array structure as described in any one of the above, comprising:

[0052] Obtaining a target anti-fuse unit to be programmed in the anti-fuse array structure, and obtaining a target word line, a target programming conductor, and a target bit line corresponding to the target anti-fuse unit;

[0053] Applying an on voltage to the target word line and an off voltage to the other word lines, applying a zero voltage to the target programming wire and the other programming wires, applying a read voltage to the target bit line and applying a zero voltage to the other bit lines, and reading a current flowing through the first anti-fuse device of the target anti-fuse unit to read the first anti-fuse device of the target anti-fuse unit;

[0054] A turn-off voltage is applied to the target word line and other word lines, and a zero voltage is applied to the target programming wire, while a read voltage is applied to other programming wires. A read voltage is applied to the target bit line, while a zero voltage is applied to other bit lines, and the current flowing through the second anti-fuse device of the target anti-fuse unit is read to read the second anti-fuse device of the target anti-fuse unit.

[0055] In the aforementioned antifuse cell and antifuse array structure, each antifuse cell includes a select transistor and two antifuse devices (a first antifuse device and a second antifuse device). In addition to conventional antifuse cells, a second antifuse device is provided. Furthermore, within the same antifuse cell, the second antifuse device and the first antifuse device are connected to the same programming conductor, and the second antifuse device and the select transistor are connected to the same bit line. This allows programming, writing, and reading of both antifuse devices within the same antifuse cell through the same programming and bit line, effectively improving storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0057] Figure 1 is a circuit diagram of an antifuse array structure provided in one embodiment;

[0058] Figure 2 is a schematic diagram of a partial top view of an antifuse array structure provided in one embodiment;

[0059] Figure 3 For the Figure 2 Schematic diagram of the screenshot structure in the aa' direction;

[0060] Figure 4 For the Figure 2 Schematic diagram of the screenshot structure in the bb' direction;

[0061] Figure 5A schematic diagram of a partial top view of an antifuse array structure provided in another embodiment;

[0062] Figure 6 For the Figure 5 Schematic diagram of the screenshot structure in the aa' direction;

[0063] Figure 7 For the Figure 5 Schematic diagram of the screenshot structure in the bb' direction;

[0064] Figure 8 is a schematic diagram of a partial top view of an antifuse array structure provided in yet another embodiment;

[0065] Figure 9 A schematic flow chart of a programming method provided in one embodiment;

[0066] Figure 10 Schematic diagram of a flow chart of a reading method provided in one embodiment.

[0067] Description of reference numerals:

[0068] 100 - antifuse unit, 100a - antifuse unit group, 100b - antifuse row group, 110 - selection transistor, 111 - first doped region, 112 - second doped region, 113 - gate dielectric layer, 120 - first antifuse device, 130 - second antifuse device, 131 - first capacitor electrode, 132 - second capacitor electrode, 200 - first conductive layer, 210 - word line, 220 - programming wire, 300 - second conductive layer, 310 - bit line, 320 - bit line connection portion, 400 - base, 410 - substrate, 411 - first conductivity type well region, 4111 - active region, 420 - shallow trench isolation structure, 510 - first conductive plug, 520 - second conductive plug, 600 - interlayer dielectric layer. DETAILED DESCRIPTION

[0069] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0071] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0072] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0073] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0074] In one embodiment, see Figure 1 , providing an antifuse array structure. The antifuse array structure includes a plurality of antifuse unit groups 100 a, word lines 210 , programming conductors 220 and bit lines 310 .

[0075] It is understandable that in Figure 1 In FIG. 1 , WLi represents the i+1th word line 210, AFi represents the i+1th programming conductive line 220, and BLj represents the j+1th bit line 310. i is a positive integer greater than or equal to 0 and less than or equal to n, and j is a positive integer greater than or equal to 0 and less than or equal to m.

[0076] A plurality of anti-fuse cell groups 100 a are arranged in an array. Each anti-fuse cell group 100 a includes at least one anti-fuse cell 100 . The anti-fuse cell 100 includes a selection transistor 110 , a first anti-fuse device 120 , and a second anti-fuse device 130 .

[0077] In the anti-fuse cell 100, the gate of the select transistor 110 is connected to the word line 210, and one of the source and drain is connected to the bit line 310. The first anti-fuse device 120 has one end connected to the other of the source and drain of the select transistor 110, and the other end connected to the programming conductor 220. The second anti-fuse device 130 has one end connected to the same bit line 310 as the select transistor 110, and the other end connected to the same programming conductor 220 as the first anti-fuse device 120.

[0078] Different voltage differences can be formed between the programming conductive line 220 and the bit line 310, thereby programming the first anti-fuse device 120 and the second anti-fuse device 130. When the select transistor 110 is turned on, a first voltage difference can be formed between the programming conductive line 220 and the bit line 310, thereby programming the first anti-fuse device 120; and when the select transistor 110 is turned off, a second voltage difference can be formed between the programming conductive line 220 and the bit line 310, thereby programming the second anti-fuse device 130.

[0079] In this embodiment, an anti-fuse cell 100 includes a select transistor 110 and two anti-fuse devices (a first anti-fuse device 120 and a second anti-fuse device 130). Compared to conventional anti-fuse cells, the second anti-fuse device 130 is additionally provided. Furthermore, within the anti-fuse cell 100, the second anti-fuse device 130 and the first anti-fuse device 120 are connected to the same programming conductive line 220, and the second anti-fuse device 130 and the select transistor 110 are connected to the same bit line 310. This allows programming, writing, and reading of both anti-fuse devices within the same anti-fuse cell via the same programming conductive line 220 and bit line 310, thereby effectively improving storage density.

[0080] In one embodiment, see Figures 2 to 4 , the antifuse array structure includes a substrate 400 .

[0081] It should be noted that in order to make the figure clear, Figure 2The first doped region 111 , the second doped region 112 and the shallow trench isolation structure 420 are not shown in the figure, and the second conductive layer 300 is made transparent.

[0082] The base 400 includes a substrate 410 and a shallow trench isolation structure 420 . The shallow trench isolation structure 420 separates the substrate 410 into a plurality of active regions 4111 .

[0083] The substrate 410 may include, for example, a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 410 may include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate.

[0084] As an example, a first conductivity type well region 411 can be formed on the substrate 410 by doping. A shallow trench isolation structure 420 can be formed in the first conductivity type well region 411. The shallow trench isolation structure 420 can isolate a plurality of spaced active regions 4111 in the first conductivity type well region 411, thereby dividing the substrate 410 into the plurality of active regions 4111.

[0085] A plurality of antifuse unit groups 100 a of the antifuse array structure are arranged in an array on a substrate 400 .

[0086] The antifuse cell group 100a may include at least one antifuse cell 100 formed based on the same active region 4111 on the substrate 400. That is, the antifuse cells 100 in the same antifuse cell group 100a may be formed based on the same active region 4111.

[0087] In the anti-fuse cell 100 , the gate of the select transistor 110 is connected to a word line 210 . The same word line 210 can serve as a common gate of multiple select transistors 110 .

[0088] Meanwhile, the selection transistor 110 includes a first doping region 111 and a second doping region 112. The first doping region 111 and the second doping region 112 can be formed by doping the active region 4111. The active region 4111 between the first doping region 111 and the second doping region 112 can form a channel region of the selection transistor 110.

[0089] One of the first doping region 111 and the second doping region 112 serves as a source of the selection transistor 110 , and the other serves as a drain of the selection transistor 110 . Furthermore, the first doping region 111 is connected to the bit line 310 through a first conductive plug 510 .

[0090] It is understood that the selection transistor 110 further includes a gate dielectric layer 113 located between its gate and the active region 4111. The gate dielectric layer 113 may include, for example, a gate oxide layer.

[0091] The first anti-fuse device 120 is a transistor-type anti-fuse device, which is formed based on the same active region 4111 as the selection transistor 110 . In addition, the first anti-fuse device 120 and the selection transistor 110 share the second doping region 112 .

[0092] Furthermore, the gate of the first anti-fuse device 120 is connected to the programming conductive line 220 . The same programming conductive line 220 can serve as a common gate of a plurality of first anti-fuse devices 120 .

[0093] The second anti-fuse device 130 includes a first capacitor electrode 131 and a second capacitor electrode 132 oppositely disposed. The first capacitor electrode 131 is connected to the bit line 310 , and the second capacitor electrode 132 is connected to the programming wire 220 of the first anti-fuse device 120 .

[0094] In this embodiment, the anti-fuse cells 100 in the same anti-fuse cell group 100 a may be formed based on the same active region 4111 , thereby facilitating the arrangement of the anti-fuse cell groups 100 a in an array.

[0095] In one embodiment, the first capacitor electrode 131 and the second capacitor electrode 132 of the second anti-fuse device 130 may be disposed in the same layer.

[0096] At this time, it is convenient to control the distance between the first capacitor electrode 131 and the second capacitor electrode 132 , thereby facilitating the control of the breakdown of the second anti-fuse device 130 .

[0097] Of course, in other embodiments, the first capacitor electrode 131 and the second capacitor electrode 132 of the second anti-fuse device 130 may also be provided in different layers, which is not limited here.

[0098] In one embodiment, please refer to Figures 2 to 4 The antifuse array structure includes a first conductive layer 200 and a second conductive layer 300 .

[0099] The first conductive layer 200 includes word lines 210 and programming conductive lines 220. As an example, the programming conductive lines 220 may be disposed in parallel with the word lines 210.

[0100] The material of the first conductive layer 200 may include, but is not limited to, polysilicon. For example, the material of the first conductive layer 200 may also include conductive materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0101] The second conductive layer 300 includes a bit line 310. The material of the second conductive layer 300 may include, but is not limited to, a metal material, such as Cu, Al, W, Co, Ni, and Ti.

[0102] The first capacitor electrode 131 and the second capacitor electrode 132 are located in the second conductive layer 300 , and the second capacitor electrode 132 is connected to the programming wire 220 through a second conductive plug 520 .

[0103] As an example, the first conductive layer 200 may be disposed between the substrate 400 and the second conductive layer 300. The antifuse array structure may further include an interlayer dielectric layer 600. The interlayer dielectric layer 600 may cover the first conductive layer 200. The second conductive layer 300 may be located on the interlayer dielectric layer 600. A first conductive plug 510 may be formed within the interlayer dielectric layer 600 to connect the bit line 310 to the first doped region 111 of the select transistor 110. A second conductive plug 520 may also be formed within the interlayer dielectric layer 600 to connect the second capacitor electrode 132 to the programming wire 220.

[0104] During the fabrication of the antifuse array structure, a gate dielectric layer 113 can be first formed on a substrate 400. A first conductive material layer can then be formed on the gate dielectric layer 113. The first conductive material layer can then be patterned to form a first conductive layer 200 comprising programming wires 220 and word lines 210. An interlayer dielectric layer 600 can then be formed on the surfaces of the programming wires 220, the word lines 210, and the remaining portion of the upper surface of the gate dielectric layer 113.

[0105] The interlayer dielectric layer 600 can be formed, for example, by a deposition process. The deposition process may include, but is not limited to, one or more of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), and a spin-on dielectric layer (SOD). The material of the interlayer dielectric layer 500 may include, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3), or a silicon oxynitride layer (SiON).

[0106] Then, a first contact hole and a second contact hole may be opened in the interlayer dielectric layer 600. The first contact hole extends to the first doped region 111. The second contact hole extends to the programming wire 220. Then, a first conductive plug 510 is filled in the first contact hole, and a second conductive plug 520 is filled in the second contact hole.

[0107] Afterwards, a second conductive material layer can be formed on the first conductive plug 510, the second conductive plug 520, and the interlayer dielectric layer 600. The second conductive material layer is then patterned to form a second conductive layer 300. The second conductive layer 300 includes a bit line 310, a first capacitor electrode 131, and a second capacitor electrode 132.

[0108] In this embodiment, the first capacitor electrode 131 and the second capacitor electrode 132 are provided in the second conductive layer 300, thereby forming the first capacitor electrode 131 and the second capacitor electrode 132 simultaneously with the bit line 310. This effectively simplifies the manufacturing process. Furthermore, the idle area of ​​the second conductive layer 300 can be effectively utilized, thereby facilitating the addition of the second anti-fuse device 130 within the anti-fuse unit 100 while occupying the same chip area as the anti-fuse unit, thereby effectively improving storage density.

[0109] In one embodiment, see Figures 5 to 7 , the bit line 310 is multiplexed as the first capacitor electrode 131 . That is, the first capacitor electrode 131 is a part of the bit line 310 .

[0110] It should be noted that in order to make the figure clear, Figure 5 The first doped region 111 , the second doped region 112 and the shallow trench isolation structure 420 are not shown in the figure, and the second conductive layer 300 is made transparent.

[0111] At this time, compared with the traditional process, only the second capacitor electrode 132 needs to be added to the second conductive layer 300, which makes it easier to design and prepare the second capacitor electrode 132 in the idle area of ​​the second conductive layer 300, thereby reducing the difficulty of designing and preparing the second anti-fuse device 130.

[0112] Of course, in other embodiments, the first capacitor electrode 131 may also be configured in other forms. For example, see Figure 2 Alternatively, a first capacitor electrode 131 disposed opposite to the second capacitor electrode 132 may be led out on the bit line 310 .

[0113] In one embodiment, see Figure 2 or Figure 5 The antifuse array structure includes a second conductive layer 300, which includes a bit line 310. The bit line 310 is at least partially offset from the active area 4111. That is, the bit line 310 can be completely offset from the active area 4111, or can be partially offset from the active area 111.

[0114] See also Figure 2When the bit line 310 is completely offset from the active area 4111, the orthographic projection of the bit line 310 on the substrate 400 does not overlap with the active area 4111. Figure 5 When the bit line 310 is partially offset from the active area 4111 , the orthographic projection of the bit line 310 on the substrate 400 intersects with the active area 4111 , but there is no overlap between the two.

[0115] In this case, parasitic capacitance between the bit line 310 and the active region 4111 can be effectively prevented or reduced, thereby improving device performance.

[0116] Meanwhile, the second conductive layer 300 includes not only the bit line 310 but also a bit line connecting portion 320 . The bit line connecting portion 320 is connected to the bit line 310 and is disposed opposite to the first doped region 111 .

[0117] At this time, since the bit line connection portion 320 is disposed opposite to the first doped region 111, it is convenient to dispose the first conductive plug 510 between the bit line connection portion 320 and the first doped region 111. At this time, the bit line 310, the bit line connection portion 320, the first conductive plug 510, and the first doped region 111 form a conductive circuit, thereby electrically connecting the bit line 310 and the first doped region 111.

[0118] By disposing the bit line connecting portion 320 , the bit line 310 and the active area 4111 can be completely offset, thereby better preventing parasitic capacitance from being generated between the bit line 310 and the active area 4111 .

[0119] Of course, in other embodiments, when the bit line 310 is partially offset from the active area 4111, the first conductive plug 510 may be formed directly between the bit line 310 and the first doped region 111. Alternatively, in some embodiments, the bit line 310 may not be offset from the active area 4111.

[0120] In one embodiment, see Figure 2 The anti-fuse unit group 100 a includes at least two anti-fuse units 100 . That is, at least two anti-fuse units 100 are formed based on the same active region 4111 .

[0121] The same anti-fuse unit group 100 a includes adjacent anti-fuse units 100 that share the same first conductive plug 510 .

[0122] In adjacent anti-fuse units 100 that share the same first conductive plug 510, each anti-fuse unit 100 may have a select transistor 110 located on a side close to the other anti-fuse unit 100, while the first anti-fuse device 120 is located on a side away from the other anti-fuse unit 100. In this case, the select transistors 110 of two adjacent first anti-fuse devices 120 may share the same first doped region 111, and thus the two adjacent first anti-fuse devices 120 may share the first conductive plug 510.

[0123] As an example, two anti-fuse units 100 are formed in each active region 4111 . The two anti-fuse units 100 formed in the same active region 4111 share one first conductive plug 510 .

[0124] In this embodiment, by disposing adjacent anti-fuse units 100 sharing the same first conductive plug 510 in the same anti-fuse unit group 100 a , the number of first conductive plugs 510 can be effectively reduced and the arrangement density of the anti-fuse units 100 can be increased.

[0125] Of course, in other embodiments, all anti-fuse units 100 may not share the first conductive plug 510 .

[0126] In one embodiment, see Figure 2 In the arrangement array of the anti-fuse unit group 100a, the row direction is the first direction. Meanwhile, in the arrangement array of the anti-fuse unit group 100a, the column direction is the second direction, and the second direction intersects with the first direction.

[0127] The bit lines 310 and the active regions 4111 extend along the first direction. The anti-fuse units 100 in the same row are connected to the same bit line 310. In this case, the density of the bit lines 310 can be effectively reduced.

[0128] In one embodiment, see Figure 2 In the antifuse array structure, every two rows of antifuse units 100 form an antifuse row group 100 b.

[0129] Each antifuse row group 100b includes two adjacent rows of antifuse cells 100. In the same antifuse row group 100b, the two rows of antifuse cells 100 are connected to two different bit lines 310. Therefore, each antifuse row group 100b is connected to two bit lines 310.

[0130] Meanwhile, the two bit lines 310 connected to each antifuse row group 100 b are respectively located on two opposite sides of the antifuse row group 100 b in the second direction.

[0131] At this time, it is convenient to form a memory module between two bit lines 310 through two rows of anti-fuse units 100 . For example, an 8-bit memory module is formed through two rows of anti-fuse units 100 .

[0132] Of course, in other embodiments, the bit lines 310 connected to the anti-fuse units 100 in each row may be located on the same side of the row where the anti-fuse units 100 are located.

[0133] In one embodiment, see Figure 8 In the arrangement array of the anti-fuse unit group 100a, the row direction is the first direction. Meanwhile, in the arrangement array of the anti-fuse unit group 100a, the column direction is the second direction, and the second direction intersects with the first direction.

[0134] The bit line 310 and the active area 4111 both extend along the first direction, and the bit line 310 and the active area 4111 are staggered.

[0135] Among the anti-fuse cells 100 located in the same row, the anti-fuse cells 100 formed on adjacent active regions 4111 are respectively connected to different bit lines 310 located on both sides of the active region 4111 .

[0136] As an example, two antifuse units 100 are formed in each active region 4111. The two antifuse units 100 formed in the same active region 4111 are connected to the same bit line 310 through the same first conductive plug 510. The antifuse units 100 formed in adjacent active regions 4111 in the same row are respectively connected to different bit lines 310 located on both sides of the antifuse unit 100.

[0137] It should be noted that in order to make the figure clear, Figure 8 The first doped region 111 , the second doped region 112 and the shallow trench isolation structure 420 are not shown in the figure, and the second conductive layer 300 is made transparent.

[0138] In this case, mutual interference between the anti-fuse units 100 formed on the same row and adjacent to each other in the active regions 4111 can be reduced.

[0139] In one embodiment, see Figure 1 In the arrangement array of the anti-fuse unit group 100a, the row direction is the first direction. Meanwhile, in the arrangement array of the anti-fuse unit group 100a, the column direction is the second direction, and the second direction intersects with the first direction.

[0140] The word lines 210 and programming conductors 220 extend along the second direction. Antifuse cells 100 in the same column are connected to the same word line 210, and the antifuse cells 100 in the same column are connected to the same programming conductor 220. Furthermore, in the first direction, the word lines 210 and programming conductors 220 connected to the antifuse cells 100 in the same column are located on either side of the antifuse cells 100.

[0141] At this time, it is convenient to arrange the word lines 210 and the programming conductive lines 220 .

[0142] In one embodiment, see Figure 9 , also provides a programming method, which is applied to any of the above antifuse array structures. The programming method includes:

[0143] Step S110, obtaining a target anti-fuse unit to be programmed in the anti-fuse array structure, and obtaining a target word line, a target programming conductor, and a target bit line corresponding to the target anti-fuse unit;

[0144] Step S120, applying an on voltage to the target word line and an off voltage to the other word lines, applying a first programming voltage to the target programming wire and a zero voltage to the other programming wires, and applying a zero voltage to the target bit line and a first intermediate voltage to the other bit lines, wherein the first intermediate voltage is equal to half of the first programming voltage, so as to write to the first anti-fuse device of the target anti-fuse cell;

[0145] In step S130, a turn-off voltage is applied to the target word line and other word lines, and a second programming voltage is applied to the target programming wire, while a zero voltage is applied to other programming wires, and a zero voltage is applied to the target bit line, while a second intermediate voltage is applied to other bit lines, and the second intermediate voltage is equal to half of the second programming voltage, so as to program and write the second anti-fuse device of the target anti-fuse unit.

[0146] In step S110, the target antifuse cell is the antifuse cell 100 to be programmed. The target word line corresponding to the target antifuse cell is the word line 210 connected to the gate of the select transistor 110 of the target antifuse cell. The target programming conductor corresponding to the target antifuse cell is the programming conductor 220 connected to the gate of the first antifuse device 120 of the target antifuse cell. The programming conductor 220 is also connected to the second capacitor electrode 132 of the second antifuse device 130 of the target antifuse cell. The target bit line corresponding to the target antifuse cell is the bit line 310 connected to the first doped region 111 of the select transistor 110 of the target antifuse cell. The bit line 310 is also connected to the first capacitor electrode 131 of the second antifuse device 130 of the target antifuse cell.

[0147] In step S120, an on voltage is applied to the target word line, while an off voltage is applied to other word lines, thereby turning on the select transistor 110 connected to the target word line. The select transistor 110 connected to the target word line includes the select transistor 110 of the target anti-fuse cell.

[0148] Applying a first programming voltage Vblow1 to the target programming conductor and applying zero voltage to the target bit line, the first anti-fuse device 120 of the target anti-fuse cell can be broken down by the voltage difference Vblow1 between the target bit line and the target programming conductor, thereby being programmed.

[0149] In the anti-fuse cells where the other turned-on selection transistors 110 are located, a zero voltage is applied to the programming conductor and a first intermediate voltage is applied to the bit line. Therefore, the first anti-fuse device 120 in these anti-fuse cells cannot be broken down and thus cannot be programmed.

[0150] For anti-fuse cells whose select transistors 110 are not turned on, zero voltage is applied to the programming conductor. Since the voltage on the bit line cannot be applied to the second doped region 112, the voltage on the second doped region 112 is also zero. Therefore, the first anti-fuse devices 120 in these anti-fuse cells cannot be broken down, and thus cannot be programmed.

[0151] In step S130, after the turn-off voltage is applied to the target word line and other word lines, the selection transistors 110 of all anti-fuse units 100 are turned off. At this time, all first anti-fuse devices 120 (including the first anti-fuse device 120 of the target anti-fuse unit) will not be programmed.

[0152] After applying a second programming voltage Vblow2 to the target programming conductor and applying zero voltage to the target bit line, the second anti-fuse device 130 of the target anti-fuse unit can be broken down by the voltage difference Vblow2 between the target bit line and the target programming conductor, thereby being programmed.

[0153] Zero voltage is applied to the other programming conductors, and a second intermediate voltage is applied to the other bit lines. Therefore, the voltage difference between the bit line and the programming conductor of the other antifuse cells is Therefore, it will not be programmed.

[0154] Vblow1 may be smaller than Vblow2 , so that when the first anti-fuse device 120 is broken down, the second anti-fuse device 130 will not be broken down, thereby enabling independent programming of the first anti-fuse device 120 and the second anti-fuse device 130 .

[0155] In one embodiment, see Figure 10, also provides a reading method, which is applied to any of the above antifuse array structures. The reading method includes:

[0156] Step S210, obtaining a target anti-fuse unit to be programmed in the anti-fuse array structure, and obtaining a target word line, a target programming conductor, and a target bit line corresponding to the target anti-fuse unit;

[0157] Step S220: applying an on voltage to the target word line, applying an off voltage to the other word lines, applying a zero voltage to the target programming wire and the other programming wires, applying a read voltage to the target bit line, and applying a zero voltage to the other bit lines, reading the current flowing through the first anti-fuse device of the target anti-fuse unit, so as to read the first anti-fuse device of the target anti-fuse unit;

[0158] In step S230, a turn-off voltage is applied to the target word line and other word lines, and a zero voltage is applied to the target programming wire, while a read voltage is applied to other programming wires. A read voltage is applied to the target bit line, while a zero voltage is applied to other bit lines, and the current of the second anti-fuse device flowing through the target anti-fuse unit is read to read the second anti-fuse device of the target anti-fuse unit.

[0159] In step S210, the target antifuse cell is the antifuse cell 100 to be programmed. The target word line corresponding to the target antifuse cell is the word line 210 connected to the gate of the select transistor 110 of the target antifuse cell. The target programming conductor corresponding to the target antifuse cell is the programming conductor 220 connected to the gate of the first antifuse device 120 of the target antifuse cell. The programming conductor 220 is also connected to the second capacitor electrode 132 of the second antifuse device 130 of the target antifuse cell. The target bit line corresponding to the target antifuse cell is the bit line 310 connected to the first doped region 111 of the select transistor 110 of the target antifuse cell. The bit line 310 is also connected to the first capacitor electrode 131 of the second antifuse device 130 of the target antifuse cell.

[0160] In step S220, an on voltage is applied to the target word line, while an off voltage is applied to other word lines, thereby turning on the select transistor 110 connected to the target word line. The select transistor 110 connected to the target word line includes the select transistor 110 of the target anti-fuse cell.

[0161] After applying a zero voltage to the target programming conductor and a read voltage Vblr to the target bit line, a conductive loop is formed between the target programming conductor and the target bit line due to the conduction of the select transistor 110, thereby allowing current to flow through the first anti-fuse device 120 of the target anti-fuse cell. When the data programmed into the first anti-fuse device 120 of the target anti-fuse cell is different, the breakdown of the first anti-fuse device 120 varies. Whether or not the breakdown occurs can affect the current flowing through the first anti-fuse device 120 of the target anti-fuse cell. Therefore, the current flowing through the first anti-fuse device 120 of the target anti-fuse cell can be used to determine whether the data stored in the first anti-fuse device 120 of the target anti-fuse cell is "1" or "0."

[0162] When zero voltage is applied to other programming conductors 220 and other bit lines 310, even if the selection transistor 110 of the anti-fuse unit is turned on, no current flows through the corresponding first anti-fuse device 120, so data cannot be read.

[0163] For the anti-fuse unit whose selection transistor 110 is not turned on, no current flows through the corresponding first anti-fuse device 120 , and thus data cannot be read.

[0164] In step S230, after the turn-off voltage is applied to the target word line and other word lines, the selection transistors 110 of all anti-fuse units 100 are turned off. At this time, all first anti-fuse devices 120 (including the first anti-fuse device 120 of the target anti-fuse unit) cannot read data.

[0165] At the same time, when the data programmed into the second anti-fuse device 130 of the target anti-fuse cell is different, the breakdown of the second anti-fuse device 130 varies. However, after applying a zero voltage to the target programming conductor and a read voltage Vblr to the target bit line, whether the second anti-fuse device 130 breaks down can affect the current flowing through the second anti-fuse device 130 of the target anti-fuse cell. Therefore, the magnitude of the current flowing through the second anti-fuse device 130 of the target anti-fuse cell can be used to determine whether the data stored in the second anti-fuse device 130 of the target anti-fuse cell is "1" or "0."

[0166] At the same time, for other anti-fuse units connected to the target bit line, the same read voltage Vblr as the target bit line is applied to their programming wires, so that no current is formed in the second anti-fuse devices 130 of other anti-fuse units, and the second anti-fuse devices 130 of other anti-fuse units are not read.

[0167] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0168] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An anti-fuse unit, characterized in that: include: A selection transistor, wherein the gate is connected to a word line, and one of the source and the drain is connected to a bit line; a first anti-fuse device, one end of which is connected to the other of the source and the drain of the selection transistor, and the other end of which is used to connect to the programming wire; The second anti-fuse device has one end connected to the same bit line as the selection transistor, and the other end connected to the same programming conductor as the first anti-fuse device.

2. The anti-fuse unit according to claim 1, wherein: The selection transistor includes a first doping region and a second doping region, one of the first doping region and the second doping region serves as a source of the selection transistor, and the other serves as a drain of the selection transistor, and the first doping region is used to connect to a bit line; The first anti-fuse device is a transistor-type anti-fuse device, and the first anti-fuse device and the selection transistor are formed based on the same active region and share the second doped region with the selection transistor, and the gate of the first anti-fuse device is connected to the programming wire; The second anti-fuse device includes a first capacitor electrode and a second capacitor electrode that are arranged opposite to each other. The first capacitor electrode is used to connect to the bit line, and the second capacitor electrode is used to connect to the programming wire.

3. The anti-fuse unit according to claim 2, wherein: The first capacitor electrode and the second capacitor electrode are arranged in the same layer.

4. An antifuse array structure, characterized in that: The circuit comprises a plurality of anti-fuse unit groups, word lines, programming conductors and bit lines, wherein the plurality of anti-fuse unit groups are arranged in an array, and each anti-fuse unit group comprises at least one anti-fuse unit. Wherein, the anti-fuse unit includes: A selection transistor having a gate connected to a word line and one of a source and a drain connected to a bit line; A first anti-fuse device has one end connected to the other of the source and the drain of the selection transistor and the other end connected to the programming wire. A second anti-fuse device has one end connected to the same bit line as the selection transistor, and the other end connected to the same programming conductive line as the first anti-fuse device.

5. The antifuse array structure according to claim 4, wherein: The antifuse array structure includes a substrate, the substrate includes a substrate and a shallow trench isolation structure, the shallow trench isolation structure separates the substrate into a plurality of active areas, The plurality of antifuse unit groups are arranged in an array on the substrate, and the antifuse units in the same antifuse unit group are formed based on the same active region. In the anti-fuse unit, the selection transistor includes a first doped region and a second doped region, one of the first doped region and the second doped region serves as a source of the selection transistor, and the other serves as a drain of the selection transistor, and the first doped region is connected to the bit line through a first conductive plug; The first anti-fuse device is a transistor-type anti-fuse device, and the first anti-fuse device and the selection transistor are formed based on the same active region and share the second doped region with the selection transistor, and the gate of the first anti-fuse device is connected to the programming wire; The second anti-fuse device includes a first capacitor electrode and a second capacitor electrode that are oppositely arranged. The first capacitor electrode is connected to the bit line, and the second capacitor electrode is connected to the programming wire of the first anti-fuse device.

6. The antifuse array structure according to claim 5, wherein: The first capacitor electrode and the second capacitor electrode are arranged in the same layer.

7. The antifuse array structure according to claim 6, wherein: The antifuse array structure includes a first conductive layer and a second conductive layer, the first conductive layer includes the word line and the programming wire, and the second conductive layer includes the bit line; The first capacitor electrode and the second capacitor electrode are located in the second conductive layer, and the second capacitor electrode is connected to the programming wire through a second conductive plug.

8. The antifuse array structure according to claim 7, wherein: The bit line is multiplexed as the first capacitor electrode.

9. The antifuse array structure according to claim 5, wherein: The antifuse array structure includes a second conductive layer, wherein the second conductive layer includes a bit line, The bit line and the active area are at least partially staggered. The second conductive layer further includes a bit line connecting portion connected to the bit line and opposite to the first doped area.

10. The antifuse array structure according to claim 5, wherein: The anti-fuse unit group includes at least two anti-fuse units, and the same anti-fuse unit group includes adjacent anti-fuse units that share the same first conductive plug.

11. The antifuse array structure according to claim 5, wherein: In the arrangement array of the antifuse unit group, the row direction is a first direction, the column direction is a second direction, and the second direction intersects the first direction. The bit line and the active area both extend along the first direction, The anti-fuse units in the same row are connected to the same bit line.

12. The antifuse array structure according to claim 11, wherein: In the antifuse array structure, every two rows of antifuse units form an antifuse row group, and two bit lines connected to each antifuse row group are respectively located on two opposite sides of the antifuse row group in the second direction.

13. The antifuse array structure according to claim 5, wherein: In the arrangement array of the antifuse unit group, the row direction is a first direction, the column direction is a second direction, and the second direction intersects the first direction. The bit line and the active area both extend along the first direction, and the bit line and the active area are staggered. In the anti-fuse units located in the same row, the anti-fuse units formed on adjacent active regions are respectively connected to different bit lines located on both sides of the anti-fuse unit.

14. The antifuse array structure according to claim 5, wherein: In the arrangement array of the antifuse unit group, the row direction is a first direction, the column direction is a second direction, and the second direction intersects the first direction. The word lines and the programming wires both extend along the second direction, The anti-fuse units in the same column are connected to the same word line, and the anti-fuse units in the same column are connected to the same programming wire. In the first direction, the word line and the programming wire connected to the anti-fuse units in the same column are respectively located on both sides of the anti-fuse units.

15. A programming method, characterized in that: The antifuse array structure according to any one of claims 4 to 14 comprises: Obtaining a target anti-fuse unit to be programmed in the anti-fuse array structure, and obtaining a target word line, a target programming conductor, and a target bit line corresponding to the target anti-fuse unit; Applying an on voltage to the target word line and an off voltage to the other word lines, applying a first programming voltage to the target programming conductor and a zero voltage to the other programming conductors, and applying a zero voltage to the target bit line and a first intermediate voltage to the other bit lines, wherein the first intermediate voltage is equal to half of the first programming voltage, so as to write to the first anti-fuse device of the target anti-fuse cell; A turn-off voltage is applied to the target word line and other word lines, and a second programming voltage is applied to the target programming wire, while a zero voltage is applied to other programming wires, and a zero voltage is applied to the target bit line, while a second intermediate voltage is applied to other bit lines, and the second intermediate voltage is equal to half of the second programming voltage, so as to program and write the second anti-fuse device of the target anti-fuse unit.

16. A reading method, characterized in that: The antifuse array structure according to any one of claims 4 to 14 comprises: Obtaining a target anti-fuse unit to be programmed in the anti-fuse array structure, and obtaining a target word line, a target programming conductor, and a target bit line corresponding to the target anti-fuse unit; Applying an on voltage to the target word line and an off voltage to the other word lines, applying a zero voltage to the target programming wire and the other programming wires, applying a read voltage to the target bit line and applying a zero voltage to the other bit lines, and reading a current flowing through the first anti-fuse device of the target anti-fuse unit to read the first anti-fuse device of the target anti-fuse unit; A turn-off voltage is applied to the target word line and other word lines, and a zero voltage is applied to the target programming wire, while a read voltage is applied to other programming wires. A read voltage is applied to the target bit line, while a zero voltage is applied to other bit lines, and the current flowing through the second anti-fuse device of the target anti-fuse unit is read to read the second anti-fuse device of the target anti-fuse unit.

Images