Method for reducing gate-source capacitance
By forming a multilayer dielectric layer and a polysilicon gate on the epitaxial layer, the problem of insufficient polysilicon trench depth in the prior art is solved, the gate-source capacitance is reduced, and the switching performance of power devices is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2024-08-12
- Publication Date
- 2026-06-05
AI Technical Summary
In the prior art, the depth of the gate polysilicon trench is 300 to 800 angstroms, and the input capacitance needs to be further reduced to improve the switching performance of power devices.
By forming a gate trench on the epitaxial layer and forming multiple dielectric layers on its bottom and sidewalls, a polysilicon gate is then filled and a groove 1000 to 2000 angstroms deep is formed by etching back. Ion implantation is performed using an etch protection layer and sidewalls as masking layers, and finally contact holes and metal layers are formed.
The gate-source capacitance has been effectively reduced, and wafer-level testing shows that the input capacitance value is about 10% lower than that of existing technologies, meeting mass production requirements.
Smart Images
Figure CN119108271B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for reducing gate-source capacitance. Background Technology
[0002] like Figure 1 The parasitic capacitance of the power device shown directly affects its switching performance. The input capacitance (Ciss) consists of two parts: the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd). In the prior art, the depth of the gate polysilicon trench is typically formed to be 300 to 800 angstroms, and the input capacitance needs to be further reduced.
[0003] To solve the above problems, a novel method for reducing gate-source capacitance is needed. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for reducing gate-source capacitance, which solves the problem that the depth of the gate polysilicon trench is usually 300 to 800 angstroms in the prior art, and the input capacitance needs to be further reduced.
[0005] To achieve the above and other related objectives, the present invention provides a method for reducing gate-source capacitance, comprising:
[0006] Step 1: Epitaxially form an epitaxial layer of the second conductivity type on a substrate of the first conductivity type;
[0007] Step 2: A gate trench is formed on the top of the epitaxial layer. The gate trench extends downward from the upper surface of the epitaxial layer through the area to be formed in the body region. A first gate dielectric layer and a first polysilicon gate are formed on the first gate dielectric layer at the bottom of the gate trench. An isolation layer is formed on the first polysilicon gate and the first gate dielectric layer. A second gate dielectric layer is formed on the remaining sidewalls of the gate trench and on the epitaxial layer.
[0008] Step 3: Form a second polysilicon gate to fill the remaining gate trench, and grind the second polysilicon gate onto the second gate dielectric layer;
[0009] Step 4: Etch back the second polysilicon gate to form a groove with a depth of 1000 to 2000 angstroms at the gate trench. Determine whether the thickness of the second gate dielectric layer on the step at the top of the gate trench is less than the target value. If so, form an etching protection layer on the epitaxial layer and the groove.
[0010] Step 5: A sidewall is formed at the sidewall of the groove using deposition and etching methods, which serves as a masking layer for ion implantation;
[0011] Step 6: Form a body region and a source region on the epitaxial layer using ion implantation, with the sidewalls serving as a masking layer for ion implantation, and then remove the sidewalls.
[0012] Preferably, the method for forming the gate trench in step two includes: forming a photoresist layer on the epitaxial layer; photolithographically opening the photoresist layer to define the formation region of the gate trench; forming the gate trench on the epitaxial layer by etching; and removing the remaining photoresist layer.
[0013] Preferably, the material of the isolation layer in step two is silicon dioxide.
[0014] Preferably, the grinding method in step three is chemical mechanical planarization grinding.
[0015] Preferably, the etching method in step four is dry etching, and the etching time is 30 to 60 seconds.
[0016] Preferably, the preset value in step four is 450 angstroms.
[0017] Preferably, the material of the etched protective layer in step four is an oxide.
[0018] Preferably, the thickness of the etched protective layer in step four is 100 to 500 angstroms.
[0019] Preferably, the sidewall material in step five is silicon nitride.
[0020] Preferably, the silicon nitride deposition thickness in step five is 500 to 1500 angstroms.
[0021] Preferably, the silicon nitride is formed in step five using a low-pressure chemical vapor deposition method.
[0022] Preferably, the etching method in step five is anisotropic dry etching.
[0023] Preferably, the sidewalls are removed in step six using a wet etching method.
[0024] Preferably, the method further includes step seven: forming an interlayer dielectric layer covering the epitaxial layer using deposition and polishing methods; forming a contact hole communicating with the second polysilicon gate on the interlayer dielectric layer; and forming a metal layer filling the contact hole.
[0025] Preferably, the method is used for the manufacture of power devices.
[0026] As described above, the method for reducing gate-source capacitance of the present invention has the following beneficial effects:
[0027] The input capacitance value of the wafer-level testing process of this invention is reduced by about 10% compared with the existing technology process, and it can enter the mass production state after the customer's packaging and testing data is obtained. Attached Figure Description
[0028] Figure 1 The diagram shows the dynamic parameter parasitic capacitance of a power device in the prior art.
[0029] Figure 2 The diagram shown is a schematic representation of the process flow of the present invention.
[0030] Figure 3 The diagram shown illustrates the formation of the second polysilicon gate according to the present invention.
[0031] Figure 4 The diagram shown is a schematic diagram of the milled second polysilicon gate of the present invention.
[0032] Figure 5 The diagram shows the formation of the groove and the etching of the protective layer according to the present invention.
[0033] Figure 6 The diagram shown is a schematic representation of the etching protective layer of the present invention.
[0034] Figure 7 The diagram shows a schematic of the deposited sidewall material layer of the present invention.
[0035] Figure 8 The diagram shown illustrates the formation of the sidewalls according to the present invention.
[0036] Figure 9 The diagram shows the forming region and source region of the present invention.
[0037] Figure 10 The diagram shown illustrates the removal of the sidewalls according to the present invention. Detailed Implementation
[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0039] Please see Figure 2 The present invention provides a method for reducing gate-source capacitance, comprising:
[0040] Step 1: An epitaxial layer 101 of the second conductivity type is formed on a substrate of the first conductivity type (not shown in the figure);
[0041] Step 2: A gate trench is formed on the top of the epitaxial layer 101. The gate trench extends downward from the upper surface of the epitaxial layer 101 through the area to be formed in the body region 102. A first gate dielectric layer 103 and a first polysilicon gate 104 formed on the first gate dielectric layer 103 are formed at the bottom of the gate trench. An isolation layer 105 is formed on the first polysilicon gate 104 and the first gate dielectric layer 103. A second gate dielectric layer 106 is formed on the sidewalls of the remaining gate trench and on the epitaxial layer 101.
[0042] In some embodiments, the gate dielectric layer may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SION). It can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may also include a high-k dielectric layer, which may include hafnium oxide (HfO2). Optionally, the gate dielectric layer may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HMO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride 108 (Si3N4), oxynitride (SiON), and combinations thereof.
[0043] In some embodiments, the method for forming the gate trench in step two includes: forming a photoresist layer on the epitaxial layer 101; photolithographically opening the photoresist layer to define the formation region of the gate trench; forming the gate trench on the epitaxial layer 101 by etching; and removing the remaining photoresist layer.
[0044] In some embodiments, the material of the isolation layer 105 in step two is silicon dioxide.
[0045] Step 3: Form a second polysilicon gate 107 to fill the remaining gate trench, forming as shown in the figure. Figure 3 The structure shown is formed by grinding the second polysilicon gate 107 onto the second gate dielectric layer 106, as shown. Figure 4 The structure shown;
[0046] In some embodiments, the grinding method in step three is chemical mechanical planarization grinding.
[0047] Step 4: Etch back the second polysilicon gate 107 to form a groove with a depth of 1000 to 2000 angstroms at the gate trench of the second trench gate, forming a shape as shown in the image. Figure 5 The structure shown in the prior art has a groove depth of 300-800 angstroms. Increasing the groove etching depth effectively shortens the channel length affecting the gate-source capacitance, thereby reducing the gate-source capacitance (Cgs). Optionally, the groove depth can be 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms, or 2000 angstroms. To prevent over-etching during the subsequent wet removal of sidewalls 110, resulting in sharp corner structures at the top of the step sidewalls, it is determined whether the thickness of the second gate dielectric layer 106 on the step at the top of the gate trench is less than the target value. If so, an etching protection layer 108 is formed on the epitaxial layer 101 and the groove, forming a structure as shown in the diagram. Figure 6 The structure shown;
[0048] In some embodiments, the etching method in step four is dry etching, and the etching time is 30 to 60 seconds. The specific etching time is determined by the required groove depth.
[0049] In some embodiments, the preset value in step four is 450 angstroms.
[0050] In some embodiments, the material of the etched protective layer 108 in step four is an oxide, which can be formed using a low-pressure chemical vapor deposition method.
[0051] In some embodiments, the thickness of the etched protective layer 108 in step four is 100 to 500 angstroms.
[0052] Step 5: A sidewall 110 is formed on the sidewall of the groove using deposition and etching methods. This sidewall serves as a masking layer for ion implantation. Specifically, a sidewall material layer 109 is first deposited to form a layer as shown in the image. Figure 7 The structure shown is then formed by etching the sidewall material layer 109 to create the sidewall 110, forming a structure as shown. Figure 8 The structure shown;
[0053] In some embodiments, the sidewall 110 in step five is made of silicon nitride.
[0054] In some embodiments, the silicon nitride deposition thickness in step five is 500 to 1500 angstroms.
[0055] In some embodiments, silicon nitride is formed in step five using a low-pressure chemical vapor deposition method.
[0056] In some embodiments, the etching method in step five is anisotropic dry etching.
[0057] Step 6: Using ion implantation, a body region 102 and a source region 111 are formed on the epitaxial layer 101. The sidewall 110 serves as a masking layer for ion implantation, forming a structure as shown in the figure. Figure 9 The structure shown prevents channel leakage caused by the side of the groove during source region 111 injection. To prevent the sidewall 110 from affecting the subsequent contact hole etching range, the sidewall 110 is then removed, forming the structure shown. Figure 10 The structure shown does not affect the final structure of the device.
[0058] In some embodiments, the sidewall 110 is removed in step six using a wet etching method, for example, using an H3PO4 solution.
[0059] In some embodiments, the method further includes step seven: forming an interlayer dielectric layer covering the epitaxial layer 101 using deposition and polishing methods; forming a contact hole communicating with the second polysilicon gate 107 on the interlayer dielectric layer; and forming a metal layer to fill the contact hole.
[0060] In some embodiments, the method is used for the manufacture of power devices.
[0061] The input capacitance value of the wafer-level testing process of this invention is reduced by about 10% compared with the existing technology process, and it can enter the mass production state after the customer's packaging and testing data is obtained.
[0062] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0063] In summary, the input capacitance value of this invention's wafer-level testing process is reduced by approximately 10% compared to existing technologies, allowing for mass production immediately after receiving client packaging and testing data. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.
[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for reducing gate-source capacitance, characterized in that, At least including: Step 1: Epitaxially form an epitaxial layer of the second conductivity type on a substrate of the first conductivity type; Step 2: A gate trench is formed on the top of the epitaxial layer. The gate trench extends downward from the upper surface of the epitaxial layer through the area to be formed in the body region. A first gate dielectric layer and a first polysilicon gate are formed on the first gate dielectric layer at the bottom of the gate trench. An isolation layer is formed on the first polysilicon gate and the first gate dielectric layer. A second gate dielectric layer is formed on the remaining sidewalls of the gate trench and on the epitaxial layer. Step 3: Form a second polysilicon gate to fill the remaining gate trench, and grind the second polysilicon gate onto the second gate dielectric layer; Step 4: Etch back the second polysilicon gate to form a second trench gate, so that the second trench gate forms a groove with a depth of 1000 to 2000 angstroms at the gate trench. Determine whether the thickness of the second gate dielectric layer on the step at the top of the gate trench is less than the target value. If so, form an etching protection layer on the epitaxial layer and the groove. The etching protection layer is used to prevent sharp corner structures from being generated on the top sidewall of the step at the top of the gate trench due to over-etching during subsequent sidewall removal. The material of the etching protection layer is oxide, and the thickness of the etching protection layer is 100 to 500 angstroms. Step 5: A sidewall is formed at the side wall of the groove using deposition and etching methods. This sidewall serves as a masking layer for ion implantation. The material of the sidewall is silicon nitride. Step 6: Form a body region and a source region on the epitaxial layer using ion implantation, with the sidewalls serving as a masking layer for ion implantation, and then remove the sidewalls.
2. The method for reducing gate-source capacitance according to claim 1, characterized in that: The method for forming the gate trench in step two includes: forming a photoresist layer on the epitaxial layer; photolithographically opening the photoresist layer to define the formation region of the gate trench; forming the gate trench on the epitaxial layer by etching; and removing the remaining photoresist layer.
3. The method for reducing gate-source capacitance according to claim 1, characterized in that: The material of the isolation layer in step two is silicon dioxide.
4. The method for reducing gate-source capacitance according to claim 1, characterized in that: The grinding method described in step three is chemical mechanical planarization grinding.
5. The method for reducing gate-source capacitance according to claim 1, characterized in that: The etching method described in step four is dry etching, and the etching time is 30 to 60 seconds.
6. The method for reducing gate-source capacitance according to claim 1, characterized in that: The target value mentioned in step four is 450 angstroms.
7. The method for reducing gate-source capacitance according to claim 1, characterized in that: The deposition thickness of the sidewalls described in step five is 500 to 1500 angstroms.
8. The method for reducing gate-source capacitance according to claim 1, characterized in that: In step five, the silicon nitride is formed using low-pressure chemical vapor deposition.
9. The method for reducing gate-source capacitance according to claim 1, characterized in that: The etching method described in step five is anisotropic dry etching.
10. The method for reducing gate-source capacitance according to claim 1, characterized in that: In step six, the sidewalls are removed using a wet etching method.
11. The method for reducing gate-source capacitance according to claim 1, characterized in that: The method further includes step seven: forming an interlayer dielectric layer covering the epitaxial layer using deposition and polishing methods; forming a contact hole communicating with the second polysilicon gate on the interlayer dielectric layer; and forming a metal layer filling the contact hole.
12. The method for reducing gate-source capacitance according to claim 1, characterized in that: The method is used for the manufacture of power devices.