Semiconductor element and semiconductor manufacturing process for forming gate dielectric layer

Abstract

The invention discloses a semiconductor element with a double-layer gate dielectric layer and a semiconductor manufacturing process for forming the gate dielectric layer, and the semiconductor manufacturing process for forming the gate dielectric layer comprises the following steps: providing a substrate; the method includes forming a substrate having a first region and a second region, forming CMOS elements on the first region of the substrate, forming a dielectric layer on the entire substrate and the CMOS elements, forming a rear-segment metal interconnect structure in the dielectric layer, performing a lithography process to remove a portion of the dielectric layer, and forming a second-segment metal interconnect structure on the second region of the substrate. The second region of the substrate is exposed, an oxygen plasma fabrication process is performed to form a native oxide layer on the exposed second region, and a high dielectric constant dielectric layer is formed on the native oxide layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor manufacturing process, and more particularly to a semiconductor manufacturing process for forming a gate dielectric layer and a semiconductor element having a double-layer gate dielectric layer formed thereby. Background Art

[0002] As the circuit line width of complementary metal oxide semiconductor (CMOS) continues to shrink, the thickness of the gate oxide layer of transistor components is also shrinking. However, when the thickness of the gate oxide layer is thinner than 2nm, the gate oxide layer made of silicon dioxide (SiO2) is no longer an ideal insulator, and obvious tunneling leakage will occur. In response to this, the industry currently uses high dielectric constant materials such as hafnium dioxide (HfO2) to replace silicon dioxide as the gate oxide layer. The dielectric constant of hafnium dioxide is 25, which is 6 times that of silicon dioxide. Therefore, under the same voltage or electric field strength, the thickness of its dielectric layer can be 6 times that of the silicon dioxide dielectric layer, which can greatly reduce the tunneling leakage phenomenon.

[0003] Although high dielectric constant materials can increase the thickness of the gate oxide layer, the high dielectric constant will inevitably lead to the problem of channel mobility degradation, which will increase the critical voltage and thus significantly reduce the performance of semiconductor devices. In order to solve this problem, the current industry practice is to set a silicon dioxide dielectric layer between the channel and the high dielectric constant gate oxide layer. In this way, the dielectric layer in direct contact with the channel will be a silicon dioxide dielectric layer with a lower dielectric constant, which can solve the problem of channel mobility degradation.

[0004] At present, the manufacturing processes used to form the above silicon dioxide dielectric layer are roughly divided into rapid thermal oxidation and chemical oxidation. Rapid thermal oxidation is a high-temperature manufacturing process, while chemical oxidation will corrode metal wires. Both can only be used in semiconductor front-end manufacturing processes (FEOL) and are not suitable for semiconductor back-end manufacturing processes (BEOL). Considering the complex application environment in the future, such as the application of biochips, the general skilled person in this field needs to improve the method of the above gate oxide layer so that it can be applied to the semiconductor back-end manufacturing process without being restricted by the production factors of the manufacturing process. Summary of the invention

[0005] In view of the above-mentioned current state of the art, the present invention proposes a novel semiconductor manufacturing process, which is characterized in that a dielectric layer of silicon dioxide material is formed by oxygen plasma treatment. The low-temperature manufacturing process characteristics of oxygen plasma treatment make it applicable during or after the semiconductor back-end manufacturing process, and it is not limited by the production factors of the manufacturing process. In addition, no products containing water components are generated during the process, so there is no risk of corroding the back-end metal interconnection structure.

[0006] One aspect of the present invention is to provide a semiconductor manufacturing process for forming a gate dielectric layer, the steps of which include providing a substrate having a first region and a second region, forming a CMOS device on the first region of the substrate, forming a dielectric layer on the entire substrate and the CMOS devices, forming a back-end metal interconnection structure in the dielectric layer, performing a photolithography process to remove a portion of the dielectric layer to expose the second region of the substrate, performing an oxygen plasma process to form a native oxide layer on the exposed second region, and forming a high dielectric constant dielectric layer on the native oxide layer.

[0007] Another aspect of the present invention is to provide a semiconductor element with a double-layer gate dielectric layer, whose structure includes a substrate, a native oxide layer located on the substrate, wherein the native oxide layer is formed by an oxygen plasma manufacturing process after the semiconductor back-end manufacturing process, a high dielectric constant dielectric layer located on the native oxide layer, a gate located on the high dielectric constant dielectric layer, and a source and a drain located in the substrate on both sides of the gate respectively.

[0008] These and other objects of the present invention will become more apparent to the reader after reading the following detailed description of the preferred embodiment which is described in various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 5 is a cross-sectional schematic diagram of a semiconductor manufacturing process for forming a gate dielectric layer in a preferred embodiment of the present invention; and

[0010] Figure 6 FIG. 4 is a schematic cross-sectional view of a semiconductor manufacturing process for forming a gate dielectric layer according to another embodiment of the present invention.

[0011] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0012] Explanation of symbols

[0013] 100 Semiconductor substrate

[0014] 100a First Area

[0015] 100b Second Area

[0016] 102 Gate Oxide

[0017] 104 Dielectric layer

[0018] 106 Back-end Metal Interconnect Structure

[0019] 108 Passivation layer

[0020] 110 Opening

[0021] 112 Native Oxide

[0022] 114 High dielectric constant dielectric layer 114

[0023] D1, D2 drain

[0024] G1, G2 gate

[0025] S1, S2 source DETAILED DESCRIPTION

[0026] Now, the exemplary embodiments of the present invention will be described in detail below, and the features described will be shown with reference to the accompanying drawings so that the reader can understand and achieve the technical effects. The reader will understand that the description in the text is only by way of example and is not intended to limit the present invention. The various embodiments of the present invention and the various features that do not conflict with each other in the embodiments can be combined or reset in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention are understandable to those skilled in the art and are intended to be included in the scope of the present invention.

[0027] Readers should be able to easily understand that the meanings of "on", "over" and "above" in this case should be interpreted in a broad manner, so that "on" not only means "directly on" something but also includes the meaning of being "on" something with an intervening feature or layer, and "on" or "above" not only means "on" or "above" something but also includes the meaning of being "on" or "above" something with no intervening features or layers (i.e., directly on something). In addition, spatially related terms such as "under", "below", "lower", "over", "upper", etc. may be used herein for convenience of description to describe the relationship between one element or feature and another or more elements or features, as shown in the accompanying drawings.

[0028] As used herein, the term "substrate" refers to a material onto which subsequent materials are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0029] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (where contacts, interconnects and / or vias are formed) and one or more dielectric layers.

[0030] The reader can generally understand the term at least in part from the usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a", "an", "the", or "said" can also be understood to convey singular usage or to convey plural usage. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0031] The reader can further understand that when the words "include" and / or "contain" are used in this specification, they specify the existence of the stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0032] Now the following will refer to Figures 1 to 5 The semiconductor manufacturing process for forming a gate dielectric layer in a preferred embodiment of the present invention is described in the figure. The relative positions and connection relationships of various components in the vertical direction in the manufacturing process are described in the form of cross-sectional views. The figure uses three transistor elements as examples to allow readers to understand the evolution relationship between the components and structures in the manufacturing process. In the actual structure, depending on the position of the cross section, the semiconductor element may have different structural compositions, such as whether the substrate is an active region or a shallow trench structure (STI) and whether a metal silicide layer is formed thereon, and the gate may have multiple types arranged in stripes, but this is not limited to this.

[0033] Please refer to Figure 1. At the beginning of the manufacturing process, a semiconductor substrate 100 is provided as a setting basis for the semiconductor element of the present invention. The material of the semiconductor substrate 100 is preferably a silicon substrate, such as a P-type doped silicon substrate, but other silicon-containing substrates may also be used, including III-V silicon-coated substrates (such as GaN-on-silicon) or silicon-on-insulator (SOI) substrates, etc., or other doping types of substrates, but are not limited to this. In an embodiment of the present invention, the semiconductor substrate 100 has a first region 100a and a second region 100b, wherein a general complementary metal oxide semiconductor (CMOS) element is predetermined to be formed on the first region 100a, and other semiconductor elements, such as a biochip or an ion-sensitive field-effect transistor (ISFET, ion-sensitive field-effect transistor) are predetermined to be formed on the second region 100b.

[0034] Re-reference Figure 1 . First, an ion implantation process is performed to form doped regions such as source S1, S2 and drain D1, D2 in the first region 100a and the second region 100b of the semiconductor substrate 100. Taking an N-type metal oxide semiconductor (NMOS) device as an example, an N-type dopant, such as pentavalent phosphorus (P), antimony (Sb), arsenic (As) and other elements, is doped into a P-type semiconductor substrate 100 or a P-type well region through an ion implantation process to form source S1, S2 and drain D1, D2 doped regions. A gate oxide layer (gateoxide) 102, such as silicon dioxide or a high-k dielectric layer, can be formed on the surface of the silicon semiconductor substrate 100 by rapid thermal oxidation and chemical oxidation. Then, a gate G1 is formed on the gate oxide layer 102 in the first region 100a, and its material can be polysilicon or metal. The gate G1 , the source S1 and the drain D1 in the first region 100 a may form a CMOS field effect transistor device, such as an NMOS device or a PMOS device.

[0035] Please refer to Figure 2. After the semiconductor elements are fabricated on the first region 100a of the semiconductor substrate 100, a semiconductor back-end manufacturing process (BEOL) is then performed to form a dielectric layer 104 on the entire semiconductor substrate 100 and the CMOS elements, and a back-end metal interconnect structure 106 is formed in the dielectric layer 104, including structures such as contacts, metal wires, and vias. The dielectric layer 104 may include structures such as an interlayer dielectric layer (ILD) and a multi-layer intermetallic dielectric layer (IMD). The metal interconnect structure may include multiple metal layers, such as a first metal layer (M1) to a top metal layer (TM), which are connected to the gate G1, source S1, and drain D1 below through contacts and vias. After the back-end metal interconnect structure 106 is completed, a passivation layer 108, such as a thick silicon oxide or silicon nitride layer, is formed to cover the entire dielectric layer 104 and the back-end metal interconnect structure 106. Since the above-mentioned semiconductor back-end manufacturing process and related structures are prior arts and are not the focus of the present invention, the detailed steps and feature descriptions thereof will be omitted here.

[0036] Please refer to Figure 3 After the passivation layer 108 is formed, a photolithography process is then performed to remove the passivation layer 108 , the dielectric layer 104 , and the gate oxide layer 102 on the second region 100 b , thereby forming an opening 110 to expose the second region 100 b of the semiconductor substrate 100 .

[0037] Please refer to Figure 4 . Then, an oxygen plasma (O2 plasma) treatment is performed to form a native oxide layer (native oxide) 112 on the second region 100b exposed by the opening 110. In the embodiment of the present invention, since the oxygen plasma treatment is a low-temperature manufacturing process (the manufacturing process temperature is less than 400°C), compared with the existing rapid thermal oxidation manufacturing process (the manufacturing process temperature is far more than 400°C and can even reach thousands of°C), its low thermal budget can avoid the contamination of dopant diffusion or damage to the material structure of the previously formed semiconductor element and the back-end metal interconnection structure 106. Furthermore, compared with the existing chemical oxidation method using hydrogen peroxide (H2O2) to form the native oxide layer, the oxygen plasma treatment process will not form a product containing water components, so there is no risk of corroding the back-end metal interconnection structure 106. The above two reasons make the method of using oxygen plasma treatment to generate the native oxide layer in the present invention suitable for use in or after the semiconductor back-end manufacturing process, and is not limited by the production factors of the manufacturing process, and can be used to manufacture semiconductor elements such as biochips or ion-sensitive field-effect transistors (ISFETs).

[0038] Please refer to Figure 5. After the native oxide layer 112 is formed, a high-k dielectric layer 114 is then formed on the entire semiconductor substrate 100, such as by atomic layer deposition, which covers the passivation layer 108 on the second region 100b and is in direct contact with the native oxide layer 112 on the first region 100a. After the high-k dielectric layer 114 is formed, a gate G2 is then formed on the high-k dielectric layer 114 in the second region 100b, and its material can be polysilicon, metal, or a reaction solvent that can generate a potential difference. The gate G2 can form a semiconductor element, such as an ion sensitive field effect transistor (ISFET), together with the source S2 and the drain D2 in the second region 100b. In an embodiment of the present invention, the native oxide layer 112 and the high-k dielectric layer 114 are used together as the gate dielectric layer of the semiconductor element on the second region 100b. In this way, the high-k dielectric layer 114 can greatly reduce the tunneling leakage phenomenon, and the native oxide layer 112 can avoid the problem of channel mobility degradation.

[0039] Please refer to Figure 6 , which is a cross-sectional schematic diagram of a semiconductor manufacturing process for forming a gate dielectric layer according to another embodiment of the present invention. In this embodiment, the aforementioned Figure 3 The planar size of the opening 110 formed by the photolithography process can be specially designed to be the same as the planar size of the gate G2 to be formed later. Figure 6 As shown, the gate G2 can be formed by directly depositing a gate material such as polysilicon, metal or a reactive solvent that can generate a potential difference in the opening 110 in a self-aligned manner and then performing a back etching process, without the need for an additional photolithography process to pattern the gate material.

[0040] The semiconductor manufacturing process of the present invention is particularly suitable for manufacturing ion-sensitive field-effect transistors (ISFETs). The main difference between ISFETs and traditional field-effect transistors is that an electrolyte solution is used instead of metal to form the gate G2, which can be used to manufacture biosensors. In an embodiment, the material of such electrolytes may be Ta2O5, WO3, SnO2, AlN, Al2O3, SiO2, Si3N4, etc., which may be formed by vacuum sputtering or sol-gel method. ISFETs can be used to measure the concentration of specific ions in a solution, and because their structure is similar to that of a metal oxide semi-field-effect transistor (MOSFET), they are compatible with existing CMOS manufacturing processes for mass production. In biomedical applications, ISFETs are often used to detect DNA hybridization detection, biomarker detection in blood, antibody detection, glucose measurement, and pH value, etc. Taking pH measurement as an example, the principle of ISFET is that since protons can be bound or free in the electrolyte, this will cause a potential difference in the solid-liquid interface, thereby forming the surface potential of the element, which can be regarded as the action of applying voltage. This can drive the current in the element, and finally measure the related electrical signal to convert and infer the pH value of the solution.

[0041] According to the aforementioned semiconductor manufacturing process, the present invention also proposes a semiconductor device having a double-layer gate dielectric layer, such as Figure 5 As shown, the structure includes a semiconductor substrate 100, a native oxide layer 112 located on the semiconductor substrate 100, wherein the native oxide layer 112 is formed by oxygen plasma treatment after the semiconductor back-end manufacturing process, a high dielectric constant dielectric layer 114 is located on the native oxide layer 112, a gate G2 is located on the high dielectric constant dielectric layer 114, and a source S2 and a drain D2 are respectively located in the semiconductor substrate 100 on both sides of the gate G2.

[0042] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor manufacturing process for forming a gate dielectric layer, comprising: Providing a substrate having a first region and a second region, and a gate oxide layer is formed on the surface of the substrate; forming a first semiconductor element on the gate oxide layer in the first region of the substrate; forming a dielectric layer on the entire substrate and the first semiconductor elements; forming a back-end metal interconnect structure connected to the first semiconductor elements in the dielectric layer; Performing a photolithography process to remove a portion of the dielectric layer and the gate oxide layer to expose the second region of the substrate; Performing an oxygen plasma process to form a native oxide layer on the exposed second region of the substrate; as well as A high-k dielectric layer is formed on the native oxide layer.

2. The semiconductor manufacturing process for forming a gate dielectric layer as claimed in claim 1, wherein forming the first semiconductor elements on the first region of the substrate comprises: Performing an ion implantation process to form a source and a drain in the first region and the second region of the substrate; and First gates are formed on the first region of the substrate. The first gates and the source electrodes and the drain electrodes in the first region constitute the first semiconductor elements.

3. The semiconductor manufacturing process for forming a gate dielectric layer as described in claim 2 further includes forming a second gate on the second region after the high dielectric constant dielectric layer is formed, and the second gates and the source electrodes and the drain electrodes in the second region constitute a second semiconductor element, wherein the native oxide layer and the high dielectric constant dielectric layer together serve as the gate dielectric layer of the second semiconductor elements. 4 . The semiconductor manufacturing process for forming a gate dielectric layer as claimed in claim 3 , wherein the second gates are formed by a self-alignment method.

5. The semiconductor manufacturing process for forming a gate dielectric layer as claimed in claim 3, wherein the second semiconductor devices are ion-sensitive field-effect transistors (ISFETs).

6. The semiconductor manufacturing process for forming a gate dielectric layer as claimed in claim 1, further comprising forming a passivation layer on the dielectric layer and the back-end metal interconnect structure after the back-end metal interconnect structure is formed and before the photolithography manufacturing process is performed. 7 . The semiconductor process for forming a gate dielectric layer as claimed in claim 6 , wherein the photolithography process removes a portion of the passivation layer.

8. A semiconductor device having a double gate dielectric layer, comprising: substrate; A native oxide layer, located on the substrate, wherein the native oxide layer is formed by an oxygen plasma manufacturing process after the back-end metal interconnect structure is formed; A high-k dielectric layer is located on the native oxide layer; a gate disposed on the high-k dielectric layer; and The source and the drain are respectively located in the substrate at two sides of the gate, wherein the native oxide layer and the high dielectric constant dielectric layer are used together as a gate dielectric layer. 9 . The semiconductor device with a double gate dielectric layer as claimed in claim 8 , wherein the material of the native oxide layer is silicon dioxide, and the material of the high-k dielectric layer is hafnium dioxide.

10. The semiconductor device with a double gate dielectric layer as claimed in claim 8, wherein the semiconductor device is an ion-sensitive field-effect transistor (ISFET).

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