Semiconductor structure and method of manufacturing the same, memory

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof and a memory, and relates to the technical field of semiconductor technology, and aims to solve the technical problem of poor control ability of a gate on a channel, the semiconductor structure comprising a columnar first gate, a semiconductor layer and a ring-shaped second gate, the first gate extending along a first direction; the semiconductor layer covering at least part of the outer circumferential surface of the first gate; the second gate covering at least part of the outer circumferential surface of the semiconductor layer; the projection area of the second gate on the semiconductor layer being a channel region; wherein the regions on both sides of the channel region in the semiconductor layer are a source region and a drain region respectively; and a gate dielectric layer is arranged between the first gate and the semiconductor layer and between the second gate and the semiconductor layer. Through the arrangement of the double gates, the control ability of the gate on the channel region can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor structure, a preparation method thereof, and a memory. BACKGROUND

[0002] A semiconductor structure is usually arranged on an electronic device such as a memory or a controller, and the semiconductor structure includes a transistor for realizing functions such as switching and amplification. In the related art, the transistor includes an active structure and a gate electrode, the active structure includes a channel region and source and drain regions located on both sides of the channel region, and the gate electrode is arranged on the channel region and at least covers the channel region in projection on the active structure. However, the above-mentioned gate electrode has poor control ability on the channel region. SUMMARY

[0003] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, and a memory, to improve the control ability of a gate electrode on a channel region.

[0004] A first aspect of embodiments of the present disclosure provides a semiconductor structure, comprising: a transistor, the transistor comprising:

[0005] a first gate electrode in a column shape, the first gate electrode extending along a first direction;

[0006] a semiconductor layer, the semiconductor layer covering at least part of an outer peripheral surface of the first gate electrode;

[0007] a second gate electrode in a ring shape, the second gate electrode covering at least part of an outer peripheral surface of the semiconductor layer; a region of the semiconductor layer in projection on the second gate electrode is a channel region; wherein regions of the semiconductor layer located on both sides of the channel region are respectively a source region and a drain region; and a gate dielectric layer is arranged between the first gate electrode and the semiconductor layer and between the second gate electrode and the semiconductor layer.

[0008] In some embodiments, along the first direction, the first gate electrode includes oppositely arranged first and second end surfaces; and the semiconductor layer further covers the first end surface of the first gate electrode.

[0009] The semiconductor structure further comprises first and second contact structures, the first and second contact structures are respectively located on both sides of the second gate electrode along the first direction and are arranged in insulation with the second gate electrode and the first gate electrode; wherein one of the first and second contact structures is connected with the source region, and the other is connected with the drain region.

[0010] In some embodiments, the semiconductor layer includes a main body portion, a first extension portion, and a second extension portion, the first extension portion and the second extension portion are both connected with the main body portion; the main body portion covers at least a part of the outer circumferential surface of the first gate electrode, the second gate electrode covers at least a part of the outer circumferential surface of the main body portion; and the second gate electrode projects onto the channel region of the main body portion.

[0011] The first extension portion covers the first end surface of the first gate electrode.

[0012] The second gate electrode includes a first surface and a second surface opposite to each other along the first direction, the first surface corresponds to the first end surface; wherein the second extension portion is located on one side of the second surface of the second gate electrode, or respectively on one side of the first surface and the second surface, and is connected with the first contact structure or the second contact structure.

[0013] In some embodiments, the gate medium layer includes a first gate medium layer and a second gate medium layer.

[0014] The first gate medium layer is located between the semiconductor layer and the first gate electrode, and covers at least the outer circumferential surface of the first gate electrode.

[0015] The second gate medium layer is located between the semiconductor layer and the second gate electrode, and covers the main body portion of the semiconductor layer.

[0016] A medium layer is arranged between the first contact structure and the second gate electrode, and between the second contact structure and the second gate electrode.

[0017] In some embodiments, the materials of the semiconductor layer, the first contact structure, and the second contact structure all include indium gallium zinc oxide.

[0018] A second aspect of the embodiments of the present disclosure provides a preparation method of a semiconductor structure, including the following steps:

[0019] forming a laminated structure, the laminated structure includes a first material layer, a first conductive material layer, and a second material layer which are sequentially stacked; the first material layer and the second material layer are both insulated from the first conductive material layer;

[0020] removing part of the first conductive material layer and part of the second material layer to form a groove in the laminated structure, the groove exposes part of the first material layer; wherein the remaining first conductive material layer constitutes a second gate electrode, one of the first material layer and the remaining second material layer forms a first contact structure, and the other forms a second contact structure.

[0021] forming a semiconductor layer, a gate dielectric layer and a first gate electrode in the trench; wherein the semiconductor layer covers at least part of the outer circumferential surface of the first gate electrode, and the second gate electrode covers at least part of the outer circumferential surface of the semiconductor layer, and the region opposite to the semiconductor layer and the second gate electrode is a channel region, the regions on both sides of the channel region are a source region and a drain region respectively, and the gate dielectric layer is between the first gate electrode and the semiconductor layer and between the second gate electrode and the semiconductor layer respectively; one of the first contact structure and the second contact structure is connected with the source region, and the other is connected with the drain region.

[0022] In some embodiments, the gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer; and the step of forming the semiconductor layer and the gate dielectric layer in the trench comprises:

[0023] forming a first gate dielectric layer on the sidewall of the trench;

[0024] forming a semiconductor layer, which covers the bottom wall of the trench which is not covered, the first gate dielectric layer and the first contact structure or the second contact structure above the second gate electrode; wherein the semiconductor layer on the first gate dielectric layer constitutes a main body, the semiconductor layer on the bottom wall of the trench constitutes a first extension, and the semiconductor layer on the first contact structure or the second contact structure above the second gate electrode constitutes a second extension;

[0025] forming a second gate dielectric layer, which covers the semiconductor layer.

[0026] In some embodiments, the step of forming the first gate electrode comprises:

[0027] forming a second conductive material layer, which covers the region surrounded by the second gate dielectric layer and fills the region surrounded by the second gate dielectric layer;

[0028] removing part of the second conductive material layer, and the second conductive material layer remaining in the region surrounded by the second gate dielectric layer constitutes the first gate electrode.

[0029] In some embodiments, after the step of forming the stack structure and before the step of removing part of the first conductive material layer and the second material layer, the method further comprises:

[0030] rapid thermal annealing the stack structure at a preset temperature.

[0031] A third aspect of the embodiments of the present disclosure provides a memory comprising the semiconductor structure of the first aspect.

[0032] The semiconductor structure and the preparation method thereof and the memory provided by the embodiments of the present disclosure can increase the thickness of the inversion layer, improve the control ability of the first gate and the second gate on the channel region, and reduce the power consumption of the transistor.

[0033] In addition to the technical problems solved by the embodiments of the present disclosure described above, the technical features constituting the technical solutions, and the beneficial effects brought by these technical features, other technical problems solved by the semiconductor structure and the preparation method thereof and the memory provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0035] Figure 1 Schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure Figure 1 ;

[0036] Figure 2 Schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure Figure 2 ;

[0037] Figure 3 Process flow chart of the preparation method of the semiconductor structure provided by the embodiments of the present disclosure

[0038] Figure 4 Schematic diagram after forming the stack structure in the preparation method of the semiconductor structure provided by the embodiments of the present disclosure

[0039] Figure 5 Schematic diagram after forming the trench in the preparation method of the semiconductor structure provided by the embodiments of the present disclosure

[0040] Figure 6 Schematic diagram after forming the gate dielectric material layer in the preparation method of the semiconductor structure provided by the embodiments of the present disclosure

[0041] Figure 7A schematic diagram of the semiconductor structure after forming a second gate dielectric layer in the method for preparing the semiconductor structure according to an embodiment of the present disclosure;

[0042] Figure 8 A schematic diagram of a method for preparing a semiconductor structure according to an embodiment of the present disclosure after forming a semiconductor layer;

[0043] Figure 9 This is a schematic diagram after forming a first gate dielectric layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0044] Figure 10 This is a schematic diagram of the semiconductor structure manufacturing method provided in an embodiment of the present disclosure after the second conductive material layer is formed.

[0045] Reference numerals:

[0046] 100: transistor; 110: first gate; 111: first end surface; 112: second end surface; 113: second conductive material layer; 120: semiconductor layer; 121: main body; 122: first extension; 123: second extension; 130: second gate; 131: first surface; 132: second surface; 141: first gate dielectric layer; 411: gate dielectric material layer; 142: second gate dielectric layer;

[0047] 200: substrate; 300: first contact structure; 400: second contact structure; 500: dielectric layer; 600: stacked structure; 610: first material layer; 620: dielectric material layer; 630: first conductive material layer; 640: second material layer; 650: trench. DETAILED DESCRIPTION

[0048] As described in the background technology, there is a problem in the related technology that the gate of the transistor has poor control over the channel region. The inventors have found that the reason for this problem is that current transistors are usually single-gate. When voltage is applied to the gate, an inversion layer of a certain thickness is formed on the side of the channel region close to the gate. The thickness of the inversion layer is relatively small, resulting in poor control of the gate over the channel region, which increases the power consumption of the transistor.

[0049] In response to the above technical problems, the embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, wherein a first gate and a second gate are respectively arranged on both sides of a semiconductor layer perpendicular to a first direction. When voltage is applied to the first gate and the second gate, an inversion layer of a certain thickness is formed on the side of the semiconductor layer close to the first gate, and an inversion layer of a certain thickness is formed on the side of the semiconductor layer close to the second gate. In this way, the thickness of the inversion layer can be increased, the control ability of the first gate and the second gate over the channel region can be improved, and the power consumption of the transistor can be reduced.

[0050] In order to make the above objectives, characteristics and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative labor shall fall within the protection scope of the present disclosure.

[0051] The accompanying drawings are referred to in the description of the embodiments of the present disclosure. Figure 1 The embodiments of the present disclosure provide a semiconductor structure, comprising a transistor 100, wherein the transistor 100 comprises a first gate 110, a semiconductor layer 120 and a second gate 130. The first gate 110 comprises a columnar structure, and the first gate 110 extends along a first direction, that is, the first direction is the axis direction of the first gate 110. It should be noted that if the transistor 100 is arranged along the vertical direction, the first direction is the vertical direction, that is, the Z direction in the accompanying drawings; if the transistor 100 is arranged along the horizontal direction, the first direction is the X direction or the Y direction in the accompanying drawings. Figure 1 Figure 1

[0052] The semiconductor layer 120 covers at least part of the outer circumferential surface of the first gate 110, that is, the semiconductor layer covers part of the outer circumferential surface of the first gate 110, and can also cover the entire outer circumferential surface of the first gate 110. In this way, the transistor formed by the first gate 110 and the semiconductor layer 120 can be a Gate-Channel All-Around (GCAA) transistor.

[0053] The second gate 130 is a ring structure, and the second gate 130 covers at least part of the outer circumferential surface of the semiconductor layer 120; when the second gate 130 covers part of the outer circumferential surface of the semiconductor layer 120, the transistor defined by the second gate 130 and the semiconductor layer 120 is a semi-ring gate structure; when the second gate 130 covers the entire outer circumferential surface of the semiconductor layer 120, the transistor defined by the second gate 130 and the semiconductor layer 120 is a Gate-All-Around (GAA) transistor.

[0054] The region of the semiconductor layer 120 corresponding to the second gate 130 is a channel region, in other words, the projection region of the second gate 130 on the semiconductor layer 120 is a channel region. The regions of the semiconductor layer 120 located on both sides of the channel region are source and drain regions.

[0055] ​​The gate dielectric layer is arranged between the first gate electrode 110 and the semiconductor layer 120, and between the second gate electrode 130 and the semiconductor layer 120. One of the gate dielectric layers separates the first gate electrode 110 from the semiconductor layer 120, and the other of the gate dielectric layers separates the second gate electrode 130 from the semiconductor layer 120.

[0056] The material of the gate dielectric layer can be a conventional insulating material, for example, the material of the gate dielectric layer includes at least one of silicon dioxide (SiO2), silicon nitride (SiN) and graphene. The material of the gate dielectric layer can also have a high dielectric constant, for example, the material of the gate dielectric layer includes hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3). In this way, the direct tunneling of electrons through the gate dielectric layer to generate gate leakage current can be effectively avoided, which is beneficial to reducing the thickness of the gate dielectric layer and meeting the requirement of reducing the process size, and provides a guarantee for the development of the semiconductor structure or the memory cell towards the integrated direction.

[0057] The first gate electrode 110 and the second gate electrode 130 are respectively located on two sides of the semiconductor layer 120 in a direction perpendicular to the first direction, i.e. perpendicular to the axis direction of the first gate electrode 110. When the first gate electrode 110 and the second gate electrode 130 are respectively applied with a voltage, a certain thickness of inversion layer is formed on the side of the semiconductor layer 120 close to the first gate electrode 110, and a certain thickness of inversion layer is formed on the side of the semiconductor layer 120 close to the second gate electrode 130. In this way, the thickness of the inversion layer can be increased, and even the thickness of the inversion layer is equal to the thickness of the entire semiconductor layer 120, so as to improve the control ability of the first gate electrode 110 and the second gate electrode 130 on the channel region, and reduce the power consumption of the semiconductor structure.

[0058] In addition, the semiconductor layer 120 can be a metal oxide semiconductor layer. In a first aspect, the metal oxide semiconductor layer has a high carrier mobility, which can greatly improve the sensitivity of the transistor and reduce the power consumption of the storage unit. When the transistor is in an on state, a high-carrier-mobility inversion layer can be formed in the channel region of the semiconductor layer 120, which improves the switching speed of the transistor and thus improves the read-write operation rate of the storage unit. In a second aspect, the transistor using the metal oxide semiconductor layer has a large saturation current, so the volume of the transistor can be reduced, thereby reducing the volume of the storage unit and improving the integration of the memory. In a third aspect, the transistor using the metal oxide semiconductor layer has a small off-state current, and when the transistor is in an off state, the carrier loss rate in the capacitor is slow, so the stability of the storage unit is good. In addition, when the carrier loss rate in the capacitor is slow, the time interval between two refreshes of the storage unit can be extended, thereby reducing the power consumption of the storage unit. In a fourth aspect, the transistor using the metal oxide semiconductor layer has a large switching current, and the current changes quickly from the off state to the on state, which can improve the switching speed of the transistor and improve the read-write operation efficiency of the storage unit. In summary, in the embodiments of the present disclosure, when the channel layer includes a metal oxide semiconductor layer, the electrical performance of the transistor can be improved, thereby improving the storage performance of the storage unit and improving the storage performance and integration of the memory.

[0059] In the present example, the material of the semiconductor layer 120 can include at least one of indium gallium zinc oxide (InGaZnO, referred to as IGZO), indium tin oxide (ITO), indium tungsten oxide (InWO), indium zinc oxide (InZnO), gallium oxide (GaOx), and indium oxide (InOx). In an example, the material of the semiconductor layer 120 is indium gallium zinc oxide (IGZO), in which the indium and zinc elements can improve the mobility of the carriers in the semiconductor layer 120, and the gallium element can also adjust other parameters of the transistor, such as the threshold voltage of the transistor, thereby enabling the transistor to have better overall performance.

[0060] In some possible examples, along the first direction, the first gate 110 includes oppositely arranged first and second end surfaces 111 and 112; when the first gate 110 is vertically arranged, the first end surface 111 can be one of the upper and lower surfaces of the first gate 110, and the second end surface 112 can be the other of the upper and lower surfaces of the first gate 110. As an example, the first end surface 111 can be the lower surface of the first gate 110, and the second end surface 112 can be the upper surface of the first gate 110.

[0061] The semiconductor layer 120 also covers the first end surface of the first gate 110, which can increase the contact area between the semiconductor layer 120 and the first gate 110 and improve the load-bearing capacity of the semiconductor layer 120.

[0062] It should be noted that the semiconductor structure further comprises a substrate 200, and the first gate 110, the semiconductor layer 120 and the second gate 130 are all disposed on the substrate 200, so that the substrate 200 can provide support for the above structure. The first end surface 111 is located between the substrate 200 and the second end surface 112. In this embodiment, the substrate 200 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate, etc.

[0063] The semiconductor structure further comprises a first contact structure 300 and a second contact structure 400. In the first direction, the first contact structure 300 and the second contact structure 400 are respectively located on both sides of the second gate 130 and are disposed in an insulating manner with the second gate 130 and the first gate 110. The first contact structure 300 can be located above the second gate 130 or below the second gate 130.

[0064] Exemplarily, a dielectric layer 500 is disposed between the first contact structure 300 and the second gate 130 and between the second contact structure 400 and the second gate 130, and the material of the dielectric layer 500 comprises silicon oxide, but is not limited thereto.

[0065] One of the first contact structure 300 and the second contact structure 400 is connected with the source region, and the other is connected with the drain region. In an example, when the first contact structure 300 is connected with the source region, the second contact structure 400 is correspondingly connected with the drain region. When the first contact structure 300 is connected with the drain region, the second contact structure 400 is correspondingly connected with the source region.

[0066] The first contact structure 300 and the second contact structure 400 are used to apply signals to the transistor 100. It should be noted that in this embodiment, the transistor 100 can be used as part of a storage unit. When the storage unit is a 1T1C structure, one of the first contact structure 300 and the second contact structure 400 is used for bit line connection, and the other is used for connection with a capacitor. When the storage unit is a 2T0C structure, and the transistor is used as a write transistor, one of the first contact structure 300 and the second contact structure 400 is used for bit line connection, and the other is used for connection with the gate of a read-in transistor.

[0067] In the embodiment, the material of the first contact structure 300 and the material of the second contact structure 400 are indium gallium zinc oxide (IGZO), which can improve the signal transmission speed between the first contact structure 300 and the transistor 100 and between the second contact structure 400 and the transistor 100, and improve the performance of the semiconductor structure.

[0068] In some possible examples, the semiconductor layer 120 includes a main body part 121, a first extension part 122, and a second extension part 123, the first extension part 122 and the second extension part 123 are respectively located on two sides of the main body part 121 and are both connected with the main body part 121.

[0069] The main body part 121 can include a hollow cylindrical structure with an upper opening and a lower opening, and at least part of the first gate electrode 110 is arranged in the main body part 121, so that the main body part 121 covers at least part of the outer circumferential surface of the first gate electrode 110. In other words, the top surface of the first gate electrode 110 can be substantially flush with the top surface of the main body part 121, or can be higher than the top surface of the main body part 121.

[0070] The second gate electrode 130 covers at least part of the outer circumferential surface of the main body part 121, and the projection area of the second gate electrode 130 on the main body part 121 is the channel region. That is, the region corresponding to the second gate electrode 130 in the main body part 121 is the channel region. In order to clearly describe the position of the channel region, the main body part 121 in the region within the dashed line frame is marked as the channel region. Figure 1 The main body part 121 in the region within the dashed line frame is marked as the channel region.

[0071] The first extension part 122 is arranged at the end of the main body part 121 close to the substrate 200 and covers the first end surface 111 of the first gate electrode 110, and the second extension part 123 is arranged at the end of the main body part 121 away from the substrate 200. The region of the main body part 121 connected with the first extension part 122 and the first extension part 122 constitute one of the source region and the drain region, and the region of the main body part 121 connected with the second extension part 123 and the second extension part 123 constitute the other of the source region and the drain region.

[0072] The second gate electrode 130 includes a first surface 131 and a second surface 132 opposite to each other in the first direction, and the first surface 131 corresponds to the first end surface 111. For example, if the first end surface 111 is the surface of the first gate electrode 110 close to the substrate 200, the first surface 131 is the surface of the second gate electrode 130 close to the substrate 200.

[0073] The second extension part 123 is located on one side of the second surface 132 of the second gate electrode 130, or is respectively located on one side of the first surface 131 and the second surface 132, and is connected with the first contact structure 300 or the second contact structure 400.

[0074] In an example, please refer to the accompanyingFigure 1 The second extension 123 is located on one side of the second surface 132 of the second gate 130, that is, the second extension 123 is connected with the end of the main body 121 away from the substrate 200.

[0075] The second extension 123 covers the surface of the first contact structure 300 or the second contact structure 400 away from the second gate 130 located on the second surface 132; it should be understood that when the first contact structure 300 is located above the second surface 132 of the second gate 130, correspondingly, the second extension 123 covers the surface of the first contact structure 300 away from the second gate 130. When the second contact structure 400 is located above the second surface 132 of the second gate 130, correspondingly, the second extension 123 covers the surface of the second contact structure 400 away from the second gate 130.

[0076] The surface of the second extension 123 away from the second gate 130 is lower than the second end surface 112, which is configured to set the gate dielectric layer between the surface of the second extension 123 away from the second gate 130 and the second end surface 112, prevent the first gate 110 from being in contact and electrically connected with the second extension 123, and improve the yield of the transistor.

[0077] In another example, please refer to the accompanying drawings Figure 2 The second extension 123 is located on one side of the first surface 131 and the second surface 132 of the second gate 130, respectively, and is connected with the first contact structure 300 and the second contact structure 400, respectively.

[0078] The number of the second extension 123 is two, and the two second extensions 123 are located on two sides of the second gate 130, for example, one of the second extensions 123 is arranged on the first surface 131 of the second gate 130 and covers part of the surface of the first contact structure 300 or the second contact structure 400 facing the second gate 130. The second extension 123 is connected with the first extension 122 and covers the entire surface of the first contact structure 300 or the second contact structure 400 facing the second gate 130, which can improve the contact area of the source region or the drain region of the semiconductor layer 120 with the first contact structure 300 or the second contact structure 400, thereby reducing the contact resistance of the source region or the drain region of the semiconductor layer 120 with the first contact structure 300 or the second contact structure 400, and improving the performance of the semiconductor structure.

[0079] Another second extension 123 is arranged on the second surface 132 of the second gate 130 and covers the surface of the first contact structure 300 or the second contact structure 400 facing away from the second gate 130. In this way, the contact area between the source region or the drain region of the semiconductor layer 120 and the first contact structure 300 or the second contact structure 400 can be increased, thereby reducing the contact resistance between the source region or the drain region of the semiconductor layer 120 and the first contact structure 300 or the second contact structure 400, and improving the performance of the semiconductor structure.

[0080] Please continue to refer to the accompanying drawings Figure 1 For the convenience of describing the positional relationship between the gate dielectric layer and the semiconductor layer 120, the gate dielectric layer is further refined. For example, the gate dielectric layer includes a first gate dielectric layer 141 and a second gate dielectric layer 142.

[0081] The first gate dielectric layer 141 is located between the semiconductor layer 120 and the first gate 110 and covers the outer surface and the first end surface 111 of the first gate 110. In other words, the shape of the first gate dielectric layer 141 matches the shape of the semiconductor layer 120, that is, the first gate dielectric layer 141 covers the semiconductor layer 120, or in other words, the first gate dielectric layer 141 can also include a main body, a first extension and a second extension. The main body of the first gate dielectric layer 141 corresponds to the main body 121 of the semiconductor layer 120, the first extension of the first gate dielectric layer 141 corresponds to the first extension 122 of the semiconductor layer 120, and the second extension of the first gate dielectric layer 141 corresponds to the second extension 123 of the semiconductor layer 120.

[0082] The second gate dielectric layer 142 is located between the semiconductor layer 120 and the second gate 130 and covers part of the outer surface of the semiconductor layer 120, that is, the second gate dielectric layer 142 covers the outer surface of the main body 121 of the semiconductor layer 120.

[0083] Please refer to the accompanying drawings Figure 3 The present disclosure also provides a preparation method of a semiconductor structure, including the following steps:

[0084] Step S100: forming a laminated structure, the laminated structure includes a first material layer, a first conductive material layer and a second material layer arranged in sequence; the first material layer and the second material layer are both insulated from the first conductive material layer.

[0085] It should be noted that the laminated structure 600 of this step can be arranged on the substrate 200, and the substrate 200 provides support for the laminated structure.

[0086] For example, please refer to the accompanying drawings Figure 4The first material layer 610, the dielectric material layer 620, the first conductive material layer 630, the dielectric material layer 620 and the second material layer 640 can be sequentially formed on the substrate 200 by a deposition process. The first material layer 610 is disposed on the substrate 200.

[0087] The material of the first material layer 610 and the material of the second material layer 640 are the same, and both include indium gallium zinc oxide (IGZO). The material of the first conductive material layer 630 can include a metal material, for example, tungsten.

[0088] The substrate 200 and the stacked structure 600 are subjected to rapid thermal annealing at a preset temperature. The substrate 200 and the stacked structure 600 are subjected to rapid thermal annealing at 350-450°C, for example, at 400°C, to refine the grains of the film layers in the stacked structure 600 and improve the density of the film layers in the stacked structure 600. In this embodiment, the stacked structure 600 is subjected to rapid thermal annealing for about one minute, which avoids over-oxidation of the stacked structure 600 and the substrate 200 and improves the performance of the formed semiconductor structure.

[0089] In step S200, part of the first conductive material layer and the second material layer are removed to form a trench in the stacked structure, and the trench exposes the first material layer. The remaining first conductive material layer forms a second gate electrode, and one of the first material layer and the remaining second material layer forms a first contact structure, and the other forms a second contact structure.

[0090] For example, referring to FIG. 6, the second material layer 640, the dielectric material layer 620, the first conductive material layer 630 and the dielectric material layer 620 located below the first conductive material layer 630 are removed by a patterning process to form a trench 650 in the stacked structure 600, and the trench 650 exposes the first material layer 610. Figure 5 The trench 650 has a bottom located at the top surface of the first material layer 610 or in the first material layer 610.

[0091] The remaining first conductive material layer 630 forms a second gate electrode 130, one of the first material layer 610 and the remaining second material layer 640 forms a first contact structure 300, and the other forms a second contact structure 400. The remaining dielectric material layer 620 forms two dielectric layers 500, one of which is disposed between the second gate electrode 130 and the first contact structure 300, and the other is disposed between the second gate electrode 130 and the second contact structure 400.

[0092] Step S300: forming a semiconductor layer, a gate dielectric layer and a first gate in the trench; wherein the semiconductor layer covers at least a portion of the outer peripheral surface of the first gate, and the second gate covers at least a portion of the outer peripheral surface of the semiconductor layer, and the area opposite to the semiconductor layer and the second gate is a channel region, the areas on both sides of the channel region are the source region and the drain region, respectively, and the gate dielectric layer is respectively located between the first gate and the second gate and the semiconductor layer; one of the first contact structure and the second contact structure is connected to the source region, and the other is connected to the drain region.

[0093] In this embodiment, the gate dielectric layer includes a first gate dielectric layer 141 and a second gate dielectric layer 142. The first gate dielectric layer 141 is located between the second gate electrode 130 and the semiconductor layer 120 (see the attached FIG. Figure 1 ), the second gate dielectric layer 142 is located between the semiconductor layer 120 and the first gate 110 (please refer to the attached Figure 1 )between.

[0094] Please refer to the attached Figure 6 and attached Figure 7 , a first gate dielectric layer 141 is formed on the sidewalls of the trench 650. Exemplarily, a gate dielectric material layer 411 is formed on the inner wall of the trench 650 using an atomic layer deposition process. The gate dielectric material layer 411 also covers the top surface of the first contact structure 300 or the second contact structure 400. In one example, the gate dielectric material layer 411 covers the top surface of the first contact structure 300.

[0095] Afterwards, an etching process is used to remove the top surface of the first contact structure 300 or the second contact structure 400 and the gate dielectric material layer 411 on the bottom wall of the trench 650 , and the gate dielectric material layer 411 on the sidewall of the trench 650 is retained to form the first gate dielectric layer 141 .

[0096] Afterwards, please refer to the attached Figure 8 The semiconductor layer 120 is formed using an atomic layer deposition process, wherein the semiconductor layer covers the uncovered bottom wall of the trench 650, the first gate dielectric layer 141, and the first contact structure 300 or the second contact structure 400 located above the second gate 130. In other words, when the first contact structure 300 is located above the second gate 130, the semiconductor layer 120 accordingly covers the first contact structure 300; when the second contact structure 400 is located above the second gate 130, the semiconductor layer 120 accordingly covers the second contact structure 400.

[0097] Among them, the semiconductor layer 120 located on the first gate dielectric layer 141 constitutes the main body 121, the semiconductor layer 120 located on the bottom wall of the trench 650 constitutes the first extension portion 122, and the semiconductor layer 120 located on the first contact structure 300 or the second contact structure 400 above the second gate 130 constitutes the second extension portion 123.

[0098] The area of ​​the main body 121 corresponding to the second gate 130 is the channel area, that is, the projection area of ​​the second gate 130 on the semiconductor layer 120 is the channel area. Figure 8 The area of ​​the central body portion 121 within the dashed box is the channel region, and the areas on either side of the channel region are the source region and the drain region, respectively. In one example, the source region can be formed by the second extension portion 123 and the portion of the central body portion 121 connected to the second extension portion 123, and the drain region can be formed by the first extension portion 122 and the portion of the central body portion 121 connected to the first extension portion 122.

[0099] Afterwards, please refer to the attached Figure 9 A second gate dielectric layer 142 is formed by an atomic layer deposition process. The second gate dielectric layer 142 covers the semiconductor layer 120 , that is, the second gate dielectric layer 142 conformally covers the semiconductor layer 120 .

[0100] Afterwards, please refer to the attached Figure 10 , forming a second conductive material layer 113, the second conductive material layer 113 covers the area surrounded by the second gate dielectric layer 142, and fills the area surrounded by the second gate dielectric layer 142.

[0101] Please continue to refer to the attached Figure 1 The second conductive material layer 113 is partially removed, for example, by etching or chemical mechanical polishing to remove the second conductive material layer 113 located on the top surface of the second gate dielectric layer 142. The second conductive material layer 113 remaining in the region enclosed by the second gate dielectric layer 142 forms the first gate 110. The top surface of the first gate 110 is flush with the top surface of the second gate dielectric layer 142.

[0102] The semiconductor structure formed by the fabrication method provided by the embodiments of the present disclosure has a dual gate, that is, it includes both a first gate 110 and a second gate 130, with the first gate 110 and the second gate 130 located on either side of the semiconductor layer 120. When voltages are applied to the first gate 110 and the second gate 130, an inversion layer of a certain thickness forms on the side of the semiconductor layer 120 near the first gate 110, and an inversion layer of a certain thickness forms on the side of the semiconductor layer 120 near the second gate 130. This increases the thickness of the inversion layer, improves the control capability of the first gate 110 and the second gate 130 over the channel region, and reduces power consumption.

[0103] It should be noted that when the number of the second extension 123 is two, the structure can refer to the structure shown in FIG. 6A when the second extension 123 needs to cover the first contact structure 300 and the second contact structure 400. Figure 2 At this time, when the stack structure 600 is deposited, a semiconductor material layer with a certain thickness needs to be deposited between the first material layer 610 and the dielectric material layer 620, and then the semiconductor structure is formed according to the preparation method described above.

[0104] The embodiments of the present disclosure also disclose a memory, which can include a plurality of repeated memory cells, wherein each memory cell includes at least one semiconductor structure described in any of the above embodiments.

[0105] It should be understood that the memory cell of the memory in the embodiments of the present disclosure can include one transistor and one capacitor (1T1C structure), and the transistor is the semiconductor structure described in any of the above embodiments.

[0106] The memory cell of the memory can also include two transistors (2T0C), and at least one of the two transistors is the semiconductor structure described in any of the above embodiments.

[0107] Since the memory includes the semiconductor structure described in any of the above embodiments, the memory has the beneficial effects of the semiconductor structure described in any of the above embodiments, and the embodiments will not be described here.

[0108] In the description of the present specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0109] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0110] In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0111] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, and are not intended to limit the present disclosure; although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that A transistor is included, the transistor comprising: a first columnar gate extending along a first direction and including a first end surface and a second end surface opposite to each other along the first direction; a semiconductor layer, wherein the semiconductor layer covers at least a portion of an outer peripheral surface of the first gate and covers a first end surface of the first gate; an annular second gate, the second gate covering at least a portion of an outer peripheral surface of the semiconductor layer; a projected area of ​​the second gate on the semiconductor layer forming a channel region; wherein regions of the semiconductor layer located on either side of the channel region are a source region and a drain region, respectively; and a gate dielectric layer is disposed between the first gate and the semiconductor layer, and between the second gate and the semiconductor layer; In which, the semiconductor structure also includes a first contact structure and a second contact structure. Along the first direction, the first contact structure and the second contact structure are respectively located on both sides of the second gate and are insulated from the second gate and the first gate; wherein, one of the first contact structure and the second contact structure is connected to the source region, and the other is connected to the drain region.

2. The semiconductor structure according to claim 1, wherein: The semiconductor layer includes a main portion, a first extension portion, and a second extension portion, wherein the first extension portion and the second extension portion are both connected to the main portion; the main portion covers at least a portion of an outer circumference of the first gate, and the second gate covers at least a portion of an outer circumference of the main portion; and the second gate forms a channel region in an area projected by the main portion; The first extension portion covers the first end surface of the first gate; The second gate includes a first surface and a second surface opposite to each other along the first direction, and the first surface corresponds to the first end surface; wherein the second extension portion is located on one side of the second surface of the second gate, or is located on one side of the first surface and the second surface respectively, and is connected to the first contact structure or the second contact structure.

3. The semiconductor structure according to claim 2, wherein: The gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer; The first gate dielectric layer is located between the semiconductor layer and the first gate and covers at least the outer peripheral surface of the first gate; The second gate dielectric layer is located between the semiconductor layer and the second gate and covers the main body of the semiconductor layer; A dielectric layer is provided between the first contact structure and the second gate, and between the second contact structure and the second gate.

4. The semiconductor structure according to claim 3, wherein: Materials of the semiconductor layer, the first contact structure, and the second contact structure all include indium gallium zinc oxide.

5. A method for preparing a semiconductor structure, characterized in that: The steps include: forming a stacked structure, the stacked structure comprising a first material layer, a first conductive material layer, and a second material layer stacked in sequence; the first material layer and the second material layer are both insulated from the first conductive material layer; removing a portion of the first conductive material layer and a portion of the second material layer to form a trench in the stacked structure, wherein the trench exposes a portion of the first material layer; wherein the retained first conductive material layer constitutes a second gate, and one of the first material layer and the retained second material layer forms a first contact structure, and the other forms a second contact structure; A semiconductor layer, a gate dielectric layer and a first gate are formed in the trench; wherein the semiconductor layer covers at least a portion of the outer peripheral surface of the first gate, and the second gate covers at least a portion of the outer peripheral surface of the semiconductor layer, and the area opposite to the semiconductor layer and the second gate is a channel region, the areas on both sides of the channel region are the source region and the drain region, respectively, and the gate dielectric layer is respectively located between the first gate and the second gate and the semiconductor layer; one of the first contact structure and the second contact structure is connected to the source region, and the other is connected to the drain region.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer; The step of forming the semiconductor layer and the gate dielectric layer in the trench comprises: forming a first gate dielectric layer on the sidewalls of the trench; forming a semiconductor layer, the semiconductor layer covering the uncovered bottom wall of the trench, the first gate dielectric layer, and the first contact structure or the second contact structure located above the second gate; wherein the semiconductor layer located on the first gate dielectric layer constitutes a main portion, the semiconductor layer located on the bottom wall of the trench constitutes a first extension portion, and the semiconductor layer located on the first contact structure or the second contact structure located above the second gate constitutes a second extension portion; A second gate dielectric layer is formed, where the second gate dielectric layer covers the semiconductor layer.

7. The method for preparing a semiconductor structure according to claim 6, wherein: The step of forming the first gate includes: forming a second conductive material layer, wherein the second conductive material layer covers the area surrounded by the second gate dielectric layer and completely fills the area surrounded by the second gate dielectric layer; A portion of the second conductive material layer is removed, and the second conductive material layer remaining in the area surrounded by the second gate dielectric layer constitutes the first gate.

8. The method for preparing a semiconductor structure according to claim 7, wherein: After the step of forming the stacked structure and before the step of removing a portion of the first conductive material layer and the second material layer, the method further includes: The stacked structure is subjected to a rapid thermal annealing process at a preset temperature.

9. A memory, characterized in that: The semiconductor structure comprises the semiconductor structure according to any one of claims 1 to 4.

Images