A gallium oxide monolithic heterogeneous integrated device and its manufacturing method

Abstract

This application discloses a single-chip heterogeneous integrated device based on gallium oxide and a manufacturing method thereof, which can be used in the field of semiconductor devices. In this device, an N-type gallium oxide epitaxial wafer includes an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of a P-type material layer; an N-type doped region is disposed within the P-type material layer and contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer; a gate control region covers the N-type doped region and is disposed on the other side of the P-type material layer; an ohmic contact is formed between the source electrode and the P-type material layer; a drain electrode is disposed on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer; and the substrate layer is bonded to the drain electrode. Thus, bonding small-sized gallium oxide to a substrate for tape-out enables large-scale device fabrication on a production line and improves the heat dissipation performance of the gallium oxide device. By bonding the N-type gallium oxide to the P-type material, a heterogeneous PN junction is formed to compensate for the missing gallium oxide homogeneous PN junction, thereby improving the stability of the structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a gallium oxide monolithic heterogeneous integrated device and a manufacturing method thereof. Background Art

[0002] Gallium oxide (Ga2O3) is a new type of ultra-wide bandgap semiconductor material with the advantages of ultra-wide bandgap, ultra-high breakdown field strength, super-transparent conductivity and radiation resistance. It is an ideal material for making high-voltage devices, radio frequency devices and solar-blind ultraviolet detectors.

[0003] Existing gallium oxide wafers are mostly 2-inch and 4-inch, while semiconductor mass production equipment is mostly 6-inch or 8-inch. Therefore, gallium oxide wafers often cannot be used to mass-produce devices on the production line. Moreover, existing gallium oxide transistors lack P-type for effective gate control and can only be implemented using unstable P-type oxides or difficult-to-manufacture fin structures, resulting in complex manufacturing processes and poor stability.

[0004] Therefore, how to prepare highly stable gallium oxide heterojunction integrated devices based on low-difficulty processes under mass production conditions is an urgent problem that technicians in this field need to solve. Summary of the Invention

[0005] Based on the above problems, the present application provides a heterogeneous integrated device based on a gallium oxide monolithic chip and a manufacturing method thereof. By bonding the gallium oxide monolithic chip to a substrate for tape-out, large-scale production of gallium oxide devices on the production line can be achieved. In addition, by bonding N-type gallium oxide to P-type material to form a heterogeneous PN junction to compensate for the missing gallium oxide homogeneous PN junction, the stability of the structure is improved.

[0006] In a first aspect, an embodiment of the present application provides a gallium oxide monolithic heterogeneous integrated device, characterized in that the device comprises: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, an interlayer dielectric, a source, a drain, and a substrate layer; the N-type gallium oxide epitaxial wafer comprises an epitaxial layer and a substrate layer;

[0007] One side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer;

[0008] The N-type doped region is provided in the P-type material layer and contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer;

[0009] The gate control region covers the N-type doping region and is provided on the other side of the P-type material layer;

[0010] The source electrode contacts the N-type doped region and forms an ohmic contact with the P-type material layer, and the source electrode is isolated from the gate electrode by the interlayer dielectric;

[0011] The drain electrode is provided on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer;

[0012] The substrate layer is bonded to the drain electrode.

[0013] Optionally, the N-type doped region includes: a deep-implanted N-type region and a shallow-implanted N-type region;

[0014] The implantation depth of the shallow implanted N-type region does not exceed the thickness of the P-type material layer;

[0015] The implantation depth of the deep implanted N-type region exceeds the thickness of the P-type material layer, and one end thereof contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer.

[0016] Optionally, the gate control region includes: a gate dielectric and a gate metal;

[0017] The gate dielectric, the gate metal and the interlayer dielectric are sequentially arranged on the other side of the P-type material layer;

[0018] The gate dielectric and the interlayer dielectric have the same width and are wider than the gate metal;

[0019] The gate metal covers the deep implantation N-type region and a portion of the shallow implantation N-type region.

[0020] Optionally, the device further comprises: a first electrode;

[0021] The first electrode is disposed on the other side of the interlayer dielectric and contacts the upper surface of the source and a portion of the upper surface of the gate metal.

[0022] Optionally, the substrate layer includes: a high-resistance substrate and a conductive metal layer;

[0023] The conductive metal layer is deposited on the upper surface of the high-resistance substrate, and the other end is bonded to the drain electrode;

[0024] The width of the conductive metal layer is greater than the width of the drain electrode.

[0025] Optionally, the device further comprises: a second electrode;

[0026] The second electrode is disposed on the lower surface of the high-resistance substrate, penetrates the high-resistance substrate, and is connected to the conductive metal layer.

[0027] Optionally, a groove is etched on the upper surface of the high-resistance substrate;

[0028] The width of the groove is greater than the width of the substrate layer outside the N-type gallium oxide epitaxial wafer, and the depth of the groove is less than or equal to the height of the N-type gallium oxide epitaxial wafer.

[0029] In a second aspect, an embodiment of the present application provides a method for manufacturing a gallium oxide monolithic heterogeneous integrated device, characterized in that the method is used to manufacture the gallium oxide monolithic heterogeneous integrated device as described above, and the method includes:

[0030] Provide N-type gallium oxide epitaxial wafers and substrates;

[0031] Bonding a P-type material layer on one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer;

[0032] Etching the upper surface of the substrate to form a groove, and bonding one side of the substrate layer of the N-type gallium oxide epitaxial wafer into the groove;

[0033] forming an N-type doped region in the P-type material layer based on an ion implantation process;

[0034] Based on a deposition process, depositing a first insulating dielectric on the upper surface of the P-type material layer to form a gate dielectric;

[0035] Based on a deposition process, depositing a first metal film on the gate dielectric layer, and performing pattern etching to form a gate;

[0036] Depositing a second insulating dielectric on the gate based on a deposition process to form an interlayer dielectric;

[0037] Pattern-etching the gate dielectric and the interlayer dielectric to expose a portion of the upper surface of the P-type material layer;

[0038] Depositing a second metal film on the pattern-etched areas of the interlayer dielectric and the gate dielectric and annealing the film to form an ohmic contact, which serves as a source electrode;

[0039] Pattern-etching the interlayer dielectric to expose a portion of the upper surface of the gate;

[0040] Depositing a third metal film on the upper surface of the interlayer dielectric and contacting the gate and the source as a first electrode;

[0041] The substrate layer side of the N-type gallium oxide epitaxial wafer and the groove are debonded, and a fourth metal film is deposited on the substrate layer side of the N-type gallium oxide epitaxial wafer and annealed to form an ohmic contact, which serves as a drain.

[0042] Optionally, the method further includes:

[0043] Depositing a fifth metal film on the surface of the groove, and bonding the drain electrode to the fifth metal film;

[0044] The lower surface of the substrate is punched to expose the back surface of the fifth metal film, and metal deposition is continued on the lower surface of the substrate based on a deposition process. The deposited metal contacts the back surface of the fifth metal film and serves as a second electrode.

[0045] It can be seen from the above technical solutions that compared with the existing technology, this application has the following advantages:

[0046] The present application provides a gallium oxide monolithic heterogeneous integrated device comprising: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, an interlayer dielectric, a source, a drain, and a substrate layer; the N-type gallium oxide epitaxial wafer comprises an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer; the N-type doped region is disposed within the P-type material layer and contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer; the gate control region covers the N-type doped region and is disposed on the other side of the P-type material layer; an ohmic contact is formed between the source and the P-type material layer; the drain is disposed on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer; and the substrate layer is bonded to the drain. Thus, bonding the gallium oxide monolithic wafer to the substrate for tape-out enables wafer-scale device fabrication on the production line. Furthermore, by bonding the N-type gallium oxide to the P-type material, a heterojunction is formed to compensate for the missing gallium oxide homojunction, thereby improving the stability of the structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] Figure 1 A schematic structural diagram of a gallium oxide monolithic heterogeneous integrated device provided in an embodiment of the present application;

[0049] Figure 2 A schematic diagram of the structure of an N-type doping region provided in an embodiment of the present application;

[0050] Figure 3 A schematic structural diagram of a gate control region provided in an embodiment of the present application;

[0051] Figure 4 A schematic structural diagram of a first electrode provided in an embodiment of the present application;

[0052] Figure 5 A schematic structural diagram of a substrate layer provided in an embodiment of the present application;

[0053] Figure 6 A schematic structural diagram of a second electrode provided in an embodiment of the present application;

[0054] Figure 7 A schematic structural diagram of a high-resistance substrate provided in an embodiment of the present application;

[0055] Figure 8 A schematic structural diagram of a diode device provided in an embodiment of the present application;

[0056] Figure 9 A schematic structural diagram of a gallium oxide SBD device provided in an embodiment of the present application;

[0057] Figure 10 A schematic structural diagram of another diode device provided for the implementation of this application;

[0058] Figure 11 A flow chart of a method for manufacturing a gallium oxide monolithic heterogeneous integrated device provided in an embodiment of the present application;

[0059] Figure 12 A flowchart of a method for manufacturing a second electrode provided in an embodiment of the present application;

[0060] Figure 13 A schematic diagram of current flow provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] As mentioned above, existing gallium oxide wafers cannot be used for mass production, and the manufacturing process of existing gallium oxide transistor devices is complex and has poor stability. Specifically, existing gallium oxide wafers are mostly 2-inch and 4-inch, while semiconductor mass production line equipment is mostly 6-inch or 8-inch. Therefore, it is often the case that gallium oxide wafers cannot achieve large-scale manufacturing of devices on the production line. Moreover, existing gallium oxide transistor devices lack P-type to achieve effective gate control and can only be implemented using unstable P-type oxide or Fin structures with high process difficulty, resulting in complex manufacturing processes and poor stability of gallium oxide transistor devices.

[0062] To solve the above problems, an embodiment of the present application provides a gallium oxide monolithic heterogeneous integrated device and a manufacturing method thereof, wherein the device includes: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, a source, a drain, and a substrate layer; the N-type gallium oxide epitaxial wafer includes an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer; the N-type doped region is arranged in the P-type material layer and contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer; the gate control region covers the N-type doped region and is arranged on the other side of the P-type material layer; the source electrode penetrates the gate control region and forms an ohmic contact with the P-type material layer; the drain electrode is arranged on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer; and the substrate layer is bonded to the drain electrode.

[0063] Therefore, bonding the gallium oxide monolith to the substrate for tape-out can achieve device-scale preparation of wafers on the production line, and by bonding N-type gallium oxide with P-type material to form a heterogeneous PN junction to compensate for the missing gallium oxide homogeneous PN junction, the stability of the structure is improved.

[0064] It should be noted that the gallium oxide monolithic heterogeneous integrated device and its manufacturing method provided in this application can be applied in the field of semiconductor devices. The above is only an example and does not limit the application field of the gallium oxide monolithic heterogeneous integrated device and its manufacturing method provided in this application.

[0065] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0066] Figure 1 A schematic diagram of the structure of a gallium oxide monolithic heterogeneous integrated device provided in an embodiment of the present application. Figure 1 As shown, the device includes: an N-type gallium oxide epitaxial wafer 100, a P-type material layer 200, an N-type doped region 300, a gate control region 400, an interlayer dielectric 403, a source 500, a drain 600, and a substrate layer 700; the N-type gallium oxide epitaxial wafer includes an epitaxial layer 101 and a substrate layer 102;

[0067] One side of the epitaxial layer 101 of the N-type gallium oxide epitaxial wafer 100 is bonded to one side of the P-type material layer 200 ;

[0068] The N-type doping region 300 is provided in the P-type material layer 200 and contacts the epitaxial layer 101 of the N-type gallium oxide epitaxial wafer 100 ;

[0069] The gate control region 400 covers the N-type doping region 300 and is provided on the other side of the P-type material layer 200;

[0070] The source electrode 500 contacts the N-type doped region and forms an ohmic contact with the P-type material layer 200 , and the source electrode is isolated from the gate electrode by the interlayer dielectric;

[0071] The drain electrode 600 is provided on one side of the substrate layer 102 of the N-type gallium oxide epitaxial wafer 100 and forms an ohmic contact with the substrate layer 102 ;

[0072] The substrate layer 700 is bonded to the drain electrode 600 .

[0073] Specifically, the size of the N-type gallium oxide epitaxial wafer 100 is not limited and can be a 2-inch or 4-inch wafer or a cut piece. It includes a heavily gallium oxide-doped substrate layer 102 and a lightly gallium oxide-doped epitaxial layer 101 with a thickness of 10 to 20 μm. The P-type material in the P-type material layer 200 bonded to the epitaxial layer 101 can be P-Si, P-SiC, or P-GaN. The thickness of the P-type material layer 200 is approximately 1 μm, the same size as the N-type gallium oxide epitaxial wafer 100. The source electrode 500 is made of Ti / Au or Ti / Al.

[0074] Figure 2 A schematic diagram of the structure of an N-type doping region provided in an embodiment of the present application. Figure 2 As shown, the N-type doping region 300 includes: a deep-implanted N-type region 301 and a shallow-implanted N-type region 302; the implantation depth of the shallow-implanted N-type region 302 does not exceed the thickness of the P-type material layer 200;

[0075] The implantation depth of the deep implanted N-type region 301 exceeds the thickness of the P-type material layer 200 , and one end thereof contacts the epitaxial layer 101 of the N-type gallium oxide epitaxial wafer 100 .

[0076] Specifically, two N-type doped regions 300 with different implantation depths are formed in the P-type material through an ion implantation process using N, Si, or P ions, serving as conductive channels. The shallow implantation N-type region 302 has an implantation depth of no more than 1 μm, while the deep implantation N-type region 301 has an implantation depth exceeding 1 μm and contacts the epitaxial layer 101.

[0077] As an embodiment, a device cell includes at least one shallow implantation N-type region 302 and one deep implantation N-type region 301.

[0078] Specifically, the N-type doping region 300 may include two shallow implantation N-type regions 302 and one deep implantation N-type region 301 , wherein the shallow implantation regions 302 are distributed on both sides of the deep implantation N-type region 301 .

[0079] Figure 3 A schematic diagram of the structure of a gate control region provided in an embodiment of the present application. Figure 3 As shown, the gate control region 400 includes: a gate dielectric 401 and a gate metal 402;

[0080] The gate dielectric 401, the gate metal 402 and the interlayer dielectric 403 are sequentially arranged on the other side of the P-type material layer 200;

[0081] The gate dielectric 401 and the interlayer dielectric 403 have the same width, and are wider than the gate metal 402;

[0082] The gate metal 402 covers the deep implantation N-type region 301 and a portion of the shallow implantation N-type region 302 .

[0083] Specifically, a gate dielectric 401, a gate metal 402, and an interlayer dielectric 403 are sequentially deposited above the P-type material layer 200 to a width sufficient to cover the deeply implanted N-type region 301 and a portion of the shallowly implanted N-type region 302. The gate dielectric 401 is an insulating dielectric such as SiO2, Al2O3, or Si3N4; the gate metal 402 is a metallic material such as Al or Ni; and the interlayer dielectric 403 is also an insulating dielectric such as SiO2, Al2O3, or Si3N4. It will be appreciated that the gate dielectric 401 and the interlayer dielectric 403 can be selected from Al2O3 or SiO2, for example, based on density requirements or cost requirements.

[0084] Figure 4 A schematic diagram of the structure of a first electrode provided in an embodiment of the present application. Figure 4 As shown, the device further includes: a first electrode 800;

[0085] The first electrode 800 is disposed on the other side of the interlayer dielectric 403 and contacts the upper surface of the source 500 and a portion of the upper surface of the gate metal 402 .

[0086] Specifically, a thick layer of Ti / Ni / Al is deposited on the source 500 and the interlayer dielectric 403 and patterned to serve as a thickened electrode of the gate and the source 500 , namely, the first electrode 800 .

[0087] Figure 5 A schematic diagram of the structure of a substrate layer provided in an embodiment of the present application. Figure 5 As shown, the substrate layer 700 includes: a high-resistance substrate 701 and a conductive metal layer 702;

[0088] The conductive metal layer 702 is deposited on the upper surface of the high-resistance substrate 701 , and the other end is bonded to the drain electrode 600 ;

[0089] The width of the conductive metal layer 702 is greater than the width of the drain electrode 600 .

[0090] Specifically, the high-resistance substrate 701 can be a Si substrate, a SiC substrate, or sapphire, and can be 6, 8, or 12 inches in size. The conductive metal layer 702 is Al or Cu metal, and is smaller than the high-resistance substrate 701 and larger than the substrate layer 102 .

[0091] Figure 6 A schematic diagram of the structure of a second electrode provided in an embodiment of the present application. Figure 6 The device further includes: a second electrode 900;

[0092] The second electrode 900 is disposed on the lower surface of the high-resistance substrate 701 , passes through the high-resistance substrate 701 , and is connected to the conductive metal layer 702 .

[0093] Specifically, the second electrode 900 can be regarded as an extension of the conductive metal layer 702 , and is also made of Al or Cu metal. It is disposed on the lower surface of the high-resistance substrate 701 , penetrates the high-resistance substrate 701 , and is connected to the conductive metal layer 702 .

[0094] Figure 7 A schematic diagram of the structure of a high-resistance substrate provided in an embodiment of the present application. Figure 7 As shown, a groove is etched on the upper surface of the high-resistance substrate 701;

[0095] The width of the groove is greater than the width of the substrate layer 102 outside the N-type gallium oxide epitaxial wafer 100 , and the depth of the groove is less than or equal to the height of the N-type gallium oxide epitaxial wafer 100 .

[0096] Specifically, the groove shape should be similar to the N-type gallium oxide epitaxial wafer 100 to be bonded, and slightly larger than the N-type gallium oxide epitaxial wafer 100. The groove depth is determined by three factors: the thickness of the high-resistance substrate 701, the thickness of the N-type gallium oxide epitaxial wafer 100, and the wafer thickness limit allowed by the production line equipment. It is typically 300 to 650 μm. The N-type gallium oxide epitaxial wafer 100 must be higher than or flush with the high-resistance substrate 701, and the height from the bottom of the high-resistance substrate 701 to the top of the N-type gallium oxide epitaxial wafer 100 must not exceed the maximum wafer thickness allowed by the process equipment.

[0097] In summary, the gallium oxide monolithic heterogeneous integrated device provided in this application includes: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, an interlayer dielectric, a source, a drain, and a substrate layer; the N-type gallium oxide epitaxial wafer includes an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer; the N-type doped region is disposed within the P-type material layer and contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer; the gate control region covers the N-type doped region and is disposed on the other side of the P-type material layer; an ohmic contact is formed between the source and the P-type material layer; the drain is disposed on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer; and the substrate layer is bonded to the drain. Therefore, bonding the gallium oxide monolithic wafer to the substrate for tape-out can achieve wafer-scale device fabrication on the production line, and by bonding the N-type gallium oxide to the P-type material, a heterogeneous PN junction is formed to compensate for the missing gallium oxide homogeneous PN junction, thereby improving the stability of the structure.

[0098] Figure 8 A schematic diagram of the structure of a diode device provided in an embodiment of the present application. Figure 8 As shown in the figure, based on the above-mentioned technical solution of bonding small-sized epitaxial wafers to substrates for tape-out to achieve large-scale device production on the production line, gallium oxide devices can be replaced with other devices. a is a gallium oxide Schottky barrier diode (SBD). One side of the substrate layer of the gallium oxide epitaxial wafer is directly bonded to a substrate (Si, SiC, sapphire) with grooves and a metal layer deposited in the grooves. A metal layer is also deposited on the epitaxial layer side of the gallium oxide epitaxial wafer. b is a gallium oxide field-effect transistor, which also has a P-type material layer bonded between the epitaxial layer and the metal layer.

[0099] Figure 9 A schematic diagram of the structure of a gallium oxide SBD device provided in an embodiment of the present application. Figure 9 As shown, based on the above-mentioned gallium oxide SBD device, it is also possible to etch away part of the gallium oxide epitaxial layer and connect the back metal to the side wall of the substrate layer and part of the side wall of the epitaxial layer, thereby increasing the current flow area and reducing the device on-resistance.

[0100] Figure 10 A schematic diagram of the structure of another diode device provided for the implementation of this application. Figure 10 As shown, based on the above-mentioned diode device, the high-resistance substrate used for bonding with the epitaxial wafer can be replaced with a conductive Si wafer, SiC or diamond, so that there is no need to drill a hole on the back of the device to form a back electrode. The back metal electrode can be formed directly by metal deposition and stripping, and the current channel will pass through conductive materials such as Si, SiC or diamond.

[0101] In addition, as another embodiment, an electrode can be prepared on the side where Si or SiC is bonded to gallium oxide, and the cathode electrode of the gallium oxide diode device or the drain electrode of the transistor device can be formed by means of a front electrode.

[0102] Figure 11 This is a flow chart of a method for manufacturing a gallium oxide monolithic heterogeneous integrated device provided in an embodiment of the present application. Figure 11 As shown, the method may include:

[0103] S1: Provide N-type gallium oxide epitaxial wafers and substrates.

[0104] In practical applications, the substrate, or high-resistance substrate mentioned above, can be a Si substrate, SiC substrate, or sapphire. To facilitate mass production on equipment, it is typically 6, 8, or 12 inches in size. The N-type gallium oxide (Ga2O3) epitaxial wafer is of any size, but no larger than the high-resistance substrate. It consists of a heavily N-type gallium oxide substrate layer and a lightly N-type gallium oxide epitaxial layer with a thickness of 10 to 20 μm.

[0105] S2: Bonding a P-type material layer on one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer.

[0106] In practical applications, the P-type material can be P-Si, P-SiC, or P-GaN. A layer of P-type material approximately 1μm thick can be first removed using smart cut technology and planarized using a CMP process. This layer is then directly bonded to an N-type gallium oxide epitaxial wafer using surface activated bonding or plasma activated bonding, with the bonding surfaces connecting the epitaxial layer and the P-type material layer of the N-type gallium oxide epitaxial wafer. Alternatively, a layer of P-type material of a certain thickness can be directly bonded to an N-type gallium oxide epitaxial wafer using surface activated bonding or plasma activated bonding, and then thinned to approximately 1μm, with the bonding surfaces connecting the epitaxial layer and the P-type material layer of the N-type gallium oxide epitaxial wafer.

[0107] S3: etching the upper surface of the substrate to form a groove, and bonding one side of the substrate layer of the N-type gallium oxide epitaxial wafer into the groove.

[0108] In practical applications, the substrate can be a Si, SiC, or sapphire substrate. Based on photolithography and etching techniques, dry or wet etching is used to etch the substrate's top surface, forming a groove that closely matches the shape of the N-type GaO epitaxial wafer to be bonded, but slightly larger than the N-type GaO epitaxial wafer. The N-type GaO epitaxial wafer heterogeneously integrated with the P-type material layer is then bonded within the groove using coupon-to-wafer technology. The bonding surfaces are the substrate groove surface and the backside of the N-type GaO epitaxial wafer's substrate layer. The bonding method can be achieved by directly bonding the substrate to the wafer using an adhesive, such as bonding glue or foaming glue. This bonding method allows for temperature control to achieve bonding and debonding, making it flexible for device tape-out preparation.

[0109] S4: Based on an ion implantation process, an N-type doping region is formed in the P-type material layer.

[0110] In practical applications, N-type gallium oxide epitaxial wafers are bonded to substrates, which can be processed on mass production machines. On these machines, ion implantation, such as with N, Si, or P ions, forms two N-type doped regions of varying depths within the P-type material layer, serving as conductive channels. These N-type doped regions can include two shallowly implanted N-type regions and one deeply implanted N-type region. The deeply implanted N-type region is flanked by shallowly implanted regions.

[0111] S5: depositing a first insulating dielectric on the upper surface of the P-type material layer based on a deposition process to form a gate dielectric;

[0112] Based on a deposition process, depositing a first metal film on the gate dielectric layer, and performing pattern etching to form a gate;

[0113] Depositing a second insulating dielectric on the gate based on a deposition process to form an interlayer dielectric;

[0114] The gate dielectric and the interlayer dielectric are pattern-etched to expose a portion of the upper surface of the P-type material layer.

[0115] In practical applications, after forming the N-type doped region, a deposition process can be continued on the P-type material layer using mass production equipment. Specifically, thin film deposition is first performed to deposit a layer of insulating material (i.e., a first insulating dielectric, which can be SiO2, Al2O3, or Si3N4, etc.) on the upper surface of the P-type material layer to serve as the gate dielectric. A metal thin film deposition process is then performed on the gate dielectric to deposit a metal thin film (i.e., a first metal thin film, which can be Al or Ni). The first metal thin film is then patterned and etched using photolithography to form the gate. It is important to note that the gate must cover the deep-implanted N-type region and a portion of the shallow-implanted N-type region. Next, a layer of insulating dielectric (i.e., a second insulating dielectric, which can be SiO2, Al2O3, or Si3N4, etc.) is deposited on the first metal thin film to form the interlayer dielectric. Finally, photolithography and etching are used to create a pattern at the source location, exposing a portion of the upper surface of the P-type material layer. It is important to note that the gate dielectric and interlayer dielectric are slightly wider than the gate width, equally covering the deep-implanted N-type region and portions of the shallow-implanted N-type regions on either side.

[0116] S6: depositing a second metal film on the pattern-etched areas of the interlayer dielectric and the gate dielectric and annealing the film to form an ohmic contact, which serves as a source.

[0117] In practical applications, a second metal film (Ti / Au or Ti / Al metal) is deposited in the dielectric etched area by metal evaporation and lift-off process and annealed to form an ohmic contact between the second metal film and the P-type material, and serve as a source.

[0118] S7: pattern-etching the interlayer dielectric to expose a portion of the upper surface of the gate;

[0119] A third metal film is deposited on the upper surface of the interlayer dielectric and is in contact with the gate and the source to serve as a first electrode.

[0120] Finally, through photolithography and etching, a pattern is opened above the gate and part of the upper surface of the gate is exposed. Metal film deposition is continued on the upper surface of the interlayer dielectric. A thicker third metal film (Ti / Ni / Al metal) is deposited and patterned so that the third metal film can contact the gate metal and the source metal, serving as a thickened electrode (first electrode) for the gate and source.

[0121] S8: Debonding the substrate layer side of the N-type gallium oxide epitaxial wafer and the groove, and depositing a fourth metal film on the substrate layer side of the N-type gallium oxide epitaxial wafer and annealing it to form an ohmic contact, which serves as a drain.

[0122] In practical applications, the substrate is heated to melt the adhesive between the bottom of the substrate layer and the surface of the groove, achieving debonding between the N-type gallium oxide epitaxial wafer and the substrate. The N-type gallium oxide epitaxial wafer is then flipped over, and a metal film is deposited on the back of the substrate layer. A fourth metal film (Ti / Au or Ti / Al) is deposited and annealed, allowing the fourth metal film to form a non-rectifying contact (ohmic contact) with the N-type material and serve as the drain electrode, completing the fabrication of a single-chip gallium oxide heterojunction integrated device.

[0123] In summary, the method provided in the embodiments of the present application utilizes coupon-to-wafer technology to bond small-sized gallium oxide epitaxial wafers onto 6-, 8-, or 12-inch substrates suitable for mass production equipment for tape-out, enabling the mass production of heterogeneous integrated devices made of single-chip gallium oxide. Furthermore, by bonding an N-type gallium oxide epitaxial wafer to a P-type material, using the P-type material as the gate control region, effective gate control is achieved without the need for unstable P-type oxides or the complex fin structure required for fabrication. This improves structural stability and provides a heat dissipation path, enhancing the heat dissipation capability of the gallium oxide device.

[0124] Figure 12 A flow chart of a method for manufacturing a second electrode provided in an embodiment of the present application. Figure 9 As shown, the method further includes:

[0125] S9: depositing a fifth metal film on the surface of the groove, and bonding the drain electrode to the fifth metal film.

[0126] In practical applications, the above-mentioned process can be combined with the deposition of a metal film on the surface of the groove to deposit a fifth metal film (Al or Cu metal). The N-type gallium oxide epitaxial wafer is then bonded to the substrate using the coupon-to-wafer technique. The bonding surface is the metal surface in the substrate groove and the electrode metal surface (drain surface) on the back of the substrate layer of the N-type gallium oxide epitaxial wafer. The bonding method can be direct metal-metal bonding or placing the N-type gallium oxide epitaxial wafer in the groove and directly heating or laser heating the substrate to melt the metal for bonding.

[0127] S10: punching a hole in the lower surface of the substrate to expose the back side of the fifth metal film, and continuing to deposit metal on the lower surface of the substrate based on a deposition process, the deposited metal contacts the back side of the fifth metal film and serves as a second electrode.

[0128] In actual applications, the substrate is turned over and the back of the substrate is punched until the inner surface of the metal in the groove is exposed. Then, by metal film deposition, (Al or Cu) metal is deposited on the back of the substrate or a back electrode (as a second electrode) is formed by welding. The second electrode covers the entire back of the substrate and is conductive to the fifth metal film. In this way, when the substrate is Si, Si wafer preparation can be carried out to prepare CMOS, and through silicon and gallium oxide monolithic heterogeneous integration technology, an integrated circuit with heterogeneous integration of CMOS digital control circuits and Ga2O3 devices can be formed.

[0129] Figure 13 A schematic diagram of current flow provided in an embodiment of the present application. Figure 10 As shown, when the gallium oxide monolithic heterojunction device is forward-conducted, the ion-implanted N-type region is expanded through gate control, thereby depleting the P-type region under the gate, forming a conduction path. The current flows from the source through the shallowly implanted N-type region, the depletion region, the deeply implanted N-type region, the epitaxial layer of the N-type gallium oxide epitaxial wafer, and the substrate layer of the N-type gallium oxide epitaxial wafer to the drain and the back electrode.

[0130] In summary, since the thermal conductivity of the substrate and P-type materials (Si, SiC, GaN) is better than that of gallium oxide, this heterogeneous integration solution also improves the heat dissipation of gallium oxide devices. The P-type material on the top of the gallium oxide device and the heterogeneous substrate on the bottom both provide heat dissipation paths for the Ga2O3 device, achieving double-sided heat dissipation of the gallium oxide device.

[0131] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gallium oxide monolithic heterogeneous integrated device, characterized in that: The device comprises: an N-type gallium oxide epitaxial wafer, a P-type material layer, an N-type doped region, a gate control region, an interlayer dielectric, a source electrode, a drain electrode, and a substrate layer; the N-type gallium oxide epitaxial wafer comprises an epitaxial layer and a substrate layer; One side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded to one side of the P-type material layer; The N-type doped region is provided in the P-type material layer and contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer; The gate control region covers the N-type doping region and is provided on the other side of the P-type material layer; The source electrode contacts the N-type doped region and forms an ohmic contact with the P-type material layer, and the source electrode is isolated from the gate electrode by the interlayer dielectric; The drain electrode is provided on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms an ohmic contact with the substrate layer; The substrate layer is bonded to the drain electrode; The substrate layer includes: a high-resistance substrate and a conductive metal layer; The conductive metal layer is deposited on the upper surface of the high-resistance substrate, and the other end is bonded to the drain electrode; The width of the conductive metal layer is greater than the width of the drain electrode.

2. The device according to claim 1, characterized in that The N-type doping region includes: a deep-implanted N-type region and a shallow-implanted N-type region; The implantation depth of the shallow implanted N-type region does not exceed the thickness of the P-type material layer; The implantation depth of the deep implanted N-type region exceeds the thickness of the P-type material layer, and one end thereof contacts the epitaxial layer of the N-type gallium oxide epitaxial wafer.

3. The device according to claim 2, characterized in that The gate control region includes: a gate dielectric and a gate metal; The gate dielectric, the gate metal and the interlayer dielectric are sequentially arranged on the other side of the P-type material layer; The gate dielectric and the interlayer dielectric have the same width and are wider than the gate metal; The gate metal covers the deep implantation N-type region and a portion of the shallow implantation N-type region.

4. The device according to claim 3, characterized in that The device further includes: a first electrode; The first electrode is disposed on the other side of the interlayer dielectric and contacts the upper surface of the source and a portion of the upper surface of the gate metal.

5. The device according to claim 1, wherein The device further comprises: a second electrode; The second electrode is disposed on the lower surface of the high-resistance substrate, penetrates the high-resistance substrate, and is connected to the conductive metal layer.

6. The device according to claim 1, characterized in that A groove is etched on the upper surface of the high-resistance substrate; The width of the groove is greater than the width of the substrate layer outside the N-type gallium oxide epitaxial wafer, and the depth of the groove is less than or equal to the height of the N-type gallium oxide epitaxial wafer.

7. A method for manufacturing a gallium oxide monolithic heterogeneous integrated device, characterized in that: A method for manufacturing a gallium oxide monolithic heterogeneous integrated device according to any one of claims 1 to 6, comprising: Provide N-type gallium oxide epitaxial wafers and substrates; Bonding a P-type material layer on one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer; Etching the upper surface of the substrate to form a groove, and bonding one side of the substrate layer of the N-type gallium oxide epitaxial wafer into the groove; forming an N-type doped region in the P-type material layer based on an ion implantation process; Based on a deposition process, depositing a first insulating dielectric on the upper surface of the P-type material layer to form a gate dielectric; Based on a deposition process, depositing a first metal film on the gate dielectric layer, and performing pattern etching to form a gate; Depositing a second insulating dielectric on the gate based on a deposition process to form an interlayer dielectric; Pattern-etching the gate dielectric and the interlayer dielectric to expose a portion of the upper surface of the P-type material layer; Depositing a second metal film on the pattern-etched areas of the interlayer dielectric and the gate dielectric and annealing the film to form an ohmic contact, which serves as a source electrode; Pattern-etching the interlayer dielectric to expose a portion of the upper surface of the gate; Depositing a third metal film on the upper surface of the interlayer dielectric and contacting the gate and the source as a first electrode; The substrate layer side of the N-type gallium oxide epitaxial wafer and the groove are debonded, and a fourth metal film is deposited on the substrate layer side of the N-type gallium oxide epitaxial wafer and annealed to form an ohmic contact, which serves as a drain.

8. The method according to claim 7, characterized in that The method further comprises: Depositing a fifth metal film on the surface of the groove, and bonding the drain electrode to the fifth metal film; The lower surface of the substrate is punched to expose the back surface of the fifth metal film, and metal deposition is continued on the lower surface of the substrate based on a deposition process. The deposited metal contacts the back surface of the fifth metal film and serves as a second electrode.

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