A CAN transceiver

Abstract

The present application discloses a CAN transceiver, including a data transmission port, a high-side bus port, a low-side bus port, an output stage circuit, a first regulation circuit and a second regulation circuit. The first regulation circuit and the second regulation circuit increase the pull-up current or the pull-down current in the output circuit by receiving an abnormal voltage signal and outputting a regulation signal, thereby eliminating the error of the differential signal. The first regulation circuit regulates the error generated by the abnormal positive high-voltage pulse coupled into the high-side bus port, and the second regulation circuit regulates the error generated by the abnormal negative high-voltage pulse coupled into the low-side bus port. After the CAN transceiver applies the first regulation circuit and the second regulation circuit, the influence of the abnormal high-voltage pulse signal in the CAN bus on the error of the output signal of the CAN transceiver is reduced, thereby improving the EMC performance of the CAN transceiver.

Description

Technical Field

[0001] The present application belongs to the technical field of CAN transceivers, and specifically relates to a CAN transceiver. Background Art

[0002] The CAN transceiver is a key component in CAN (Controller Area Network) bus communications. It transmits data between the CAN bus and the CAN controller, converting the single-ended signals output by the CAN controller into the differential signals required by the CAN bus, and converting the differential signals on the CAN bus back into single-ended signals for transmission to the CAN controller. Due to the complex electromagnetic environment in CAN bus communication applications, CAN transceivers are often subject to abnormally high voltage interference. For example, the onboard electrical environment can couple tens or even hundreds of volts of positive and negative voltage into the CAN bus. This can cause the protection diodes in the CAN transceiver's output stage circuit to generate reverse recovery current as they transition from forward conduction to reverse blocking. This can cause the CAN transceiver's output state to change from dominant to recessive, thus affecting the stability of the differential signal. Summary of the Invention

[0003] The present application provides a CAN transceiver to solve the problem that the output circuit of the current CAN transceiver is easily interfered by abnormal high voltage, resulting in bit errors in the output signal of the CAN transceiver, so as to improve the EMC (Electromagnetic Compatibility) of the CAN transceiver.

[0004] According to the first aspect of the present application, the present application provides a CAN transceiver, comprising: a transmitting data port, receiving a transmitting data signal; a high-side bus port, outputting a high-side bus signal; a low-side bus port, outputting a low-side bus signal; a high-side transistor, having a first end, a second end and a third end, wherein the first end receives a power supply voltage and the second end receives a high-side gate signal; a high-side switch tube, having a first end coupled to the third end of the high-side transistor, a second end coupled to the high-side bus port, and a voltage at the first end of the high-side switch tube being a high-side detection voltage; a low-side transistor, having a first end, a second end and a third end, wherein the first end is coupled to a reference ground and the second end receives a low-side gate signal; a low-side switch tube, having a first end coupled to the low-side bus port, a second end coupled to the third end of the low-side transistor, and a voltage at the second end of the low-side switch tube being a low-side detection voltage. measuring voltage; a first regulating circuit having a first input terminal and a second input terminal, wherein the first input terminal receives a power supply voltage and the second input terminal receives a high-side detection voltage, and the first regulating circuit generates a first regulating signal according to the power supply voltage and the high-side detection voltage; a second regulating circuit having a first input terminal and a second input terminal, wherein the first input terminal is coupled to a reference ground and the second input terminal receives a low-side detection voltage, and the second regulating circuit generates a second regulating signal according to the reference ground and the low-side detection voltage; and a logic circuit, generating a high-side gate signal and a low-side gate signal according to the transmitted data signal, the first regulating signal and the second regulating signal; wherein, when the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold value, the forward current flowing through the low-side switch tube increases, and when the low-side detection voltage is less than the second threshold value, the forward current flowing through the high-side switch tube increases.

[0005] According to a second aspect of the present application, the present application provides a CAN transceiver, comprising: a transmitting data port, receiving a transmitting data signal; a high-side bus port, outputting a high-side bus signal; a low-side bus port, outputting a low-side bus signal; a high-side transistor, having a first end, a second end and a third end, wherein the first end receives a power supply voltage and the second end receives a transmitting data signal; a high-side switch tube, having a first end coupled to the third end of the high-side transistor, a second end coupled to the high-side bus port, and the voltage of the first end of the high-side switch tube is a high-side detection voltage; a low-side transistor, having a first end, a second end and a third end, wherein the first end is coupled to a reference ground and the second end receives a transmitting data non-signal; a low-side switch tube, having a first end coupled to the low-side bus port, a second end coupled to the third end of the low-side transistor, and the voltage of the second end of the low-side switch tube is a low-side detection voltage; a first regulating circuit, having a first input end and a second input end, wherein the first input end receives the power supply voltage, The second input terminal receives the high-side detection voltage, and the first regulation circuit generates a first regulation signal based on the power supply voltage and the high-side detection voltage; the second regulation circuit has a first input terminal and a second input terminal, wherein the first input terminal is coupled to the reference ground, and the second input terminal receives the low-side detection voltage, and the second regulation circuit generates a second regulation signal based on the reference ground and the low-side detection voltage; the first regulation transistor has a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to the second terminal of the low-side switch tube, the second terminal is coupled to the reference ground, and the third terminal receives the first regulation signal; and the second regulation transistor has a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to the power supply voltage, the second terminal is coupled to the first terminal of the high-side switch tube, and the third terminal receives the second regulation signal; wherein, when the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the forward current flowing through the low-side switch tube increases, and when the low-side detection voltage is less than the second threshold, the forward current flowing through the high-side switch tube increases.

[0006] Through one or more of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0007] In this embodiment, the regulation circuit samples the terminal voltage of the switching tube in the output circuit of the CAN transceiver to detect abnormal high-voltage pulses by obtaining a voltage signal, and uses the abnormal voltage signal to generate a regulation signal to regulate the abnormal CAN bus current caused by the abnormal high-voltage pulse, thereby ensuring that the differential signal does not have bit errors when the high-side output current or the low-side output current of the CAN transceiver is abnormal, thereby improving the anti-interference capability of the CAN transceiver and achieving EMC enhancement of the CAN transceiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 The schematic diagram of the output stage circuit structure of the existing CAN transceiver is given;

[0010] Figure 2 The signal timing diagram of the existing CAN transceiver output stage circuit is given;

[0011] Figure 3 A circuit structure diagram of a CAN transceiver according to an embodiment of the present invention is provided;

[0012] Figure 4 A schematic diagram of a logic switch S2 according to an embodiment of the present invention is provided;

[0013] Figure 5 A circuit structure diagram of a CAN transceiver according to an embodiment of the present invention is provided;

[0014] Figure 6 Provided are signal timing diagrams of CAN transceiver circuits according to various embodiments of the present invention; DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0016] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0017] It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or subcircuit connected electrically or electromagnetically. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two elements.

[0018] In the application scenario of CAN bus communication, high-voltage pulse interference may exist in the complex electrical environment, such as sudden pulse (Impulse, IMP) events or direct power injection (DPI) events in the vehicle electrical environment. Therefore, diodes are usually used inside the CAN transceiver for transient high-voltage protection. Under normal circumstances, the difference signal between the high-side bus signal CANH and the low-side bus signal CANL in the CAN bus is defined as the differential signal VDIFF of the CAN bus. When the high-side bus signal CANH is a logic high level and the low-side bus signal CANL is a logic low level, the actual level difference between the two is large, and the differential signal VDIFF is a logic high state, indicating that the CAN bus is working in a dominant state. When the high-side bus signal CANH is a logic low level and the low-side bus signal CANL is a logic high level, the actual level difference between the two is small, and the differential signal VDIFF is a logic low state, indicating that the CAN bus is working in a recessive state. When an IMP event or a DPI event occurs, due to the influence of the instantaneous high voltage, the diode may be forward-conducted. When switching to reverse cutoff, due to the presence of diffusion capacitance in the forward-conducting diode, it takes some time for the voltage of the diffusion capacitance to reverse charge after the diode bias is switched from positive to negative. Furthermore, it takes time for the carriers within the diode to recombine and completely dissipate before the internal voltage drop reaches a negative voltage, allowing the diode to fully cut off. During this time, the current seen from the outside of the diode flows from the cathode to the anode, a phenomenon known as the diode reverse recovery current. This reverse recovery current can cause the CAN bus input and output states to transition from logic high to logic low, potentially causing communication on the CAN bus to be subject to bit errors. Transmitted messages may be mistakenly interpreted as recessive rather than dominant. Similarly, when a field-effect transistor (FET) is used as a protection switch within a CAN transceiver, the parasitic diode within the FET, under the influence of transient high voltage, will also generate reverse recovery current, leading to abnormal CAN bus input and output states and bit errors.

[0019] Figure 1 The schematic diagram of the output stage circuit structure of the existing CAN transceiver is given, as shown in Figure 1As shown, the CAN transceiver output stage circuit 10 includes a high-side transistor MH, a high-side switch tube DH, a low-side switch tube DL, and a low-side transistor ML. The gate end of the high-side transistor MH receives a transmit data signal TXD, and the gate end of the low-side transistor ML receives a transmit data non-signal TXDN. That is, the transmit data signal TXD and the transmit data non-signal TXDN of the CAN transceiver are used as control signals of the high-side transistor MH and the low-side transistor ML, respectively. When the TXD signal is dominant, the gate voltage of the high-side transistor MH is low, the high-side transistor MH is turned on, the high-side switch tube DH is forward-conducted, and the high-side bus port CANH outputs the forward conduction current ID_H of the high-side switch tube DH, that is, the high-side bus signal CANH is a logic high level. At this time, the TXDN signal is high, that is, the gate voltage of the low-side transistor ML is high, which controls the low-side transistor ML to be turned on, and the low-side switch tube DL is forward-conducted. The low-side bus port CANL outputs the forward conduction current ID_L of the low-side switch tube DL, that is, the low-side bus signal CANL is a logic low level. At this time, the differential signal in the CAN bus is a logic high level, indicating that the CAN bus state is dominant. When the TXD signal is recessive, the gate voltage of the high-side transistor MH is high, the high-side transistor MH is turned off, the high-side switch tube DH is cut off, the forward conduction current ID_H of the high-side switch tube DH is approximately zero, and the high-side bus signal CANH is a logic low. At this time, the TXDN signal is low, that is, when the gate voltage of the low-side transistor ML is low, the low-side transistor ML is cut off, the low-side switch tube DL is cut off, the forward conduction current ID_L of the low-side switch tube DL is approximately zero, and the low-side bus signal CANL is a logic high. Since both the high-side switch tube DH and the low-side switch tube DL are cut off, the high-side bus and low-side bus voltages in the CAN bus are close, that is, the differential signal in the CAN bus is a logic low, indicating that the CAN bus state is recessive.

[0020] Figure 2 The signal timing diagram of the existing CAN transceiver output stage circuit is given to illustrate Figure 1 The existing CAN transceiver output stage circuit structure shown in the figure has EMC performance problems. Take the sudden IMP event or DPI event causing +100V high voltage interference in the CAN bus as an example. When the high voltage interference signal RF_IN is coupled into the CAN bus through the capacitor, if the TXD signal is dominant at this time, then at the moment of the IMP event or DPI event, the negative terminal voltage of the high-side switch tube DH rises sharply, and the bias state of the high-side switch tube DH switches from forward conduction to reverse cutoff. Its reverse recovery current flows from the negative electrode of the high-side switch tube DH to the positive electrode, resulting in Figure 2At the moment of the onset of the +100V high voltage, the mid- and high-side detection voltage VD_H exceeds the power supply voltage VCC. The forward conduction current ID_H of the high-side switch tube DH jumps ①, that is, the forward conduction current ID_H of the high-side switch tube DH cannot be cut off to 0 at the moment the high-side switch tube DH switches to reverse cutoff. Instead, a reverse current appears, causing the polarity of the high-side bus signal CANH in the CAN bus to jump, which in turn causes the differential signal VDIFF in the CAN bus to jump accordingly ③, that is, a bit error occurs. Similarly, when a sudden IMP event or DPI event causes -100V high voltage interference in the CAN bus, the TXD signal is dominant at this time. Then, at the moment of the IMP event or DPI event, the positive terminal voltage of the low-side switch tube DL drops sharply, and the bias state of the low-side switch tube DL switches from forward conduction to reverse cutoff. The reverse recovery current flows from the negative pole to the positive pole of the low-side switch tube DL, resulting in Figure 2 When the -100V high voltage is applied, the mid- and low-side detection voltage VD_L drops below GND, causing the forward current ID_L of the low-side switch DL to jump (②). This means that the forward current ID_L of the low-side switch DL cannot be cut off to zero when the low-side switch DL switches to reverse cutoff. Instead, reverse current flows, causing the polarity of the low-side bus signal CANL on the CAN bus to jump. This, in turn, causes the differential signal VDIFF on the CAN bus to jump (④), resulting in a bit error.

[0021] Figure 3 A circuit structure diagram of a CAN transceiver according to an embodiment of the present invention is given. Figure 3As shown, the circuit structure of a CAN transceiver includes a transmit data port, a high-side bus port, a low-side bus port, a high-side transistor MH, a high-side switch DH, a low-side transistor ML, a low-side switch DL, a first regulation circuit 103, a second regulation circuit 104, and a logic circuit. The transmit data port receives a transmit data signal TXD, the high-side bus port outputs a high-side bus signal CANH, and the low-side bus port outputs a low-side bus signal CANL. The high-side transistor MH has a first terminal, a second terminal, and a third terminal. The first terminal receives a supply voltage VCC, and the second terminal receives a high-side gate signal GH. The high-side switch DH has a first terminal coupled to the third terminal of the high-side transistor MH and a second terminal coupled to the high-side bus port. The voltage at the first terminal serves as the high-side detection voltage VD_H in this embodiment. The low-side transistor ML has a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the reference ground GND, and the second terminal receives the low-side gate signal GL. The low-side switch DL has a first terminal coupled to the low-side bus port and a second terminal coupled to the third terminal of the low-side transistor ML. The voltage at the second terminal serves as the low-side detection voltage VD_L in this embodiment. The first regulation circuit 103 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the supply voltage VCC, the second input terminal is coupled to the positive terminal of the high-side switch DH and receives the high-side detection voltage VD_H, and the output terminal outputs a first regulation signal CompH based on the high-side detection voltage VD_H and the supply voltage VCC. The second regulation circuit 104 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the reference ground GND, the second input terminal is coupled to the negative terminal of the low-side switch DL and receives the low-side detection voltage VD_L, and the output terminal outputs a second regulation signal CompL based on the low-side detection voltage VD_L and the reference ground GND.

[0022] Furthermore, the first regulation circuit 103 includes a first regulation voltage source Vos1 and a first comparison circuit 1031. The first regulation voltage source Vos1 has a first terminal and a second terminal, wherein the first terminal is coupled to the positive terminal of the high-side switch DH. The first comparison circuit 1031 has a first input terminal receiving a supply voltage VCC, a second input terminal coupled to the second terminal of the first regulation voltage source Vos1, and an output terminal coupled to the second terminal of the low-side transistor ML. The first regulation voltage source Vos1 provides a first threshold value required for the first regulation circuit 103 to generate the first regulation signal CompH. The second regulation circuit 104 includes a second regulation voltage source Vos2 and a second comparison circuit 1041. The second regulation voltage source Vos2 has a first terminal and a second terminal, wherein the first terminal is coupled to the negative terminal of the low-side switch DL. The second comparison circuit has a first input terminal coupled to the reference ground GND, a second input terminal coupled to the second terminal of the first regulation voltage source Vos1, and an output terminal coupled to the second terminal of the high-side transistor MH. The second regulation voltage source Vos2 provides a second threshold value required for the second regulation circuit 104 to generate the second regulation signal CompL. In this embodiment, the first comparison circuit 1031 includes a first comparator Comp1. The first input terminal of the first comparison circuit 1031 is the inverting input terminal of the first comparator Comp1. The voltage of the first regulating voltage source Vos1 ranges from 0 mV to 500 mV, the first terminal is the positive terminal of the power supply, and the second terminal is the negative terminal of the power supply, so that the first threshold value provided is from 0 mV to 500 mV. The second comparison circuit 1041 includes a second comparator Comp2. The first input terminal of the second comparison circuit is the non-inverting input terminal of the second comparator Comp2. The voltage of the second regulating voltage source Vos2 ranges from 0 mV to 500 mV, the first terminal is the negative terminal of the power supply, and the second terminal is the positive terminal of the power supply, so that the second threshold value provided is from -500 mV to 0 mV.

[0023] In the above embodiment, when the voltage at the first terminal of the high-side switch DH is greater than the sum of the power supply voltage VCC and the voltage of the first regulation voltage source Vos1, that is, when the high-side detection voltage VD_H is greater than the sum of the power supply voltage VCC and the first threshold, the first regulation circuit 103 increases the voltage at the second terminal of the low-side transistor ML by outputting the first regulation signal CompH, thereby increasing the on-current of the low-side transistor ML by increasing the bias voltage of the low-side transistor ML, that is, increasing the forward current ID_L of the low-side switch DL. When the voltage at the second terminal of the low-side switch DL is less than the negative value of the voltage of the second regulation voltage source, that is, when the low-side detection voltage VD_L is less than the second threshold, the second regulation circuit 104 outputs the second regulation signal CompL to decrease the voltage at the second terminal of the high-side transistor MH, thereby increasing the bias voltage of the high-side transistor MH, that is, increasing the on-current of the high-side transistor MH, that is, increasing the forward current ID_H of the high-side switch DH.

[0024] exist Figure 3 In the circuit structure of the CAN transceiver shown, the logic circuit includes a logic switch S1 and a logic switch S2, wherein the output end of the logic switch S1 is coupled to the second end of the high-side transistor MH, and the output end of the logic switch S2 is coupled to the second end of the low-side transistor ML. The logic switch S2 generates a low-side gate signal GL according to the first adjustment signal CompH and the transmit data negative signal TXDN, and the logic switch S1 generates a high-side gate signal GH according to the second adjustment signal CompL and the transmit data signal TXD. Furthermore, in order to unify the gate voltage selection logic of the high-side transistor MH and the low-side transistor ML and use the same logic switch structure, after the transmit data port receives the transmit data signal TXD, the transmit data signal TXD is input into the logic switch S1 and input into the high-side output stage circuit 101 through the logic switch S1. The transmit data signal TXD is inverted and generated into the transmit data negative signal TXDN, which is then input into the logic switch S2 and input into the low-side output stage circuit 102 through the logic switch S2. Through the logic switch S1 and the logic switch S2, the data transmission signal line and the data transmission non-signal line can be prevented from directly participating in the control logic of the high-side transistor MH and the low-side transistor ML, thereby preventing the short circuit of the root logic line. In this embodiment, the root logic line corresponds to the transmission line for transmitting the data transmission signal TXD and the data transmission non-signal TXDN.

[0025] exist Figure 3 In the illustrated embodiment, the high-side transistor MH is a P-channel field-effect transistor, and the low-side transistor ML is an N-channel field-effect transistor.

[0026] In the above embodiment, the high-side switch DH and the low-side switch DL in the high-side output stage circuit 101 and the low-side output stage circuit 102 may be field effect transistors or diodes.

[0027] Figure 4 A schematic diagram of a logic switch S2 according to an embodiment of the present invention is given. Figure 3 The CAN transceiver shown in FIG. 1 illustrates the working process of the logic switch S2. Figure 4As shown, the logic switch S2 outputs the low-side gate signal GL at its output terminal coupled to the gate of the low-side transistor ML according to the transmitted data signal TXD, the inverted transmitted data signal TXDN, the first regulation signal CompH and the first inverted regulation signal CompHN of the first regulation circuit 103. At the same time, three selection voltages V1 > V2 > V3 = 0 are set. The first inverted regulation signal CompHN and the first regulation signal CompH are complementary signals. That is, when the first regulation signal CompH is at a logic high level, the first inverted regulation signal CompHN is at a logic low level, and when the first regulation signal CompH is at a logic low level, the first inverted regulation signal CompHN is at a logic high level. When the CAN transceiver operates in the recessive state, the transmitted data signal TXD is at a logic high level, making GL = V3, and the low-side transistor ML operates in the cut-off state. When the CAN transceiver operates in the dominant state, the inverted transmitted data signal TXDN is at a logic high level. The logic switch S2 selects the low-side gate signal GL to be V1 or V2 according to the first regulation signal CompH and the first inverted regulation signal CompHN. When the first regulation signal CompH is at a logic high level, the low-side gate signal GL is V1, and when the first inverted regulation signal CompHN is at a logic high level, the low-side gate signal GL is V2. When the voltage at the first end of the high-side switch tube DH, i.e., the high-side detection voltage VD_H, is greater than the sum of the supply voltage VCC and the voltage value of the first regulation voltage source Vos1, the first regulation circuit 103 controls the bias voltage of the low-side transistor ML, i.e., the low-side gate signal GL, to change from V2 to V1 by outputting the first regulation signal CompH, so as to increase the conduction current of the low-side transistor ML, that is, the forward current ID_L of the low-side switch tube DL increases. Similarly, in the above Figure 3 The logic switch S1 in the embodiment shown is similar in structure and principle to the logic switch S2 in this embodiment. Correspondingly, the selection logic voltages V1, V2, and V3 are set as V1 < V2 < V3 = VCC. The specific structure and principle are not described here.

[0028] Figure 5 Fig. shows a schematic circuit diagram of a CAN transceiver according to another embodiment of the present invention. As Figure 5As shown, the circuit structure of a CAN transceiver includes a transmit data port, a high-side bus port, a low-side bus port, a high-side transistor MH, a high-side switch DH, a low-side transistor ML, a low-side switch DL, a first regulation circuit 103, and a second regulation circuit 104. After the transmit data port receives a transmit data signal TXD, the high-side output stage circuit 101 receives the transmit data signal TXD, and the low-side output stage circuit 102 receives a transmit data non-signal TXDN. The transmit data non-signal TXDN is a complementary signal to the transmit data signal TXD. The high-side bus port outputs a high-side bus signal CANH, and the low-side bus port outputs a low-side bus signal CANL. The high-side transistor MH has a first terminal, a second terminal, and a third terminal. The first terminal receives a supply voltage VCC, and the second terminal receives the transmit data signal TXD. The high-side switch DH has a first terminal coupled to the third terminal of the high-side transistor MH and a second terminal coupled to the high-side bus port. The voltage at the first terminal serves as the high-side detection voltage VD_H in this embodiment. The low-side transistor ML has a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the reference ground GND, and the second terminal receives the transmit data non-signal TXDN. The low-side switch DL has a first terminal coupled to the low-side bus port and a second terminal coupled to the third terminal of the low-side transistor ML. The voltage at the second terminal serves as the low-side detection voltage VD_L in this embodiment. The first regulation circuit 103 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives the supply voltage VCC, the second input terminal is coupled to the first terminal of the high-side switch DH and receives the high-side detection voltage VD_H, and the output terminal is coupled to the second terminal of the low-side switch DL. The circuit outputs a first regulation signal CompH based on the high-side detection voltage VD_H and the supply voltage VCC. The second regulation circuit 104 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the reference ground GND, the second input terminal is coupled to the second terminal of the low-side switch DL, and receives the low-side detection voltage VD_L. The output terminal is coupled to the first terminal of the high-side switch DH, and outputs a second regulation signal CompL based on the low-side detection voltage VD_L and the reference ground GND.

[0029] Figure 5 The circuit structure of the CAN transceiver shown also includes a first regulating transistor MR1 and a second regulating transistor MR2. The first regulating transistor MR1 has a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the second terminal of the low-side switch DL, the second terminal is coupled to the reference ground GND, and the third terminal receives a first regulating signal CompH. The second regulating transistor MR2 has a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the supply voltage VCC, the second terminal is coupled to the first terminal of the high-side switch DH, and the third terminal receives a second regulating signal CompL.

[0030] Furthermore, the first regulation circuit 103 includes a first regulation voltage source Vos1 and a first comparison circuit 1031. The first regulation voltage source Vos1 has a first terminal and a second terminal, wherein the first terminal is coupled to the first terminal of the high-side switch DH. The first comparison circuit 1031 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a supply voltage VCC, the second input terminal is coupled to the second terminal of the first regulation voltage source Vos1, and the output terminal is coupled to the third terminal of the first regulation transistor MR1 and outputs a first regulation signal CompH. The first regulation voltage source Vos1 provides a first threshold required for the first regulation circuit 103 to generate the first regulation signal CompH. The second regulation circuit 104 includes a second regulation voltage source Vos2 and a second comparison circuit 1041. The second regulation voltage source Vos2 has a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the low-side switch DL. The second comparison circuit 1041 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the reference ground GND, the second input terminal is coupled to the second terminal of the first regulation voltage source Vos1, and the output terminal is coupled to the third terminal of the second regulation transistor MR2, and outputs a second regulation signal CompL. The second regulation voltage source Vos2 provides a second threshold value required for the second regulation circuit 104 to generate the second regulation signal CompL. In this embodiment, the first comparison circuit 1031 includes a first comparator Comp1, the first input terminal of the first comparison circuit 1031 is the non-inverting input terminal of the first comparator Comp1, the first adjustment transistor MR1 is an N-channel field effect transistor, the voltage value of the first adjustment voltage source Vos1 is 0mV~500mV, the first terminal is the positive terminal of the power supply, and the second terminal is the negative terminal of the power supply, so that the provided first threshold value is 0mV~500mV; the second comparison circuit 1041 includes a second comparator Comp2, the first input terminal of the second comparison circuit 1041 is the non-inverting input terminal of the second comparator Comp1, the second adjustment transistor MR2 is a P-channel field effect transistor, the voltage value of the second adjustment voltage source Vos2 is 0mV~500mV, the first terminal is the negative terminal of the power supply, and the second terminal is the positive terminal of the power supply, so that the provided second threshold value is -500mV~0mV. In an embodiment of the present application, normal fluctuations in the bus signal may cause the high-voltage detection signal VD_H to be close to the power supply voltage VCC or slightly higher than the power supply voltage VCC, and may also cause the low-voltage detection signal VD_L to be slightly lower than the reference voltage GND, resulting in the regulation mechanism of the circuit being falsely triggered. The setting of the first threshold and the second threshold can prevent the regulation mechanism from being falsely triggered in the absence of abnormal high voltage disturbance.

[0031] In the above Figure 5In the illustrated embodiment, when the voltage at the first terminal of the high-side switch DH is greater than the voltage value of the power supply voltage VCC and the voltage of the first regulating current source Vos1, the first comparison circuit 1031 in the first regulation circuit 103 outputs a first regulation signal CompH to the third terminal of the first regulation transistor MR1, turning on the first regulation transistor MR1, thereby increasing the current flowing from the second terminal of the low-side switch DL to the reference ground GND to supplement the current of the low-side bus in the CAN bus. When the voltage at the second terminal of the low-side switch DL is less than the negative value of the voltage value of the second regulating current source Vos2, the second comparison circuit 1041 in the second regulation circuit 104 outputs a second regulation signal CompL to the third terminal of the second regulation transistor MR2, turning on the second regulation transistor MR2, thereby increasing the current flowing from the power supply voltage VCC to the first terminal of the high-side switch DH, i.e., the forward conduction current ID_H of the high-side switch DH, to supplement the current of the high-side bus in the CAN bus.

[0032] exist Figure 5 In the illustrated embodiment, the high-side transistor MH is a P-channel field-effect transistor, and the low-side transistor ML is an N-channel field-effect transistor.

[0033] In another embodiment, the high-side switch tube and the low-side switch tube in the high-side output stage circuit 101 and the low-side output stage circuit 102 can use field effect transistors to replace the above-mentioned Figure 5 The high-side switch tube DH and the low-side switch tube DL in the embodiment shown.

[0034] Figure 6 An example diagram of the signal timing of a CAN transceiver circuit according to an embodiment of the present invention is provided to further illustrate the principle of improving the EMC performance of the circuit structure of the CAN transceiver according to the above embodiments. Figure 3 or Figure 5 In the embodiment shown, a sudden IMP event or DPI event causes a +100V high voltage interference in the CAN bus. For example, when the high voltage interference signal RF_IN is coupled into the CAN bus through a capacitor, if the TXD signal is dominant at this time, then at the moment the IMP event or DPI event occurs, the voltage at the second end of the high-side switch tube DH rises sharply, and the bias state of the high-side switch tube DH switches from forward conduction to reverse cutoff. The reverse recovery current flows from the second end of the high-side switch tube DH to the first end, resulting in Figure 2At the moment when the +100V high voltage comes, the VD_H signal in the middle appears a high voltage exceeding the power supply voltage VCC, and the forward conduction current ID_H of the high-side switch tube DH jumps at this time ①, that is, the forward conduction current ID_H of the high-side switch tube DH cannot be cut off to 0 at the moment when the high-side switch tube DH switches to the reverse cut-off state, but a reverse current appears, causing the high-side bus signal CANH in the CAN bus to jump in level or even polarity. According to the circuit structure of the first regulation circuit 103 in the above embodiments, it can be seen that at this time, the high-side detection voltage VD_H is collected to the second input terminal of the first regulation circuit 103, and after being compared with the power supply voltage VCC, the first regulation circuit 103 generates a first regulation signal CompH. In the embodiment using the first comparator Comp1, the voltage at the output terminal of Comp1, i.e., the first regulation signal CompH, generates a corresponding jump voltage when the high voltage of +100V is applied, causing the high-side detection voltage VD_H to change from a logic low LogicL to a logic high LogicH, thereby increasing the bias voltage of the low-side transistor ML or turning on the first regulation transistor MR1, causing the forward conduction current ID_L of the low-side switch DL to jump ⑤, that is, compensating the current in the low-side bus, causing the absolute value of the actual level of the low-side bus signal CANL to increase accordingly, so that the polarity of the differential signal VDIFF does not jump to a logic low state or jump to an inverted state, but appears as follows: Figure 6 In the transition ⑦ shown in FIG, the differential signal VDIFF is still dominant, which prevents the occurrence of bit errors. The differential signal VDIFF is the difference signal between the high-side bus signal CANH and the low-side bus signal CANL in the CAN bus.

[0035] Similarly, when a sudden IMP event or DPI event causes a -100V high voltage interference in the CAN bus, the TXD signal is dominant at this time. Then, at the moment the IMP event or DPI event occurs, the voltage at the second end of the low-side switch tube DL drops sharply, and the bias state of the low-side switch tube DL switches from forward conduction to reverse cutoff. The reverse recovery current flows from the second end of the low-side switch tube DL to the first end, resulting in Figure 2At the moment the -100V high voltage is applied, the mid-low-side detection voltage VD_L becomes a negative high voltage lower than the reference ground voltage GND. At this time, ID_L experiences a jump ②. That is, the forward conduction current ID_L of the low-side switch tube DL cannot be cut off to 0 at the moment the low-side switch tube DL switches to the reverse cut-off state. Instead, a reverse current appears, causing the low-side bus signal CANL in the CAN bus to experience a level jump or even a polarity jump. According to the circuit structure of the second regulation circuit 104 in the above embodiments, it can be seen that at this time, the low-side detection voltage VD_L is collected to the second input terminal of the second regulation circuit 104. After being compared with the reference ground voltage GND, the second regulation circuit 104 generates a second regulation signal CompL. The second comparator Comp2 is applied to the second comparison circuit 1041. In the embodiment, the voltage at the output end of Comp2, i.e., the second regulation signal CompL, generates a corresponding jump voltage when the high voltage of -100V comes, and the low-side detection voltage VD_L causes the second regulation signal CompL to change from a logic low LogicL to a logic high LogicH, thereby increasing the bias of the high-side transistor MH or turning on the second regulation transistor MR2, causing the forward conduction current ID_H of the high-side diode DH to jump ⑥ at this time, that is, compensating for the current in the high-side bus, so that the actual level of the high-side bus signal CANH increases accordingly, thereby compensating for the actual level difference between the high-side bus signal CANH and the low-side bus signal CANL, that is, the polarity of the differential signal VDIFF does not jump to a logic low state or jump to an inverted state, but appears as follows. Figure 5 In the transition ⑧ shown in FIG, the differential signal VDIFF is still dominant, which prevents the occurrence of bit errors. The differential signal VDIFF is the difference signal between the high-side bus signal CANH and the low-side bus signal CANL in the CAN bus.

[0036] The circuit structure of the CAN transceiver provided in each embodiment of the present application utilizes two regulating circuits to sample abnormal pulse voltages of the high-side output stage circuit 101 and the low-side output stage circuit 103, respectively, and prevents the dominant differential voltage from being too low due to the reverse recovery current of the switching tube by increasing the pull-up and pull-down currents, thereby keeping the differential voltage of the bus output stable, thereby improving the overall anti-interference capability of the circuit and improving the reliability and stability of communication.

[0037] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims cover all such modifications or embodiments.

Claims

1. A CAN transceiver, comprising: Send data port, receiving and sending data signals; High-side bus port, outputs high-side bus signal; Low-side bus port, outputs low-side bus signal; A high-side transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal receives a power supply voltage and the second terminal receives a high-side gate signal; A high-side switch tube has a first end coupled to the third end of the high-side transistor, a second end coupled to the high-side bus port, and a voltage at the first end of the high-side switch tube is a high-side detection voltage; A low-side transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to a reference ground and the second terminal receives a low-side gate signal; A low-side switch tube has a first end coupled to the low-side bus port, a second end coupled to the third end of the low-side transistor, and a voltage at the second end of the low-side switch tube is a low-side detection voltage; a first regulating circuit having a first input terminal and a second input terminal, wherein the first input terminal receives a power supply voltage, the second input terminal receives a high-side detection voltage, and the first regulating circuit generates a first regulating signal according to the power supply voltage and the high-side detection voltage; a second regulating circuit having a first input terminal and a second input terminal, wherein the first input terminal is coupled to a reference ground, the second input terminal receives a low-side detection voltage, and the second regulating circuit generates a second regulating signal according to the reference ground and the low-side detection voltage; as well as a logic circuit, generating a low-side gate signal according to the transmission data signal and the first adjustment signal, and generating a high-side gate signal according to the transmission data signal and the second adjustment signal; Among them, when the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the forward current flowing through the low-side switch tube is increased based on the first adjustment signal; when the low-side detection voltage is less than the second threshold, the forward current flowing through the high-side switch tube is increased based on the second adjustment signal.

2. The CAN transceiver according to claim 1, wherein: When the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the low-side gate signal controls the current flowing through the low-side transistor to increase; when the low-side detection voltage is less than the second threshold, the high-side gate signal controls the current flowing through the high-side transistor to increase. 3 . The CAN transceiver according to claim 1 , wherein the first threshold value ranges from 0 mV to 500 mV. The CAN transceiver according to claim 1 , wherein the second threshold value is in a range of −500 mV to 0 mV. The CAN transceiver according to claim 1 , wherein the high-side transistor is a P-type field-effect transistor, and the low-side transistor is an N-type field-effect transistor. The CAN transceiver according to claim 1 , wherein the high-side switch tube and the low-side switch tube comprise field-effect transistors or diodes.

7. A CAN transceiver comprising: Send data port, receiving and sending data signals; High-side bus port, outputs high-side bus signal; Low-side bus port, outputs low-side bus signal; A high-side transistor having a first end, a second end and a third end, wherein the first end receives a power supply voltage and the second end receives a transmission data signal; A high-side switch tube has a first end coupled to the third end of the high-side transistor, a second end coupled to the high-side bus port, and a voltage at the first end of the high-side switch tube is a high-side detection voltage; A low-side transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to a reference ground and the second terminal receives a transmission data non-signal; A low-side switch tube has a first end coupled to the low-side bus port, a second end coupled to the third end of the low-side transistor, and a voltage at the second end of the low-side switch tube is a low-side detection voltage; a first regulating circuit having a first input terminal and a second input terminal, wherein the first input terminal receives a power supply voltage, the second input terminal receives a high-side detection voltage, and the first regulating circuit generates a first regulating signal according to the power supply voltage and the high-side detection voltage; a second regulating circuit having a first input terminal and a second input terminal, wherein the first input terminal is coupled to a reference ground, the second input terminal receives a low-side detection voltage, and the second regulating circuit generates a second regulating signal according to the reference ground and the low-side detection voltage; A first regulating transistor has a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to the second terminal of the low-side switch tube, the second terminal is coupled to the reference ground, and the third terminal receives the first regulating signal; as well as A second regulating transistor has a first end, a second end and a third end, wherein the first end is coupled to the power supply voltage, the second end is coupled to the first end of the high-side switch tube, and the third end receives a second regulating signal; Among them, when the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the forward current flowing through the low-side switch tube is increased based on the first adjustment signal; when the low-side detection voltage is less than the second threshold, the forward current flowing through the high-side switch tube is increased based on the second adjustment signal.

8. The CAN transceiver according to claim 7, wherein: When the high-side detection voltage is greater than the sum of the power supply voltage and the first threshold, the first adjustment signal controls the first adjustment transistor to turn on; when the low-side detection voltage is less than the second threshold, the second adjustment signal controls the second adjustment transistor to turn on. 9 . The CAN transceiver according to claim 7 , wherein the first threshold value ranges from 0 mV to 500 mV. 10 . The CAN transceiver according to claim 7 , wherein the second threshold value is in a range of −500 mV to 0 mV. 11 . The CAN transceiver according to claim 7 , wherein the high-side transistor is a P-channel field-effect transistor, and the low-side transistor is an N-channel field-effect transistor. 12 . The CAN transceiver according to claim 7 , wherein the first regulating transistor is an N-channel field effect transistor, and the second regulating transistor is a P-channel field effect transistor.

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