Acceleration method and accelerator for auto-negotiation of physical layer chip, and auto-negotiation method

Abstract

The invention relates to a physical layer chip auto-negotiation acceleration method, an accelerator and an auto-negotiation method. The acceleration method comprises the following steps: monitoring and acquiring a signal related to chip auto-negotiation time; and when the signal value of the signal does not reach the target value required by the auto-negotiation protocol and the signal value of the signal reaches a corresponding set threshold value, modifying the signal value of the signal into the target value required by the auto-negotiation protocol to accelerate the auto-negotiation process. Based on the scheme, the auto-negotiation time of the Ethernet physical layer chip can be greatly shortened, the simulation is faster, the waveform is smaller, and the working efficiency of research and development personnel is improved.

Description

Technical Field

[0001] The present application relates to the technical field of Ethernet physical layer chips, and in particular to an acceleration method, an accelerator, and a self-negotiation method for a physical layer chip. Background Art

[0002] Physical layer chip auto-negotiation is a technology used to determine the best connection parameters between two devices. This technology is usually used in Ethernet communication protocols. Auto-negotiation generally occurs at the physical layer, for example, it can be used to determine the transmission rate, duplex mode and other parameters between two devices.

[0003] The time that the physical layer chip of the prior art takes to perform self-negotiation is very long, often lasting more than 1 second. When performing chip circuit simulation, the circuit running for more than 1 second is an extremely long time, and the waveform file generated by self-negotiation will also be very large. When performing chip circuit simulation, when the chip uses the self-negotiation mode, it is necessary to wait for the chip self-negotiation process to complete before the chip can work normally. However, waiting for the self-negotiation process to complete consumes a lot of time, and the huge waveform file will also take up a lot of server memory space, which greatly affects the work efficiency of R&D personnel. Summary of the invention

[0004] In view of the above problems in the prior art, the present application provides an acceleration method, an accelerator, and a self-negotiation method for physical layer chip self-negotiation, which can greatly shorten the self-negotiation time of the Ethernet physical layer chip, make the simulation waveform file smaller, and improve the work efficiency of R&D personnel.

[0005] To achieve the above-mentioned objectives, the first aspect of the present application provides a method for accelerating physical layer chip self-negotiation, including: monitoring and acquiring signals related to the chip self-negotiation time; when the signal value of the signal does not reach the target value required by the self-negotiation protocol and the signal value of the signal reaches the corresponding set threshold, modifying the signal value of the signal to the target value required by the self-negotiation protocol to accelerate the self-negotiation process.

[0006] From the above, by monitoring the signal related to the self-negotiation time, and without affecting the normal operation of the chip, when the signal does not reach the target value specified by the protocol, the signal value of the signal is modified to the target value required by the protocol in advance, so as to quickly complete the current negotiation stage and enter the next stage, which can greatly shorten the self-negotiation time. In addition, since the negotiation process specified by the protocol is simplified, the simulation waveform can also be reduced to reduce the requirement for storage capacity.

[0007] As an implementation method of the present aspect, the signal includes at least one of the following: a first signal, used to indicate the waiting time of the chip before entering the self-negotiation process; a second signal, used to indicate the number of times the same fast link pulse is repeatedly sent during the chip self-negotiation process; a third signal, used to indicate the time interval between each group of fast link pulses during the chip self-negotiation process; a fourth signal, used to indicate the time interval between each sub-pulse in each group of fast link pulses during the chip self-negotiation process; wherein a group of the fast link pulses includes multiple sub-pulses; a fifth signal, used to indicate the time corresponding to when the received fast link pulse is loaded into the register during the chip self-negotiation process.

[0008] As described above, by monitoring multiple signals at multiple stages such as before and during the self-negotiation, the negotiation time can be shortened at each stage, thereby shortening the negotiation time as much as possible.

[0009] As an implementation method of this aspect, the monitoring and obtaining of signals related to the chip self-negotiation time includes: monitoring and obtaining the count value of the counter corresponding to each of the signals; when the count value reaches the corresponding set threshold, modifying the count value to the target value; wherein the corresponding set threshold is less than the target value; the thresholds corresponding to each signal are different, and the target values ​​corresponding to each signal are different.

[0010] As an implementation manner of this aspect, modifying the signal value of the signal to the target value required by the self-negotiation protocol includes: using a forced modification method to modify the signal value of the signal to the target value required by the self-negotiation protocol.

[0011] As described above, by monitoring the count value of the counter that obtains the corresponding signal and modifying the relevant count value by the forced modification method, the negotiation can quickly enter the next stage, thereby accelerating the negotiation process.

[0012] As an implementation method of this aspect, it also includes: after completing the acceleration, releasing the forcibly modified signal to restore the normal state of the chip.

[0013] From the above, by releasing the forced modified signal value after acceleration, it is possible to avoid interfering with the normal operation of the hardware, avoid the impact of subsequent tests, and ensure the consistency and accuracy of the simulation.

[0014] As an implementation method of this aspect, it also includes: calling the acceleration method by calling a macro during the compilation stage.

[0015] As an implementation of this aspect, it also includes: the acceleration method is applied in a chip verification environment.

[0016] The second aspect of the present application provides an accelerator for physical layer chip self-negotiation, including: a monitoring module, used to monitor and obtain signals related to the chip self-negotiation time; a signal modification module, used to modify the signal value of the signal to the target value required by the self-negotiation protocol when the signal value of the signal does not reach the target value required by the self-negotiation protocol and the signal value of the signal reaches the corresponding set threshold to accelerate the self-negotiation process.

[0017] The beneficial effects of this aspect can also be found in the description of the beneficial effects of each part of the first aspect above.

[0018] The third aspect of the present application provides a method for physical layer chip self-negotiation, comprising: connecting the chip participating in the self-negotiation to an accelerator, wherein one chip is connected to one accelerator; the accelerator is used to execute any one of the methods described in the first aspect when the chip performs self-negotiation.

[0019] The beneficial effects of this aspect can also be found in the description of the beneficial effects of each part of the first aspect above.

[0020] The fourth aspect of the present application provides a computing device, comprising: at least one processor; and at least one memory, which is connected to the processor and stores program instructions, and when the program instructions are executed by the at least one processor, the at least one processor executes the method for accelerating or negotiating the physical layer chip self-negotiation described in any one of the first aspects above.

[0021] The beneficial effects of this aspect can also be found in the description of the beneficial effects of each part of the first aspect above.

[0022] A fifth aspect of the present application provides a computer-readable storage medium having program instructions stored thereon, wherein when the program instructions are executed by a computer, the computer executes the method for accelerating or negotiating the physical layer chip self-negotiation described in any one of the first aspects above.

[0023] The beneficial effects of this aspect can also be found in the description of the beneficial effects of each part of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The various technical features of the present application and the relationship between them are further explained below with reference to the accompanying drawings. The accompanying drawings are exemplary, and some technical features are not shown in actual proportion. In addition, some drawings may omit technical features that are commonly used in the technical field to which the present application belongs and are not essential for understanding and implementing the present application, or additional technical features that are not essential for understanding and implementing the present application may be shown. In other words, the combination of the various technical features shown in the accompanying drawings is not used to limit the present application. In addition, throughout the present application, the same figure numbers refer to the same content. The specific description of the drawings is as follows:

[0025] Figure 1 The timing diagram of FLP specified in the 802.3 protocol provided for related technologies;

[0026] Figure 2 A flowchart of a method for accelerating physical layer chip self-negotiation is provided for an embodiment of the present application;

[0027] Figure 3 A schematic diagram of the structure of the accelerator for physical layer chip self-negotiation provided in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The technical solution provided by the present application is further described below with reference to the accompanying drawings and examples. It should be understood that the system structure and business scenarios provided in the examples of the present application are mainly to illustrate the possible implementation methods of the technical solution of the present application and should not be interpreted as the only limitation on the technical solution of the present application. It is known to those of ordinary skill in the art that with the evolution of the system structure and the emergence of new business scenarios, the technical solution provided by the present application is also applicable to similar technical problems.

[0030] It should be understood that the embodiments of the present application provide an acceleration solution in the physical layer chip self-negotiation process. Since the principles of solving the problems in these technical solutions are the same or similar, some repetitions may not be repeated in the following specific embodiments, but it should be considered that these specific embodiments have been referenced to each other and can be combined with each other.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. In case of any inconsistency, the meaning described in this specification or the meaning derived from the contents recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0032] Before introducing the embodiments of the present application, the related technologies are first studied.

[0033] In Ethernet, the relevant technology generally implements chip auto-negotiation based on the 802.3 protocol. The 802.3 protocol stipulates that the auto-negotiation information is sent using Fast Link Pulse (FLP). Figure 1The figure shows the timing diagram of FLP specified in the 802.3 protocol. In the 802.3 protocol, a sub-pulse pulse is sent every 62.5us in each group of fast link pulses. Each group of FLP includes 33 sub-pulses pulses in total, of which 17 pulses represent clock pulses (odd-numbered pulses), that is, Figure 1 The clock pulse shown in FIG. 1 shows that 16 pulses represent data pulses (even-numbered pulses), that is, Figure 1 In some stages of auto-negotiation (such as the initial link establishment stage, parameter confirmation stage, fault recovery stage, etc.), multiple groups of identical FLPs need to be sent before auto-negotiation can enter the next stage (such as the capability detection stage, parameter negotiation stage, etc.), and there is a certain time interval between each group of sent FLPs.

[0034] Based on the above related technologies, it often takes 1 second or more to complete the chip self-negotiation, resulting in a waste of time resources. Based on the research on the above related technologies, the self-negotiation acceleration solution of the present application is proposed.

[0035] Before introducing the acceleration solution of the physical layer chip self-negotiation of the present application, the application scenario of the solution is first introduced.

[0036] The acceleration scheme of the physical layer chip self-negotiation provided by the present application has the advantages of shortening the self-negotiation time and reducing the simulation waveform, so it is particularly suitable for use in fields with high time requirements and limited storage space. For example: the scheme can be applied to the development and testing of network communication equipment, such as in the design and verification of chips, through the scheme of the present application, the optimal transmission rate and duplex mode and other parameters can be quickly determined, thereby verifying the function and stability of the chip in various network environments. For another example: the scheme can also be applied to the fields of data centers and cloud computing, such as the need to quickly establish a network connection between servers, and the efficiency can be improved through the scheme. For another example: the scheme can also be applied to the fields of industrial automation and the Internet of Things, such as for industrial networks such as industrial Ethernet and fieldbus, the scheme based on the present application can accelerate the self-negotiation process of the physical layer, ensure fast communication and collaborative work between devices, and improve production efficiency and quality; for example, for Internet of Things applications such as smart homes and smart cities, the scheme based on the present application can accelerate the physical layer self-negotiation process of Internet of Things devices, so that devices can access the network faster and realize intelligent control and management.

[0037] It should be understood that the above application scenarios are exemplary descriptions and are not intended to limit the scope of this application.

[0038] Referring to the accompanying drawings below, a method for accelerating physical layer chip self-negotiation provided in an embodiment of the present application is described in detail.

[0039] like Figure 2 As shown, the physical layer chip self-negotiation acceleration method includes steps S110-S120:

[0040] S110: Monitor and obtain a signal related to the chip self-negotiation time.

[0041] In this embodiment, the signal may include the first signal to the fifth signal. Specifically:

[0042] The first signal is used to indicate the waiting time before the chip enters the self-negotiation process. Generally, the waiting time is tens of milliseconds to hundreds of milliseconds.

[0043] The second signal is used to indicate the number of times the same fast link pulse is repeatedly sent during the chip self-negotiation process. Generally, during one negotiation process, the same FLP will be repeatedly sent several to dozens of times.

[0044] The third signal is used to indicate the time interval between each group of fast link pulses during the chip self-negotiation process. Generally, the time interval is several microseconds to tens of microseconds.

[0045] The fourth signal is used to indicate the time interval between each sub-pulse in each group of fast link pulses during the chip self-negotiation process. Generally, the time interval is several microseconds to tens of microseconds, such as 62.5us in the above-mentioned related art. It should be understood that the fourth signal is the time interval between multiple sub-pulses included in a group of fast link pulses, and the third signal is the time interval between each group of fast link pulses.

[0046] The fifth signal is used to indicate the time corresponding to when the received fast link pulse is loaded into the register during the chip self-negotiation process, which is generally in nanosecond level.

[0047] In this step, the count value of the corresponding signal can be obtained by monitoring the counter corresponding to the above signal for subsequent processing.

[0048] S120: When the signal value of the signal does not reach the target value required by the auto-negotiation protocol and the signal value of the signal reaches the corresponding set threshold, modify the signal value of the signal to the target value required by the auto-negotiation protocol to accelerate the auto-negotiation process.

[0049] In this embodiment, the threshold is a predetermined minimum value that does not affect the chip self-negotiation process.

[0050] The following is a detailed introduction to the processing of each signal.

[0051] Before the chip enters the self-negotiation process, the count value of the counter corresponding to the chip waiting time (first signal) is monitored. When the count value reaches a preset value (i.e., the threshold corresponding to the first signal), the count value is forcibly modified to the target value to end the target stage and enter the next stage.

[0052] During the chip's self-negotiation process, the count value of the counter corresponding to the number of times the same fast link pulse is repeatedly sent (the second signal) is monitored. When the count value reaches the preset value (i.e., the threshold corresponding to the second signal), the count value is forcibly modified to the target value to end the target stage and enter the next stage. For example, during self-negotiation, the same fast link pulse needs to be sent 7 times in a certain stage to complete the count and enter the next stage. Here, through analysis, it is found that sending only once does not affect the normal operation of the chip. Therefore, when the count value is 1, the count value is forcibly modified to 7, so that it can quickly enter the next stage. It should be understood that in this example, 7 times is the target value of the second signal of this stage required by the self-negotiation protocol, and 1 time is the pre-set threshold for the second signal.

[0053] During the chip's self-negotiation process, the count value of the counter corresponding to the time interval (third signal) between each group of fast link pulses is monitored. When the count value reaches the corresponding preset value (i.e., the threshold corresponding to the third signal), the count value is forcibly modified to the target value to end the target stage and enter the next stage.

[0054] Monitor the count value of the counter corresponding to the time interval between each sub-pulse in each group of fast link pulses (the fourth signal). When the count value reaches the corresponding preset value (i.e., the threshold corresponding to the fourth signal), force the count value to be modified to the target value so that it ends the target stage and enters the next stage. For example, generally, the next stage can only be entered when the count value corresponding to the fourth signal reaches 63. Through analysis, it is found that entering the next stage after counting to 40 does not affect the normal function of the chip. Therefore, when the count value of the counter corresponding to the fourth signal is 40, it is forced to be modified to 63, so that it can quickly enter the next stage. It should be understood that in this example, 63 is the target value of the fourth signal of this stage required by the self-negotiation protocol, and 40 is the pre-set threshold for the fourth signal.

[0055] When receiving a fast link pulse, the count value of the counter corresponding to the time (fifth signal) corresponding to the time when the received fast link pulse is loaded into the register is monitored (i.e., the threshold value corresponding to the fifth signal), and the counter is used to determine what value is suitable for receiving the fast link pulse into the corresponding register. In this embodiment, when the receiving condition is met, the count value can be forcibly modified to the target value at any time to speed up the loading process.

[0056] It should be understood that not affecting the chip's self-negotiation process means that when the signal value of the relevant signal reaches a certain value, the smooth progress of the self-negotiation can be guaranteed. For example, although the self-negotiation protocol stipulates that the second signal needs to be sent 7 times before proceeding to the next stage, actually sending it only once will not affect the chip's self-negotiation result. Therefore, when the second signal value is 1, it means that the chip's self-negotiation process is not affected. At this time, the count value of the counter corresponding to the second signal can be forcibly modified to 7 to quickly enter the next stage, thereby saving self-negotiation time and reducing the size of the waveform file of the self-negotiation process.

[0057] As an implementation method, the above acceleration method can be written in System Verilog language, then the above forced modification of the count value of the counter can be implemented by the force keyword in the System Verilog language.

[0058] In this embodiment, after completing the acceleration of each stage, the signal that is forcibly modified can be released, that is, the signal that is forcibly modified can be restored to the actual real value. As an implementation method, the release keyword in the System Verilog language can be used to realize the release of the signal. By releasing the signal value that is forcibly modified, it is possible to avoid interfering with the normal operation of the hardware, avoid the impact of subsequent tests, and ensure the consistency and accuracy of the simulation.

[0059] In this embodiment, the above acceleration method can be implemented by calling a macro during the compilation stage.

[0060] Based on the above-mentioned acceleration scheme of the present embodiment, by monitoring the signal identical with the self-negotiation time, and forcibly modifying it to quickly complete the current stage to enter the next stage without affecting the normal operation of the chip, the acceleration of self-negotiation is realized, and the self-negotiation time is greatly shortened. And because some repeated pulses are omitted in the pulse transmission stage, the final simulation waveform file is made smaller, thereby reducing the requirement for storage space. Based on the scheme of the present application, in the simulation process of the zy06 (chip model) Ethernet 4-port physical layer chip, the negotiation process of clause 28 (a part of the IEEE802.3 standard for determining the optimal connection parameters supported between two devices to achieve the most efficient communication) can be accelerated, and the Gigabit self-negotiation is accelerated from 2.1s to 97ms, and the 100M self-negotiation is accelerated from 1.52s to 34ms, and the 10M self-negotiation is accelerated from 1.58s to 96ms, which shows the acceleration effect of the present application.

[0061] Another embodiment of the present application provides a physical layer chip self-negotiation accelerator 20, which should be understood as follows: Figure 3This is only a structural schematic diagram of a physical layer chip self-negotiation accelerator 20, and the present application does not limit the division of functional modules in the physical layer chip self-negotiation accelerator. Figure 3 As shown, the device 20 can be logically divided into multiple modules, each module can have different functions, and the function of each module can be implemented by a processor in a computing device reading and executing instructions in a memory. Exemplarily, the device 20 includes a monitoring module 210 and a signal modification module 220. In one implementation, the physical layer chip self-negotiation accelerator 20 is used to perform Figure 2 The content shown.

[0062] Specifically: the monitoring module 210 is used to monitor and obtain signals related to the chip self-negotiation time. The signal modification module 220 is used to modify the signal value of the signal to the target value required by the self-negotiation protocol when the signal value of the signal does not reach the target value required by the self-negotiation protocol and the signal value of the signal reaches the corresponding set threshold to accelerate the self-negotiation process.

[0063] The specific implementation of each functional module in this embodiment can refer to the introduction of the above embodiments, and this embodiment will not describe it in detail.

[0064] Another embodiment of the present application further provides a method for physical layer chip self-negotiation, including:

[0065] The chip participating in the self-negotiation is connected to the accelerator provided in the above embodiment, wherein one chip is connected to one accelerator. The accelerator is used to execute the acceleration method described in the above embodiment (i.e. Figure 2 The acceleration method shown).

[0066] As an implementation method, the accelerator is implemented in System Verilog language and can be integrated into the chip verification environment. The accelerator is called by defining macros during compilation. The accelerator interacts with the Ethernet physical layer chip self-negotiation module, automatically identifies the self-negotiation process during the simulation process, and controls chip-related signals to quickly skip the corresponding state, thereby accelerating the chip's self-negotiation process. By using the accelerator in the self-negotiation process, the self-negotiation time can be shortened to less than one-tenth of the original time (for example, from 2.14s to 97ms at Gigabit).

[0067] The specific implementation method of this embodiment can refer to the introduction of the above embodiments, and will not be described in detail in this embodiment.

[0068] Figure 4900 is a schematic structural diagram of a computing device 900 provided in an embodiment of the present application. The computing device can execute the above-mentioned acceleration method of physical layer chip self-negotiation or each optional embodiment of the method of physical layer chip self-negotiation. The computing device can be a terminal or a chip or chip system inside the terminal. Figure 4 As shown, the computing device 900 includes: a processor 910 , a memory 920 , and a communication interface 930 .

[0069] It should be understood that Figure 4 The communication interface 930 in the computing device 900 shown may be used to communicate with other devices, and may specifically include one or more transceiver circuits or interface circuits.

[0070] The processor 910 may be connected to a memory 920. The memory 920 may be used to store the program code and data. Therefore, the memory 920 may be a storage unit inside the processor 910, or an external storage unit independent of the processor 910, or a component including a storage unit inside the processor 910 and an external storage unit independent of the processor 910.

[0071] Optionally, the computing device 900 may further include a bus. The memory 920 and the communication interface 930 may be connected to the processor 910 via the bus. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 A line without an arrow is used to represent the bus, but this does not mean that there is only one bus or one type of bus.

[0072] It should be understood that in the embodiment of the present application, the processor 910 may adopt a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. Alternatively, the processor 910 may adopt one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiment of the present application.

[0073] The memory 920 may include a read-only memory and a random access memory, and provides instructions and data to the processor 910. A portion of the processor 910 may also include a nonvolatile random access memory. For example, the processor 910 may also store information on the device type.

[0074] When the computing device 900 is running, the processor 910 executes the computer-executable instructions in the memory 920 to perform any operation step of the above method and any optional embodiment thereof.

[0075] It should be understood that the computing device 900 according to the embodiment of the present application can correspond to the corresponding subjects in the methods according to the embodiments of the present application, and the above-mentioned and other operations and / or functions of each module in the computing device 900 are respectively for implementing the corresponding processes of each method of the present embodiment. For the sake of brevity, they will not be repeated here.

[0076] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0077] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0078] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0079] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0080] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0081] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0082] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, it is used to execute the above method, which includes at least one of the solutions described in the above embodiments.

[0083] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive lists) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing programs, which can be used by instruction execution systems, devices or devices or used in combination with them.

[0084] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0085] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0086] Computer program code for performing the operation of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., using an Internet service provider to connect through the Internet).

[0087] In addition, the words "first, second, third, etc." or module A, module B, module C and other similar terms in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that the specific order or sequence can be interchanged where permitted so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0088] In the above description, the numbers representing the steps, such as S110, S120, etc., do not necessarily mean that the steps will be executed in this manner. If permitted, the order of the steps can be interchanged or they can be executed simultaneously.

[0089] The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the features, integers, steps or components mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components and groups thereof. Therefore, the expression "a device comprising means A and B" should not be limited to a device consisting of components A and B only.

[0090] References to "one embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. In addition, in one or more embodiments, the particular features, structures, or characteristics can be combined in any appropriate manner, as would be apparent to one of ordinary skill in the art from this disclosure.

[0091] Note that the above are only preferred embodiments of the present application and the technical principles used. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present application, all of which belong to the scope of protection of the present application.

Claims

1. A method for accelerating physical layer chip self-negotiation, characterized in that: include: Monitor and obtain signals related to chip self-negotiation time; When the signal value of the signal does not reach the target value required by the auto-negotiation protocol and the signal value of the signal reaches the corresponding set threshold, the signal value of the signal is modified to the target value required by the auto-negotiation protocol to accelerate the auto-negotiation process.

2. The method according to claim 1, characterized in that: The signal includes at least one of the following: A first signal, used to indicate the waiting time of the chip before entering the auto-negotiation process; A second signal, used to indicate the number of times the same fast link pulse is repeatedly sent during the chip self-negotiation process; A third signal is used to indicate the time interval between each group of fast link pulses during the chip self-negotiation process; A fourth signal is used to indicate the time interval between each sub-pulse in each group of fast link pulses during the chip self-negotiation process; wherein a group of the fast link pulses includes a plurality of sub-pulses; The fifth signal is used to indicate the time corresponding to when the received fast link pulse is loaded into the register during the chip self-negotiation process.

3. The method according to claim 2, characterized in that The monitoring and obtaining of the signal related to the chip self-negotiation time includes: Monitor and obtain the count value of the counter corresponding to each of the signals; When the count value reaches the corresponding set threshold, modifying the count value to the target value; Among them, the corresponding set threshold is less than the target value; the thresholds set corresponding to each signal are different, and the target values ​​corresponding to each signal are different.

4. The method according to claim 1, characterized in that: The step of modifying the signal value of the signal to a target value required by the self-negotiation protocol includes: By using a forced modification method, the signal value of the signal is modified to a target value required by the self-negotiation protocol.

5. The method according to claim 1, characterized in that Also includes: After the acceleration is completed, the forcibly modified signal is released to restore the normal state of the chip.

6. The method according to claim 1, characterized in that Also includes: The acceleration method is called by calling a macro during the compilation phase.

7. The method according to any one of claims 1 to 6, characterized in that: Also includes: The acceleration method is applied in a chip verification environment.

8. A physical layer chip self-negotiation accelerator, characterized in that: include: A monitoring module is used to monitor and obtain signals related to the chip self-negotiation time; A signal modification module is used to modify the signal value of the signal to the target value required by the self-negotiation protocol to accelerate the self-negotiation process when the signal value of the signal does not reach the target value required by the self-negotiation protocol and the signal value of the signal reaches the corresponding set threshold.

9. A method for physical layer chip self-negotiation, characterized in that: include: Connect the chips participating in the auto-negotiation to the accelerator, where one chip is connected to one accelerator; The accelerator is used to execute the method according to any one of claims 1 to 7 when the chip performs self-negotiation.

10. A computing device, characterized in that include: at least one processor; And at least one memory connected to the processor and storing program instructions, which, when executed by the at least one processor, enable the at least one processor to execute the acceleration method described in any one of claims 1-7 or the self-negotiation method described in claim 9.

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