Semiconductor structure, stacked structure and preparation method thereof

Abstract

The present disclosure relates to a semiconductor structure, a stacked structure, and a method for preparing the same. The semiconductor structure includes a first tensioning layer, a second tensioning layer, a floating structure, a source structure and a drain structure located on opposite sides of the floating structure along a vertical direction, and a first gate structure located on one side of the floating structure along a first direction. The first tensioning layer covers the top surface of the first gate structure and the surface of the floating structure away from the floating structure along the first direction; the second tensioning layer covers the surface of the floating structure away from the first gate structure along the first direction. The semiconductor structure can increase the lifetime of holes in the floating structure and reduce leakage current. It can also improve sensing margin, reduce the bit error rate during data reading, and enhance storage performance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a stacked structure, and a preparation method thereof. Background Art

[0002] With the advancement of semiconductor technology and the shrinking of process nodes, dynamic random access memory (DRAM), which has a memory cell consisting of one transistor and one capacitor (1Transistor 1Capacitor, or 1T1C), requires capacitors for data storage. However, the manufacturing process and storage performance of capacitors have constrained the development of DRAM. Consequently, DRAM with a memory cell consisting of one transistor and no capacitor (1T0C) has been proposed. The commonly used 1T0C memory cell is composed of a floating body transistor cell (FBC).

[0003] However, the storage performance of the floating body transistor unit has many deficiencies and needs to be further improved. Therefore, a semiconductor structure is urgently needed to enhance the overall performance of the floating body transistor unit to improve its storage accuracy and storage efficiency. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure, a stacked structure and a method for manufacturing the same, so as to improve the storage yield and storage efficiency of an 1T0C memory composed of floating body transistor units.

[0005] According to various embodiments of the present disclosure, on the one hand, a semiconductor structure is provided, which includes a first tensile layer, a second tensile layer, a floating body structure, a source structure and a drain structure located on opposite sides of the floating body structure along the vertical direction, and a first gate structure located on one side of the floating body structure along the first direction; wherein the first tensile layer covers the top surface of the first gate structure and the surface away from the floating body structure along the first direction; the second tensile layer covers the surface of the floating body structure along the first direction away from the first gate structure.

[0006] In the semiconductor structure of the above embodiment, the first tensile layer covers the top surface of the first gate structure and the surface away from the floating structure along the first direction, and the second tensile layer covers the surface of the floating structure away from the first gate structure along the first direction. The first tensile layer and the second tensile layer apply tension to the floating structure on both sides of the floating structure along the first direction, thereby generating corresponding tensile stress in the floating structure. Therefore, for the holes in the floating structure, the tensile stress separates the light and heavy hole bands, which can increase the effective mass of the holes, thereby increasing the lifetime of the holes and reducing leakage current, thereby improving the storage performance of the transistor. In addition, the first tensile layer is arranged on one side of the first gate structure along the first direction, which can also improve the mobility of the channel electrons. While improving the hole lifetime, it can also increase the sensing margin, reduce the bit error rate of the storage process, and improve storage accuracy. In the related art, as the size of DRAM devices shrinks, the sensing margin continues to decrease, affecting the storage performance of the device. The present disclosure provides tension to the first gate structure and the floating structure by setting a first tension layer and a second tension layer near the first gate structure and the floating structure, thereby generating tensile stress to improve the carrier mobility and increase the read current, thereby improving the overall performance of the memory.

[0007] In some embodiments, a dimension of the first tensile layer in the vertical direction is greater than or equal to a dimension of the floating structure in the vertical direction.

[0008] In some embodiments, a dimension of the second tensile layer in the vertical direction is greater than or equal to a dimension of the floating structure in the vertical direction.

[0009] In some embodiments, the material of the first tensile layer is selected from silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride oxynitride, silicon hydrogenated carbon, and combinations thereof.

[0010] In some embodiments, the material of the second tensile layer is selected from silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon hydrogenated carbon, and combinations thereof.

[0011] In some embodiments, the source structure includes a source isolation layer and a third tension layer; wherein the source isolation layer is located on the bottom surface of the floating structure; and the third tension layer is located on the surface of the source isolation layer away from the floating structure in a vertical direction.

[0012] In some embodiments, the floating body structure includes a first floating body portion and a second floating body portion arranged along a first direction and adjacent to each other; the top surface of the first floating body portion is higher than the top surface of the second floating body portion; the bottom surface of the first floating body portion is connected to the source structure and the top surface is connected to the drain structure; the first gate structure is located on one side of the first floating body structure along the first direction, and the bottom surface of the second floating body portion is connected to the source structure. The semiconductor structure also includes a second gate structure, the second gate structure is located on the other side of the first floating body portion along the first direction and is also located on the second floating body portion; wherein the top surface of the second gate structure is no higher than the top surface of the first floating body portion.

[0013] In some embodiments, the semiconductor structure further includes a first dielectric layer, a second dielectric layer and a third dielectric layer; wherein the first dielectric layer is located on a surface of the drain structure close to the first tensile layer along the first direction, and a surface of the first floating body portion close to the first tensile layer along the first direction; the second dielectric layer is located on a surface of the drain structure away from the first tensile layer along the first direction, and a surface of the first floating body portion that is higher than the second floating body portion away from the first tensile layer along the first direction; the third dielectric layer is located on the top surface of the second floating body portion.

[0014] In some embodiments, the first gate structure includes a first gate dielectric layer and a first gate conductive layer; wherein the first gate dielectric layer is a portion of the first dielectric layer located on the surface of the floating body structure along the first direction close to the first tensile layer, and the first gate conductive layer is located on the surface of the first gate dielectric layer along the first direction away from the first floating body portion.

[0015] In some embodiments, the second gate structure includes a second gate conductive layer and a second gate dielectric layer; wherein, the second gate conductive layer is located on the second floating body portion, and the second gate dielectric layer includes a third dielectric layer and a portion of the second dielectric layer located between the first floating body portion and the second gate conductive layer; wherein, the second gate dielectric layer covers the bottom surface of the second gate conductive layer and its surface close to the first floating body portion.

[0016] Another aspect of the present disclosure provides a stacked structure comprising a substrate, and a plurality of semiconductor structures according to any one of the embodiments of the present disclosure arranged along a first direction on a top surface of the substrate; the first tensile layer of the semiconductor structure serves as the second tensile layer of another adjacent semiconductor structure.

[0017] In the stacked structure in the above embodiment, by arranging a first tensile layer and a second tensile layer adjacent to the floating structure and the first gate structure, tensile stress is generated inside the first gate structure and the floating structure, which can improve the mobility of carriers inside the floating structure and increase the effective mass of holes, thereby achieving technical effects such as improving the sensing margin, increasing the effective life of holes, and reducing leakage current.

[0018] Another aspect of the present disclosure provides a method for preparing a stacked structure, including: providing a substrate; forming active columns arranged at intervals along a first direction on the top surface of the substrate, the active columns including a floating structure, and a source structure and a drain structure located on opposite sides of the floating structure along the vertical direction; forming a first gate structure on one side of the floating structure along the first direction; forming a first tensile layer and a second tensile layer, the first tensile layer covering the top surface of the first gate structure and the surface away from the floating structure along the first direction; the second tensile layer covering the surface of the floating structure along the first direction away from the first gate structure.

[0019] In the preparation method of the stacked structure in the above embodiment, a first gate structure is formed on one side of the floating structure along the first direction, and then a first tensile layer is formed on the top surface of the first gate structure and the surface away from the floating structure along the first direction, and a second tensile layer is formed on the surface of the floating structure along the first direction away from the first gate structure, so that corresponding tensile stress is generated inside the floating structure, thereby changing the effective mass of the holes inside it, thereby increasing the effective lifetime of the holes and reducing leakage current; in addition, tensile stress can also increase the migration speed of carriers and the reading current, thereby increasing the sensing margin and thereby improving storage performance.

[0020] In some embodiments, active pillars are formed, including: forming a stacked layer on the top surface of the substrate, the stacked layer including a source material layer, an initial floating material layer and an initial drain material layer stacked in a vertical direction; patterning the stacked layer to form initial pillars arranged at intervals along a first direction, the initial pillars including a floating material layer, and a source structure and a drain material layer located on opposite sides of the floating material layer along the vertical direction, wherein the source structure includes a third tension layer and a source isolation layer, the source isolation layer is located on the bottom surface of the floating structure, and the third tension layer is located on the surface of the source isolation layer away from the floating structure in the vertical direction; removing part of the drain material layer to form a drain structure, and removing part of the floating material layer to form a floating structure.

[0021] In some embodiments, the floating body structure includes a first floating body portion and a second floating body portion arranged along a first direction and adjacent to each other; the top surface of the first floating body portion is higher than the top surface of the second floating body portion; the bottom surface of the first floating body portion is connected to the source structure and the top surface is connected to the drain structure; the bottom surface of the second floating body portion is connected to the source structure; while forming the first gate structure, it also includes: forming a second gate structure, the second gate structure is located on a side of the first floating body portion away from the first gate structure along the first direction and also on the second floating body portion; wherein the top surface of the second gate structure is not higher than the top surface of the first floating body portion.

[0022] In some embodiments, a first gate structure and a second gate structure are formed, including: forming a third dielectric layer on the top surface of the second floating body portion; forming a first dielectric layer on the surface of the drain structure close to the first tensile layer along the first direction, and on the surface of the first floating body portion close to the first tensile layer along the first direction, and forming a second dielectric layer on the surface of the drain structure away from the first tensile layer along the first direction, and on the surface of the portion of the first floating body portion higher than the second floating body portion, away from the first tensile layer along the first direction; wherein, the portion of the first dielectric layer located on the surface of the floating body structure close to the first tensile layer along the first direction is the first gate dielectric layer; forming a first gate conductive layer on the surface of the first gate dielectric layer away from the first floating body portion along the first direction, and forming a second gate conductive layer on the second floating body portion; wherein the third dielectric layer and the portion of the second dielectric layer located between the first floating body portion and the second gate conductive layer are used to jointly constitute the second gate dielectric layer; the first gate dielectric layer and the first gate conductive layer are used to jointly constitute the first gate structure, and the second gate dielectric layer and the second gate conductive layer are used to jointly constitute the second gate structure.

[0023] In some embodiments, there is a first isolation material layer between the initial columns adjacent along the first direction; after the active column is formed, it also includes: removing the portion of the first isolation material layer located between the floating structures adjacent along the first direction and between the drain structures adjacent along the first direction, and the remaining first isolation material layer forms a first isolation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 A schematic cross-sectional view of a semiconductor structure in a related art according to an embodiment of the present disclosure is shown;

[0026] Figure 2 A schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure is shown;

[0027] Figure 3 A schematic cross-sectional view of a semiconductor structure provided by another embodiment of the present disclosure is shown;

[0028] Figure 4 Figure (a) shows a simple schematic diagram of the valence band distribution in a floating structure provided by one embodiment of the present disclosure;

[0029] Figure 4FIG. (b) shows a simple schematic diagram of valence band distribution in a floating structure provided by another embodiment of the present disclosure;

[0030] Figure 5 A schematic cross-sectional view of a semiconductor structure provided by another embodiment of the present disclosure is shown;

[0031] Figure 6 Shown is a schematic diagram of a three-dimensional structure of a stacking structure provided by an embodiment of the present disclosure;

[0032] Figure 7 A flowchart showing a method for preparing a stacked structure provided by an embodiment of the present disclosure;

[0033] Figures 8-19 Shown is a schematic cross-sectional view of a structure obtained in each step of a method for preparing a stacked structure provided in one embodiment of the present disclosure.

[0034] Description of reference numerals:

[0035] 10. Floating unit; 11. Source; 12. Drain; 13. First gate; 14. Second gate; 20. Substrate; 21. Source structure; 21a. Source isolation layer; 21b. Third tension layer; 211. Source material layer; 211a. Source isolation material layer; 211b. Third tension material layer; 22. Floating structure; 221. Floating material layer; 2211. Initial floating material layer; 23. Second isolation layer; 24. Drain structure; 241. Drain material layer; 25. Initial column; 26. First isolation layer; 26a. First sub-isolation layer; 26b. Second sub-isolation layer; 26 c. third sub-isolation layer; 261. first isolation material layer; 261a. first sub-isolation material layer; 261b. second sub-isolation material layer; 261c. third sub-isolation material layer; 27. active pillar; 28. third dielectric layer; 281. third dielectric material layer; 29a. first tension layer; 29b. second tension layer; 2911. initial tension material layer; 291. intermediate tension material layer; 292. tension filling layer; 30. first dielectric layer; 31. second dielectric layer; 32. first gate conductive layer; 33. second gate conductive layer; G1. first gate structure; G2. second gate structure. DETAILED DESCRIPTION

[0036] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0038] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0039] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0040] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0042] See also Figure 1, the 1T DRAM cell adopts a floating body transistor cell, which includes a floating body cell 10 and a source 11 and a drain 12 on opposite sides of the floating body cell 10 in the vertical direction, and a first gate 13 and a second gate 14 on opposite sides in the horizontal direction. It has high cell density, high compatibility with other structures, and can replace capacitors to meet complex storage processes. However, there are also some problems, such as its low body potential, low sensing margin, and short reading time after programming. As the size of DRAM devices shrinks, the sensing margin continues to decrease, and due to the narrow channel effect and short channel effect of each node, the change of the sensing amplifier transistor is aggravated, resulting in reduced accuracy of memory reading data and reduced reading efficiency, which seriously affects the storage performance of the memory.

[0043] Based on the above technical problems, the present disclosure provides a semiconductor structure, a stacked structure and a preparation method thereof, aiming to improve the storage yield and storage efficiency of an 1T0C memory composed of floating body transistor units.

[0044] It should be noted that the vertical direction described in the embodiments of the present disclosure is the oy direction, that is, the direction perpendicular to the top surface of the substrate, the first direction is the ox direction, and the second direction is the oz direction.

[0045] As an example, see Figure 2 On the one hand, the present disclosure provides a semiconductor structure, which includes a first tensile layer 29a, a second tensile layer 29b, a floating structure 22, a source structure 21 and a drain structure 24 located on opposite sides of the floating structure 22 along the vertical direction, and a first gate structure G1 located on one side of the floating structure 22 along the first direction; wherein, the first tensile layer 29a covers the top surface of the first gate structure G1 and the surface away from the floating structure 22 along the first direction; the second tensile layer 29b covers the surface of the floating structure 22 along the first direction away from the first gate structure G1.

[0046] In the semiconductor structure of the above embodiment, the first tensile layer 29a covers the top surface of the first gate structure G1 and the surface away from the floating structure 22 along the first direction, and the second tensile layer 29b covers the surface of the floating structure 22 along the first direction away from the first gate structure G1. The first tensile layer 29a and the second tensile layer 29b apply tension to the floating structure 22 on both sides of the floating structure 22 along the first direction, thereby generating corresponding tensile stress in the floating structure 22. Therefore, for the holes in the floating structure 22, the tensile stress separates the light and heavy hole bands, which can increase the effective mass of the holes, thereby increasing the hole lifetime and reducing leakage current, thereby improving the storage performance of the transistor. In addition, the first tensile layer 29a is arranged on one side of the first gate structure G1 along the first direction, which can also improve the mobility of channel electrons. While improving the hole lifetime, it can also increase the sensing margin, reduce the bit error rate of the storage process, and improve storage accuracy. The present disclosure provides tension to the first gate structure G1 and the floating structure 22 by setting a first tension layer 29a and a second tension layer 29b near the first gate structure G1 and the floating structure 22, thereby generating tensile stress to improve the mobility of carriers and increase the read current, thereby improving the overall performance of the memory.

[0047] As an example, see Figure 2 The dimension of the first tensile layer 29a along the vertical direction is greater than or equal to the dimension of the floating structure 22 along the vertical direction, so that the first tensile layer 29a completely covers the top surface of the first gate structure G1 and the surface away from the floating structure 22 along the first direction, and indirectly covers the entire side surface of the floating structure 22 close to the first gate structure G1 along the first direction, thereby changing the effective mass of the holes in the floating structure 22 through tensile stress to increase the lifetime of the holes; at the same time, the first tensile layer 29a can also improve the mobility of electrons in the channel to increase the sensing margin.

[0048] As an example, see Figure 2 The dimension of the second tensile layer 29b along the vertical direction is greater than or equal to the dimension of the floating structure 22 along the vertical direction, so that the second tensile layer 29b completely covers the surface of the floating structure 22 along the first direction away from the first gate structure G1, thereby providing tension for the entire surface of the floating structure 22 along the first direction away from the first gate structure G1, thereby generating tensile stress inside the floating structure 22.

[0049] As an example, see Figure 2 The material of the first tensile layer 29a is selected from silicon nitride, silicon oxynitride, silicon carbide nitride, silicon oxycarbon nitride, silicon hydrogenated carbon, and combinations thereof. The material of the first tensile layer 29a may also be other materials capable of generating tension or tension to provide tension to the floating structure 22. In this embodiment, the material of the first tensile layer 29a is silicon nitride.

[0050] As an example, see Figure 3 The source structure 21 includes a source isolation layer 21a and a third tensile layer 21b; wherein the source isolation layer 21a is located on the bottom surface of the floating structure 22; and the third tensile layer 21b is located on the surface of the source isolation layer 21a away from the floating structure 22 in the vertical direction. In the source structure 21, biaxial tensile stress is generated for the floating structure 22 by the combination of the source isolation layer 21a and the third tensile layer 21b, thereby increasing the lifetime of the holes in the floating structure 22 close to the source structure 21. In addition, the source isolation layer 21a isolates the floating structure 22 and the third tensile layer 21b from each other to prevent the low energy level of the third tensile layer 21b from causing the holes in the floating structure 22 to accumulate in the source structure 21, thereby preventing the holes from being extracted from the floating structure 22. The above-mentioned setting of the source structure 21 can make the floating structure 22 be affected by the biaxial tensile stress, thereby increasing the effective mass of the holes and thus increasing the lifetime of the holes.

[0051] As an example, see Figure 3 , the floating body structure 22 includes a first floating body portion and a second floating body portion arranged along the first direction and adjacent to each other; the top surface of the first floating body portion is higher than the top surface of the second floating body portion; the bottom surface of the first floating body portion is connected to the source structure 21 and the top surface is connected to the drain structure 24, the first gate structure G1 is located on one side of the first floating body portion along the first direction, and the bottom surface of the second floating body portion is connected to the source structure 21. The semiconductor structure also includes a second gate structure G2, which is located on the other side of the first floating body portion along the first direction and on the second floating body portion; wherein the top surface of the second gate structure G2 is not higher than the top surface of the first floating body portion. The present disclosure also improves the hole generation rate under the gate-induced drain leakage (GIDL) effect by arranging a double-gate structure on both sides of the drain structure 24, thereby improving the storage performance.

[0052] As an example, see Figure 3 The semiconductor structure also includes a first dielectric layer 30, a second dielectric layer 31, and a third dielectric layer 28; wherein the first dielectric layer 30 is located on the surface of the drain structure 24 close to the first tensile layer 29a along the first direction, and the surface of the first floating body portion close to the first tensile layer 29a along the first direction; the second dielectric layer 31 is located on the surface of the drain structure 24 away from the first tensile layer 29a along the first direction, and the surface of the portion of the first floating body portion that is higher than the second floating body portion away from the first tensile layer 29a along the first direction; the third dielectric layer 28 is located on the top surface of the second floating body portion. The first dielectric layer 30, the second dielectric layer 31, and the third dielectric layer 28 can isolate the first tensile layer 29a, the second tensile layer 29b from the drain structure 24 and the floating body structure 22, and provide a gate dielectric layer for the first gate structure G1 and the second gate structure G2.

[0053] As an example, see Figure 3 The first gate structure G1 is composed of a first gate dielectric layer and a first gate conductive layer 32. The first gate dielectric layer is the portion of the first dielectric layer 30 located on the surface of the floating body structure 22 along the first direction, close to the first tensile layer 29a. The first gate conductive layer 32 is located on the surface of the first gate dielectric layer along the first direction, away from the first floating body portion. The first gate structure G1 can control the source structure 21 and the drain structure 24. It is adjacent to the first tensile layer 29a. The first tensile layer 29a can provide tension to the first gate conductive layer 32, thereby improving the mobility of channel electrons and enhancing the sensing margin.

[0054] As an example, see Figure 3 The second gate structure G2 includes a second gate conductive layer 33 and a second gate dielectric layer. The second gate conductive layer 33 is located on the second floating body portion. The second gate dielectric layer includes a third dielectric layer 28 and a portion of the second dielectric layer 31 located between the first floating body portion and the second gate conductive layer 33. The second gate dielectric layer covers the bottom surface of the second gate conductive layer 33 and its surface near the first floating body portion. The second gate structure G2 can work together with the first gate structure G1 to control the end of the floating body structure 22 near the drain structure 24, thereby forming a dual-gate structure near the drain structure 24 to improve the hole generation rate near the drain structure 24.

[0055] As an example, see Figure 3 The semiconductor structure further includes a first isolation layer 26 that covers at least the bottom surface of the first gate structure G1; and a second isolation layer 23 located between the first isolation layer 26 and the substrate 20. The first isolation layer 26 and the second isolation layer 23 can isolate the substrate 20 from the first gate structure G1, and can also isolate the substrate 20 from the first tensile layer 29a and the second tensile layer 29b.

[0056] As an example, see Figure 4 Figure (a) and Figure 3 Before the semiconductor structure provided by the present disclosure is adopted, since the first tension layer 29a and the second tension layer 29b are not provided to provide tension, no tensile stress is generated in the floating structure 22. Therefore, the light hole (LH) band and the heavy hole (HH) band are almost located at the same position, the electron mobility is low, the hole lifetime is short, and the sensing margin is low. SO in the figure represents the band split by spin-orbit coupling; please refer to Figure 4 (b) in FIG, after adopting the Figure 3After the semiconductor structure shown, for holes, tensile stress can separate the light and heavy hole bands. After the action of uniaxial tensile stress, the light and heavy hole energy bands separate. The heavy hole energy band is lower, so carriers preferentially occupy the heavy holes, thereby increasing the effective mass of the holes. According to the principle that the greater the effective mass of the carrier, the smaller the thermal motion speed, the carriers occupying the heavy holes leak more slowly, thereby increasing their lifespan and reducing leakage current, improving the sensing margin, and thus improving the storage performance of 1T DRAM.

[0057] As an example, see Figure 5 The first isolation layer 26 includes a first sub-isolation layer 26a, a second sub-isolation layer 26b, and a third sub-isolation layer 26c. The first sub-isolation layer 26a covers at least the bottom surface of the first gate structure G1; the second sub-isolation layer 26b covers at least the bottom surface of the first sub-isolation layer 26a and its opposite side surfaces along the first direction; and the third sub-isolation layer 26c covers at least the bottom surface of the second sub-isolation layer 26b and its opposite side surfaces along the first direction. The material of the first sub-isolation layer 26a is the same as that of the third sub-isolation layer 26c, and different from that of the second sub-isolation layer 26b.

[0058] As an example, see Figure 5 The semiconductor structure further includes a bit line structure (not shown), which is located on a side of the drain structure 24 away from the floating structure 22 along the vertical direction.

[0059] As an example, see Figure 5 The material of the floating structure 22 may include but is not limited to first type light ion doped silicon or other materials; specifically, the doping concentration range may be greater than or equal to 1E16cm -3 , less than or equal to 1E18cm -3 .

[0060] As an example, see Figure 5 The material of the drain structure 24 may include silicon or other materials doped with the second type of heavy ions; specifically, the doping concentration range may be greater than or equal to 1E20 cm -3 , less than or equal to 1E21cm -3 .

[0061] As an example, see Figure 5 The material of the source isolation layer 21a may include silicon or other materials doped with the second type of heavy ions; specifically, the doping concentration range may be greater than or equal to 1E20cm -3 , less than or equal to 1E21cm -3 .

[0062] As an example, see Figure 5The material of the third tension layer 21b may include second type heavy ion doped silicon germanium or other materials; specifically, the doping concentration range may be greater than or equal to 1E20cm -3 , less than or equal to 1E21cm -3 .

[0063] As an example, see Figure 5 The materials of the first sub-isolation layer 26a and the third sub-isolation layer 26c may include but are not limited to silicon nitride; the material of the second sub-isolation layer 26b may include but are not limited to silicon oxide.

[0064] As an example, see Figure 5 The materials of the first gate conductive layer 32 and the second gate conductive layer 33 may include conductive materials such as polysilicon, titanium, titanium nitride, tungsten silicide or tungsten.

[0065] As an example, see Figure 5 The materials of the first dielectric layer 30 and the second dielectric layer 31 may include but are not limited to insulating materials such as silicon oxide.

[0066] As an example, see Figure 5 The material of the third dielectric layer 28 may include any insulating material with a low dielectric constant.

[0067] As an example, in the above embodiments, the first type is P-type and the second type is N-type, or the first type is N-type and the second type is P-type. P-type impurity ions may include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. N-type impurity ions may include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0068] As an example, see Figure 5 and Figure 6 Another aspect of the present disclosure provides a stacked structure comprising a substrate and, located on a top surface of the substrate and arranged along a first direction, a plurality of semiconductor structures according to any of the embodiments of the present disclosure; the first tensile layer of each semiconductor structure serves as the second tensile layer of another adjacent semiconductor structure. Furthermore, the stacked structure may further comprise a plurality of semiconductor structures according to any of the embodiments of the present disclosure arranged along a second direction, wherein both the first gate structure G1 and the second gate structure G2 extend along the second direction, and each of the first gate structure G1 and the second gate structure G2 is connected to a plurality of floating structures 22 arranged along the second direction.

[0069] In the stacking structure in the above embodiment, please refer to Figure 5 and Figure 6By setting a first tensile layer 29a and a second tensile layer 29b adjacent to the floating structure 22 and the first gate structure G1, tensile stress is generated inside the first gate structure G1 and the floating structure 22, which can improve the mobility of carriers inside the floating structure 22 and increase the effective mass of holes, thereby achieving technical effects such as improving the sensing margin, increasing the effective life of holes, and reducing leakage current.

[0070] As an example, see Figure 7 Another aspect of the present disclosure provides a method for preparing a stacked structure, comprising:

[0071] Step S2: providing a substrate;

[0072] Step S4: forming active pillars spaced apart along a first direction on the top surface of the substrate, the active pillars comprising a floating structure, and a source structure and a drain structure located on opposite sides of the floating structure in a vertical direction;

[0073] Step S6: forming a first gate structure on one side of the floating structure along the first direction;

[0074] Step S8: forming a first tension layer and a second tension layer, wherein the first tension layer covers the top surface of the first gate structure and the surface away from the floating structure along the first direction; the second tension layer covers the surface of the floating structure away from the first gate structure along the first direction.

[0075] In the preparation method of the stacked structure in the above embodiment, a first gate structure is formed on one side of the floating structure along the first direction, and then a first tensile layer is formed on the top surface of the first gate structure and the surface away from the floating structure along the first direction, and a second tensile layer is formed on the surface of the floating structure along the first direction away from the first gate structure, so that corresponding tensile stress is generated inside the floating structure, thereby changing the effective mass of the holes inside it, thereby increasing the effective life of the holes and reducing leakage current; in addition, tensile stress can also increase the migration speed of carriers and the reading current, thereby increasing the sensing margin, thereby improving storage accuracy and other storage performance.

[0076] As an example, see Figure 7 Step S2 and Figure 8The substrate 20 can be made of semiconductor material, insulating material, conductive material or any combination thereof. The substrate 20 can be a single-layer structure or a multi-layer structure. For example, the substrate 20 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 20 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Those skilled in the art can select the type of substrate 20 according to the type of transistor formed on the substrate 20. Therefore, the type of substrate 20 should not limit the scope of protection of the present disclosure.

[0077] As an example, see Figure 7 Step S4 in the step of forming the active pillar comprises:

[0078] Step S41: forming a stacked layer on the top surface of the substrate, the stacked layer including a source material layer, an initial floating body material layer, and an initial drain material layer stacked in a vertical direction;

[0079] Step S42: patterning the stacked layers to form initial columns spaced apart along a first direction, the initial columns comprising a floating material layer, and a source structure and a drain material layer located on opposite sides of the floating material layer along a vertical direction, wherein the source structure comprises a third tensioning layer and a source isolation layer, the source isolation layer being located on a bottom surface of the floating structure, and the third tensioning layer being located on a surface of the source isolation layer vertically away from the floating structure;

[0080] Step S45: removing a portion of the drain material layer to form a drain structure, and removing a portion of the floating body material layer to form a floating body structure.

[0081] As an example, see Figure 7 Step S4 in the method further includes, after step S42 and before step S45:

[0082] Step S43: forming a second isolation layer covering the top surface of the substrate;

[0083] Step S44: forming a first isolation material layer between adjacent initial pillars along the first direction and on the second isolation layer.

[0084] In step S41, refer to Figure 7 Step S4 and Figure 8First, the stacked layers are patterned to form initial columns 25 spaced apart along a first direction. The initial columns 25 include a floating material layer 221 and a source structure 21 located on one side of the floating material layer 221 along the vertical direction thereof. The initial columns 25 may also include an initial drain material layer (not shown) located on the other side of the floating material layer 221 along the vertical direction thereof. The drain material layer 241 is formed during the patterning process (see Figure 11 It should be noted that the drain structure 24 can also be formed directly after the patterning in step S42 . The source material layer 211 includes a third tensile material layer 211 b and a source isolation material layer 211 a stacked in sequence in a direction away from the substrate 20 .

[0085] In step S42, refer to Figure 7 Step S4 in Figure 8 and Figure 9 , the stacked layers are patterned to form initial columns 25 spaced apart along a first direction. The initial columns 25 include a floating material layer 221, and a source structure 21 and a drain material layer 241 located on opposite sides of the floating material layer 221 along its vertical direction. The source structure 21 includes a third tensioning layer 21b and a source isolation layer 21a. Specifically, the initial drain material layer 241 is patterned to form the drain material layer 241, the initial floating material layer 2211 is patterned to form the floating material layer 221, and the source material layer 211 is patterned to form the source structure 21. The third tensioning material layer 211b is patterned to form the third tensioning layer 21b, and the source isolation material layer 211a is patterned to form the source isolation layer 21a.

[0086] In step S43, refer to Figure 7 Step S4 and Figure 10 , forming a second isolation layer 23 covering the top surface of the substrate 20 , the second isolation layer 23 is also located on two opposite sides of the third tensile layer 21 b along the first direction.

[0087] In step S44, refer to Figure 7 Step S4 and Figure 11 The first isolation material layer 261 includes a third sub-isolation material layer 261c, a second sub-isolation material layer 261b, and a first sub-isolation material layer 261a formed in sequence; wherein, the third sub-isolation material layer 261c is located on the side surface of the initial column 25 and the top surface of the substrate 20, and the second sub-isolation material layer 261b is located on the surface of the third sub-isolation material layer 261c, and the third sub-isolation material layer 261c, the second sub-isolation material layer 261b, and the first sub-isolation material layer 261a jointly fill the gaps between adjacent initial columns 25.

[0088] As an example, see Figure 12The floating structure 22 includes a first floating portion and a second floating portion arranged along a first direction and adjacent to each other; the top surface of the first floating portion is higher than the top surface of the second floating portion; the bottom surface of the first floating portion is connected to the source structure 21 and the top surface is connected to the drain structure 24; the bottom surface of the second floating portion is connected to the source structure 21.

[0089] In step S45, refer to Figure 7 Step S4 and Figure 12 , remove a portion of the drain material layer 241 away from the first tension layer 29a along the first direction, and the remaining portion forms the drain structure 24; and remove a portion of the top of the floating material layer 221 away from the first tension layer 29a along the first direction, and the remaining portion forms the floating structure 22 to define the second gate structure G2 to be formed subsequently (see Figure 3 ) location.

[0090] As an example, see Figure 7 In step S6, while forming the first gate structure in step S6, it also includes: forming a second gate structure, the second gate structure is located on the side of the first floating body portion away from the first gate structure along the first direction and is also located on the second floating body portion; wherein the top surface of the second gate structure is not higher than the top surface of the first floating body portion.

[0091] As an example, forming the first gate structure and the second gate structure in step S6 includes:

[0092] Step S64: forming a third dielectric layer on the top surface of the second floating body;

[0093] Step S65: forming a first dielectric layer on a surface of the drain structure close to the first tensile layer along the first direction, and on a surface of the first floating body portion close to the first tensile layer along the first direction, and forming a second dielectric layer on a surface of the drain structure away from the first tensile layer along the first direction, and on a surface of a portion of the first floating body portion that is higher than the second floating body portion and away from the first tensile layer along the first direction; wherein the portion of the first dielectric layer located on the surface of the floating body structure close to the first tensile layer along the first direction is a first gate dielectric layer;

[0094] Step S66: forming a first gate conductive layer on the surface of the first gate dielectric layer away from the first floating body portion along the first direction, and forming a second gate conductive layer on the second floating body portion; wherein the third dielectric layer and the portion of the second dielectric layer located between the first floating body portion and the second gate conductive layer are used to jointly constitute the second gate dielectric layer; the first gate dielectric layer and the first gate conductive layer are used to jointly constitute a first gate structure, and the second gate dielectric layer and the second gate conductive layer are used to jointly constitute a second gate structure.

[0095] As an example, after step S45 and before step S64, the following steps are further included:

[0096] Step S61: forming a third dielectric material layer at the locations of the removed portion of the drain material layer and the portion of the floating body material layer;

[0097] Step S62: removing portions of the first isolation material layer located between adjacent floating body structures along the first direction and between adjacent drain structures along the first direction, and the remaining first isolation material layer forms a first isolation layer;

[0098] Step S63 : forming an initial tension material layer between the active pillars adjacent to each other along the first direction and on the first isolation layer, the layer covering the side surfaces and top surfaces of the active pillars.

[0099] In step S61, refer to Figure 7 Step S6 and Figure 13 A third dielectric material layer 281 is formed at the position of the removed portion of the drain material layer 241 and the portion of the floating material layer 221 , wherein the top surface of the third dielectric material layer 281 can be at least flush with the top surface of the drain structure 24 .

[0100] In step S62, refer to Figure 7 Step S6 in Figure 13 ,and Figure 14 , remove the portion of the first isolation material layer 261 located between the floating structures 22 adjacent along the first direction and the drain structures 24 adjacent along the first direction, and the remaining first sub-isolation material layer 261a forms a first sub-isolation layer 26a, the remaining second sub-isolation material layer 261b forms a second sub-isolation layer 26b, and the remaining third sub-isolation material layer 261c forms a third sub-isolation layer 26c.

[0101] In step S63, refer to Figure 7 Step S6 and Figure 15 An initial tension material layer 2911 is formed between the active pillars 27 adjacent to each other along the first direction and on the first isolation layer 26 , covering the side surfaces and top surfaces of the active pillars 27 .

[0102] In step S64, refer to Figure 7 Step S6 in Figure 15 ,and Figure 16 A portion of the third dielectric material layer 281 and the initial tension material layer 2911 thereon are removed. The remaining third dielectric material layer 281 forms the third dielectric layer 28, and the remaining initial tension material layer 2911 forms the intermediate tension material layer 291. Simultaneously, a portion of the initial tension material layer 2911 on the surface of the first floating body portion away from the second floating body portion along the first direction is removed, exposing a portion of the top surface of the first isolation layer 26.

[0103] In step S65, refer to Figure 7 Step S6 and Figure 17A first dielectric layer 30 is formed on the surface of the drain structure 24 close to the first tensile layer 29a along the first direction, and on the surface of the first floating body portion close to the first tensile layer 29a along the first direction, and a second dielectric layer 31 is formed on the surface of the drain structure 24 away from the first tensile layer 29a along the first direction, and on the surface of the first floating body portion higher than the second floating body portion away from the first tensile layer 29a along the first direction.

[0104] In step S66, refer to Figure 7 Step S6 and Figure 18 A first gate conductive layer 32 is formed on the surface of the first gate dielectric layer away from the first floating body portion along the first direction, and a second gate conductive layer 33 is formed on the second floating body portion. The second gate conductive layer 33 is also located on the second gate dielectric layer.

[0105] In step S8, refer to Figure 7 Step S8 in the embodiment, step S8 includes:

[0106] Step S81 : forming a tension filling layer on the top surface of the first gate conductive layer and the top surface of the second gate conductive layer, wherein the tension filling layer and the intermediate tension material layer together constitute a first tension layer and a second tension layer.

[0107] In step S81, refer to Figure 7 Step S8 and Figure 19 A tensile filling layer 292 is formed on the top surface of the first gate conductive layer 32 and the top surface of the second gate conductive layer 33, so that the top surface of the tensile filling layer 292 is flush with the top surface of the intermediate tensile material layer 291, and the tensile filling layer 292 and the intermediate tensile material layer 291 together constitute a first tensile layer 29a and a second tensile layer 29b; wherein, the first tensile layer 29a covers the top surface of the first gate structure G1 and the surface away from the floating structure 22 along the first direction; the second tensile layer 29b covers the surface of the floating structure 22 along the first direction away from the first gate structure G1.

[0108] In the semiconductor structure, stacked structure and preparation method thereof in the above-mentioned embodiments, the first tensile layer and the second tensile layer apply tensile force to the floating structure on both sides of the floating structure along the first direction, so that corresponding tensile stress can be generated in the floating structure, thereby increasing the effective mass of the holes, increasing the lifetime of the holes and reducing the leakage current, thereby improving the storage performance of the transistor. Secondly, the first tensile layer is arranged on one side of the first gate structure along the first direction, which can also improve the mobility of the channel electrons. While improving the lifetime of the holes, it can also increase the sensing margin, reduce the bit error rate of the storage process, and improve the storage accuracy. In addition, in the source structure, biaxial tensile stress is generated for the floating structure by combining the source isolation layer and the third tensile layer, thereby increasing the lifetime of the holes near the source structure in the floating structure. The above-mentioned structure can also control the drain structure together with the first gate structure through the second gate structure, thereby forming a double-gate structure near the drain structure to improve the hole generation rate near the drain structure.

[0109] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0110] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0111] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person of ordinary skill in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the disclosed patent shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: A first tension layer, a second tension layer, a floating body structure, a source structure and a drain structure located on opposite sides of the floating body structure along a vertical direction, and a first gate structure located on one side of the floating body structure along a first direction; The first tensile layer covers the top surface of the first gate structure and the surface away from the floating structure along the first direction; the second tensile layer covers the surface of the floating structure away from the first gate structure along the first direction; The floating structure includes a first floating body portion and a second floating body portion arranged along the first direction and adjacent to each other; the top surface of the first floating body portion is higher than the top surface of the second floating body portion; The bottom surface of the first floating body portion is connected to the source structure and the top surface is connected to the drain structure, the first gate structure is located on one side of the first floating body structure along the first direction, and the bottom surface of the second floating body portion is connected to the source structure; The semiconductor structure further includes a second gate structure, the second gate structure is located on the other side of the first floating body portion along the first direction and is also located on the second floating body portion; Wherein, the top surface of the second gate structure is not higher than the top surface of the first floating body portion.

2. The semiconductor structure according to claim 1, wherein: The dimension of the first tensile layer along the vertical direction is greater than or equal to the dimension of the floating structure along the vertical direction; and / or A dimension of the second tensile layer along the vertical direction is greater than or equal to a dimension of the floating structure along the vertical direction.

3. The semiconductor structure according to claim 2, wherein: The material of the first tensile layer is selected from silicon nitride, silicon oxynitride, silicon carbide nitride, silicon oxycarbon nitride, silicon hydrogenated carbon and combinations thereof; and / or The material of the second tensile layer is selected from silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride oxide, silicon hydrogenated carbon, and combinations thereof.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The source structure includes: a source isolation layer, located on the bottom surface of the floating structure; The third tension layer is located on a surface of the source isolation layer away from the floating structure along the vertical direction.

5. The semiconductor structure according to claim 1, wherein: Also includes: a first dielectric layer, located on a surface of the drain structure close to the first tensile layer along the first direction, and on a surface of the first floating body close to the first tensile layer along the first direction; a second dielectric layer located on a surface of the drain structure away from the first tension layer along the first direction, and a surface of a portion of the first floating body portion that is higher than the second floating body portion and away from the first tension layer along the first direction; The third dielectric layer is located on the top surface of the second floating body.

6. The semiconductor structure according to claim 5, wherein: The first gate structure includes: A first gate dielectric layer, which is a portion of the first dielectric layer located on a surface of the floating structure close to the first tension layer along the first direction; a first gate conductive layer, located on a surface of the first gate dielectric layer away from the first floating body portion along the first direction; and / or The second gate structure includes: a second gate conductive layer, located on the second floating body portion; a second gate dielectric layer, comprising the third dielectric layer and a portion of the second dielectric layer located between the first floating body portion and the second gate conductive layer; The second gate dielectric layer covers the bottom surface of the second gate conductive layer and the surface thereof close to the first floating body portion.

7. A stacking structure, characterized in that: A semiconductor device comprising a substrate, and a plurality of semiconductor structures according to any one of claims 1 to 6 arranged along a first direction on a top surface of the substrate; The first tensile layer of the semiconductor structure serves as the second tensile layer of another adjacent semiconductor structure.

8. A method for preparing a stacked structure, characterized in that: include: providing a substrate; Active pillars are formed on the top surface of the substrate and arranged at intervals along a first direction, wherein the active pillars include a floating structure, and a source structure and a drain structure located on opposite sides of the floating structure in a vertical direction; forming a first gate structure on one side of the floating structure along the first direction; forming a first tension layer and a second tension layer, wherein the first tension layer covers the top surface of the first gate structure and the surface away from the floating structure along the first direction; and the second tension layer covers the surface of the floating structure away from the first gate structure along the first direction; The floating body structure includes a first floating body portion and a second floating body portion arranged along the first direction and adjacent to each other; the top surface of the first floating body portion is higher than the top surface of the second floating body portion; the bottom surface of the first floating body portion is connected to the source structure and the top surface is connected to the drain structure; the bottom surface of the second floating body portion is connected to the source structure; While forming the first gate structure, the method further includes: forming a second gate structure, wherein the second gate structure is located on a side of the first floating body portion away from the first gate structure along the first direction and is also located on the second floating body portion; Wherein, the top surface of the second gate structure is not higher than the top surface of the first floating body portion.

9. The method for preparing a stacked structure according to claim 8, wherein: Forming the active pillar includes: forming a stacked layer on the top surface of the substrate, the stacked layer comprising a source electrode material layer, an initial floating body material layer, and an initial drain electrode material layer stacked along the vertical direction; Patterning the stacked layers to form initial columns spaced apart along the first direction, the initial columns comprising a floating material layer, and the source structure and drain material layer located on opposite sides of the floating material layer along the vertical direction thereof, wherein the source structure comprises a third tensioning layer and a source isolation layer, the source isolation layer being located on the bottom surface of the floating structure, and the third tensioning layer being located on a surface of the source isolation layer away from the floating structure along the vertical direction; A portion of the drain material layer is removed to form the drain structure, and a portion of the floating body material layer is removed to form the floating body structure.

10. The method for preparing a stacked structure according to claim 8, wherein: Forming the first gate structure and the second gate structure includes: forming a third dielectric layer on the top surface of the second floating body; A first dielectric layer is formed on a surface of the drain structure close to the first tensile layer along the first direction, and on a surface of the first floating body portion close to the first tensile layer along the first direction, and a second dielectric layer is formed on a surface of the drain structure away from the first tensile layer along the first direction, and on a surface of a portion of the first floating body portion that is higher than the second floating body portion and away from the first tensile layer along the first direction; wherein the portion of the first dielectric layer located on the surface of the floating body structure close to the first tensile layer along the first direction is a first gate dielectric layer; forming a first gate conductive layer on a surface of the first gate dielectric layer away from the first floating body portion along the first direction, and forming a second gate conductive layer on the second floating body portion; Among them, the third dielectric layer and the part of the second dielectric layer located between the first floating body portion and the second gate conductive layer are used to jointly constitute the second gate dielectric layer; the first gate dielectric layer and the first gate conductive layer are used to jointly constitute the first gate structure, and the second gate dielectric layer and the second gate conductive layer are used to jointly constitute the second gate structure.

11. The method for preparing a stacked structure according to claim 9, wherein: A first isolation material layer is provided between the adjacent initial pillars along the first direction; After forming the active pillar, the method further includes: Portions of the first isolation material layer located between the floating body structures adjacent to each other along the first direction and between the drain structures adjacent to each other along the first direction are removed, and the remaining first isolation material layer forms a first isolation layer.

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