Semiconductor structure and method for manufacturing the same

Abstract

The disclosed embodiments relate to the field of semiconductors and provide a semiconductor structure and a method for manufacturing the same. The structure comprises: a substrate, comprising an array region and a peripheral region, with a capacitor structure disposed on the array region of the substrate; a contact plug, extending along the thickness of the substrate, located in the peripheral region of the substrate, with a bottom surface in contact with the substrate and a top surface no higher than the top surface of the capacitor structure; a first wiring layer in contact with the top surface of the capacitor structure; and a second wiring layer in contact with the top surface of the contact plug, disposed on the same layer as the first wiring layer. The semiconductor structure and the method for manufacturing the same embodiments provided by the disclosed embodiments are advantageous for improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Memory is a storage component used to store programs and various data. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor memory device in computers and is composed of many repeated storage cells.

[0003] A memory cell typically includes a capacitor and a transistor. One of the source, drain, or drain of the transistor is connected to a bit line structure, and the other of the source, drain, or drain is connected to a capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the capacitor through the bit line structure, or writing the data information into the capacitor for storage through the bit line structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, embodiments of the present disclosure provide a semiconductor structure, including: a substrate, the substrate including an array area and a peripheral area, and a capacitor structure is provided on the array area of ​​the substrate; a contact plug, the contact plug extends along the thickness direction of the substrate, the contact plug is located in the peripheral area of ​​the substrate, the bottom surface contacts the substrate, and the top surface is not higher than the top surface of the capacitor structure; a first wiring layer, the first wiring layer contacts the top surface of the capacitor structure; a second wiring layer, the second wiring layer contacts the top surface of the contact plug, and the second wiring layer is arranged on the same layer as the first wiring layer.

[0006] In some embodiments, the first wiring layer includes a first diffusion barrier layer and a first conductor layer, the first diffusion barrier layer covers the bottom surface and side walls of the first conductor layer, and the first diffusion barrier layer located on the bottom surface of the first conductor layer contacts the top surface of the capacitor structure; and / or, the second wiring layer includes a second diffusion barrier layer and a second conductor layer, the second diffusion barrier layer covers the bottom surface and side walls of the second conductor layer, and the second diffusion barrier layer located on the bottom surface of the second conductor layer contacts the top surface of the contact plug.

[0007] In some embodiments, the first wiring layer is further located above the peripheral region of the substrate and between adjacent second wiring layers.

[0008] In some embodiments, the semiconductor structure further includes: a routing layer, the routing layer is located on a side of the first wiring layer away from the substrate, and is located on a side of the second wiring layer away from the substrate, the routing layer includes multiple first routings and multiple second routings, the first routings are electrically connected to the first wiring layer, and the second routings are electrically connected to the second wiring layer. The semiconductor structure further includes: a first interconnect structure, the first interconnect structure contacts the top surface of the first wiring layer located in the peripheral area, and the first interconnect structure electrically connects the first wiring layer and the first routing; a second interconnect structure, the second interconnect structure contacts the top surface of the second wiring layer located in the peripheral area, and the second interconnect structure electrically connects the second wiring layer and the second routing, and the second interconnect structure is arranged on the same layer as the first interconnect structure.

[0009] In some embodiments, the semiconductor structure further includes: a first insulating layer, the first insulating layer filling the gap between the first wiring layer and the second wiring layer; a second insulating layer, the second insulating layer filling the gap between the first routing layer and the second routing layer; a dielectric layer, the dielectric layer being located between the first wiring layer and the routing layer, and between the second wiring layer and the routing layer; wherein the relative dielectric constant of the material of the dielectric layer is smaller than the relative dielectric constant of the material of the first insulating layer, and smaller than the relative dielectric constant of the material of the second insulating layer.

[0010] In some embodiments, the capacitor structure includes multiple capacitors and an upper electrode plate, the capacitors extend along the thickness direction of the substrate, the upper electrode plate fills the gaps between the capacitors, and the top surface of the upper electrode plate is flush with the top surface of the capacitor, and the first wiring layer contacts the top surface of the capacitor and the top surface of the upper electrode plate.

[0011] In some embodiments, an orthographic projection area of ​​the first wiring on the substrate surface is larger than an orthographic projection area of ​​the second wiring on the substrate surface.

[0012] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including an array area and a peripheral area, the array area of ​​the substrate having a capacitor structure; forming a contact plug, the contact plug extending along the thickness direction of the substrate, the contact plug being located in the peripheral area of ​​the substrate, the bottom surface being in contact with the substrate, and the top surface being no higher than the top surface of the capacitor structure; forming a first wiring layer and a second wiring layer, the first wiring layer being located on the top surface of the capacitor structure, the second wiring layer being located on the top surface of the contact plug, and the second wiring layer being arranged on the same layer as the first wiring layer.

[0013] In some embodiments, forming a contact plug includes: forming an interlayer dielectric layer, the interlayer dielectric layer covering the capacitor structure and the peripheral area of ​​the substrate; patterning the interlayer dielectric layer in the peripheral area to form a contact hole, the contact hole exposing the surface of the substrate; and filling the contact hole to form a contact plug.

[0014] In some embodiments, after forming the contact plug and before forming the first wiring layer, the method further includes: performing a planarization process on the top surface of the contact plug and the top surface of the interlayer dielectric layer to expose the top surface of the capacitor structure.

[0015] The technical solution provided by the embodiment of the present disclosure has at least the following advantages: In the semiconductor structure provided by the embodiment, the substrate includes an array region and a peripheral region. The array region of the substrate can have array-arranged storage transistors, so that the storage transistors and the capacitor structure can constitute an array-arranged storage unit. The substrate in the peripheral region can have a control transistor, and the control transistor constitutes a control circuit, thereby realizing access to the storage unit. Among them, the first wiring layer on the top surface of the capacitor structure can interconnect the capacitor structure with other structures, while reducing the resistance between the capacitor structure and other structures, thereby improving signal transmission efficiency; the contact plug and the second wiring layer can interconnect the substrate in the peripheral region with other structures. Since the top surface of the contact plug is not higher than the top surface of the capacitor structure, the length of the corresponding contact plug in the direction perpendicular to the substrate surface is reduced, thereby reducing the process difficulty of forming the contact plug and reducing the delay effect of the contact plug. The first wiring layer and the second wiring layer are arranged in the same layer, so that the first wiring layer and the second wiring layer can be formed simultaneously in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0018] Figure 2 A top view of a routing layer in an array area provided in one embodiment of the present disclosure;

[0019] Figures 3 to 10 Schematic diagram of various semiconductor structures provided by another embodiment of the present disclosure;

[0020] Figure 11 A top view of a first wiring layer and a second wiring layer provided in another embodiment of the present disclosure;

[0021] Figure 12 A top view of a routing layer provided in another embodiment of the present disclosure;

[0022] Figure 13 A schematic diagram of a semiconductor structure provided by another embodiment of the present disclosure;

[0023] Figure 14 A schematic diagram of another semiconductor structure provided by another embodiment of the present disclosure;

[0024] Figures 15 to 19 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] refer to Figure 1 , Figure 1 A schematic diagram of a semiconductor structure provided in accordance with an embodiment of the present disclosure, wherein a substrate 100 generally includes an array region 101 and a peripheral region 102. The array region 101 of the substrate 100 is used to form an array of storage transistors (not shown in the figure), and the storage transistors and the corresponding capacitor structures 111 constitute a storage unit. The peripheral region 102 of the substrate 100 is used to form a control transistor (not shown in the figure), and the control transistor constitutes a control circuit to access the storage unit. In order to enhance the charge storage capacity of the capacitor structure 111, the area of ​​the capacitor structure 111 can be increased by increasing the aspect ratio of the capacitor structure 111. In this way, a height difference is generated between the capacitor structure 111 and the substrate 100 in the peripheral region 102. Reference Figure 1 and Figure 2 , Figure 2 This is a top view of a routing layer in an array region provided in accordance with an embodiment of the present disclosure. When forming routing layer 103, second routing 123 in peripheral region 102 is electrically connected to substrate 100 via contact plug 112. Second routing 123 in peripheral region 102 also passes over array region 101. To prevent interconnection between capacitor structure 111 and second routing 123, capacitor structure 111 can be extended to first routing 113 via conductive plug 121. The length of contact plug 112 is then the sum of the height of capacitor structure 111 relative to the surface of substrate 100 and the length of conductive plug 121. When fabricating contact plug 112, contact hole 115 must be formed in interlayer dielectric layer 114 and then filled to form contact plug 112. Contact holes 115 with excessively large aspect ratios increase the difficulty of fabrication, and a long contact plug 112 can also easily lead to delays in contact plug 112.

[0026] According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, which is at least beneficial to improving the performance of the semiconductor structure.

[0027] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0028] Figures 3 to 10 Schematic diagram of various semiconductor structures provided by another embodiment of the present disclosure, Figure 11 A top view of a first wiring layer and a second wiring layer provided in another embodiment of the present disclosure is shown. Figure 12 A top view of a routing layer provided in another embodiment of the present disclosure is shown. Figure 13 A schematic diagram of a semiconductor structure provided by another embodiment of the present disclosure is shown. Figure 14 This is a schematic diagram of another semiconductor structure provided by another embodiment of the present disclosure. The semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings, as follows:

[0029] refer to Figures 3 to 14 The semiconductor structure includes: a substrate 200, the substrate 200 includes an array area 201 and a peripheral area 202, and a capacitor structure 203 is provided on the array area 201 of the substrate 200; a contact plug 204, the contact plug 204 extends along the thickness direction of the substrate 200, the contact plug 204 is located in the peripheral area 202 of the substrate 200, the bottom surface of the contact plug 204 is in contact with the substrate 200, and the top surface is not higher than the top surface of the capacitor structure 203; a first wiring layer 215, the first wiring layer 215 is in contact with the top surface of the capacitor structure 203; a second wiring layer 225, the second wiring layer 225 is in contact with the top surface of the contact plug 204, and the second wiring layer 225 is arranged on the same layer as the first wiring layer 215.

[0030] The array area of ​​the substrate may have multiple storage transistors, multiple word lines, and multiple bit lines arranged in an array. The word lines are electrically connected to the gates of the storage transistors, the bit lines are electrically connected to one of the sources or drains of the storage transistors, and the other of the sources or drains of the storage transistors is electrically connected to the capacitor structure. In this way, a storage unit composed of the storage transistors and the capacitor structure is formed, and storage and reading are then achieved through the corresponding word lines and bit lines.

[0031] There may be multiple control transistors in the peripheral area of ​​the substrate, and the gate, source or drain of the control transistor is electrically connected to the contact plug, so that the gate, source or drain of the control transistor is led out to form a control circuit with other device structures, thereby realizing storage and reading of the memory cell.

[0032] In the semiconductor structure provided in this embodiment, the substrate 200 includes an array region 201 and a peripheral region 202. The array region 201 of the substrate 200 may include arrayed storage transistors, which together with the capacitor structure 203 may constitute an arrayed storage cell. The peripheral region 202 of the substrate 200 may include a control transistor, which constitutes a control circuit to enable access to the storage cell. A first wiring layer 215 on the top surface of the capacitor structure 203 may interconnect the capacitor structure 203 with other structures, while reducing the resistance between the capacitor structure 203 and other structures and improving signal transmission efficiency. Contact plugs 204 and a second wiring layer 225 may interconnect the substrate 200 in the peripheral region 202 with other structures. Because the top surface of the contact plugs 204 is not higher than the top surface of the capacitor structure 203, the length of the contact plugs 205 in a direction perpendicular to the surface of the substrate 200 is reduced, thereby reducing the process difficulty of forming the contact plugs 204 and reducing the delay effect of the contact plugs 204. The first wiring layer 215 and the second wiring layer 225 are provided on the same layer. Therefore, the first wiring layer 215 and the second wiring layer 225 can be formed simultaneously in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure.

[0033] In some embodiments, the material of substrate 200 includes a semiconductor material, such as, but not limited to, silicon. In some embodiments, substrate 200 may include crystalline silicon (e.g., a wafer). In some embodiments, substrate 200 may include: a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, a basic semiconductor includes germanium (Ge); a compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and an alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, substrate 200 may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0034] In some embodiments, reference Figure 3 The semiconductor structure further includes an interlayer dielectric layer 208, which fills the gaps between adjacent contact plugs 205. The interlayer dielectric layer 208 can insulate adjacent contact plugs 205 to prevent leakage between adjacent contact plugs 205.

[0035] The material of the interlayer dielectric layer 208 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0036] In some embodiments, reference Figure 4The capacitor structure 203 includes multiple capacitors 223 and an upper electrode plate 213. The capacitors 223 extend along the thickness direction of the substrate 200. The upper electrode plate 213 fills the gaps between the capacitors 223 and covers the top surface of the capacitors 223. The first wiring layer 215 covers the top surface of the upper electrode plate 213. The capacitors 223 may include a lower electrode layer, a dielectric layer, and an upper electrode layer. The upper electrode plate 213 between the capacitors 223 may connect the upper electrode layers of multiple capacitors 223, thereby allowing the multiple capacitors 223 to share the upper electrode plate. In this way, the upper electrode plates of the multiple capacitors 223 can share the same control terminal, thereby improving the control efficiency of the semiconductor structure.

[0037] In some embodiments, reference Figure 5 , the top surface of the upper electrode plate 213 can be flush with the top surface of the capacitor 223, and the first wiring layer 215 is in contact with the top surface of the capacitor 223 and the top surface of the upper electrode plate 213. In other words, the upper electrode plate 213 only fills the gap between the capacitors 223 and exposes the top surface of the capacitor 223, then the first wiring layer 215 can directly cover the top surface of the capacitor 223 and the upper electrode plate 213, and the thickness of the upper electrode plate 213 on the top surface of the corresponding capacitor 223 is thinned. In this way, the distance between the second wiring layer 225 and the surface of the substrate 200 can be further reduced, and the length of the corresponding contact plug 204 in the direction perpendicular to the surface of the substrate 200 can be further reduced, further reducing the process difficulty of the contact plug 204 and reducing the delay effect of the contact plug 204.

[0038] The capacitor may include a lower electrode layer, a capacitor dielectric layer and an upper electrode layer stacked in sequence in a direction away from the substrate surface, wherein the materials of the lower electrode layer and the upper electrode layer include at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium; the material of the capacitor dielectric layer includes a high dielectric constant material such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate.

[0039] In some embodiments, the material of the upper electrode plate 213 includes silicon germanium. By adjusting the proportion of germanium atoms in the upper electrode plate 213, it is possible to ensure that the upper electrode plate 213 has a good filling capacity and a low contact resistance.

[0040] It should be noted that, for ease of description, in the drawings provided in this embodiment, the top surface of the contact plug 204 is taken as an example to be flush with the top surface of the capacitor structure 203. In some embodiments, the top surface of the contact plug may also be lower than the top surface of the capacitor structure.

[0041] In some embodiments, reference Figure 6The contact plug 204 includes a barrier layer 224 and a conductive layer 214. The barrier layer 224 is located on the bottom surface and sidewalls of the conductive layer 214. The barrier layer 224 located on the bottom surface of the conductive layer 214 contacts the substrate 200. The barrier layer 224 can prevent ions in the conductive layer 214 from diffusing into the substrate 200 or diffusing into other structures filled between adjacent contact plugs 204, thereby improving the stability of the semiconductor structure.

[0042] The material of the barrier layer 224 may include titanium nitride, and the material of the conductive layer 214 may include tungsten.

[0043] In some embodiments, reference Figure 7 The first wiring layer 215 includes a first diffusion barrier layer 415 and a first conductor layer 315. The first diffusion barrier layer 415 covers the bottom surface and sidewalls of the first conductor layer 315. The first diffusion barrier layer 415 located on the bottom surface of the first conductor layer 315 contacts the top surface of the capacitor structure 203. The first diffusion barrier layer 415 can prevent ions in the first conductor layer 315 from diffusing into the capacitor structure 203, thereby improving the stability of the semiconductor structure.

[0044] The material of the first diffusion barrier layer 415 includes titanium nitride. The material of the first conductor layer 315 includes copper.

[0045] refer to Figure 8 The first wiring layer 215 may further include a first adhesion layer 515, which may be located between the first diffusion barrier layer 415 and the first conductor layer 315. When the first conductor layer 315 is made of copper, the first adhesion layer 515 may be a copper seed layer. The first adhesion layer 515 is used to improve the adhesion between the first conductor layer 315 and the first diffusion barrier layer 415, thereby improving the conductivity of the first conductor layer 315 and enhancing data transmission efficiency.

[0046] In some embodiments, reference Figure 9 The second wiring layer 225 includes a second diffusion barrier layer 425 and a second conductor layer 325. The second diffusion barrier layer 425 covers the bottom surface and sidewalls of the second conductor layer 325. The second diffusion barrier layer 425 located on the bottom surface of the second conductor layer 325 contacts the top surface of the contact plug 204. The second diffusion barrier layer 425 can prevent ions in the second conductor layer 325 from diffusing into the contact plug 204, thereby improving the stability of the semiconductor structure.

[0047] The material of the second diffusion barrier layer 425 includes titanium nitride. The material of the second conductor layer 325 includes copper.

[0048] refer to Figure 10The second wiring layer 225 may further include a second adhesion layer 525, which may be located between the second diffusion barrier layer 42 and the second conductor layer 325. When the second conductor layer 325 is made of copper, the second adhesion layer 525 may be a copper seed layer. The second adhesion layer 525 is used to improve the adhesion between the second conductor layer 325 and the second diffusion barrier layer 425, thereby improving the conductivity of the second conductor layer 325 and enhancing data transmission efficiency.

[0049] In some embodiments, the material of the first wiring layer 215 is the same as that of the second wiring layer 225. When the first wiring layer 215 includes a first diffusion barrier layer 415 and a first conductor layer 315, and the second wiring layer 225 includes a second diffusion barrier layer 425 and a second conductor layer 325, the material of the first diffusion barrier layer 415 is the same as that of the second diffusion barrier layer 425, and the material of the first conductor layer 315 is the same as that of the second conductor layer 325. When the first wiring layer 215 also includes a first adhesion layer 515, and the second wiring layer 225 also includes a second adhesion layer 525, the material of the first adhesion layer 515 is the same as that of the second adhesion layer 525. Thus, the first wiring layer 215 and the second wiring layer 225 can be formed in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure.

[0050] In some embodiments, the orthographic projection area of ​​the first wiring layer 215 on the surface of the substrate 200 is larger than the orthographic projection area of ​​the second wiring layer 225 on the surface of the substrate 200. It is understood that the first wiring layer 215 is used to lead out the capacitor structure 203. When a routing layer is subsequently formed above the first wiring layer 215 and the second wiring layer 225, in order to increase the lead-out window of the capacitor structure 203, the area of ​​the first wiring layer 215 is set larger to facilitate subsequent connection with the routing layer.

[0051] In a direction perpendicular to the substrate surface, the orthographic projection of the first wiring layer may be a continuous, entire structure, or the first wiring layer may be a plurality of independent block structures, for example, a plurality of independent rectangles, squares, or circles. This embodiment does not limit the shape of the first wiring layer.

[0052] In some embodiments, the orthographic projection area of ​​the second wiring layer 225 on the surface of the substrate 200 is larger than the orthographic projection area of ​​the contact plug 204 on the surface of the substrate 200. It is understood that when a wiring layer is subsequently formed, it is necessary to connect to the contact plug 204. The second wiring layer 225 can increase the connection window of the contact plug 204, which is beneficial for the subsequent interconnection between the wiring layer and the contact plug 204.

[0053] In a direction perpendicular to the substrate surface, the orthographic projection of the second wiring layer can be a plurality of independent regular patterns, each of which is connected to a contact plug. For example, the regular pattern can be a rectangle, a square, or a circle. The regular pattern shape of the second wiring layer can facilitate the layout of the subsequent second wiring layer and thus facilitate the connection of subsequent routing layers.

[0054] In some embodiments, in a direction perpendicular to the surface of the substrate 200, the thickness of the first wiring layer 215 ranges from 100 to 300 nm, for example, 100 nm, 120 nm, 150 nm, 175 nm, 198 nm, 225 nm, 268 nm, 291 nm, or 300 nm. It will be appreciated that the first wiring layer 215 is used to connect the capacitor structure 203 to the subsequent routing layer. The greater the thickness of the first wiring layer 215, the longer the path connecting the capacitor structure 203 to the subsequent routing layer, and the more likely it is to cause delay. Therefore, the thickness of the first wiring layer 215 needs to be within an appropriate range.

[0055] In some embodiments, the width of the first wiring layer 215 in a direction parallel to the surface of the substrate 200 is smaller than the thickness of the first wiring layer 215 in a direction perpendicular to the surface of the substrate 200. This can increase the integration density of multiple first wiring layers 215 in the same layer. For example, the width of the first wiring layer 215 in a direction parallel to the surface of the substrate 200 can range from 80 to 200 nm, and specifically can be 80 nm, 85 nm, 100 nm, 125 nm, 155 nm, 178 nm, 190 nm, or 200 nm.

[0056] In some embodiments, the thickness of the second wiring layer 225 in a direction perpendicular to the surface of the substrate 200 ranges from 100 to 300 nm, for example, 100 nm, 120 nm, 150 nm, 175 nm, 198 nm, 225 nm, 268 nm, 291 nm, or 300 nm. It will be appreciated that the second wiring layer 225 is used to connect the contact plug 204 to the subsequent routing layer. The thicker the second wiring layer 225, the longer the path connecting the contact plug 204 to the subsequent routing layer, which is more likely to cause delays. Therefore, the thickness of the second wiring layer 225 needs to be within an appropriate range.

[0057] In some embodiments, the width of the second wiring layer 225 in a direction parallel to the surface of the substrate 200 is smaller than the thickness of the second wiring layer 225 in a direction perpendicular to the surface of the substrate 200. This can increase the integration density of multiple second wiring layers 225 in the same layer. For example, the width of the second wiring layer 225 in a direction parallel to the surface of the substrate 200 can range from 80 to 200 nm, and specifically can be 80 nm, 85 nm, 100 nm, 125 nm, 155 nm, 178 nm, 190 nm, or 200 nm.

[0058] refer to Figure 11 The first wiring layer 215 can also be located above the peripheral area 202 of the substrate 200 and between adjacent second wiring layers 225. In this way, when the wiring layer is subsequently formed, the connection window between the wiring layer and the capacitor structure 203 can be in the peripheral area 202 to facilitate the arrangement of the wiring layer.

[0059] refer to Figure 12 The semiconductor structure may further include: a routing layer 207, the routing layer 207 being located on a side of the first wiring layer 215 away from the substrate 200 and on a side of the second wiring layer 225 away from the substrate 200, the routing layer 207 including a plurality of first routing lines 217 and a plurality of second routing lines 227, the first routing lines 217 being electrically connected to the first wiring layer 215, and the second routing lines 227 being electrically connected to the second wiring layer 225; and a first interconnect structure 216, the first interconnect structure 216 being in contact with a top surface of the first wiring layer 215 located in the peripheral region 202, and electrically connecting the first wiring layer 215 and the first routing lines 217; and a second interconnect structure 226, the second interconnect structure 226 being in contact with a top surface of the second wiring layer 225 located in the peripheral region 202, and electrically connecting the second wiring layer 225 and the second routing lines 227, the second interconnect structure 226 being arranged on the same layer as the first interconnect structure 216.

[0060] In this manner, the first interconnect structure 216 and the second interconnect structure 226 are both located in the peripheral region 202, and the first interconnect structure 216 and the second interconnect structure 226 are disposed on the same layer, allowing the first interconnect structure 216 and the second interconnect structure 226 to be formed simultaneously in the same process step. Furthermore, by forming the first interconnect structure 216 and the second interconnect structure 226 in the peripheral region 202, the first trace 217 corresponding to the capacitor structure 203 and the second trace 227 corresponding to the contact plug 204 can both utilize the space above the array region 201 and the peripheral region 202. This allows the first interconnect structure 216 and the second interconnect structure 226 to be more centrally located, facilitating the design and layout of the trace layer 207. Furthermore, the height of the contact plug 204 is reduced while fully utilizing the space above the array region 201 and the peripheral region 202.

[0061] The material of the wiring layer 207 includes copper, aluminum, or tungsten, etc. The material of the first interconnect structure 216 and the material of the second interconnect structure 226 both include copper.

[0062] In some embodiments, the material of the first interconnect structure 216 is the same as the material of the second interconnect structure 226, the material of the first trace 217 is the same as the material of the second trace 227, and the material of the first interconnect structure 216 is the same as the material of the first trace 217. Therefore, the first interconnect structure 216, the second interconnect structure 226, the first trace 217, and the second trace 227 can be formed simultaneously in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure.

[0063] In some embodiments, reference Figure 13 The semiconductor structure further includes an interlayer dielectric layer 208 , which fills the gaps between adjacent contact plugs 204 . The interlayer dielectric layer 208 can insulate adjacent contact plugs 204 and insulate the contact plugs 204 from the capacitor structure 203 .

[0064] The material of the interlayer dielectric layer 208 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0065] refer to Figure 14 The semiconductor structure further includes: a first insulating layer 219, the first insulating layer 219 filling the gap between the first wiring layer 215 and the second wiring layer 225; a second insulating layer 229, the second insulating layer 229 filling the gap between the first routing 217 and the second routing 227; a dielectric layer 239, the dielectric layer 239 being located between the first wiring layer 215 and the routing layer 207, and between the second wiring layer 225 and the routing layer 207; wherein the relative dielectric constant of the material of the dielectric layer 239 is smaller than the relative dielectric constant of the material of the first insulating layer 219, and smaller than the relative dielectric constant of the material of the second insulating layer 229.

[0066] The first insulating layer 219 is used to insulate adjacent first wiring layers 215, adjacent second wiring layers 225, and between the first wiring layer 215 and the second wiring layer 225; the second insulating layer 229 is used to insulate adjacent first traces 217, adjacent second traces 227, and between the first trace 217 and the second trace 227; and the dielectric layer 239 is used to insulate the trace layer 207 from the first wiring layer 215 and the second wiring layer 225. For dielectric materials, the smaller the relative dielectric constant, the better the insulation. The smaller the relative dielectric constant of the dielectric layer 239, the better the insulation performance. Since the trace layer 207 is also located above the first wiring layer 215 in the array area 201, the dielectric layer 239 with better insulation performance can prevent parasitic capacitance from being generated between the first wiring layer 215 and the trace layer 207.

[0067] The material of the first insulating layer 219 and the material of the second insulating layer 229 both include silicon oxide. The material of the dielectric layer 239 includes silicon nitride.

[0068] In the semiconductor structure provided by the embodiment of the present disclosure, the substrate 200 includes an array region 201 and a peripheral region 202. The array region 201 of the substrate 200 may include storage transistors arranged in an array, and the storage transistors and the capacitor structure 203 may constitute an array-arranged storage unit. The substrate 200 in the peripheral region 202 may include a control transistor, and the control transistor constitutes a control circuit to achieve access to the storage unit. Among them, the first wiring layer 215 on the top surface of the capacitor structure 203 can interconnect the capacitor structure 203 with other structures, while reducing the resistance between the capacitor structure 203 and other structures, thereby improving signal transmission efficiency; the contact plug 204 and the second wiring layer 225 can interconnect the substrate 200 in the peripheral region 202 with other structures. Since the top surface of the contact plug 204 is not higher than the top surface of the capacitor structure 203, the length of the corresponding contact plug 205 in the direction perpendicular to the surface of the substrate 200 is reduced, thereby reducing the process difficulty of forming the contact plug 204 and reducing the delay effect of the contact plug 204. The first wiring layer 215 and the second wiring layer 225 are provided on the same layer. Therefore, the first wiring layer 215 and the second wiring layer 225 can be formed simultaneously in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure.

[0069] According to some embodiments of the present disclosure, another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure to improve the performance of the semiconductor structure. It should be noted that for the parts that are the same or corresponding to the above-mentioned embodiments, reference can be made to the corresponding description of the above-mentioned embodiments, and will not be repeated in detail below.

[0070] Figures 15 to 19 This is a schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. The method for manufacturing a semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings, as follows:

[0071] refer to Figures 15 to 19 , a method for manufacturing a semiconductor structure, comprising:

[0072] refer to Figure 15 , providing a substrate 200, the substrate 200 includes an array area 201 and a peripheral area 202, and a capacitor structure 203 is provided on the array area 201 of the substrate 200.

[0073] refer to Figure 16, forming a contact plug 204 , which extends along the thickness direction of the substrate 200 , and is located in the peripheral region 202 of the substrate 200 , with its bottom surface in contact with the substrate 200 and its top surface not higher than the top surface of the capacitor structure 203 .

[0074] In some embodiments, forming the contact plug 204 includes: referring to Figure 17 , forming an interlayer dielectric layer 208, the interlayer dielectric layer 208 covers the capacitor structure 203 and the peripheral region 202 of the substrate 200; patterning the interlayer dielectric layer 208 located in the peripheral region 202 to form a contact hole 304, the contact hole 304 exposes the surface of the substrate 200; referring to Figure 18 , filling the contact hole 304 to form the contact plug 204 .

[0075] When forming the contact plug 204 , a thin interlayer dielectric layer 208 may be formed to cover the surface of the capacitor structure 203 , thereby protecting the top surface of the capacitor structure 203 from being affected by other processes.

[0076] In some embodiments, after forming the contact plug 204 and before forming the first wiring layer, the method further includes: referring to Figure 19 The top surface of the contact plug 204 and the top surface of the interlayer dielectric layer 208 are planarized to expose the top surface of the capacitor structure 203. In this way, the first wiring layer formed subsequently can directly cover the top surface of the capacitor structure 203.

[0077] Return Reference Figure 3 , forming a first wiring layer 215 and a second wiring layer 225, the first wiring layer 215 is located on the top surface of the capacitor structure 203, the second wiring layer 225 is located on the top surface of the contact plug 204, and the second wiring layer 225 is arranged on the same layer as the first wiring layer 215.

[0078] In some embodiments, forming a first wiring layer and a second wiring layer includes: forming a first insulating layer, the first insulating layer covering the top surface of the capacitor structure, the top surface of the interlayer dielectric layer, and the top surface of the contact plug; patterning the first insulating layer and the interlayer dielectric layer in the array area to form a first wiring hole and a second wiring hole, the first wiring hole exposing the top surface of the capacitor structure, and the second wiring hole exposing the top surface of the contact plug; filling the first wiring hole and the second wiring hole to form the first wiring layer and the second wiring layer.

[0079] In some embodiments, forming a first wiring layer and a second wiring layer includes: forming an initial wiring layer, the initial wiring layer covering the top surface of the capacitor structure, the top surface of the interlayer dielectric layer, and the top surface of the contact plug; patterning the initial wiring layer to form the first wiring layer and the second wiring layer; forming a first insulating layer, the first insulating layer filling the gap between the first wiring layer and the second wiring layer.

[0080] In the semiconductor structure manufacturing method provided by the embodiments of the present disclosure, a substrate 200 includes an array region 201 and a peripheral region 202. The array region 201 of the substrate 200 may include storage transistors arranged in an array. These storage transistors and capacitor structures 203 may form arrayed storage cells. The peripheral region 202 of the substrate 200 may include control transistors to form a control circuit, thereby enabling access to the storage cells. Contact plugs 204 are formed to connect structures within the peripheral region 202 of the substrate 200 to other structures. The top surface of the contact plugs 204 is no higher than the top surface of the capacitor structure 203, thereby reducing the difficulty of the contact plug manufacturing process and also minimizing delay issues associated with the contact plugs 204. Furthermore, the first wiring layer 215 on the top surface of the capacitor structure 203 can interconnect the capacitor structure 203 with other structures, while reducing the resistance between the capacitor structure 203 and other structures, thereby improving signal transmission efficiency. The second wiring layer 225 on the top surface of the contact plug 204 can interconnect the structures within the peripheral region 202 of the substrate 200 with other structures. In addition, the first wiring layer 215 and the second wiring layer 225 are arranged on the same layer, and the first wiring layer 215 and the second wiring layer 225 can be formed simultaneously in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure.

[0081] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A substrate, the substrate comprising an array area and a peripheral area, the array area of ​​the substrate having a capacitor structure; a contact plug, the contact plug extending along the thickness direction of the substrate, the contact plug being located in a peripheral area of ​​the substrate, the bottom surface of the contact plug being in contact with the substrate, and the top surface of the contact plug being no higher than the top surface of the capacitor structure; a first wiring layer, the first wiring layer being in contact with a top surface of the capacitor structure; a second wiring layer, the second wiring layer being in contact with a top surface of the contact plug, and the second wiring layer being provided on the same layer as the first wiring layer; The first wiring layer includes a first adhesion layer, a first diffusion barrier layer, and a first conductor layer, wherein the first diffusion barrier layer covers the bottom surface and sidewalls of the first conductor layer, the first diffusion barrier layer located on the bottom surface of the first conductor layer contacts the top surface of the capacitor structure, and the first adhesion layer is located between the first diffusion barrier layer and the first conductor layer; And / or, the second wiring layer includes a second adhesion layer, a second diffusion barrier layer and a second conductor layer, the second diffusion barrier layer covers the bottom surface and side walls of the second conductor layer, the second diffusion barrier layer located on the bottom surface of the second conductor layer is in contact with the top surface of the contact plug, and the second adhesion layer is located between the second diffusion barrier layer and the second conductor layer.

2. The semiconductor structure according to claim 1, wherein: The first wiring layer is also located above the peripheral region of the substrate and between adjacent second wiring layers.

3. The semiconductor structure according to claim 2, wherein: Also includes: a routing layer, the routing layer being located on a side of the first wiring layer away from the substrate and on a side of the second wiring layer away from the substrate, the routing layer comprising a plurality of first routing lines and a plurality of second routing lines, the first routing lines being electrically connected to the first wiring layer, and the second routing lines being electrically connected to the second wiring layer, the semiconductor structure further comprising: a first interconnect structure, the first interconnect structure being in contact with a top surface of the first wiring layer located in the peripheral region, and the first interconnect structure being electrically connected to the first wiring layer and the first routing lines; The second interconnect structure contacts the top surface of the second wiring layer located in the peripheral area, and the second interconnect structure electrically connects the second wiring layer and the second trace, and the second interconnect structure is arranged on the same layer as the first interconnect structure.

4. The semiconductor structure according to claim 3, wherein: Also includes a first insulating layer filling a gap between the first wiring layer and the second wiring layer; a second insulating layer, wherein the second insulating layer fills a gap between the first trace and the second trace; a dielectric layer, the dielectric layer being located between the first wiring layer and the routing layer, and between the second wiring layer and the routing layer; The relative dielectric constant of the material of the dielectric layer is smaller than the relative dielectric constant of the material of the first insulating layer, and smaller than the relative dielectric constant of the material of the second insulating layer.

5. The semiconductor structure according to claim 1, wherein: The capacitor structure includes multiple capacitors and an upper electrode plate, the capacitors extend along the thickness direction of the substrate, the upper electrode plate fills the gaps between the capacitors, and the top surface of the upper electrode plate is flush with the top surface of the capacitors, and the first wiring layer is in contact with the top surface of the capacitors and the top surface of the upper electrode plate. The semiconductor structure according to claim 1 , wherein: An orthographic projection area of ​​the first wiring layer on the substrate surface is larger than an orthographic projection area of ​​the second wiring layer on the substrate surface.

7. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array area and a peripheral area, the array area of ​​the substrate having a capacitor structure; forming a contact plug, wherein the contact plug extends along the thickness direction of the substrate, the contact plug is located in the peripheral area of ​​the substrate, the bottom surface of the contact plug contacts the substrate, and the top surface is not higher than the top surface of the capacitor structure; forming a first wiring layer and a second wiring layer, wherein the first wiring layer is located on a top surface of the capacitor structure, the second wiring layer is located on a top surface of the contact plug, and the second wiring layer is provided on the same layer as the first wiring layer; In which, the first wiring layer includes a first adhesion layer, a first diffusion barrier layer and a first conductor layer, the first diffusion barrier layer covers the bottom surface and side walls of the first conductor layer, the first diffusion barrier layer formed on the bottom surface of the first conductor layer is in contact with the top surface of the capacitor structure, and the first adhesion layer is formed between the first diffusion barrier layer and the first conductor layer; and / or, the second wiring layer includes a second adhesion layer, a second diffusion barrier layer and a second conductor layer, the second diffusion barrier layer covers the bottom surface and side walls of the second conductor layer, the second diffusion barrier layer formed on the bottom surface of the second conductor layer is in contact with the top surface of the contact plug, and the second adhesion layer is formed between the second diffusion barrier layer and the second conductor layer.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: Forming the contact plug includes: forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the capacitor structure and the peripheral area of ​​the substrate; Patterning the interlayer dielectric layer in the peripheral region to form a contact hole, wherein the contact hole exposes the substrate surface; The contact hole is filled to form the contact plug.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: After forming the contact plug and before forming the first wiring layer, the method further includes: performing a planarization process on the top surface of the contact plug and the top surface of the interlayer dielectric layer to expose the top surface of the capacitor structure.

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