Memory cell structure, memory cell array and manufacturing method thereof

Abstract

The present disclosure relates to a memory cell structure, a memory cell array, and a method for fabricating the same. The memory cell structure includes an active platform, a target active pillar, a bit line structure, a first word line structure, and a second word line structure. The target active pillar is located on the top surface of the active platform and includes a common active pillar, a first active pillar, an intermediate isolation structure, and a second active pillar located on the top surface of the common active pillar and sequentially distributed along a first direction. The bit line structure is located on the top surface of the active platform and circumferentially surrounds the bottom of the target active pillar. The first word line structure and the second word line structure are located on opposite sides of the common active pillar along the first direction. This method effectively avoids the floating body effect and improves bit line flatness and leakage current.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and in particular to a memory cell structure, a memory cell array and a preparation method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the integration of semiconductor devices has continued to increase in order to form more devices within the same area, and the process nodes of devices have continued to decrease. To increase device integration, researchers have developed vertical channel transistors (VCTs) with vertical distribution of source, gate, and drain by improving the topology of semiconductor units, replacing horizontal transistors with horizontal distribution of source, gate, and drain. This reduces the area occupied by semiconductor units under the same feature size conditions.

[0003] However, conventional vertical channel transistors have the problem of floating body effect, and the fabricated bit lines have poor flatness and leakage current, which results in reduced performance and reliability of the vertical channel transistors. Summary of the Invention

[0004] Based on this, the present disclosure provides a memory cell structure, a memory cell array and a preparation method thereof, which can at least effectively avoid the floating body effect of vertical channel transistors and improve bit line flatness and leakage current problems.

[0005] In order to solve the above-mentioned technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a memory cell structure, which includes an active base, a target active pillar, a bit line structure, a first word line structure and a second word line structure; the target active pillar is located on the top surface of the active base and includes a common active pillar, and a first active pillar, an intermediate isolation structure and a second active pillar located on the top surface of the common active pillar and distributed in sequence along a first direction; the bit line structure is located on the top surface of the active base and circumferentially surrounds the bottom of the target active pillar; the first word line structure and the second word line structure are located on opposite sides of the common active pillar along the first direction.

[0006] In the memory cell structure of the above embodiment, the bitline structure circumferentially surrounds the bottom of the target active pillar, thereby reducing the resistance of the bitline structure and lowering leakage current, while effectively improving the flatness of the bitline structure, thereby enhancing the performance and reliability of the semiconductor device. Furthermore, the first active pillar and the second active pillar can be used to form two transistors, corresponding to the first wordline structure and the second wordline structure, respectively. Since the two transistors are located on the same target active pillar, that is, the two transistors share the same bitline structure, the number of bitline structures can be reduced by half, saving structural size and facilitating improved semiconductor device integration.

[0007] In some embodiments, the common active pillar includes a first common channel layer and a second common channel layer; the first common channel layer is located between the first active pillar and the second active pillar and the bottom surface is connected to the active base; the second common channel layer is located on the top surface of the first common channel layer and is located between the first word line structure and the second word line structure.

[0008] In some embodiments, the target active column also includes a first source structure, a second source structure, a first drain structure and a second drain structure; the first source structure includes the first active column and part of the common active column below it; the second source structure includes the second active column and part of the common active column below it; the first drain structure is located between the second common channel layer and the active base, and is located on the first side of the first common channel layer along the first direction; the second drain structure is located between the second common channel layer and the active base, and is located on the second side of the first common channel layer opposite to the first side along the first direction; or the first drain structure includes the first active column and part of the common active column below it; the second drain structure includes the second active column and part of the common active column below it; the first source structure is located between the second common channel layer and the active base, and is located on the first side of the first common channel layer along the first direction; the second source structure is located between the second common channel layer and the active base, and is located on the second side of the first common channel layer opposite to the first side along the first direction.

[0009] In some embodiments, the active platform further includes a first doped region directly below the first common channel layer and second doped regions located on opposite sides of the first doped region along a second direction; the second direction intersects the first direction.

[0010] In some embodiments, the doping type of the first doping region is opposite to the doping type of the second doping region; the doping type of the first doping region is the same as the doping type of the first common channel layer and the second common channel layer; the doping type of the second doping region is the same as the doping type of the first source structure, the second source structure, the first drain structure, and the second drain structure.

[0011] In some embodiments, the first word line structure includes a first gate dielectric layer and a first gate conductive layer stacked along a first direction; the first gate dielectric layer is located between the first gate conductive layer and the second common channel layer; and / or the second word line structure includes a second gate dielectric layer and a second gate conductive layer stacked along the first direction; the second gate dielectric layer is located between the second gate conductive layer and the second common channel layer.

[0012] In some embodiments, the storage cell structure further includes a first capacitor contact plug, a second capacitor contact plug, a first capacitor structure, and a second capacitor structure; the first capacitor contact plug is located on the top surface of the first active pillar; the second capacitor contact plug is located on the top surface of the second active pillar; the first capacitor structure is located on the top surface of the first capacitor contact plug; and the second capacitor structure is located on the top surface of the second capacitor contact plug.

[0013] According to some embodiments, the present disclosure provides a memory cell array on the other hand, comprising a plurality of memory cell structures of any one of the above embodiments arranged in an array along a first direction and a second direction; memory cell structures adjacent along the first direction share a bit line structure, and memory cell structures adjacent along the second direction are connected to different bit line structures; memory cells adjacent along the second direction share a first word line structure and a second word line structure, and memory cell structures adjacent along the first direction are connected to different first word line structures / second word line structures.

[0014] In the memory cell array of the above-described embodiment, the bitline structure circumferentially surrounding the bottom of the target active pillar can reduce the resistance of the bitline structure, lower leakage current, and effectively improve the flatness of the bitline structure, thereby enhancing the performance and reliability of the semiconductor device. Furthermore, the first active pillar and the second active pillar can be used to form two transistors, corresponding to the first wordline structure and the second wordline structure, respectively. Since the two transistors are located on the same target active pillar, that is, the two transistors share the same bitline structure, the number of bitline structures can be reduced by half, saving structural size and facilitating improved semiconductor device integration.

[0015] In some embodiments, the memory cell array further includes a bit line isolation structure and a word line isolation structure; the bit line isolation structure is located between bit line structures adjacent along the second direction; and / or the word line isolation structure is located between a first word line structure and a second word line structure adjacent along the first direction, and is located between target active pillars adjacent along the first direction.

[0016] According to some embodiments, the present disclosure provides a method for preparing a memory cell array on another aspect, the method comprising: providing a target substrate, the target substrate comprising reference cells and bit line structures arrayed along a first direction and a second direction, the reference cells comprising an active base and an initial active column stacked in sequence along a thickness direction of the target substrate, the bit line structure being located on a top surface of the active base and circumferentially surrounding a bottom of the initial active column; the first direction intersects with the second direction; forming a first word line structure and a second word line structure on opposite sides of the initial active column along the first direction; forming an intermediate isolation structure in the initial active column to obtain a target active column, the target active column comprising a common active column and a first active column, an intermediate isolation structure and a second active column located on a top surface of the common active column and distributed in sequence along the first direction.

[0017] In the memory cell array of the above-described embodiment, by forming a bitline structure that circumferentially surrounds the bottom of the initial active pillar, the resistance of the bitline structure can be reduced, leakage current can be lowered, and the flatness of the bitline structure can be effectively improved, thereby enhancing the performance and reliability of the semiconductor device. Furthermore, the first active pillar and the second active pillar can be used to form two transistors, corresponding to the first wordline structure and the second wordline structure, respectively. Since the two transistors are located on the same target active pillar, that is, the two transistors share the same bitline structure, the number of bitline structures can be reduced by half, saving structural size and facilitating improved semiconductor device integration.

[0018] In some embodiments, a target substrate is provided, including: providing an initial substrate, the initial substrate including initial active pillars arrayed along a first direction and a second direction; forming a bit line material layer on the initial substrate between the initial active pillars adjacent along the first direction and the second direction; forming a bit line isolation structure extending along the first direction in the initial substrate between the initial active pillars adjacent along the second direction to obtain active bases arranged at intervals along the second direction and extending along the first direction, with the initial active pillars located in the middle of the active base directly below them; the bit line material layer located on the top surface of the active base is used to form a bit line structure.

[0019] In some embodiments, forming a first word line structure and a second word line structure includes: forming a dielectric material layer, the dielectric material layer being located on a top surface of a bit line structure and between adjacent initial active pillars; removing a portion of the dielectric material layer to form a first word line trench and a second word line trench located on opposite sides of the initial active pillar along a first direction, as well as a first gate dielectric layer between the initial active pillar and the first word line trench, and a second gate dielectric layer between the initial active pillar and the second word line trench; the bottom surface of the first word line trench and the bottom surface of the second word line trench are both higher than the top surface of the bit line structure; forming a first gate conductive layer in the first word line trench and forming a second gate conductive layer in the second word line trench; the top surface of the first gate conductive layer and the top surface of the second gate conductive layer are both lower than the bottom surface of the intermediate isolation structure; wherein the first gate dielectric layer and the first gate conductive layer are used to constitute the first word line structure, and the second gate dielectric layer and the second gate conductive layer are used to constitute the second word line structure.

[0020] In some embodiments, forming the first word line structure and the second word line structure includes: forming a dielectric material layer, the dielectric material layer being located on the top surface of the bit line structure and between adjacent initial active pillars; removing a portion of the dielectric material layer to form a third word line trench and a fourth word line trench located on opposite sides of the initial active pillar along a first direction, the bottom surfaces of the third word line trench and the fourth word line trench being higher than the top surface of the bit line structure and lower than the bottom surface of the intermediate isolation structure; the third word line trench exposing a portion of the first side surface of the initial active pillar, and the fourth word line trench exposing a portion of the first side surface of the initial active pillar. A portion of the second side surface of the initial active pillar is exposed; the first side surface and the second side surface are surfaces of the initial active pillar that are opposite to each other along the first direction; a first gate dielectric layer covering the first side surface is formed in the third word line trench, and a second gate dielectric layer covering the second side surface is formed in the fourth word line trench; a first gate conductive layer is formed in the third word line trench, and a second gate conductive layer is formed in the fourth word line trench; wherein the first gate dielectric layer and the first gate conductive layer are used to constitute a first word line structure, and the second gate dielectric layer and the second gate conductive layer are used to constitute a second word line structure.

[0021] In some embodiments, after forming the intermediate isolation structure, the method further includes: forming a first capacitor contact plug located on the top surface of the first active pillar, and a second capacitor contact plug located on the top surface of the second active pillar; forming a first capacitor structure located on the top surface of the first capacitor contact plug, and a second capacitor structure located on the top surface of the second capacitor contact plug.

[0022] In some embodiments, it also includes: forming a first common channel layer and a second common channel layer in the common active pillar after forming the intermediate isolation structure and before forming the first capacitor contact plug and the second capacitor contact plug, or after forming the initial active pillar and before forming the bit line material layer; the first common channel layer is located between the first active pillar and the second active pillar and the bottom surface is connected to the active base; the second common channel layer is located on the top surface of the first common channel layer and between the first word line structure and the second word line structure.

[0023] In some embodiments, it also includes: after forming the initial substrate and before forming the first common channel layer, forming a first doped region in the initial substrate directly below the first common channel layer; after forming the first common channel layer and before forming the second common channel layer, forming a second doped region in the initial substrate and on opposite sides of the first common channel layer along a second direction; the second direction intersects with the first direction.

[0024] In some embodiments, the method further includes forming a second doped region at least in the first active pillar and the second active pillar after forming the second common channel layer and before forming the first capacitor contact plug and the second capacitor contact plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 A schematic diagram of an SOI device provided in one embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of a principle of a floating body effect provided in one embodiment of the present disclosure;

[0028] Figure 3 Schematic diagram of a vertical channel transistor provided in one embodiment of the present disclosure;

[0029] Figure 4 A schematic diagram of a bit line structure provided in one embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of a bit line structure provided in another embodiment of the present disclosure;

[0031] Figure 6 A schematic top view of a storage unit structure provided in one embodiment of the present disclosure;

[0032] Figure 7 A memory cell structure according to an embodiment of the present disclosure Figure 6 Schematic diagram of the cross section in the aa' direction;

[0033] Figure 8 A memory cell structure according to an embodiment of the present disclosure Figure 6 Schematic diagram of the cross section in the cc' direction;

[0034] Figure 9 A schematic flow chart of a method for preparing a memory cell array provided in one embodiment of the present disclosure;

[0035] Figure 10A The structure obtained in step S20 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0036] Figure 10B The structure obtained in step S20 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cc' and dd' directions;

[0037] Figure 11AThe structure obtained in step S21 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0038] Figure 11B The structure obtained in step S21 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cc' and dd' directions;

[0039] Figure 12A The structure obtained in step S22 of the method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0040] Figure 12B The structure obtained in step S23 of the method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cc' and dd' directions;

[0041] Figure 13A The structure obtained in step S23 of the method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0042] Figure 13B The structure obtained in step S23 of the method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cc' and dd' directions;

[0043] Figure 14A The structure obtained in step S40 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0044] Figure 14B The structure obtained in step S40 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cc' and dd' directions;

[0045] Figure 15A The structure obtained in step S60 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0046] Figure 15B The structure obtained in step S60 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6Schematic diagram of the cc' and dd' directions;

[0047] Figure 16A The structure obtained in step S80 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0048] Figure 16B The structure obtained in step S80 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cc' and dd' directions;

[0049] Figure 17A The structure obtained in step S70 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of aa' and bb' directions;

[0050] Figure 17B The structure obtained in step S70 of a method for preparing a memory cell array provided in one embodiment of the present disclosure corresponds to Figure 6 Schematic diagram of the cc' and dd' directions.

[0051] Description of reference numerals:

[0052] 1. Active platform; 11. First doped region; 12. Second doped region; 2. Target active pillar; 201. Initial active pillar; 21. Common active pillar; 211. First common channel layer; 212. Second common channel layer; 213. First source structure; 214. Second source structure; 215. First drain structure; 216. Second drain structure; 22. First active pillar; 23. Intermediate isolation structure; 24. Second active pillar; 3. Bit line structure; 31. Bit line material layer; 301. Bit line groove; 4. First word line structure; 41. First gate dielectric layer; 42. First gate conductive layer; 5. Second word line structure; 51. Second gate dielectric layer; 52. Second gate conductive layer; 61. First capacitor contact plug; 62. Second capacitor contact plug; 71. Bit line isolation structure; 72. Word line isolation structure; 8. Target substrate; 9. Initial substrate; 91. Mask stack; 911. First mask layer; 912. Second mask layer; 913. Third mask layer; 914. Fourth mask layer; 915. Fifth mask layer. DETAILED DESCRIPTION

[0053] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0055] The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. Where "include," "have," and "comprises" are used herein, another component may be added unless a clear limiting term, such as "only," "consisting of," or the like, is used. Unless otherwise noted, a term in the singular may include a plural form and is not to be construed as being one.

[0056] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0057] In the description of this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0058] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0059] Please refer to Figure 1 and Figure 2 Silicon on insulator (SOI) devices can be divided into thin film fully depleted SOI (FDSOI) devices and Figure 1 The thick film partially depleted SOI (PDSOI) device shown in Figure 1 is a PDSOI device. In SOI devices, the device's body potential and bias are related to the carrier recombination process. Since the top silicon film is floating relative to the substrate, the transistor forms a capacitor relative to the bottom plate, as shown in Figure 1. Figure 2 As shown by the floating body F in the figure, charge accumulates on the capacitor, creating an adverse effect known as the floating body effect. An inherent issue in SOI devices, the floating body effect can cause warping, parasitic bipolar transistor effects, abnormal subthreshold slopes, and device threshold voltage drift. These effects not only reduce device gain and cause unstable operation, lowering the drain breakdown voltage, but also trigger single-transistor latch-up, resulting in larger leakage currents and increased power consumption.

[0060] Please refer to Figure 3 Some VCT structure memories include a vertically stacked source structure S, a vertical channel CH, and a drain structure D, which are used to form a selection transistor T. The first word line structure 4 is located on one side of the vertical channel CH and is used to control the on and off of the selection transistor T. A first capacitor contact plug 61 and a capacitor structure C are formed on the top surface of the source structure S to store charge. The influence of the floating body effect in the VCT structure cannot be underestimated. For example, parasitic transistor leakage leads to higher current loss. In the memory, the floating body effect can also cause information loss in the storage cell. It can be seen that the floating body effect seriously affects the performance of VCT structure memory devices and hinders the development of VCT structure memory devices.

[0061] Please refer to Figure 4 In the process of forming some bit line structures 3, a method is usually adopted to form a bit line groove 301 at the bottom of the active pillar and then form the bit line structure 3 in the bit line groove 301. However, the flatness of the bit line structure 3 prepared in this way is poor and there is a risk of leakage. Please refer to Figure 5 In the process of forming the bit line structure 3 of other systems, an ion implantation process is usually used to form the bit line structure 3 on both sides of the active pillar. The resistance of the bit line structure 3 prepared in this way is relatively large, and there is a leakage current problem between adjacent bit line structures 3.

[0062] The present disclosure aims to provide a memory cell structure, a memory cell array and a preparation method thereof, which can at least effectively avoid the floating body effect of vertical channel transistors and improve the bit line flatness and leakage current problems.

[0063] Please refer to Figures 6 to 8According to some embodiments, one aspect of the present disclosure provides a memory cell structure, which includes an active base 1, a target active pillar 2, a bit line structure 3, a first word line structure 4, and a second word line structure 5; the target active pillar 2 is located on the top surface of the active base 1 and includes a common active pillar 21, and a first active pillar 22, an intermediate isolation structure 23, and a second active pillar 24 located on the top surface of the common active pillar 21 and distributed in sequence along a first direction; the bit line structure 3 is located on the top surface of the active base 1 and circumferentially surrounds the bottom of the target active pillar 2; the first word line structure 4 and the second word line structure 5 are located on opposite sides of the common active pillar 21 along the first direction.

[0064] For example, the first direction may be the OY direction, and the first direction may be Figure 6 The aa' direction or the bb' direction shown in the figure is parallel to each other, and the first direction can be parallel to the extension direction of the bit line structure 3; the directions in subsequent embodiments can refer to the directions in this embodiment, and will not be repeated hereafter.

[0065] Please continue to refer to Figures 6 to 8 In the memory cell structure of the above embodiment, the bitline structure 3 circumferentially surrounding the bottom of the target active pillar 2 can reduce the resistance of the bitline structure 3, lowering leakage current while effectively improving the flatness of the bitline structure 3, thereby enhancing the performance and reliability of the semiconductor device. Furthermore, the first active pillar 22 and the second active pillar 24 can be used to form two transistors, corresponding to the first wordline structure 4 and the second wordline structure 5, respectively. Since the two transistors are located on the same target active pillar 2, i.e., they share the same bitline structure 3, the number of bitline structures 3 can be reduced by half, saving structural size and facilitating improved semiconductor device integration.

[0066] Please continue to refer to Figures 6 to 8 For example, the material of the bit line structure 3 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon and combinations thereof.

[0067] Please continue to refer to Figures 6 to 8 For example, the material of the first word line structure 4 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide and their combinations; the material of the second word line structure 5 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide and their combinations.

[0068] Please continue to refer to Figures 6 to 8In some embodiments, the common active pillar 21 includes a first common channel layer 211 and a second common channel layer 212. The first common channel layer 211 is located between the first active pillar 22 and the second active pillar 24, with its bottom surface connected to the active platform 1. The second common channel layer 212 is located on the top surface of the first common channel layer 211 and between the first word line structure 4 and the second word line structure 5. The first active pillar 22 and the second active pillar 24 share the first common channel layer 211 or the second common channel layer 212, which can effectively improve the size utilization of the memory cell structure, thereby increasing the device integration and facilitating the preparation of high-density memory devices.

[0069] Please continue to refer to Figures 6 to 8 For example, the material of the common active pillar 21 is selected from single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, silicon germanium, etc. and combinations thereof.

[0070] Please continue to refer to Figures 6 to 8In some embodiments, the target active pillar 2 further includes a first source structure 213, a second source structure 214, a first drain structure 215, and a second drain structure 216; the first source structure 213 includes the first active pillar 22 and a portion of the common active pillar 21 thereunder; the second source structure 214 includes the second active pillar 24 and a portion of the common active pillar 21 thereunder; the first drain structure 215 is located between the second common channel layer 212 and the active base 1, and is located on the first side of the first common channel layer 211 along the first direction; the second drain structure 216 is located between the second common channel layer 212 and the active base 1, and Located on the second side of the first common channel layer 211 opposite to the first side along the first direction; or the first drain structure 215 includes the first active pillar 22 and part of the common active pillar 21 thereunder; the second drain structure 216 includes the second active pillar 24 and part of the common active pillar 21 thereunder; the first source structure 213 is located between the second common channel layer 212 and the active base 1, and is located on the first side of the first common channel layer 211 along the first direction; the second source structure 214 is located between the second common channel layer 212 and the active base 1, and is located on the second side of the first common channel layer 211 opposite to the first side along the first direction. The first source structure 213 and the first drain structure 215 can be used to form a first transistor. Correspondingly, the second source structure 214 and the second drain structure 216 can be used to form a second transistor. The first word line structure 4 is located on a side close to the first transistor, and the second word line structure 5 is located on a side close to the second transistor. Since the first transistor and the second transistor are located on the same target active column 2, that is, the two transistors share the same bit line structure 3, the number of bit line structures 3 can be reduced by half, thereby saving structural size and facilitating the improvement of the integration of the semiconductor device. In addition, since the corresponding transistors share the channel structure, the channel range corresponding to each transistor is increased, thereby improving the floating body effect. In addition, based on the first common channel layer 211 and the second common channel layer 212, vertical channel transistors can be formed. Since the drain of the vertical channel transistor is located at the bottom of the transistor, it does not need to be directly drawn from the surface of the transistor, making it easier to form isolation between transistors in the array, thereby reducing the power consumption of the semiconductor device. While ensuring the storage capacity of the semiconductor device, the volume of the semiconductor unit can be reduced, thereby improving the response speed and storage density of the semiconductor device.

[0071] Please continue to refer to Figures 6 to 8 In some embodiments, the active base 1 further includes a first doping region 11 located directly below the first common channel layer 211 and a second doping region 12 located on opposite sides of the first doping region 11 along a second direction; the second direction intersects with the first direction.

[0072] For example, the second direction may be the OX direction. For example, the second direction may be Figure 6The cc' direction or dd' direction shown in FIG is parallel to each other, and the second direction can be parallel to the directions of the first word line structure 4 and the second word line structure 5. The directions in subsequent embodiments can refer to the directions in this embodiment and will not be repeated here.

[0073] Please continue to refer to Figures 6 to 8 In some embodiments, the doping type of the first doping region 11 may be N-type or P-type; the doping type of the second doping region 12 may be N-type or P-type.

[0074] Please continue to refer to Figures 6 to 8 In some embodiments, the doping type of the first doping region 11 is opposite to the doping type of the second doping region 12; the doping type of the first doping region 11 is the same as the doping type of the first common channel layer 211 and the second common channel layer 212; the doping type of the second doping region 12 is the same as the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216.

[0075] Please continue to refer to Figures 6 to 8 In some embodiments, the doping type of the first common channel layer 211 and the second common channel layer 212 can be N-type or P-type; the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216 can also be N-type or P-type.

[0076] Please continue to refer to Figures 6 to 8 For example, the first common channel layer 211 and the second common channel layer 212 have the same doping type, both of which are P-type, the doping type of the first doping region 11 is also P-type, the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216 are all N-type, and the doping type of the second doping region 12 is also N-type. The first source structure 213 and the first drain structure 215, the second source structure 214, and the second drain structure 216 can be used to form two selection transistors respectively. Since the two selection transistors are located in the same target active column 2 and share the P-type first common channel layer 211 and the P-type second common channel layer 212 between the two selection transistors, the device structure size can be saved, which is beneficial to improving the integration of the semiconductor device, and the floating body effect can be further improved by forming a P-type channel through doping.

[0077] Please continue to refer to Figures 6 to 8In some embodiments, the first word line structure 4 includes a first gate dielectric layer 41 and a first gate conductive layer 42 stacked along a first direction; the first gate dielectric layer 41 is located between the first gate conductive layer 42 and the second common channel layer 212; and / or the second word line structure 5 includes a second gate dielectric layer 51 and a second gate conductive layer 52 stacked along the first direction; the second gate dielectric layer 51 is located between the second gate conductive layer 52 and the second common channel layer 212.

[0078] Please continue to refer to Figures 6 to 8 For example, the material of the first gate conductive layer 42 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide and combinations thereof; the material of the second gate conductive layer 52 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide and combinations thereof; the material of the first gate dielectric layer 41 is selected from silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide and combinations thereof; the material of the second gate dielectric layer 51 is selected from silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide and combinations thereof.

[0079] Please continue to refer to Figures 6 to 8 In some embodiments, the memory cell structure further includes a first capacitor contact plug 61, a second capacitor contact plug 62, a first capacitor structure (not shown), and a second capacitor structure (not shown). The first capacitor contact plug 61 is located on the top surface of the first active pillar 22; the second capacitor contact plug 62 is located on the top surface of the second active pillar 24; the first capacitor structure is located on the top surface of the first capacitor contact plug 61; and the second capacitor structure is located on the top surface of the second capacitor contact plug 62. The first capacitor structure and the second capacitor structure are used to store charge. The first capacitor contact plug 61 is used to reduce the contact resistance between the first capacitor structure and the first active pillar 22, and the second capacitor contact plug 62 is used to reduce the contact resistance between the second capacitor structure and the second active pillar 24.

[0080] Please continue to refer to Figures 6 to 8 For example, the material of the first capacitor contact plug 61 and the second capacitor contact plug 62 may be metal silicide, thereby further reducing the contact resistance between the first capacitor structure and the first active pillar 22 , and further reducing the contact resistance between the second capacitor structure and the second active pillar 24 .

[0081] Please continue to refer to Figures 6 to 8According to some embodiments, a memory cell array is provided, comprising a plurality of memory cell structures of any one of the above embodiments arranged in an array along a first direction and a second direction; memory cell structures adjacent along the first direction share a bit line structure 3, and memory cell structures adjacent along the second direction are connected to different bit line structures 3; memory cells adjacent along the second direction share a first word line structure 4 and a second word line structure 5, and memory cell structures adjacent along the first direction are connected to different first word line structures 4 / second word line structures 5.

[0082] Please continue to refer to Figures 6 to 8 In the memory cell array of the above embodiment, the bitline structure 3 circumferentially surrounding the bottom of the target active pillar 2 can reduce the resistance of the bitline structure 3, lowering leakage current while effectively improving the flatness of the bitline structure 3, thereby enhancing the performance and reliability of the semiconductor device. Furthermore, the first active pillar 22 and the second active pillar 24 can be used to form two transistors, corresponding to the first wordline structure 4 and the second wordline structure 5, respectively. Since the two transistors are located on the same target active pillar 2, i.e., the two transistors share the same bitline structure 3, the number of bitline structures 3 can be reduced by half, saving structural size and facilitating improved semiconductor device integration.

[0083] Please continue to refer to Figures 6 to 8 In some embodiments, the memory cell array further includes a bit line isolation structure 71 and a word line isolation structure 72. The bit line isolation structure 71 is located between bit line structures 3 adjacent along the second direction; and / or the word line isolation structure 72 is located between a first word line structure 4 and a second word line structure 5 adjacent along the first direction, and between target active pillars 2 adjacent along the first direction. The bit line isolation structure 71 insulates the bit line structures 3 adjacent along the second direction from each other. The word line isolation structure insulates the first word line structure 4 and the second word line structure 5 adjacent along the first direction from each other.

[0084] Please continue to refer to Figures 6 to 9 According to some embodiments, the present disclosure further provides a method for preparing a memory cell array, the method comprising:

[0085] Step S20: Providing a target substrate 8, the target substrate 8 including a reference cell and a bit line structure 3 arrayed along a first direction and a second direction, the reference cell including an active platform 1 and an initial active pillar 201 stacked sequentially along the thickness direction of the target substrate 8, the bit line structure 3 being located on a top surface of the active platform 1 and circumferentially surrounding a bottom of the initial active pillar 201; the first direction intersects the second direction;

[0086] Step S40: forming a first word line structure 4 and a second word line structure 5 on two opposite sides of the initial active pillar 201 along the first direction;

[0087] Step S60: forming an intermediate isolation structure 23 in the initial active pillar 201 to obtain a target active pillar 2, wherein the target active pillar 2 includes a common active pillar 21 and a first active pillar 22, an intermediate isolation structure 23 and a second active pillar 24 located on the top surface of the common active pillar 21 and sequentially distributed along a first direction.

[0088] Please continue to refer to Figures 6 to 9 In step S20, the target substrate 8 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the target substrate 8 may be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI), or a silicon-germanium-on-insulator (SiGe-on-insulator). P-type ions may be implanted into the target substrate 8 using an ion implantation process to form a first-type doped well region (not shown). The P-type ions may include, but are not limited to, at least one of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions.

[0089] Please continue to refer to Figures 6 to 9 In step S20 , illustratively, the material of the bit line structure 3 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon and combinations thereof.

[0090] Please continue to refer to Figures 6 to 9 In step S40, for example, the material of the first word line structure 4 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide and combinations thereof; the material of the second word line structure 5 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide and combinations thereof.

[0091] Please continue to refer to Figures 6 to 9 In step S60 , for example, the material of the common active pillar 21 is selected from single crystal silicon, polycrystalline silicon, doped polycrystalline silicon, germanium silicon, etc., and combinations thereof.

[0092] Please continue to refer to Figures 6 to 9In the memory cell array of the above embodiment, by forming a bitline structure 3 circumferentially surrounding the bottom of the initial active pillar 201, the resistance of the bitline structure 3 can be reduced, leakage current can be lowered, and the flatness of the bitline structure 3 can be effectively improved, thereby improving the performance and reliability of the semiconductor device. Furthermore, the first active pillar 22 and the second active pillar 24 can be used to form two transistors, corresponding to the first wordline structure 4 and the second wordline structure 5, respectively. Because the two transistors are located on the same target active pillar 2, that is, the two transistors share the same bitline structure 3, the number of bitline structures 3 can be reduced by half, saving structural size and facilitating improved semiconductor device integration.

[0093] Please refer to 10A to 13B In some embodiments, step S20 includes:

[0094] Step S21: providing an initial substrate 9, wherein the initial substrate 9 includes initial active pillars 201 distributed in an array along a first direction and a second direction;

[0095] Step S22: forming a bit line material layer 31 on the initial substrate 9 between the initial active pillars 201 adjacent to each other along the first direction and the second direction;

[0096] Step S23: A bit line isolation structure 71 extending along the first direction is formed in the initial substrate 9 between the initial active pillars 201 adjacent to each other along the second direction to obtain active bases 1 arranged at intervals along the second direction and extending along the first direction, with the initial active pillars 201 located in the middle of the active base 1 directly below them; the bit line material layer 31 located on the top surface of the active base 1 is used to form a bit line structure 3.

[0097] Please refer to Figures 10A to 11B In step S21, for example, the method further includes:

[0098] Step S211: forming a mask stack 91 on the top surface of the initial substrate 9;

[0099] Step S212: patterning the mask stack 91 to obtain a pattern layer; etching the initial substrate 9 based on the pattern layer to obtain an initial active pillar 201; and removing the pattern layer.

[0100] Please refer to FIG. 10A to FIG. 10B For example, the mask stack 91 may be a single-layer structure, or the mask stack 91 may be a multi-layer structure. For example, the mask stack 91 includes a first mask layer 911, a second mask layer 912, a third mask layer 913, a fourth mask layer 914, and a fifth mask layer 915 stacked in sequence along the thickness direction of the initial substrate 9.

[0101] Please refer to FIG. 12A to FIG. 12BIn step S21, for example, a deposition process may be adopted to form the bit line material layer 31, and the deposition process may include but is not limited to at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process, and a spin-on dielectric layer process.

[0102] Please refer to 13A to 13B In step S23, for example, the method further includes:

[0103] Step S231 : etching the initial substrate 9 and the bit line material layer 31 to form a bit line isolation trench extending along the first direction in the initial substrate 9 between the initial active pillars 201 adjacent to each other along the second direction; the remaining bit line material layer 31 constitutes the bit line structure 3;

[0104] Step S232 : forming a bit line isolation structure 71 in the bit line isolation trench.

[0105] Please refer to FIG. 14A to FIG. 14B In some embodiments, the first word line structure 4 and the second word line structure 5 are formed, and step S40 includes:

[0106] Step S41: forming a dielectric material layer (not shown), the dielectric material layer being located on the top surface of the bit line structure 3 and between adjacent initial active pillars 201;

[0107] Step S42: removing a portion of the dielectric material layer to form a first word line trench and a second word line trench located on opposite sides of the initial active pillar 201 along the first direction, as well as a first gate dielectric layer 41 located between the initial active pillar 201 and the first word line trench, and a second gate dielectric layer 51 located between the initial active pillar 201 and the second word line trench; the bottom surfaces of the first word line trench and the second word line trench are both higher than the top surface of the bit line structure 3;

[0108] Step S43: forming a first gate conductive layer 42 in the first word line trench and forming a second gate conductive layer 52 in the second word line trench; the top surface of the first gate conductive layer 42 and the top surface of the second gate conductive layer 52 are both lower than the bottom surface of the intermediate isolation structure 23; wherein, the first gate dielectric layer 41 and the first gate conductive layer 42 are used to constitute the first word line structure 4, and the second gate dielectric layer 51 and the second gate conductive layer 52 are used to constitute the second word line structure 5.

[0109] In step S42, for example, a dry etching process may be used to remove part of the dielectric material layer. The dry etching process may include but is not limited to any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP) or high concentration plasma etching (HDP).

[0110] Please refer to FIG. 14A to FIG. 14BIn some embodiments, forming the first word line structure 4 and the second word line structure 5 includes:

[0111] Step S44: forming a dielectric material layer, the dielectric material layer being located on the top surface of the bit line structure 3 and between adjacent initial active pillars 201;

[0112] Step S45: removing a portion of the dielectric material layer to form a third word line trench and a fourth word line trench located on opposite sides of the initial active pillar 201 along the first direction. The bottom surfaces of the third word line trench and the fourth word line trench are both higher than the top surface of the bit line structure 3 and lower than the bottom surface of the intermediate isolation structure 23. The third word line trench exposes a portion of the first side surface of the initial active pillar 201, and the fourth word line trench exposes a portion of the second side surface of the initial active pillar 201. The first side surface and the second side surface are opposite surfaces of the initial active pillar 201 along the first direction.

[0113] Step S46: forming a first gate dielectric layer 41 covering the first side surface in the third word line trench, and forming a second gate dielectric layer 51 covering the second side surface in the fourth word line trench; forming a first gate conductive layer 42 in the third word line trench and forming a second gate conductive layer 52 in the fourth word line trench; wherein the first gate dielectric layer 41 and the first gate conductive layer 42 are used to constitute a first word line structure 4, and the second gate dielectric layer 51 and the second gate conductive layer 52 are used to constitute a second word line structure 5.

[0114] Please refer to Figures 14A to 15B For example, in step S60, an intermediate isolation structure 23 is formed in the initial active pillar 201 to obtain a target active pillar 2, the target active pillar 2 including a common active pillar 21 and a first active pillar 22, an intermediate isolation structure 23 and a second active pillar 24 located on the top surface of the common active pillar 21 and distributed in sequence along the first direction.

[0115] Please refer to 16A to 17B In some embodiments, after forming the intermediate isolation structure 23, the method further includes:

[0116] Step S80: forming a first capacitor contact plug 61 located on the top surface of the first active pillar 22 and a second capacitor contact plug 62 located on the top surface of the second active pillar 24; forming a first capacitor structure located on the top surface of the first capacitor contact plug 61 and a second capacitor structure located on the top surface of the second capacitor contact plug 62.

[0117] Please refer to 17A to 17B , in some embodiments, further comprising:

[0118] Step S70: After forming the intermediate isolation structure 23 and before forming the first capacitor contact plug 61 and the second capacitor contact plug 62, or after forming the initial active pillar and before forming the bit line material layer, a first common channel layer 211 and a second common channel layer 212 are formed in the common active pillar 21; the first common channel layer 211 is located between the first active pillar 22 and the second active pillar 24 and the bottom surface is connected to the active base 1; the second common channel layer 212 is located on the top surface of the first common channel layer 211 and between the first word line structure 4 and the second word line structure 5.

[0119] Please continue to refer to 17A to 17B , in some embodiments, further comprising:

[0120] Step S50: After forming the initial substrate and before forming the first common channel layer 211, a first doped region 11 is formed in the initial substrate directly below the first common channel layer 211; after forming the first common channel layer 211 and before forming the second common channel layer 212, a second doped region 12 is formed in the initial substrate and on opposite sides of the first common channel layer 211 along a second direction; the second direction intersects with the first direction.

[0121] Please continue to refer to 17A to 17B In some embodiments, the doping type of the first doping region 11 may be N-type or P-type; the doping type of the second doping region 12 may be N-type or P-type.

[0122] Please continue to refer to 17A to 17B In some embodiments, the method further includes forming a second doped region 12 at least in the first active pillar 22 and the second active pillar 24 after forming the second common channel layer 212 and before forming the first capacitor contact plug 61 and the second capacitor contact plug 62 .

[0123] Please continue to refer to 17A to 17BIn some embodiments, the method further includes: after forming the target active pillar 2, doping the target active pillar 2 to form a first source structure 213, a second source structure 214, a first drain structure 215, and a second drain structure 216; the first source structure 213 includes the first active pillar 22 and a portion of the common active pillar 21 thereunder; the second source structure 214 includes the second active pillar 24 and a portion of the common active pillar 21 thereunder; the first drain structure 215 is located between the second common channel layer 212 and the active base 1, and is located on a first side of the first common channel layer 211 along the first direction; the second drain structure 216 is located on the second common channel layer 212 and the active base 1, and is located on the second side of the first common channel layer 211 opposite to the first side along the first direction; or the first drain structure 215 includes the first active pillar 22 and part of the common active pillar 21 thereunder; the second drain structure 216 includes the second active pillar 24 and part of the common active pillar 21 thereunder; the first source structure 213 is located between the second common channel layer 212 and the active base 1, and is located on the first side of the first common channel layer 211 along the first direction; the second source structure 214 is located between the second common channel layer 212 and the active base 1, and is located on the second side of the first common channel layer 211 opposite to the first side along the first direction. The first source structure 213 and the first drain structure 215 can be used to form a first transistor. Correspondingly, the second source structure 214 and the second drain structure 216 can be used to form a second transistor. The first word line structure 4 is located on a side close to the first transistor, and the second word line structure 5 is located on a side close to the second transistor. Since the first transistor and the second transistor are located on the same target active column 2, that is, the two transistors share the same bit line structure 3, the number of bit line structures 3 can be reduced by half, thereby saving structural size and facilitating the improvement of the integration of the semiconductor device. In addition, since the corresponding transistors share the channel structure, the channel range corresponding to each transistor is increased, thereby improving the floating body effect. In addition, based on the first common channel layer 211 and the second common channel layer 212, vertical channel transistors can be formed. Since the drain of the vertical channel transistor is located at the bottom of the transistor, it does not need to be directly drawn from the surface of the transistor, making it easier to form isolation between transistors in the array, thereby reducing the power consumption of the semiconductor device. While ensuring the storage capacity of the semiconductor device, the volume of the semiconductor unit can be reduced, thereby improving the response speed and storage density of the semiconductor device.

[0124] Please continue to refer to 17A to 17BIn some embodiments, the doping type of the first doping region 11 is opposite to the doping type of the second doping region 12; the doping type of the first doping region 11 is the same as the doping type of the first common channel layer 211 and the second common channel layer 212; the doping type of the second doping region 12 is the same as the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216.

[0125] Please continue to refer to 17A to 17B For example, the doping type of the first common channel layer 211 and the second common channel layer 212 can be N-type or P-type; the doping type of the first source structure 213, the second source structure 214, the first drain structure 215, and the second drain structure 216 can also be N-type or P-type.

[0126] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0127] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0128] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The above embodiments merely illustrate several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure.

Claims

1. A memory cell structure, characterized in that: include: an active base, a target active pillar, a bit line structure, a first word line structure, and a second word line structure; The target active pillar is located on the top surface of the active base and includes a common active pillar, and a first active pillar, an intermediate isolation structure and a second active pillar located on the top surface of the common active pillar and distributed in sequence along a first direction; The bit line structure is located on the top surface of the active platform and circumferentially surrounds the bottom of the target active pillar; The first word line structure and the second word line structure are located on two opposite sides of the common active pillar along the first direction.

2. The memory cell structure according to claim 1, wherein: The common active pillar comprises: a first common channel layer, located below the intermediate isolation structure and having a bottom surface connected to the active base; The second common channel layer is located below the intermediate isolation structure and on a top surface of the first common channel layer, wherein the first word line structure and the second word line structure are located on opposite sides of the second common channel layer along the first direction.

3. The memory cell structure according to claim 2, wherein: The target active column further comprises: A first source structure, comprising the first active pillar and a portion of the common active pillar thereunder; A second source structure, comprising the second active pillar and a portion of the common active pillar thereunder; a first drain structure, located between the second common channel layer and the active platform, and located on a first side of the first common channel layer along the first direction; The second drain structure is located between the second common channel layer and the active platform, and is located on a second side of the first common channel layer opposite to the first side along the first direction.

4. The memory cell structure according to claim 2, wherein: The target active column further comprises: A first drain structure, comprising the first active pillar and a portion of the common active pillar thereunder; A second drain structure, comprising the second active pillar and a portion of the common active pillar thereunder; a first source structure, located between the second common channel layer and the active platform, and located on a first side of the first common channel layer along the first direction; The second source structure is located between the second common channel layer and the active platform, and is located on a second side of the first common channel layer opposite to the first side along the first direction.

5. The memory cell structure according to claim 3 or 4, characterized in that: A first doping region located directly below the first common channel layer and second doping regions located on opposite sides of the first doping region along a second direction are also formed in the active base; the second direction intersects with the first direction.

6. The memory cell structure according to claim 5, wherein: The doping type of the first doping region is opposite to the doping type of the second doping region; The doping type of the first doping region is the same as the doping type of the first common channel layer and the second common channel layer; the doping type of the second doping region is the same as the doping type of the first source structure, the second source structure, the first drain structure, and the second drain structure.

7. The storage unit structure according to any one of claims 2 to 4, characterized in that: The first word line structure includes a first gate dielectric layer and a first gate conductive layer stacked along the first direction; the first gate dielectric layer is located between the first gate conductive layer and the second common channel layer; and / or The second word line structure includes a second gate dielectric layer and a second gate conductive layer stacked along the first direction; the second gate dielectric layer is located between the second gate conductive layer and the second common channel layer.

8. A memory cell array, characterized in that: A storage unit structure according to any one of claims 1 to 7 comprising a plurality of storage unit structures arranged in an array along a first direction and a second direction; The memory cell structures adjacent to each other along the first direction share a bit line structure, and the memory cell structures adjacent to each other along the second direction are connected to different bit line structures; The memory cells adjacent to each other along the second direction share a first word line structure and a second word line structure, and the memory cell structures adjacent to each other along the first direction are connected to different first word line structures / second word line structures.

9. A method for preparing a memory cell array, characterized in that: The method comprises: Providing a target substrate, the target substrate comprising reference cells and bit line structures arrayed along a first direction and a second direction, the reference cells comprising active platforms and initial active pillars stacked in sequence along the thickness direction of the target substrate, the bit line structures being located on top of the active platforms and circumferentially surrounding the bottoms of the initial active pillars; the first direction intersects the second direction; forming a first word line structure and a second word line structure on two opposite sides of the initial active pillar along the first direction; An intermediate isolation structure is formed in the initial active pillar to obtain a target active pillar. The target active pillar includes a common active pillar and a first active pillar, the intermediate isolation structure and a second active pillar located on a top surface of the common active pillar and sequentially distributed along the first direction.

10. The method for preparing a memory cell array according to claim 9, wherein: The providing of a target substrate comprises: Providing an initial substrate, the initial substrate comprising initial active pillars distributed in an array along the first direction and the second direction; forming a bit line material layer on the initial substrate between the initial active pillars adjacent to each other along the first direction and the second direction; A bit line isolation structure extending along the first direction is formed in the initial substrate between the initial active pillars adjacent to each other along the second direction to obtain the active bases arranged at intervals along the second direction and extending along the first direction, wherein the initial active pillars are located in the middle of the active bases directly below them; and a bit line material layer located on the top surface of the active bases is used to form the bit line structure.

11. The method for preparing a memory cell array according to claim 10, wherein: Forming the first word line structure and the second word line structure includes: forming a dielectric material layer, wherein the dielectric material layer is located on a top surface of the bit line structure and between adjacent initial active pillars; Removing a portion of the dielectric material layer to form a first word line trench and a second word line trench located on opposite sides of the initial active pillar along the first direction, and a first gate dielectric layer between the initial active pillar and the first word line trench, and a second gate dielectric layer between the initial active pillar and the second word line trench; the bottom surfaces of the first word line trench and the second word line trench are both higher than the top surface of the bit line structure; A first gate conductive layer is formed in the first word line trench and a second gate conductive layer is formed in the second word line trench; the top surface of the first gate conductive layer and the top surface of the second gate conductive layer are both lower than the bottom surface of the intermediate isolation structure; wherein, the first gate dielectric layer and the first gate conductive layer are used to constitute the first word line structure, and the second gate dielectric layer and the second gate conductive layer are used to constitute the second word line structure.

12. The method for preparing a memory cell array according to claim 10, wherein: Forming the first word line structure and the second word line structure includes: forming a dielectric material layer, wherein the dielectric material layer is located on a top surface of the bit line structure and between adjacent initial active pillars; Removing a portion of the dielectric material layer to form a third word line trench and a fourth word line trench located on opposite sides of the initial active pillar along the first direction, wherein the bottom surfaces of the third word line trench and the fourth word line trench are both higher than the top surface of the bit line structure and lower than the bottom surface of the intermediate isolation structure; the third word line trench exposes a portion of the first side surface of the initial active pillar, and the fourth word line trench exposes a portion of the second side surface of the initial active pillar; the first side surface and the second side surface are opposite surfaces of the initial active pillar along the first direction; forming a first gate dielectric layer covering the first side surface in the third word line trench, and forming a second gate dielectric layer covering the second side surface in the fourth word line trench; A first gate conductive layer is formed in the third word line trench and a second gate conductive layer is formed in the fourth word line trench; wherein the first gate dielectric layer and the first gate conductive layer are used to constitute the first word line structure, and the second gate dielectric layer and the second gate conductive layer are used to constitute the second word line structure.

13. The method for preparing a memory cell array according to any one of claims 10 to 12, wherein: After forming the intermediate isolation structure, the method further includes: forming a first capacitor contact plug located on a top surface of the first active pillar and a second capacitor contact plug located on a top surface of the second active pillar; A first capacitor structure is formed on a top surface of the first capacitor contact plug, and a second capacitor structure is formed on a top surface of the second capacitor contact plug.

14. The method for preparing a memory cell array according to claim 13, wherein: Also includes: After forming the intermediate isolation structure and before forming the first capacitor contact plug and the second capacitor contact plug, or after forming the initial active column and before forming the bit line material layer, a first common channel layer and a second common channel layer are formed in the common active column; the first common channel layer is located below the intermediate isolation structure and the bottom surface is connected to the active base; the second common channel layer is located below the intermediate isolation structure and is located on the top surface of the first common channel layer, wherein the first word line structure and the second word line structure are located on opposite sides of the second common channel layer along the first direction.

15. The method for preparing a memory cell array according to claim 14, wherein: Also includes: After forming the initial substrate and before forming the first common channel layer, forming a first doped region directly below the first common channel layer in the initial substrate; After forming the first common channel layer and before forming the second common channel layer, second doping regions are formed in the initial substrate and on opposite sides of the first common channel layer along a second direction; the second direction intersects the first direction.

16. The method for preparing a memory cell array according to claim 15, wherein: Also includes: After forming the second common channel layer and before forming the first capacitor contact plug and the second capacitor contact plug, a second doped region is formed at least in the first active pillar and the second active pillar.

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