Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductor technology, and aims to solve the technical problem of poor performance of a semiconductor device. The semiconductor device comprises a substrate, a gate trench in the substrate, a gate dielectric layer in the substrate, covering the inner surface of the gate trench, a gate structure on the gate dielectric layer and filling the gate trench, and the gate structure comprises a metal layer and a conductive layer. The metal layer comprises a plurality of first grains and a plurality of second grains on the first grains. The first grains and the second grains contain the same metal element, and the grain size of the second grains is smaller than that of at least part of the first grains. The conductive layer is on the second grains. The conductive layer and the second grains are isolated by oxygen, and the side of the oxygen away from the first grains is in contact with the conductive layer. In the gate structure of the semiconductor device, the second grains and the conductive layer are not in direct contact, the gate-induced drain leakage current can be reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the continuous development and advancement of semiconductor manufacturing technology, the application range of semiconductor devices has become increasingly wider, and their feature sizes have continued to shrink. Semiconductor devices typically include gate structures, which are used to control other semiconductor devices within the semiconductor device. However, semiconductor devices are often prone to gate-induced drain leakage (GIDL), which can lead to poor performance. Summary of the Invention

[0003] In view of the above problems, embodiments of the present application provide a semiconductor device and a method for manufacturing the same to improve the performance of the semiconductor device.

[0004] According to some embodiments, a first aspect of the present application provides a semiconductor device, comprising: a substrate; a gate trench located in the substrate; a gate dielectric layer located in the substrate and covering the inner surface of the gate trench; a gate structure located on the gate dielectric layer and filling the gate trench, the gate structure comprising a metal layer and a conductive layer; the metal layer comprising: a plurality of first grains; a plurality of second grains located on the first grains, the first grains and the second grains containing the same metal element, and the grain size of the second grains being smaller than the grain size of at least some of the first grains; the conductive layer being located on the second grains; wherein the conductive layer and the second grains are isolated by oxygen, and the oxygen is in contact with the conductive layer on a side away from the first grains.

[0005] The semiconductor device provided by the embodiment of the present application includes a substrate, a gate trench located in the substrate, a gate dielectric layer located in the substrate and covering the inner surface of the gate trench, and a gate structure on the gate dielectric layer and filling the gate trench. The gate structure includes a metal layer and a conductive layer, and the metal layer includes a plurality of first grains and a plurality of second grains located on the first grains. The first grains and the second grains contain the same metal element to ensure the electrical properties of the metal layer. The grain size of the second grains is smaller than the grain size of at least part of the first grains, so as to avoid the grain size of the second grains being too large, which is conducive to the formation of the film layer thereon. The conductive layer and the second grains are isolated by oxygen, and the oxygen contacts the conductive layer on the side away from the first grains, so as to avoid the second grains directly contacting the conductive layer, thereby preventing the conductive layer and the metal layer from reacting during subsequent heat treatment, so as to reduce the gate-induced drain leakage current, thereby improving the electrical characteristics of the gate structure and improving the performance of the semiconductor device.

[0006] According to some embodiments, the second aspect of the present application provides a method for manufacturing a semiconductor device, which includes: providing a substrate, a gate trench being formed in the substrate, and the inner surface of the gate trench being covered with a gate dielectric layer; forming a gate structure, the gate structure being located on the gate dielectric layer and filling the gate trench, the gate structure including a metal layer and a conductive layer; the metal layer including a plurality of first grains, and second grains, the second grains being located on the first grains, the first grains and the second grains containing the same metal element, and the grain size of the second grains being smaller than the grain size of at least part of the first grains; the conductive layer being located on the second grains; the conductive layer and the second grains being isolated by oxygen, and the oxygen being in contact with the conductive layer on the side away from the first grains.

[0007] In the method for manufacturing a semiconductor device provided in an embodiment of the present application, the first crystal grain and the second crystal grain contain the same metal element to ensure the electrical properties of the metal layer. The grain size of the second crystal grain is smaller than the grain size of at least part of the first crystal grain, thereby preventing the grain size of the second crystal grain from being too large and facilitating the formation of a film layer thereon. The conductive layer is isolated from the second crystal grain by oxygen, and the oxygen contacts the conductive layer on the side away from the first crystal grain, thereby preventing the second crystal grain from directly contacting the conductive layer, thereby preventing the conductive layer and the metal layer from reacting during subsequent heat treatment, thereby reducing gate-induced drain leakage current, thereby improving the electrical characteristics of the gate structure and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic structural diagram of a semiconductor device in an embodiment of the present application;

[0009] Figure 2 for Figure 1 A schematic cross-sectional view at A in the middle;

[0010] Figure 3 for Figure 1 Schematic diagram of the cross section at point B;

[0011] Figure 4 for Figure 1 Another cross-sectional diagram at A in the middle;

[0012] Figure 5 A flowchart of a method for manufacturing a semiconductor device in an embodiment of the present application;

[0013] Figure 6 is a schematic diagram of a cross section of a substrate in an embodiment of the present application;

[0014] Figure 7 is a schematic diagram of a cross section after forming a first crystal grain in an embodiment of the present application;

[0015] Figure 8is a schematic diagram of another cross section after forming the first crystal grain in an embodiment of the present application;

[0016] Figure 9 for Figure 8 A partial enlarged view of point D in the middle;

[0017] Figure 10 is a schematic diagram of a cross section after forming a second grain in an embodiment of the present application;

[0018] Figure 11 is a schematic diagram of another cross section after forming the second grain in an embodiment of the present application;

[0019] Figure 12 for Figure 11 A partial enlarged view of point D in the middle;

[0020] Figure 13 is a schematic diagram of a cross section after forming a conductive layer in an embodiment of the present application;

[0021] Figure 14 This is a schematic diagram of another cross section after the conductive layer is formed in an embodiment of the present application.

[0022] Description of reference numerals:

[0023] 10-substrate; 11-gate trench;

[0024] 12-gate dielectric layer; 13-active region;

[0025] 14-isolation structure; 20-metal layer;

[0026] 21-first crystal grain; 22-second crystal grain;

[0027] 23- oxygen; 30- conductive layer;

[0028] 40-metal nitride layer; 50-insulating cap layer. DETAILED DESCRIPTION

[0029] In related art, the metal and polysilicon in the gate structure mix during subsequent heat treatment, forming a metal silicide layer. This increases gate-induced drain leakage current, affecting the performance of the semiconductor device. Therefore, embodiments of the present application provide a semiconductor device and a method for manufacturing the same, utilizing oxygen to isolate the metal layer from the conductive layer, preventing direct contact between the second crystal grain and the conductive layer. This prevents the conductive layer and metal layer from reacting during subsequent heat treatment, thereby reducing gate-induced drain leakage current and improving semiconductor device performance.

[0030] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0031] See Figures 1 to 4 , Figure 1 is a schematic structural diagram of a semiconductor device in an embodiment of the present application; Figure 2 for Figure 1 A schematic cross-sectional view at A in the middle; Figure 3 for Figure 1 Schematic diagram of the cross section at point B; Figure 4 for Figure 1 Another cross-sectional diagram at point A.

[0032] An embodiment of the present application provides a semiconductor device, such as a dynamic random access memory (DRAM). The semiconductor device includes a substrate 10, a gate trench 11, a gate dielectric layer 12, and a gate structure. Substrate 10 can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a silicon carbide substrate, or a gallium nitride substrate.

[0033] The substrate 10 also includes multiple active areas 13 (AA) and isolation structures 14 that isolate the active areas 13. The active areas 13 include source, drain, and channel regions. The isolation structures 14 are used to define the active areas 13 so that the multiple active areas 13 are spaced apart from each other. For example, the isolation structures 14 are shallow trench isolation (STI) structures.

[0034] The substrate 10 is also provided with a gate trench 11. There may be multiple gate trenches 11, which are spaced apart. Exemplarily, the gate trench 11 passes through the active region 13 and the isolation structure 14. The active regions 13 on either side of the gate trench 11 form a source region and a drain region, respectively. The active region 13 at the bottom of the gate trench 11 forms a channel region, with both ends of the channel region connected to the source region and the drain region, respectively.

[0035] The gate dielectric layer 12 is located within the substrate 10 and covers the inner surface of the gate trench 11. The gate dielectric layer 12 contacts the gate trench 11 and conforms to the shape of the gate trench 11, forming a film layer of substantially uniform thickness. The gate dielectric layer 12 does not completely fill the gate trench 11; the gate dielectric layer 12 within the gate trench 11 also forms a groove. The gate dielectric layer 12 can be made of an insulating material, such as silicon oxide.

[0036] Continue reading Figures 1 to 3 The gate structure is located on the gate dielectric layer 12 and fills the gate trench 11. The gate structure fills the bottom of the gate trench 11, and the top surface of the gate structure is lower than the top surface of the substrate 10. The gate structure includes a metal layer 20 and a conductive layer 30. The metal layer 20 includes a plurality of first grains 21 and a plurality of second grains 22, and the second grains 22 are located on the first grains 21.

[0037] In some examples, such as Figure 2 As shown, the grain size of the first grain 21 away from the second grain 22 is smaller than the grain size of the first grain 21 close to the second grain 22. The first grain 21 away from the second grain 22 is closer to the bottom of the gate trench 11, and the bottom of the gate trench 11 is smaller. The grain size of this part of the first grain 21 is smaller and can better fill the bottom of the gate trench 11.

[0038] The grain size of the first grains 21 gradually increases as they approach the second grains 22. The direction closer to the second grains 22 is also the direction away from the bottom of the gate trench 11. The closer to the second grains 22, the larger the grain size of the first grains 21. In this way, the grain size of the plurality of first grains 21 gradually changes, and the transition between the plurality of first grains 21 is good.

[0039] The second grains 22 contain the same metal element as the first grains 21. In some examples, both the first grains 21 and the second grains 22 contain tungsten, resulting in better electrical properties for the metal layer 20. The second grains 22 have a smaller grain size than at least some of the first grains 21, preventing the second grains 22 from being too large. This results in a denser arrangement of the plurality of second grains 22 and better flatness, facilitating the formation of film layers (e.g., the conductive layer 30) thereon.

[0040] Exemplarily, the grain size of the second grains 22 is smaller than the grain size of all the first grains 21. Furthermore, exemplarily, the grain size of the second grains 22 is smaller than the grain size of the first grains 21 near the second grains 22, and larger than the grain size of the first grains 21 away from the second grains 22. Thus, the grain size of the second grains 22 is larger than the grain size of the first grains 21 at the bottom of the gate trench 11, preventing the grain size of the second grains 22 from being too small and facilitating the formation of the second grains 22. Furthermore, the grain size of the second grains 22 is smaller than the grain size of the first grains 21 at the top of the gate trench 11, preventing the grain size of the second grains 22 from being too large and facilitating the formation of the film layer thereon.

[0041] In some specific implementations, a first spacing S is provided between the second die 22 and the isolation structure 14. The size of the first die 21 at a distance from the isolation structure 14 greater than or equal to the second spacing is greater than the size of the second die 22, and the second spacing is half the first spacing S. The size relationship between the first die 21 at a distance from the isolation structure 14 less than the second spacing and the size of the second die 22 is not limited.

[0042] like Figure 3 As shown, there is a first distance between the surfaces of the second die 22 and the isolation structure 14 facing each other. The first distance is as shown in FIG. Figure 3 As shown in S. The first distance of half of the isolation structure 14 is taken as the interface ( Figure 3 As shown in FIG. 4 , the distance between the interface M and the isolation structure 14 is the second distance, and the grain size of the first grain 21 on the side of the interface M away from the isolation structure 14 is larger than the grain size of the second grain 22 .

[0043] Continue reading Figure 2 and Figure 3 , the side of the second grain 22 away from the first grain 21 has oxygen 23, that is, the oxygen 23 is at least located on the second grain 22. For example, see Figure 4 The second crystal grain 22 is surrounded by oxygen 23 to prevent the side of the second crystal grain 22 away from the first crystal grain 21 from contacting other film layers, thereby reducing or preventing the reaction between other film layers and the second crystal grain 22 and ensuring the performance of the metal layer 20. The oxygen 23 refers to oxygen atoms, oxygen molecules, oxygen elements, or other oxygen atoms, which is not limited here.

[0044] Conductive layer 30 is located on second crystal grain 22. For example, conductive layer 30 may be made of polysilicon. Second crystal grain 22 may be elliptical or have other irregular shapes. Conductive layer 30 is isolated from second crystal grain 22 by oxygen 23. Oxygen 23 contacts conductive layer 30 on the side facing away from first crystal grain 21. Isolating second crystal grain 22 from conductive layer 30 by oxygen 23 prevents direct contact between second crystal grain 22 and conductive layer 30, thereby preventing direct contact between metal layer 20 and conductive layer 30. This prevents the formation of metal silicide during subsequent heat treatment, reduces gate-induced drain leakage current, and thus improves the electrical characteristics of the gate structure and enhances the performance of the semiconductor device.

[0045] Continue reading Figure 2 and Figure 3 The semiconductor device further includes a metal nitride layer 40, such as a titanium nitride layer. The metal nitride layer 40 is located between the gate dielectric layer 12 and the metal layer 20 to isolate the gate dielectric layer 12 from the metal layer 20, prevent the metal layer 20 from diffusing into the gate dielectric layer 12, and ensure the performance of the gate dielectric layer 12. The metal nitride layer 40 is also in contact with the conductive layer 30. For example, the conductive layer 30 is also located on the metal nitride layer 40.

[0046] The semiconductor device also includes an insulating cap layer 50 to prevent the top surface of the gate structure from being electrically connected to other film layers, thereby ensuring the performance of the semiconductor device. The insulating cap layer 50 fills the gate trench 11 and is disposed on the side of the conductive layer 30 away from the metal layer 20. The insulating cap layer 50 is located above the conductive layer 30, and the top surface of the insulating cap layer 50 is at least flush with the top surface of the substrate 10. The insulating cap layer 50 can be made of a material such as silicon nitride.

[0047] The semiconductor device in the embodiment of the present application includes a substrate 10, a gate trench 11 located in the substrate 10, a gate dielectric layer 12 located in the substrate 10 and covering the inner surface of the gate trench 11, and a gate structure on the gate dielectric layer 12 and filling the gate trench 11. The gate structure includes a metal layer 20 and a conductive layer 30. The metal layer 20 includes a plurality of first grains 21 and a plurality of second grains 22 located on the first grains 21. The first grains 21 and the second grains 22 contain the same metal elements to ensure the electrical properties of the metal layer 20. The grain size of the second grains 22 is smaller than the grain size of at least part of the first grains 21, so as to avoid the grain size of the second grains 22 being too large, which is conducive to the formation of the film layer thereon. The conductive layer 30 is isolated from the second grains 22 by oxygen 23, and the side of the oxygen 23 away from the first grains 21 is in contact with the conductive layer 30. Oxygen 23 is used to isolate the second crystal grain 22 and the conductive layer 30 to avoid direct contact between the second crystal grain 22 and the conductive layer 30, thereby preventing the conductive layer 30 and the metal layer 20 from reacting during subsequent heat treatment, thereby reducing gate induced drain leakage current, thereby improving the electrical characteristics of the gate structure and enhancing the performance of the semiconductor device.

[0048] The present invention also provides a method for manufacturing a semiconductor device. Figure 5 , Figure 5 Flowchart of a method for manufacturing a semiconductor device in an embodiment of the present application. The manufacturing method may specifically include the following steps:

[0049] Step S100: providing a substrate, wherein a gate trench is formed in the substrate, and an inner surface of the gate trench is covered with a gate dielectric layer.

[0050] See Figure 6 , Figure 6 Schematic diagram of a cross section of a substrate in an embodiment of the present application. Substrate 10 comprises a semiconductor substrate, such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, a silicon carbide substrate, or a gallium nitride substrate. Substrate 10 includes multiple active regions 13 and an isolation structure 14 that isolates active regions 13. Isolation structure 14 is used to define active regions 13 so that multiple active regions 13 are spaced apart from each other. Exemplarily, isolation structure 14 is a shallow trench isolation structure 14.

[0051] A gate trench 11 is formed in the substrate 10, for example, by etching. Multiple gate trenches 11 may be provided, with the multiple gate trenches 11 spaced apart. The gate trenches 11 pass through the active region 13 and the shallow trench isolation structure 14. The active regions 13 on either side of the gate trench 11 serve as the source region and the drain region, respectively. The active region 13 at the bottom of the gate trench 11 forms a channel region, with the two ends of the channel region connected to the source region and the drain region, respectively.

[0052] A gate dielectric layer 12 is formed on the inner surface of the gate trench 11, for example, by thermal process, atomic layer chemical vapor deposition, or in-situ water vapor oxidation. The gate dielectric layer 12 is in contact with the gate trench 11, and the gate dielectric layer 12 is adapted to the shape of the gate trench 11, and the gate dielectric layer 12 forms a film layer of substantially uniform thickness. The gate dielectric layer 12 does not completely fill the gate trench 11, and the gate dielectric layer 12 located in the gate trench 11 also forms a groove shape. The material of the gate dielectric layer 12 can be an insulating material, such as silicon oxide.

[0053] Step S200: forming a gate structure, the gate structure being located on the gate dielectric layer and filling the gate trench, the gate structure comprising a metal layer and a conductive layer; the metal layer comprising a plurality of first grains, and second grains, the second grains being located on the first grains, the first grains and the second grains containing the same metal element, and the grain size of the second grains being smaller than the grain size of at least some of the first grains; the conductive layer being located on the second grains; the conductive layer being isolated from the second grains by oxygen, and the oxygen being in contact with the conductive layer on a side away from the first grains.

[0054] See Figure 2 and Figure 3The gate structure is filled at the bottom of the gate trench 11, and the top surface of the gate structure is lower than the top surface of the substrate 10. The gate structure includes a metal layer 20 and a conductive layer 30. The metal layer 20 includes a plurality of first crystal grains 21 and a plurality of second crystal grains 22, and the second crystal grains 22 are located on the first crystal grains 21.

[0055] In some examples, the grain size of the first grain 21 farther from the second grain 22 is smaller than the grain size of the first grain 21 closer to the second grain 22. The first grain 21 farther from the second grain 22 is closer to the bottom of the gate trench 11, where the bottom of the gate trench 11 is smaller. Therefore, the first grain 21 in this portion has a smaller grain size and can better fill the bottom of the gate trench 11.

[0056] The grain size of the first grains 21 gradually increases as they approach the second grains 22. The direction closer to the second grains 22 is also the direction away from the bottom of the gate trench 11. The closer to the second grains 22, the larger the grain size of the first grains 21. In this way, the grain size of the plurality of first grains 21 gradually changes, and the transition between the plurality of first grains 21 is good.

[0057] The second grains 22 contain the same metal element as the first grains 21. In some examples, both the first grains 21 and the second grains 22 contain tungsten, resulting in better electrical properties for the metal layer 20. The second grains 22 have a smaller grain size than at least some of the first grains 21, preventing the second grains 22 from being too large. This results in a denser arrangement of the plurality of second grains 22 and better flatness, facilitating the formation of film layers (e.g., the conductive layer 30) thereon.

[0058] Exemplarily, the grain size of the second grains 22 is smaller than the grain size of all the first grains 21. Furthermore, exemplarily, the grain size of the second grains 22 is smaller than the grain size of the first grains 21 near the second grains 22, and larger than the grain size of the first grains 21 away from the second grains 22. Thus, the grain size of the second grains 22 is larger than the grain size of the first grains 21 at the bottom of the gate trench 11, preventing the grain size of the second grains 22 from being too small and facilitating the formation of the second grains 22. Furthermore, the grain size of the second grains 22 is smaller than the grain size of the first grains 21 at the top of the gate trench 11, preventing the grain size of the second grains 22 from being too large and facilitating the formation of the film layer thereon.

[0059] In some specific implementations, there is a first spacing S between the second grain 22 and the isolation structure 14, and the grain size of the first grain 21 whose distance from the isolation structure 14 is greater than or equal to the second spacing is larger than the grain size of the second grain 22, wherein the second spacing is half of the first spacing.

[0060] See Figure 3There is a first distance between the surfaces of the second grain 22 and the isolation structure 14 facing each other, and the first distance is as follows: Figure 3 As shown in S. The first distance of half of the isolation structure 14 is taken as the interface ( Figure 3 The distance between the interface M and the isolation structure 14 is the second distance. The grain size of the first grain 21 located on the side of the interface away from the isolation structure 14 is larger than the grain size of the second grain 22.

[0061] Continue reading Figure 2 and Figure 3 , the side of the second grain 22 away from the first grain 21 has oxygen 23, that is, the oxygen 23 is at least located on the second grain 22. For example, Figure 4 As shown, the second crystal grain 22 is surrounded by oxygen 23 to prevent the side of the second crystal grain 22 away from the first crystal grain 21 from contacting other film layers, thereby reducing or preventing other film layers from reacting with the second crystal grain 22 and ensuring the performance of the metal layer 20.

[0062] Conductive layer 30 is located on second crystal grain 22. For example, conductive layer 30 may be made of polysilicon. Conductive layer 30 is isolated from second crystal grain 22 by oxygen 23. Oxygen 23 contacts conductive layer 30 on the side facing away from first crystal grain 21. Isolating second crystal grain 22 from conductive layer 30 by oxygen 23 prevents direct contact between second crystal grain 22 and conductive layer 30. This, in turn, prevents direct contact between metal layer 20 and conductive layer 30. This prevents the formation of metal silicide during subsequent heat treatment, reduces gate-induced drain leakage current, and thus improves the electrical characteristics of the gate structure and enhances the performance of the semiconductor device.

[0063] See Figures 6 to 14 , Figure 7 is a schematic diagram of a cross section after forming a first crystal grain in an embodiment of the present application; Figure 8 is a schematic diagram of another cross section after forming the first crystal grain in an embodiment of the present application; Figure 9 for Figure 8 A partial enlarged view of point D in the middle; Figure 10 is a schematic diagram of a cross section after forming a second grain in an embodiment of the present application; Figure 11 is a schematic diagram of another cross section after forming the second grain in the embodiment of the present application, Figure 12 for Figure 11 A partial enlarged view of point D in the middle; Figure 13 is a schematic diagram of a cross section after forming a conductive layer in an embodiment of the present application; Figure 14 Schematic diagram of another cross section after forming the conductive layer in the embodiment of the present application. Figure 8 and Figure 11 Only the grain size of a part of the area is shown.

[0064] In some possible implementations, forming a gate structure includes: depositing a plurality of first grains 21 in the gate trench 11; performing an oxygen treatment process on the surfaces of the plurality of first grains 21, for example, continuously introducing oxygen into the surfaces of the plurality of first grains 21, forming second grains 22 away from the first grains 21 at the bottom of the gate trench 11, and forming oxygen 23 on the second grains 22; and depositing a conductive layer 30 in the gate trench 11, the conductive layer 30 being in contact with the oxygen 23.

[0065] The first crystal grains 21 away from the bottom of the gate trench 11 are treated with oxygen 23 gas to form second crystal grains 22, and oxygen 23 is formed on the second crystal grains 22. This allows the formation of the second crystal grains 22 and the formation of oxygen 23 to be completed using the same process, reducing the steps of the manufacturing method and facilitating the guarantee that the second crystal grains 22 and the first crystal grains 21 contain the same metal elements, as well as the grain sizes of the second crystal grains 22 and the first crystal grains 21.

[0066] For some examples, see Figure 13 、 Figure 14 、 Figure 2 and Figure 3 After forming the gate structure, the process further includes forming an insulating capping layer 50, which fills the gate trench 11 and is disposed on the side of the conductive layer 30 away from the metal layer 20. The insulating capping layer 50 is located above the conductive layer 30 and is made of a material such as silicon nitride. The top surface of the insulating capping layer 50 is at least flush with the top surface of the substrate 10 to prevent electrical connection between the top surface of the gate structure and other film layers, thereby ensuring the performance of the semiconductor device. The insulating capping layer 50 can be formed by processes such as chemical vapor deposition and atomic layer deposition.

[0067] In some examples, before forming the gate structure, the process further includes forming a metal nitride layer 40, which is located between the gate dielectric layer 12 and the metal layer 20. The metal nitride layer 40 isolates the gate dielectric layer 12 from the metal layer 20, preventing the metal layer 20 from diffusing into the gate dielectric layer 12 and ensuring the performance of the gate dielectric layer 12. The metal nitride layer 40 is, for example, a titanium nitride layer.

[0068] The metal nitride layer 40 covers a portion of the surface of the gate dielectric layer 12. The metal nitride layer 40 is formed in a trench shape and is located at the bottom of the gate trench 11. The metal nitride can be formed by deposition and etching back. The metal layer 20 is located in the space enclosed by the metal nitride layer 40. The conductive layer 30 is formed on the metal layer 20 and the metal nitride layer 40. Furthermore, an insulating cap layer 50 is formed on the conductive layer 30.

[0069] The manufacturing method of the semiconductor device in the embodiment of the present application includes: providing a substrate 10, a gate trench 11 is formed in the substrate 10, the inner surface of the gate trench 11 is covered with a gate dielectric layer 12, and a gate structure is formed, the gate structure is located on the gate dielectric layer 12 and fills the gate trench 11. The gate structure includes a metal layer 20 and a conductive layer 30, the metal layer 20 includes a plurality of first grains 21, and a plurality of second grains 22 located on the first grains 21. The first grains 21 and the second grains 22 contain the same metal elements to ensure the electrical properties of the metal layer 20. The grain size of the second grains 22 is smaller than the grain size of at least part of the first grains 21, so as to avoid the grain size of the second grains 22 being too large, which is conducive to the formation of the film layer thereon. The conductive layer 30 is isolated from the second grains 22 by oxygen 23, and the oxygen 23 is in contact with the conductive layer 30 on the side away from the first grains 21. Oxygen 23 is used to isolate the second crystal grain 22 and the conductive layer 30 to avoid direct contact between the second crystal grain 22 and the conductive layer 30, thereby preventing the conductive layer 30 and the metal layer 20 from reacting during subsequent heat treatment, thereby reducing gate induced drain leakage current, thereby improving the electrical characteristics of the gate structure and enhancing the performance of the semiconductor device.

[0070] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; a gate trench located in the substrate; a gate dielectric layer, located in the substrate and covering the inner surface of the gate trench; a gate structure, located on the gate dielectric layer and filling the gate trench, the gate structure comprising a metal layer and a conductive layer; The metal layer comprises: a plurality of first dies; a plurality of second crystal grains located on the first crystal grains, wherein the first crystal grains and the second crystal grains contain the same metal element, and the grain size of the second crystal grains is smaller than the grain size of at least some of the first crystal grains; The conductive layer is located on the second crystal grain; The conductive layer is isolated from the second crystal grain by oxygen, and a side of the oxygen away from the first crystal grain is in contact with the conductive layer.

2. The semiconductor device according to claim 1, wherein The second grains are surrounded by the oxygen.

3. The semiconductor device according to claim 1, wherein The grain size of the first grain far away from the second grain is smaller than the grain size of the first grain close to the second grain.

4. The semiconductor device according to claim 3, wherein The grain size of the first grain gradually increases in a direction approaching the second grain.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The grain size of the second grain is smaller than the grain size of the first grain close to the second grain, and larger than the grain size of the first grain far from the second grain.

6. The semiconductor device according to claim 5, wherein The substrate further includes a plurality of active regions and an isolation structure isolating the active regions, and the gate trench passes through the active regions and the isolation structure; There is a first spacing between the second grain and the isolation structure. The distance from the isolation structure is greater than or equal to the grain size of the first grain at the second spacing, and greater than the grain size of the second grain. The second spacing is half of the first spacing.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that: The first crystal grains and the second crystal grains both contain tungsten elements, and the conductive layer is made of polysilicon.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that: A metal nitride layer is also included, and the metal nitride layer is located between the gate dielectric layer and the metal layer.

9. The semiconductor device according to any one of claims 1 to 4, characterized in that: It also includes an insulating capping layer, which fills the gate trench and is arranged on a side of the conductive layer away from the metal layer.

10. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, wherein a gate trench is formed in the substrate, and the inner surface of the gate trench is covered with a gate dielectric layer; A gate structure is formed, the gate structure is located on the gate dielectric layer and fills the gate trench, the gate structure includes a metal layer and a conductive layer; the metal layer includes a plurality of first grains, and second grains, the second grains are located on the first grains, the first grains and the second grains contain the same metal element, and the grain size of the second grains is smaller than the grain size of at least some of the first grains; the conductive layer is located on the second grains; the conductive layer and the second grains are isolated by oxygen, and the oxygen is in contact with the conductive layer on a side away from the first grains.

11. The manufacturing method according to claim 10, characterized in that: The first grains away from the bottom of the gate trench are treated with oxygen to form the second grains, and the oxygen is formed on the second grains.

12. The manufacturing method according to claim 10, characterized in that: The second crystal grains are surrounded by the oxygen.

13. The manufacturing method according to claim 10, characterized in that: The grain size of the first grain far away from the second grain is smaller than the grain size of the first grain close to the second grain.

14. The manufacturing method according to claim 13, characterized in that: The grain size of the first grain gradually increases in a direction approaching the second grain.

15. The production method according to any one of claims 10 to 14, characterized in that: The grain size of the second grain is smaller than the grain size of the first grain close to the second grain, and larger than the grain size of the first grain far from the second grain.

16. The manufacturing method according to claim 15, characterized in that: The substrate further includes a plurality of active regions and an isolation structure isolating the active regions, and the gate trench passes through at least one of the active regions; There is a first spacing between the second grain and the isolation structure. The distance from the isolation structure is greater than or equal to the grain size of the first grain at the second spacing, and greater than the grain size of the second grain. The second spacing is half of the first spacing.

17. The production method according to any one of claims 10 to 14, characterized in that: The first crystal grains and the second crystal grains both contain tungsten elements, and the conductive layer is made of polysilicon.

18. The production method according to any one of claims 10 to 14, characterized in that: Also includes: A metal nitride layer is formed, wherein the metal nitride layer is located between the gate dielectric layer and the metal layer.

19. The production method according to any one of claims 10 to 14, characterized in that: Also includes: An insulating capping layer is formed, where the insulating capping layer fills the gate trench and is arranged on a side of the conductive layer away from the metal layer.

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