Three-dimensional memory device with segmented drain selection

Abstract

A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain select gate (DSG) cut-out structure extending through the dielectric layer. The DSG cut-out structure includes a second material different from the first material.

Description

[0001] This application is a divisional application for a patent with an application date of December 13, 2021, application number 202180004959.0, and invention name “Three-dimensional storage device with segmented drain selection gate line and method for forming the same”. Background Art

[0002] The present disclosure relates to memory devices and methods for forming memory devices.

[0003] Planar memory cells are shrunk to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit.

[0004] Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral circuits for facilitating the operation of the memory array. Summary of the invention

[0005] In one aspect, a memory device is disclosed. The memory device includes a stacked structure on a substrate, a channel structure extending in the stacked structure, and a dielectric layer on the channel structure. The dielectric layer includes a first material. The memory device may also include a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

[0006] In another aspect, a storage system is disclosed. The storage system includes a storage device configured to store data. The storage device includes a stacked structure above a substrate, a channel structure extending in the stacked structure, a dielectric layer above the channel structure, and a DSG cut structure extending through the dielectric layer, wherein the dielectric layer has a first material. The DSG cut structure includes a second material different from the first material. The storage system also includes a storage controller coupled to the storage device and configured to control the operation of the channel structure.

[0007] In yet another aspect, a method for forming a memory device is disclosed. The method includes: forming a stacked structure on a substrate, forming a channel structure extending in the stacked structure, depositing a first material to form a dielectric layer on the channel structure, and patterning the dielectric layer and the stacked structure to form an opening, the opening passing through the dielectric layer and contacting the conductive layer in the top of the stacked structure. The method may also include depositing a second material into the opening to form a DSG cut structure. The second material is different from the first material. The method may also include forming a contact in the dielectric layer that contacts the channel structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and, together with the description, serve to further explain the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0009] Figure 1A A top view of an exemplary 3D memory device according to some aspects of the present disclosure is shown.

[0010] Figure 1B A cross-sectional view of an exemplary 3D memory device according to some aspects of the present disclosure is shown.

[0011] Figure 1C-1E Each shows an exemplary DSG notch structure in a 3D memory device according to some aspects of the present disclosure.

[0012] Figures 2A-2H Cross-sections of exemplary 3D memory devices at different stages of a manufacturing process are shown according to some aspects of the present disclosure.

[0013] Figure 3 A flow chart of an exemplary method for forming a 3D memory device according to some aspects of the present disclosure is shown.

[0014] Figure 4 A block diagram of an exemplary system having a storage device according to some aspects of the present disclosure is shown.

[0015] Figure 5A A diagram showing an exemplary memory card having a storage device according to some aspects of the present disclosure is shown.

[0016] Figure 5B A diagram of an exemplary solid-state drive (SSD) having a storage device according to some aspects of the present disclosure is shown.

[0017] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0018] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the present disclosure may also be used in a variety of other applications. Functions and structural features as described in the present disclosure may be combined, adjusted, and modified with one another in a manner not specifically depicted in the accompanying drawings, so that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0019] In general, terms may be understood, at least in part, based on their use in context. For example, depending, at least in part, on the context, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending, at least in part, on the context, terms such as "a" or "the" may likewise be understood to convey singular usage or to convey plural usage. Additionally, also depending, at least in part, on the context, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described.

[0020] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest sense, so that “on” not only means being “directly on” something, but also includes being “on” something and having intervening features or layers therebetween, and “above” or “over” not only means being “above” or “over” something, but also includes being “above” or “over” something and having no intervening features or layers therebetween (i.e., directly on something).

[0021] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature relative to another (or multiple) element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0022] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire lower or upper structure, or may have a range that is less than the range of the lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of a continuous structure, or between any pair of horizontal planes at the top surface and the bottom surface of a continuous structure. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, one or more layers may be included therein, and / or one or more layers may be present thereon, above and / or below. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (forming interconnects and / or via contacts therein) and one or more dielectric layers.

[0023] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0024] As used herein, the term "3D memory device" refers to a semiconductor device having a vertically oriented memory cell transistor string (referred to herein as a "memory string", such as a NAND memory string) on ​​a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate.

[0025] In some 3D memory devices (e.g., 3D NAND memory devices), memory cells are formed in a functional channel structure that extends in a stacked structure of interlaced stacked conductive layers and stacked dielectric layers. With the rising demand for higher capacity, the channel structure now has a more compact lateral arrangement to increase the number / density of memory cells, thereby increasing the capacity of the 3D memory device. One way to increase capacity is to allocate more functional channel structures in the memory blocks of the 3D memory device. For example, instead of 9 rows, 12 rows or 16 rows of functional channel structures may be arranged in the memory block. Additionally or alternatively, another way is to reduce the number of dummy channel structures to form more functional channel structures in the memory block. Typically, memory cells are not formed in the dummy channel structure.

[0026] In order to operate a 3D memory device, the memory cells are divided into memory blocks, which are further divided into strings. For example, a drain select gate (DSG) cut structure is usually formed between adjacent strings in a memory block to disconnect the DSGs in different strings. The string can then be selected by the corresponding DSG in various operations. The DSG cut structure is usually formed above the dummy channel structure. In order to reduce the number of dummy channel structures, a dummy channel structure is not formed, and the DSG cut structure is formed between the strings while being located above the functional channel structure. The DSG cut structure contacts one or more DSGs of a row of functional channel structures and a string, so that the DSGs of adjacent strings are disconnected. In the vertical direction, the DSG cut structure partially overlaps the channel structure (e.g., the drain of the channel structure).

[0027] After forming the DSG cut structure in the stacked structure, a contact, such as a channel contact, is formed above the functional channel structure to contact the functional channel structure. During operation, the contact can apply a drain voltage to the functional channel structure. The contact is typically formed in a dielectric layer above the functional channel structure. The dielectric layer in contact with the functional channel structure and the DSG cut structure typically have the same dielectric material, such as silicon oxide. In order to form the contact, an opening is first formed in the dielectric layer to expose the drain below the functional channel structure, and a conductive material is deposited in the opening. In the vertical direction, the opening typically partially overlaps the DSG cut structure. Because the dielectric layer and the DSG cut structure have the same material, the etchant used to form the opening often over-etches the DSG cut structure, thereby creating an undesirable etched area in the functional channel structure. Conductive material may then be deposited in the undesirable etched area, leading to problems such as short circuits and / or leakage.

[0028] The present disclosure provides a 3D memory device having a DSG cut structure including an etch stop material and a manufacturing process for forming the DSG cut structure. The etch stop material is a material different from the dielectric layer above the channel structure. For example, the dielectric layer includes silicon oxide, and the etch stop material includes silicon nitride. In some embodiments, the etch stop material is composed of silicon nitride. In some embodiments, the etch stop material includes silicon nitride, silicon oxide and / or an air gap. During the formation of the opening for forming the contact, it is desired that the etching rate of the etch stop material is lower than the etching rate of the dielectric layer. The bottom surface of the opening can therefore stop on the DSG cut structure instead of extending into the channel structure. The channel structure in contact with the DSG cut structure is therefore not susceptible to over-etching during the formation of the contact. Short circuits and / or leakage are therefore less likely to occur in the 3D memory device disclosed herein.

[0029] Figure 1A A top view of a 3D storage device 100 according to some aspects of the present disclosure is shown. Figure 1B 1 shows a cross-sectional view of a 3D memory device 100 along the AA' direction according to some aspects of the present disclosure. For illustration purposes, Figure 1B Only part of the 3D storage device is depicted. Figure 1A and Figure 1B .

[0030] The 3D memory device 100 may include a substrate 110, which may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In some embodiments, the substrate 110 is a thinned substrate (e.g., a semiconductor layer) that is thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. Note that in Figure 1A and Figure 1B , includes an x-axis, a y-axis, and a z-axis to further illustrate the spatial relationship of the components in the 3D storage device 100. The substrate 110 of the 3D storage device 100 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction and the y-direction (i.e., the lateral direction). As used herein, when a substrate (e.g., substrate 110) of a 3D storage device (e.g., 3D storage device 100) is located in the lowest plane of the 3D storage device in the z-direction (i.e., the vertical direction), whether one component (e.g., a layer or a device) of the 3D storage device is "on", "above", or "below" another component (e.g., a layer or a device) in the z-direction is determined relative to the substrate of the 3D storage device. The same concept is used throughout this disclosure to describe spatial relationships.

[0031] The 3D memory device 100 may be part of a monolithic 3D memory device. The term "monolithic" refers to the fact that the components of the 3D memory device (e.g., peripheral devices and memory array devices) are formed on a single substrate. For monolithic 3D memory devices, manufacturing encounters additional limitations due to the wrapping of peripheral device processing and memory array device processing. For example, the manufacturing of memory array devices (e.g., NAND memory strings) is limited by the thermal budget associated with peripheral devices that have been or will be formed on the same substrate.

[0032] Alternatively, the 3D memory device 100 may be part of a non-monolithic 3D memory device, in which components (eg, peripheral devices and memory array devices) may be separately formed on different substrates and then bonded in, for example, a face-to-face manner. In some embodiments, the memory array device substrate (e.g., substrate 110 remains as the substrate of the bonded non-monolithic 3D memory device, and the peripheral devices (e.g., including any suitable digital, analog, and / or mixed-signal peripheral circuits for facilitating the operation of the 3D memory device 100, such as page buffers, decoders, and latches; not shown) are flipped and face down toward the memory array device (e.g., NAND memory strings) for hybrid bonding. It should be understood that in some embodiments, the memory array device substrate (e.g., substrate 110) is flipped and faces down toward the peripheral devices (not shown) for hybrid bonding, such that in the bonded non-monolithic 3D memory device, the memory array device is located above the peripheral devices. The memory array device substrate (e.g., substrate 110) can be a thinned substrate (which is not the substrate of the bonded non-monolithic 3D memory device), and the back end of line (BEOL) interconnects of the non-monolithic 3D memory device can be formed on the back side of the thinned memory array device substrate.

[0033] In some embodiments, the 3D memory device 100 is a NAND flash memory device, in which memory cells are provided in the form of an array of NAND memory strings (eg, channel structures), each NAND memory string extending vertically above the substrate 110 . Figure 1A A plan view of a portion of a memory block 101 in a 3D memory device 100 according to some aspects of the present disclosure is shown. The memory block 101 may include a plurality of memory cells (not shown) arranged between a pair of slit structures 102. The memory cells arranged in an array are formed in a plurality of channel structures 108 between the slit structures 102. The 3D memory device 100 may also include one or more DSG cut structures 106, each DSG cut structure 106 being located between a pair of adjacent strings 104.

[0034] like Figure 1BAs shown, the 3D memory device 100 may include a stacked structure 130, and a plurality of channel structures 108 extending vertically through the stacked structure 130 in the z-direction. The stacked structure 130 may include interlaced stacked conductive layers and stacked dielectric layers 118 above the substrate 110. The stacked conductive layers may include, for example, one or more DSG lines 116 on the top portion of the stacked structure 130, and a plurality of control gate lines (e.g., word lines) 120. For example, the DSG line 116 may be the top stacked conductive layer, and the number of DSG lines may be 1, 2, 3, 4, etc. The number of stacked conductive layers may be any suitable positive number, such as 16, 32, 64, 96, 128, 256, etc. The stacked conductive layers (DSG lines 116 and word lines 120) may have conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The stacked dielectric layer 118 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0035] The intersection of the control gate line 120 and the channel structure 108 forms a memory cell. The 3D memory device 100 may include a plurality of channel structures 108 (e.g., an array) located between the gap structures 102 in the y direction. In some embodiments, the channel structures 108 may be arranged in rows, each row extending in the x direction, and a plurality of rows arranged in the y direction. In some embodiments, the memory block 101 includes 4×M rows of channel structures 108 arranged in the y direction, where M is a positive integer. For example, the memory block 101 may include 8 rows, 12 rows, 16 rows, etc. In some embodiments, as Figure 1A As shown, the memory block 101 includes 16 rows of channel structures 108 .

[0036] The channel structure 108 may include a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a storage film). In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon. In some embodiments, the storage film is a composite layer including a tunneling layer, a storage layer (also referred to as a "charge trap layer"), and a barrier layer. In some embodiments, the remaining space of the channel structure 108 may be partially or completely filled with a filling layer, which includes a dielectric material such as silicon oxide. The channel structure 108 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the filling layer, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO).

[0037] In some embodiments, the channel structure 108 may further include a semiconductor plug in the lower portion (e.g., at the lower end) of the channel structure 108. As used herein, when the substrate 110 is positioned in the lowest plane of the 3D memory device 100, the "upper end" of the component (e.g., the channel structure 108) is the end farther from the substrate 110 in the z direction, and the "lower end" of the component (e.g., the channel structure 108) is the end closer to the substrate 110 in the z direction. The semiconductor plug may include a semiconductor material, such as silicon, which may be epitaxially grown from the substrate 110 in any suitable direction or deposited on the substrate 110. It should be understood that in some embodiments, the semiconductor plug includes single crystal silicon, the same material as the substrate 110. In other words, the semiconductor plug may include an epitaxially grown semiconductor layer that is the same material as the substrate 110. In some embodiments, a portion of the semiconductor plug is above the top surface of the substrate 110 and in contact with the semiconductor channel. The semiconductor plug may serve as a channel controlled by the source select gate of the channel structure 108. It should be understood that in some embodiments, the 3D memory device 100 does not include a semiconductor plug, such as Figure 1B shown.

[0038] In some embodiments, the channel structure 108 further includes a channel plug in an upper portion (e.g., at an upper end) of the channel structure 108. The channel plug may be in contact with the upper end of the semiconductor channel. The channel plug may include a semiconductor material (e.g., polysilicon). By covering the upper end of the channel structure 108 during the manufacture of the 3D memory device 100, the channel plug may be used as an etch stop layer to prevent etching of a dielectric filled in the channel structure 108, such as silicon oxide and silicon nitride. In some embodiments, the channel plug also serves as a drain of the channel structure 108.

[0039] The slit structures 102 may each extend vertically (e.g., in the z direction) and laterally (e.g., in the x direction) in the stacked structure 130. The slit structures 102 may also be referred to as gate slits. In some embodiments, a source contact structure may be formed as part of an array common source (ACS) that applies a source voltage on the channel structure 108. The slit structure 102 may contact the substrate 110. In some embodiments, the source contact structures in the slit structures 102 may each include a dielectric spacer and a source contact in the dielectric spacer. The source contact may be conductively connected to the substrate 110. The source contact may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The dielectric spacer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0040] The 3D memory device 100 may also include a dielectric layer 114 on and in contact with the channel structure 108 (e.g., a channel plug of the channel structure 108), and a contact 112 in the dielectric layer 114. The contact 112 may be in contact with the channel structure 108 (e.g., a channel plug / drain of the channel structure 108). The dielectric layer 114 may include a single layer or multiple layers, and may include one or more dielectric materials. In some embodiments, the dielectric layer 114 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. For example, the dielectric layer 114 may include a silicon nitride layer sandwiched between a pair of silicon oxide layers. In some embodiments, the channel plug (e.g., drain) of the channel structure 108 is in contact with the silicon oxide layer. In some embodiments, the contact 112 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The contact 112 may apply a drain voltage across the channel structure 108 during operation.

[0041] One or more DSG cut structures 106 may each extend vertically (e.g., in the z-direction) and laterally (e.g., in the x-direction) in the stacked structure 130. The DSG cut structures 106 may each be located between adjacent strings 104 of the memory block 101. For example, the memory block 101 may include 16 rows of channel structures 108, which are divided into four strings 104 by three DSG cut structures 106. Figure 1A and Figure 1B As shown, the DSG cut structure 106 can contact multiple channel structures 108 in the first row of each string 104. The channel structure 108 in contact with the DSG cut structure 106 can be a functional channel structure in which a memory cell is formed. The DSG cut structure 106 can also contact one or more stacked conductive layers in one of the adjacent strings 104, so that these stacked conductive layers disconnect one string 104 from another string 104 / insulate one string 104 from another string 104. The stacked conductive layers in contact with the DSG cut structure 106 can be referred to as DSG lines 116. The portion of the DSG line 116 in each string 104 can form the DSG of the corresponding string 104, and a gate selection voltage can be applied to the DSG for selecting the corresponding string 104 in operation. In some embodiments, depending on the design, the number of DSG lines 116 can be 1, 2, 3, 4, or other suitable positive numbers. In some embodiments, the DSG in each string 104 can be located at the top portion of the stack structure 130 and can be referred to as a top select gate (TSG). In some embodiments, as Figure 1A As shown, the DSG cut structure 106 is in contact with two adjacent rows of channel structures 108. For ease of explanation, in this disclosure, as an example, the DSG cut structure is depicted as being in contact with Figure 1B-1E and Figures 2A-2H A channel structure contact in the.

[0042] The DSG cut structure 106 can include a different material than the dielectric layer 114. In some embodiments, the DSG cut structure 106 can include a dielectric material that can be used as an etch stop layer in the formation of the contact 112. In some embodiments, an etchant used to form an opening in which the contact 112 is located has a higher etch rate on the dielectric layer 114 than on the DSG cut structure 106. For example, the etch selectivity of the dielectric layer 114 relative to the DSG cut structure 106 can be greater than 1. In some embodiments, the dielectric layer 114 includes silicon oxide, and the DSG cut structure 106 includes silicon nitride.

[0043] Figure 1C-1E Each shows the structure of the DSG cutout structure 106 according to some aspects of the present disclosure. In one example, Figure 1CAs shown, the DSG cut structure 106 may include silicon nitride. In some embodiments, the DSG cut structure 106 includes an etch stop layer, such as a silicon nitride layer. In another example, Figure 1D As shown, the DSG cut structure 106 may include a liner layer 106-1 and an etch stop layer 106-2 surrounded by and in contact with the liner layer 106-1. The liner layer 106-1 may be in contact with the channel structure 108 and the DSG line 116. The top surface of the etch stop layer 106-2 may be coplanar with the top surface of the dielectric layer 114. In some embodiments, the liner layer 106-1 includes silicon oxide, and the etch stop layer 106-2 includes silicon nitride. In another example, as shown in FIG. Figure 1E As shown, the DSG cut structure 106 may include a liner layer 106-1, an etch stop layer 106-2 surrounded by and in contact with the liner layer 106-1, and a filler layer 106-3 surrounded by and in contact with the etch stop layer 106-2 (e.g., in the etch stop layer 106-2). The material of the filler layer 106-3 may be different from the material of the etch stop layer 106-2. For example, the filler layer 106-3 may include silicon oxide, silicon oxynitride, or an air gap. In some embodiments, the filler layer 106-3 includes an air gap. Figure 1D and Figure 1E In the example shown, the thickness of the liner layer 106 - 1 may be in a range between 2 nm and 8 nm (eg, 2 nm, 3 nm, 5 nm, 7 nm, 8 nm). For example, the thickness of the liner layer 106 - 1 may be approximately 5 nm.

[0044] Figures 2A-2H A cross section of a 3D memory device 200 is shown at different stages of a manufacturing process according to some aspects of the present disclosure. Figure 3 1 is a flow chart of an exemplary method 300 for forming a 3D memory device 200 according to some aspects of the present disclosure. The 3D memory device 200 may be an example of the 3D memory device 100. For the purpose of illustration, the 3D memory device 200 and the 3D memory device 100 will be discussed together. Figures 2A-2H and method 300. It will be appreciated that the operations shown in method 300 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in different order. Figures 2A-2H and Figure 3 Execute in the order shown.

[0045] The method 300 begins at operation 302 , where a stack structure is formed over a substrate and a channel structure is formed in the stack structure. Figure 2A The corresponding structure is shown.

[0046] like Figure 2AAs shown, stack structure 230 is formed over a substrate (not shown), and channel structure 208 may be formed to extend vertically in stack structure 230. Stack structure 230 may include multiple stacked conductive layers (e.g., DSG lines 216 and control gate lines 220) interleaved with multiple stacked dielectric layers 218.

[0047] To form the stacked structure 230, a plurality of first material layers and a plurality of second material layers are deposited on the substrate to be stacked above the substrate. In the "gate last" process, a dielectric stack (not shown) having a plurality of alternating stacked dielectric layers and stacked sacrificial layers may be formed above the substrate. The stacked dielectric layers and the stacked sacrificial layers may form a plurality of stacked dielectric / sacrificial layer pairs above the substrate. A gate replacement process may then be performed to form a stacked conductive layer in the stacked structure 230. In some embodiments, the substrate may include a silicon substrate. The stacked dielectric layers and the stacked sacrificial layers may include different materials. In some embodiments, each stacked dielectric layer may include a silicon oxide layer, and each stacked sacrificial layer may include a silicon nitride layer. The dielectric stack may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, a pad oxide layer (not shown) is formed between the substrate and the dielectric stack by depositing a dielectric material such as silicon oxide on the substrate.

[0048] In a "gate first" process, a stack of staggered stacked conductive layers and stacked dielectric layers can be formed on a substrate, and no gate replacement process is required. Each stacked conductive layer may include a polysilicon layer, and each stacked dielectric layer may include a silicon oxide layer. The stack may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, the staggered first material layer and the second material layer may undergo a trimming process, wherein the first material layer and the second material layer are repeatedly patterned to form a stepped structure on one or more sides of the stacked structure 230. The trimming process may include photolithography and etching processes (e.g., wet etching and / or dry etching).

[0049] The channel structure 208 may be formed to extend through the stacked structure 230 (e.g., a dielectric stack) in the z-direction. The channel structure 208 may include a channel plug 215 (e.g., a drain of the channel structure 208) at a top portion of the channel structure 208 (or the stacked structure 230). The channel plug 215 may include polysilicon and / or metal and may be subsequently conductively connected to a contact that applies a drain voltage on the channel structure 208. In some embodiments, an etching process may be performed to form a plurality of channel holes extending vertically through the staggered stacked dielectric / sacrificial layer pairs. In some embodiments, the manufacturing process for forming the channel holes may include wet etching and / or dry etching, such as deep reactive ion etching (DRIE). In some embodiments, the channel holes may further extend into the top portion of the substrate. After forming the channel holes, in some embodiments, an epitaxial operation, such as a selective epitaxial growth operation, may be performed to form a semiconductor plug at the bottom of the channel holes. A storage film including a tunneling layer, a storage layer, a barrier layer, and a semiconductor channel may be formed in the channel hole. Optionally, a filling layer may be formed in the channel hole. In some embodiments, the channel structure 208 may not include a semiconductor plug. The deposition of the storage film, the semiconductor channel, and the filling layer may include any suitable thin film deposition process, such as CVD, PVD, ALD, or any combination thereof. The deposition of the channel plug 215 may include CVD, PVD, ALD, electroplating, chemical plating, or any combination thereof.

[0050] A plurality of gate slits (not shown) may be formed extending through the stack structure 230 in the z-direction. Return to Reference Figure 1A , wherein the gate slit forming the source contact structure may extend laterally in the x-direction. The gate slit may contact or extend into the top portion of the substrate. In some embodiments, the manufacturing process for forming the gate slit may include wet etching and / or dry etching, such as deep reactive ion etching (DRIE).

[0051] In the gate-last process, an anisotropic etching process may be performed to remove the stacked sacrificial layer and form a plurality of lateral recesses. One or more thin film deposition processes such as CVD, PVD, and / or ALD may be performed to form a plurality of stacked conductive layers in the lateral recesses. In some embodiments, the stacked conductive layers include W.

[0052] A source contact structure may then be formed in each gate gap (e.g., referring back to source contact structure 102). The source contact structure may include a dielectric spacer (e.g., silicon oxide) and a source contact (e.g., W) in the dielectric spacer. The formation of the dielectric spacer may include one or more thin film deposition processes, such as CVD, PVD, and / or ALD. The formation of the source contact may include CVD, PVD, ALD, electroplating, chemical plating, or any combination thereof.

[0053] The method 300 proceeds to operation 304 where a first material is deposited to form a dielectric layer over the channel structure. Figure 2A The corresponding structure is shown.

[0054] like Figure 2A As shown, after forming the stacked structure 230 and the channel structure 208, a dielectric layer 214 in contact with the channel structure 208 is formed on the channel structure 208. The formation of the dielectric layer 214 may include the deposition of a first material (e.g., silicon oxide). In some embodiments, the dielectric layer 214 having a single layer or multiple layers includes silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the dielectric layer 214 includes a silicon nitride layer sandwiched between a pair of silicon oxide layers. In some embodiments, the channel structure 208 (e.g., the drain of the channel structure 208) is in contact with the silicon oxide layer as part of the dielectric layer 214. The formation of the dielectric layer 214 may include one or more thin film deposition processes, such as CVD, PVD, and / or ALD.

[0055] The method 300 proceeds to operation 306 in which the dielectric layer and the stacked structure are patterned to form an opening through the dielectric layer and in contact with the one or more stacked conductive layers at a top portion of the stacked structure. Figure 2B The corresponding structure is shown.

[0056] like Figure 2B As shown, after forming the dielectric layer 214, an opening 222 is formed through the dielectric layer 214 and into the stacked structure 230. The opening 222 may contact the top portion of the channel structure 208 and contact one or more stacked conductive layers at the top portion of the stacked structure 230. For example, in the xy plane, the opening 222 may overlap the channel structure 208 and the one or more stacked conductive layers. The opening 222 may disconnect the one or more stacked conductive layers from the channel structure 208. At least a portion of the channel plug 215 remains intact for subsequent conductive connection with the contact. In some embodiments, the opening 222 is located between the channel structure 208 and the one or more stacked conductive layers, and the bottom surface of the opening 222 may be below the bottom surface of the one or more stacked conductive layers. The number of stacked conductive layers disconnected by the opening 222 may be 1, 2, 3, 4, etc. The disconnected stacked conductive layers may form a DSG line 216, and the stacked conductive layers below the DSG line 216 may include a control gate line 220. In some embodiments, the formation of the opening 222 includes a photolithography process and an etching process (eg, wet etching and / or dry etching).

[0057] The method 300 proceeds to operation 308 where a second material is deposited into the opening to form a DSG notch structure. Figure 2C-2E The corresponding structure is shown.

[0058] After forming the opening 222, a second material may be deposited into the opening 222 to form a DSG cut structure. The second material may include silicon nitride, which may be used as an etch stop material in subsequent etching of the dielectric layer 214. In some embodiments, the second material also includes other non-conductive materials, such as other dielectric materials and / or air gaps. In some embodiments, the second material is composed of silicon nitride, and the deposition of the second material may include one or more thin film deposition processes, such as CVD, PVD, and / or ALD. A planarization process, such as chemical mechanical polishing (CMP) and / or recess etching, is performed after deposition to remove any excess deposited material above the dielectric layer 214.

[0059] As an example, Figure 2C-2E The structure in which the second material includes silicon nitride and silicon oxide is shown. Figure 2C As shown, a liner material layer 224 of a suitable material (e.g., silicon oxide) may be deposited into the opening 222. In some embodiments, the liner material layer 224 has a thickness of 2 nm to 8 nm, such as 5 nm, and may be deposited using ALD. The liner material layer 224 may cover the bottom surface and side surfaces of the opening 222. Figure 2D As shown, an etch stop material layer 226 can be deposited on the liner material layer 224 to fill the opening 222. The deposition of the etch stop material layer 226 can include one or more thin film deposition processes, such as CVD, PVD and / or ALD. In some embodiments, an air gap (not shown) is formed in the etch stop material layer 226. The formation of the air gap can include any suitable manufacturing process, such as rapid thermal sealing. The air gap can be surrounded by the etch stop material layer 226, such as a seal.

[0060] like Figure 2E As shown, a planarization process, such as CMP and / or recess etching, is performed after the deposition of the etch stop material layer 226 to remove any excess deposited material above the dielectric layer 214. A DSG cut structure 206 may be formed having a liner layer 225 (e.g., silicon oxide) and an etch stop layer 228 (e.g., silicon nitride). The liner layer 225 may surround the etch stop layer 228 at its bottom and side surfaces. In some embodiments, the top surface of the DSG cut structure 206 may be coplanar with the dielectric layer 214.

[0061] The method 300 proceeds to operation 310 where a contact is formed in the dielectric layer, the contact contacting the channel structure. Figure 2F-2H The corresponding structure is shown.

[0062] like Figure 2FAs shown, after forming the DSG cut structure 206, a capping layer 240 may be formed over the dielectric layer 214 and the DSG cut structure 206. The capping layer 240 may cover at least the DSG cut structure 206 and the channel structure 208. In some embodiments, the capping layer 240 includes a dielectric material such as silicon oxide, and may be deposited using one or more thin film deposition processes such as CVD, PVD, and / or ALD.

[0063] like Figure 2G As shown, an opening 232 may be formed in the cap layer 240 and the dielectric layer 214. The opening 232 may extend through the dielectric layer 214 and contact the channel structure 208 (e.g., the channel plug 215). In some embodiments, the opening 232 may contact the DSG cut structure 206, for example, partially fall on the DSG cut structure 206, such as Figure 2G As shown. At least the top surface of the etch stop layer 228 may be exposed by etching to form the opening 232. The portion of the liner layer 225 that contacts the opening 232 may or may not be partially removed by the etching process that forms the opening 232. In some embodiments, the liner layer 225 may be completely or partially retained on the etch stop layer 228 in the opening 232. For example, when the liner layer 225 is completely or partially removed in the opening 232, the side surface etch stop layer 228 may be exposed in the opening 232. In another example, when the liner layer 225 is completely retained, the side surface of the etch stop layer 228 is covered by the liner layer 225 in the opening 232. In some embodiments, since the thickness of the liner layer 225 is ideally thin, the etch stop layer 228 still prevents the etching of the channel structure 208. The channel structure 208 is therefore less susceptible to damage during the formation of the opening 232. In some embodiments, the formation of the opening 232 includes a photolithography process and an etching process (eg, dry etching and / or wet etching).

[0064] like Figure 2HAs shown, a conductive material is deposited to fill the opening 232 and form a contact 212. The contact 212 may extend in the cap layer 240, pass through the dielectric layer 214, and contact the channel plug 215 of the channel structure 208. In some embodiments, if the liner layer 225 is partially or completely removed in the opening 232, the contact 212 contacts the side surface of the etch stop layer 228. In some embodiments, if the liner layer 225 remains completely on the side surface of the etch stop layer 228, the contact 212 contacts the etch stop layer 228 on the top surface instead of the side surface. In some embodiments, the conductive material includes tungsten (W), and the deposition includes CVD, PVD, ALD, electroplating, chemical plating, or any combination thereof. In some embodiments, before depositing tungsten, an adhesion layer, such as titanium nitride (TiN), is deposited on the side surface of the opening 232. In some embodiments, the deposition of the adhesive layer includes CVD, PVD, ALD, or any combination thereof.

[0065] Figure 4 A block diagram of an exemplary system 400 with a storage device according to some aspects of the present disclosure is shown. The system 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 4 As shown, system 400 may include a host 408 and a storage system 402 having one or more storage devices 404 and a storage controller 406. Host 408 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 408 may be configured to send data to storage device 404 or receive data from storage device 404.

[0066] The memory device 404 may be any memory device disclosed in the present disclosure. As disclosed in detail above, the memory device 404, such as a NAND flash memory device, may have one or more DSG cut structures with an etch stop material. According to some embodiments, the memory controller 406 is coupled to the memory device 404 and the host 408 and is configured to control the memory device 404. The memory controller 406 may manage data stored in the memory device 404 and communicate with the host 408. For example, the memory controller 406 may be coupled to the memory device 404, such as the 3D memory device 100 described above, and the memory controller 406 may be configured to control the operation of the channel structure 108 of the 3D memory device 100 through the DSG line 116.

[0067] In some embodiments, the storage controller 406 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the storage controller 406 is designed to operate in a high duty cycle environment SSD or an embedded multimedia card (eMMC) used as a data storage device for mobile devices (such as smartphones, tablets, notebook computers, etc.) and enterprise storage arrays. The storage controller 406 can be configured to control the operation of the storage device 404, such as read, erase and program operations. The storage controller 406 can also be configured to manage various functions for data stored or to be stored in the storage device 904, including but not limited to bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the storage controller 406 is also configured to process error correction code (ECC) for data read from or written to the storage device 404. The storage controller 406 may also perform any other suitable functions, such as formatting the storage device 404. The storage controller 406 may communicate with an external device (e.g., the host 408) according to a specific communication protocol. For example, the storage controller 406 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0068] The storage controller 406 and the one or more storage devices 404 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the storage system 402 can be implemented and packaged into different types of final electronic products. Figure 5A In one example shown, the storage controller 406 and the single storage device 404 may be integrated into a memory card 502. The memory card 502 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 502 may also include a computer that connects the memory card 502 to a host (e.g., Figure 4 The host 408 in the memory card connector 504 is coupled. Figure 5B In another example shown, the storage controller 406 and the plurality of storage devices 404 may be integrated into an SSD 506. The SSD 506 may also include a processor that connects the SSD 506 to a host (e.g., Figure 4 In some implementations, the storage capacity and / or operating speed of the SSD 506 is greater than the storage capacity and / or operating speed of the memory card 502.

[0069] According to one aspect of the present disclosure, a memory device includes a stacked structure on a substrate, a channel structure extending in the stacked structure, and a dielectric layer on the channel structure. The dielectric layer includes a first material. The memory device may also include a DSG cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

[0070] In some embodiments, the DSG notch structure contacts the DSG in the channel structure and the plurality of conductive layers.

[0071] In some embodiments, the etch selectivity of the first material relative to the second material is greater than 1.

[0072] In some embodiments, the first and second materials each include a respective dielectric material.

[0073] In some embodiments, the first material includes silicon oxide and the second material includes silicon nitride.

[0074] In some embodiments, the DSG notch structure does not include silicon oxide.

[0075] In some embodiments, the DSG notch structure includes silicon nitride.

[0076] In some embodiments, the DSG notch structure includes a pad silicon oxide layer and a silicon nitride layer surrounded by the pad silicon oxide layer.

[0077] In some embodiments, the thickness of the pad silicon oxide layer is in a range of 2 nm to 8 nm.

[0078] In some embodiments, the DSG notch structure includes a silicon nitride layer surrounded by a pad silicon oxide layer, and an air gap surrounded by the silicon nitride layer.

[0079] In some embodiments, the memory device further includes a pair of source contact structures extending in a lateral direction and a memory block between the pair of source contact structures. The memory block includes a plurality of memory cells in a plurality of channel structures between the source contact structures. The memory block includes a pair of strings adjacent to each other. Each of the strings includes a plurality of rows of channel structures in a lateral direction. The DSG cutout structure extending in the lateral direction is located between the pair of strings and contacts a row of channel structures in the plurality of rows of channel structures.

[0080] In some embodiments, each of the strings includes four rows of channel structures.

[0081] In some embodiments, the memory block includes four strings, each of which includes four rows of channel structures extending in a lateral direction.

[0082] According to another aspect of the present disclosure, a storage system includes a storage device configured to store data. The storage device includes a stacked structure on a substrate, a channel structure extending in the stacked structure, a dielectric layer on the channel structure, and a DSG cut structure extending through the dielectric layer, wherein the dielectric has a first material. The DSG cut structure includes a second material different from the first material. The storage system also includes a storage controller coupled to the storage device and configured to control the operation of the channel structure.

[0083] According to another aspect of the present disclosure, a method for forming a memory device includes: forming a stacked structure on a substrate, forming a channel structure extending in the stacked structure, depositing a first material to form a dielectric layer on the channel structure, and patterning the dielectric layer and the stacked structure to form an opening, the opening passing through the dielectric layer and contacting the conductive layer in the top portion of the stacked structure. The method may also include depositing a second material into the opening to form a DSG cut structure. The second material is different from the first material. The method may also include forming a contact in the dielectric layer that contacts the channel structure.

[0084] In some embodiments, the opening is in contact with the channel structure.

[0085] In some embodiments, depositing the first material includes depositing silicon oxide.

[0086] In some embodiments, depositing the second material to form the DSG notch structure includes depositing silicon nitride.

[0087] In some embodiments, depositing the second material to form the DSG notch structure includes depositing silicon nitride to fill the opening.

[0088] In some embodiments, depositing the second material to form the DSG notch structure includes: depositing a pad oxide layer in the opening, the pad oxide layer contacting a surface of the opening; and depositing a silicon nitride layer to fill the opening.

[0089] In some embodiments, deposition of the pad oxide layer includes ALD.

[0090] In some embodiments, depositing the second material to form the DSG cut structure includes depositing a pad oxide layer in the opening. The pad oxide layer contacts the surface of the opening. Depositing the second material may also include depositing a silicon nitride layer on the pad oxide layer, and forming an air gap in the silicon nitride layer during the deposition of the silicon nitride layer.

[0091] In some embodiments, forming a contact in the dielectric layer includes etching the dielectric layer to form another opening contacting the channel structure and the DSG cut structure, and depositing a conductive material to fill the another opening.

[0092] In some embodiments, the DSG notch structure is an etch stop layer for the etching of the dielectric layer.

[0093] In some embodiments, in the etching of the dielectric layer, an etching rate on the second material is lower than an etching rate on the first material.

[0094] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0095] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A storage device, comprising: Stacked structure; A channel structure extending in the stacked structure in a vertical direction; a dielectric layer, located on one side of the channel structure along the vertical direction, the dielectric layer comprising a first material; a drain select gate (DSG) cut structure, comprising a second material different from the first material, the DSG cut structure further comprising a top surface away from the channel structure in the vertical direction; as well as A contact located on one side of the channel structure along the vertical direction and in contact with the channel structure, wherein the contact extends through the dielectric layer and in contact with the DSG cut structure, the contact includes a top surface away from the channel structure in the vertical direction, and the top surface of the contact is located on a side of the top surface of the DSG cut structure away from the channel structure.

2. The storage device according to claim 1, wherein: A contact contacts the second material of the DSG notch structure.

3. The storage device according to claim 1, wherein: The DSG cut structure contacts the channel structure and the DSG in the plurality of conductive layers.

4. The storage device according to claim 1, wherein: The etching selectivity of the first material relative to the second material is greater than 1.

5. The storage device according to claim 1, wherein: The first material and the second material each include a corresponding dielectric material.

6. The storage device according to claim 1, wherein: The first material includes one of silicon oxide and silicon nitride, and the second material includes the other of silicon oxide and silicon nitride.

7. The storage device according to claim 1, further comprising a gap structure extending in a lateral direction and a storage block located between two adjacent gap structures, wherein: The number of the DSG notch structures located between two adjacent gap structures is greater than or equal to three.

8. The storage device according to claim 7, wherein: The memory block includes a plurality of memory cells in a plurality of channel structures located between two adjacent gap structures, wherein: The memory block includes a pair of strings adjacent to each other, each of the strings including a plurality of rows of channel structures in the lateral direction, and The DSG cut structure extending in the lateral direction is located between the pair of strings and contacts at least one row of the plurality of rows of channel structures.

9. The storage device according to claim 8, wherein: Each of the strings includes four rows of channel structures.

10. The storage device according to claim 8, wherein: The memory block includes four strings, each of the four strings including four rows of channel structures extending in the lateral direction.

11. The storage device according to claim 1, wherein: The DSG notch structure passes through a portion of the channel structure along the vertical direction.

12. The storage device according to claim 11, wherein: The channel structure includes a semiconductor channel, a tunneling layer, a storage layer and a barrier layer arranged in sequence in a radial direction, and the channel structure also includes a channel plug, which is located between the semiconductor channel and the contact, and the DSG cut structure is in contact with the semiconductor channel, the tunneling layer, the storage layer, the barrier layer and the channel plug.

13. A storage device, comprising: Stacked structure; A channel structure extending in the stacked structure in a vertical direction; a dielectric layer, located on one side of the channel structure along the vertical direction; a drain select gate (DSG) cut structure extending through the dielectric layer, wherein the DSG cut structure includes a top surface away from the channel structure in the vertical direction; as well as A contact located on one side of the channel structure along the vertical direction and in contact with the channel structure, wherein the contact extends through the dielectric layer and in contact with the DSG cut structure, the contact includes a top surface away from the channel structure in the vertical direction, and the top surface of the contact is located on a side of the top surface of the DSG cut structure away from the channel structure.

14. The storage device according to claim 13, wherein: The DSG cut structure and the dielectric layer both include a first material.

15. The storage device according to claim 14, wherein: The first material includes silicon oxide.

16. The storage device according to claim 13, further comprising a gap structure extending in a lateral direction and a storage block located between two adjacent gap structures, wherein: The number of the DSG notch structures located between two adjacent gap structures is greater than or equal to three.

17. The storage device according to claim 16, wherein: The memory block includes a plurality of memory cells in a plurality of channel structures located between two adjacent gap structures, wherein: The memory block includes a pair of strings adjacent to each other, each of the strings including a plurality of rows of channel structures in the lateral direction, and The DSG cut structure extending in the lateral direction is located between the pair of strings and contacts at least one row of the plurality of rows of channel structures.

18. The storage device according to claim 17, wherein: Each of the strings includes four rows of channel structures.

19. The storage device according to claim 17, wherein: The memory block includes four strings, each of the four strings including four rows of channel structures extending in the lateral direction.

20. The storage device according to claim 13, wherein: The DSG notch structure passes through a portion of the channel structure along the vertical direction.

21. The storage device according to claim 20, wherein: The channel structure includes a semiconductor channel, a tunneling layer, a storage layer and a barrier layer arranged in sequence in a radial direction, and the channel structure also includes a channel plug, which is located between the semiconductor channel and the contact, and the DSG cut structure is in contact with the semiconductor channel, the tunneling layer, the storage layer, the barrier layer and the channel plug.

22. A method for forming a memory device, comprising: Forming a stacked structure, a dielectric layer, and a channel structure extending in a vertical direction in the stacked structure, wherein the dielectric layer is located on one side of the channel structure along the vertical direction, and the dielectric layer comprises a first material; forming a drain select gate (DSG) cut structure, the DSG cut structure comprising a second material different from the first material, the DSG cut structure further comprising a top surface away from the channel structure in the vertical direction; and A contact is formed, wherein the contact is located on one side of the channel structure along the vertical direction and is in contact with the channel structure, wherein the contact extends through the dielectric layer and is in contact with the DSG cut structure, the contact includes a top surface away from the channel structure in the vertical direction, and the top surface of the contact is located on a side of the top surface of the DSG cut structure away from the channel structure.

23. The method according to claim 22, wherein: The forming of the DSG incision structure comprises: patterning the dielectric layer and the stacked structure to form openings that pass through the dielectric layer and the DSGs in the plurality of conductive layers; A second material is deposited into the opening.

24. The method according to claim 22, wherein: A contact contacts the second material of the DSG notch structure.

25. The method according to claim 22, wherein: The DSG cut structure contacts the channel structure and the DSG in the plurality of conductive layers.

26. The method of claim 22, wherein: In etching the dielectric layer, an etching rate on the second material is lower than an etching rate on the first material.

27. The method of claim 22, wherein: The first material includes one of silicon oxide and silicon nitride, and the second material includes the other of silicon oxide and silicon nitride.

28. The method of claim 22, further comprising: A gap structure extending in a lateral direction and a storage block located between two adjacent gap structures are formed, wherein the number of DSG cut structures located between two adjacent gap structures is greater than or equal to three.

29. The method according to claim 28, wherein: The memory block includes a plurality of memory cells in a plurality of channel structures located between two adjacent gap structures, wherein: The memory block includes a pair of strings adjacent to each other, each of the strings including a plurality of rows of channel structures in the lateral direction, and The DSG cut structure extending in the lateral direction is located between the pair of strings and contacts at least one row of the plurality of rows of channel structures.

30. The method of claim 29, wherein: The memory block includes four strings, each of the four strings including four rows of channel structures extending in the lateral direction.

31. The method of claim 22, wherein: The DSG notch structure passes through a portion of the channel structure along the vertical direction.

32. The method according to claim 31, wherein: The channel structure includes a semiconductor channel, a tunneling layer, a storage layer and a barrier layer arranged in sequence in a radial direction, and the channel structure also includes a channel plug, which is located between the semiconductor channel and the contact, and the DSG cut structure is in contact with the semiconductor channel, the tunneling layer, the storage layer, the barrier layer and the channel plug.

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