Semiconductor structure and method for forming the same

Abstract

The present disclosure relates to a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate and a memory cell located on a top surface of the substrate, the memory cell including a transistor and a phase change structure, the transistor including an active pillar extending along a first direction, the phase change structure located above the active pillar along the first direction, the phase change structure including a heater located above the active pillar along the first direction, a phase change layer located above the heater along the first direction, and a thermal insulation layer covering the sidewalls of the heater, the heater including a first end electrically connected to the active pillar and a second end opposite the first end along the first direction, the projected area of ​​the first end on the top surface of the substrate being smaller than the projected area of ​​the second end on the top surface of the substrate. The present disclosure increases the storage density of the semiconductor structure and improves the storage performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Throughout IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component that can be produced using a manufacturing process) has continued to decrease. In addition to smaller and more complex IC components, the wafers on which ICs are manufactured have become increasingly larger, making increasing the integration density of semiconductor devices a key development direction.

[0003] As the demand for memory performance continues to increase, higher storage density and smaller storage nodes are the main development directions of current memory. However, memories with traditional planar transistor structures suffer from problems such as difficult buried wordline manufacturing processes, high leakage currents, and poor gate control performance. These problems make it difficult for memories with traditional planar transistor structures to meet the requirements of higher storage density and smaller storage nodes.

[0004] Therefore, how to increase the storage density of the memory to improve the performance of the memory is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to increase the storage density of a memory to improve the performance of the memory.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure comprising:

[0007] substrate;

[0008] A memory cell is located on the top surface of the substrate, the memory cell includes a transistor and a phase change structure, the transistor includes an active pillar extending along a first direction, the phase change structure is located above the active pillar along the first direction, the phase change structure includes a heater located above the active pillar along the first direction, a phase change layer located above the heater along the first direction, and a thermal insulation layer covering the side wall of the heater, the heater includes a first end electrically connected to the active pillar, and a second end opposite to the first end along the first direction, the projected area of ​​the first end on the top surface of the substrate is smaller than the projected area of ​​the second end on the top surface of the substrate, and the first direction is perpendicular to the top surface of the substrate.

[0009] In some embodiments, it further includes:

[0010] a common source line, located between the memory cell and the substrate along the first direction, and electrically connected to the active pillar;

[0011] A bit line is located above the phase change structure along the first direction and is electrically connected to the phase change structure.

[0012] In some embodiments, the plurality of storage units are arranged in an array along a second direction and a third direction on the top surface of the substrate, the second direction and the third direction are both parallel to the top surface of the substrate, and the second direction is orthogonal to the third direction;

[0013] The common source line extends along the second direction and is electrically connected to the active pillars in the plurality of memory cells arranged at intervals along the second direction;

[0014] The bit line extends along the second direction and is electrically connected to the phase change structures in the plurality of memory cells arranged at intervals along the second direction.

[0015] In some embodiments, the active pillar includes a channel region, a first source / drain region located below the channel region along the first direction, and a second source / drain region located above the channel region along the first direction, and the common source line is electrically connected to the first source / drain region; the semiconductor structure further includes:

[0016] A word line extends along a third direction and continuously covers the channel regions in the plurality of active pillars spaced apart along the third direction.

[0017] In some embodiments, it further includes:

[0018] A conductive contact layer is located between the heater and the second source and drain region along the first direction, wherein one end of the conductive contact layer is electrically connected to the heater, and the other end of the conductive contact layer is electrically connected to the second source and drain region.

[0019] In some embodiments, the phase change structure further comprises:

[0020] a top electrode layer, located between the phase change layer and the bit line along the first direction, one end of the top electrode layer being electrically connected to the phase change layer, and the other end being electrically connected to the bit line;

[0021] A first isolation layer covers the sidewalls of the top electrode layer, the phase change layer, and the heat insulation layer.

[0022] In some embodiments, it further includes:

[0023] a second isolation layer, located between adjacent memory cells and covering a top surface of the word line, wherein the top surface of the second isolation layer has a groove, and the thermal insulation layer is also filled in the groove;

[0024] Along the first direction, a top surface of the second isolation layer is located above a bottom surface of the heater.

[0025] According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure, comprising the following steps:

[0026] forming a substrate;

[0027] A memory cell is formed and located above the substrate along a first direction, the memory cell comprising a transistor and a phase change structure, the transistor comprising an active pillar extending along the first direction, the phase change structure being located above the active pillar along the first direction, the phase change structure comprising a heater located above the active pillar along the first direction, a phase change layer located above the heater along the first direction, and a thermal insulation layer covering a sidewall of the heater, the heater comprising a first end electrically connected to the active pillar, and a second end opposite to the first end along the first direction, a projected area of ​​the first end on the top surface of the substrate being smaller than a projected area of ​​the second end on the top surface of the substrate, and the first direction being perpendicular to the top surface of the substrate.

[0028] In some embodiments, the steps of forming the substrate include:

[0029] providing an initial substrate;

[0030] First dopant ions are implanted into the initial substrate to form a plurality of common source lines extending along the second direction and arranged at intervals along the third direction, the initial substrate remaining below the common source lines serves as the substrate, the second direction and the third direction are both parallel to the top surface of the substrate, and the second direction is orthogonal to the third direction.

[0031] In some embodiments, the specific steps of forming a memory cell located above the substrate along the first direction include:

[0032] Etching the initial substrate above the common source line to form a plurality of first trenches extending along the second direction and arranged at intervals along the third direction, and forming a plurality of second trenches extending along the third direction and arranged at intervals along the second direction, wherein the plurality of first trenches and the plurality of second trenches separate the initial substrate above the common source line into a plurality of active pillars arranged in an array along the second direction and the third direction;

[0033] forming a conductive contact layer above the active pillar, wherein the conductive contact layer is electrically connected to the active pillar;

[0034] The phase change structure is formed above the conductive contact layer along the first direction, and the phase change structure is electrically connected to the conductive contact layer.

[0035] In some embodiments, the active pillar includes a channel region, a first source / drain region located below the channel region along the first direction, and a second source / drain region located above the channel region along the first direction, and the common source line is electrically connected to the first source / drain region. Before forming the phase change structure located above the active pillar along the first direction, the following steps are further included:

[0036] Word lines are formed in the first trench and the second trench, the word lines extending along the third direction, and the word lines continuously cover the channel regions in the plurality of active pillars spaced apart and distributed along the third direction.

[0037] In some embodiments, the specific steps of forming the phase change structure above the conductive contact layer along the first direction include:

[0038] forming a thermal insulation layer including a heater hole on the conductive contact layer, wherein the heater hole exposes the conductive contact layer, a hole diameter of a bottom portion of the heater hole is smaller than a hole diameter of a top portion of the heater hole, the bottom portion of the heater hole faces the conductive contact layer, and the top portion of the heater hole is opposite to the bottom portion of the heater hole along the first direction;

[0039] forming the heater in the heater hole and electrically connected to the conductive contact layer;

[0040] forming the phase change layer on the heater;

[0041] forming a top electrode layer on the phase change layer;

[0042] A first isolation layer is formed covering sidewalls of the top electrode layer, sidewalls of the phase change layer, and sidewalls of the heat insulation layer.

[0043] In some embodiments, the specific steps of forming a thermal insulation layer including heater holes on the conductive contact layer include:

[0044] forming a heat-insulating layer on the conductive contact layer;

[0045] forming a sacrificial layer covering the thermal insulation layer, wherein the sacrificial layer has a sacrificial hole exposing the thermal insulation layer;

[0046] forming a filling layer having an air gap in the sacrificial hole;

[0047] Etching back the filling layer to form an etching hole exposing the thermal insulation layer;

[0048] The heat insulation layer is etched along the etched hole to form the heater hole.

[0049] In some embodiments, the specific steps of forming a filling layer having an air gap in the sacrificial hole include:

[0050] Etching back a portion of the sacrificial layer along the sacrificial hole so that the width of the bottom of the sacrificial hole is greater than the width of the top of the sacrificial hole, the bottom of the sacrificial hole faces the thermal insulation layer, and the top of the sacrificial hole and the bottom of the sacrificial hole are oppositely distributed along the first direction;

[0051] The sacrificial hole is backfilled to form the filling layer having the air gap.

[0052] In some embodiments, the sacrificial layer includes a first sacrificial layer covering the thermal insulation layer, and a second sacrificial layer located above the first sacrificial layer, and the sacrificial hole continuously penetrates the first sacrificial layer and the second sacrificial layer; and the specific steps of etching back a portion of the sacrificial layer along the sacrificial hole include:

[0053] A portion of the first sacrificial layer is etched back along the sacrificial hole to increase the diameter of the sacrificial hole in the first sacrificial layer.

[0054] Some embodiments of the present disclosure provide semiconductor structures and methods for forming the same. By forming a memory cell comprising a transistor and a phase change structure, wherein the active pillar in the transistor extends in a direction perpendicular to the top surface of the substrate and the phase change structure is located above the transistor in a direction perpendicular to the top surface of the substrate, a phase change memory cell with a vertical transistor structure is formed. This reduces the size of the memory cell in the semiconductor structure, significantly improving the storage density and storage efficiency of the semiconductor structure, and achieving improved storage performance of the semiconductor structure. In some embodiments of the present disclosure, the size of the first end (i.e., the bottom end) of the heater of the phase change structure is smaller than the size of the second end (i.e., the top end) of the heater, resulting in a tapered cross-section of the heater, thereby reducing the contact area between the heater and the transistor, increasing the thermal efficiency of the heater, and improving the response speed of the memory cell, thereby further improving the performance of the semiconductor structure. In some embodiments of the present disclosure, the phase change structure further includes a thermal insulation layer covering the sidewalls of the heater, thereby preventing heat loss from the heater, further ensuring the thermal efficiency of the heater, and thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Attachment Figure 1 is a circuit diagram of a semiconductor structure in a specific embodiment of the present disclosure;

[0056] Attachment Figure 2 is a schematic top view of a semiconductor structure in a specific embodiment of the present disclosure;

[0057] Attachment Figure 3 is a schematic diagram of the three-dimensional structure of a storage unit in a specific embodiment of the present disclosure;

[0058] Attachment Figure 4 is a schematic cross-sectional view of a storage unit in a specific embodiment of the present disclosure;

[0059] Attachment Figure 5 is a voltage-current diagram on a bit line of a memory cell during a read and write operation in a specific embodiment of the present disclosure;

[0060] Attachment Figure 6 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

[0061] Attachment Figure 7-Figure 26 It is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] The specific embodiments of the semiconductor structure and the method for forming the same provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0063] This embodiment provides a semiconductor structure, Figure 1 is a circuit diagram of a semiconductor structure in a specific embodiment of the present disclosure, Figure 2 is a top view schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure, Figure 3 is a schematic diagram of the three-dimensional structure of the storage unit in the specific embodiment of the present disclosure, Figure 4 FIG is a schematic cross-sectional view of a storage unit in a specific embodiment of the present disclosure. Figure 1-Figure 4 As shown, the semiconductor structure includes:

[0064] substrate 30;

[0065] The memory cell 10 is located on the top surface of the substrate 30. The memory cell 10 includes a transistor and a phase change structure. The transistor includes an active pillar 23 extending along a first direction D1. The phase change structure is located above the active pillar 23 along the first direction D1. The phase change structure includes a heater 40 located above the active pillar 23 along the first direction D1, a phase change layer 33 located above the heater 40 along the first direction D1, and a thermal insulation layer 32 covering the side wall of the heater 40. The heater 40 includes a first end 401 electrically connected to the active pillar 23, and a second end 402 opposite to the first end 401 along the first direction D1. The projected area of ​​the first end 401 on the top surface of the substrate 30 is smaller than the projected area of ​​the second end 402 on the top surface of the substrate 30. The first direction D1 is perpendicular to the top surface of the substrate 30.

[0066] In some embodiments, the semiconductor structure further comprises:

[0067] a common source line 20 , located between the memory cell 10 and the substrate 30 along the first direction D1 , and electrically connected to the active pillar 23 ;

[0068] The bit line 21 is located above the phase change structure along the first direction D1 , and the bit line 21 is electrically connected to the phase change structure.

[0069] Specifically, the substrate 30 may be, but is not limited to, a silicon substrate. This specific embodiment is described using the substrate 30 as an example. In other embodiments, the substrate 30 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 30 is used to support the device structure above it. The top surface of the substrate 30 refers to the surface of the substrate 30 facing the memory cell 10. The common source line 20 is located on the top surface of the substrate 30 along the first direction D1. The common source line 20 is electrically connected to the transistor in the memory cell 10 and is used to transmit a selection signal to the transistor to control the conduction and shutdown of the transistor. The phase change layer 33 includes a phase change material that can be converted between a crystalline state and an amorphous state, and the resistivity of the phase change material in the crystalline state is different from the resistivity in the amorphous state. In one example, the phase change material may be germanium antimony telluride. The transistor is used to control the heating state of the phase change layer 33 by the heater 40 in the phase change structure, thereby adjusting the heat in the phase change layer 33 so that the phase change layer 33 switches between the crystalline state and the amorphous state, and finally realizing the reading and writing operations of data based on the resistance change of the phase change layer 33.

[0070] In this embodiment, the transistor is a vertical transistor extending along the first direction D1. The phase change structure is located above the transistor along the first direction D1, so that the transistor and the phase change structure extend along the first direction D1, forming a phase change memory cell with a vertical transistor structure. This reduces the size of the memory cell in the semiconductor structure, significantly improves the storage density and storage efficiency of the semiconductor structure, and improves the storage performance of the semiconductor structure. The size of the first end 401 of the heater 40 in the phase change structure facing the active pillar 23 (e.g., the width of the first end 401 along the third direction D3, where the third direction D3 is parallel to the top surface of the substrate 30) is smaller than the size of the second end 402 of the heater 40 facing the phase change layer 33 (e.g., the width of the second end 402 along the third direction D3). This gives the heater 40 a tapered structure, thereby reducing the contact area between the heater 40 and the transistor, increasing the thermal efficiency of the heater, and improving the response speed of the memory cell, thereby further improving the performance of the semiconductor structure. Moreover, this specific embodiment covers the side wall of the heater 40 with the insulation layer 32, isolating the heater 40 from the external environment through the insulation layer 32, thereby preventing heat loss of the heater 40, further ensuring the thermal efficiency of the heater 40, and thus improving the performance of the semiconductor structure.

[0071] In some embodiments, the plurality of memory cells 10 are arranged in an array along a second direction D2 and a third direction D3 on the top surface of the substrate 30 , wherein the second direction D2 and the third direction D3 are both parallel to the top surface of the substrate 30 , and the second direction D2 is orthogonal to the third direction D3 ;

[0072] The common source line 20 extends along the second direction D2 and is electrically connected to the active pillars 23 in the plurality of memory cells 10 arranged at intervals along the second direction D2;

[0073] The bit line 21 extends along the second direction D2 and is electrically connected to the phase change structures in the plurality of memory cells 10 arranged at intervals along the second direction D2.

[0074] exist Figure 2 In the perspective shown, the active pillars 23 are not visible, so the relative position relationship between the plurality of active pillars 23 is represented by dotted lines. Figure 2As shown, the semiconductor structure includes an active array and a phase change array located above the active array along the first direction D1. The active array includes a plurality of active pillars 23 arranged in a two-dimensional array along the second direction D2 and the third direction D3. The phase change array includes a plurality of phase change structures arranged in a two-dimensional array along the second direction D2 and the third direction D3, and the plurality of phase change structures correspond one-to-one to the plurality of active pillars 23, so that the plurality of memory cells 10 are arranged in a 4F2 structure, thereby further improving the storage density of the semiconductor structure. The plurality of common source lines 20 extend along the second direction D2 and are arranged at intervals along the third direction D3. Each common source line 20 is electrically connected to the plurality of active pillars 23 arranged at intervals along the second direction D2. The plurality of bit lines 21 (e.g. Figure 1 The first bit line BL0 and the second bit line BL1 in the embodiment extend along the second direction D2 and are arranged at intervals along the third direction D3. Each of the bit lines 21 is electrically connected to a plurality of phase change structures arranged at intervals along the second direction D2. In this embodiment, "a plurality" refers to more than two, and "a plurality" refers to more than two.

[0075] In some embodiments, the active pillar 23 includes a channel region, a first source / drain region located below the channel region along the first direction D1, and a second source / drain region located above the channel region along the first direction D1, and the common source line 20 is electrically connected to the first source / drain region; the semiconductor structure further includes:

[0076] The word line 22 extends along a third direction D3 and continuously covers the channel region of the plurality of active pillars 23 spaced apart along the third direction D3.

[0077] For example, if Figure 1 and Figure 2 As shown, the semiconductor structure includes a plurality of word lines 22 (eg, Figure 1 Each word line 22 continuously covers the channel regions of the plurality of active pillars 23 arranged at intervals along the third direction D3. In one example, the word lines 22 surround the periphery of the channel regions in the active pillars 23, forming a gate-all-around structure, thereby further improving the gate control performance of the transistor and further improving the performance of the semiconductor structure.

[0078] In some embodiments, the semiconductor structure further comprises:

[0079] The conductive contact layer 31 is located between the heater 40 and the second source / drain region along the first direction D1 . One end of the conductive contact layer 31 is electrically connected to the heater 40 , and the other end is electrically connected to the second source / drain region.

[0080] Specifically, to reduce the contact resistance between the transistor and the phase change structure, the conductive contact layer 31 is disposed between the heater 40 in the phase change structure and the second source and drain regions in the transistor. In one example, the conductive contact layer 31 may be made of a metal silicide material, such as cobalt silicide. In one example, the projection of the heater 40 within the plane defined by the first direction D1 and the third direction D3 is conical, such that the contact area between the heater 40 and the conductive contact layer 31 is smaller than the contact area between the heater 40 and the phase change layer 33. This increases the heating efficiency of the heater 40 and improves the response speed of the semiconductor structure.

[0081] In some embodiments, the phase change structure further comprises:

[0082] a top electrode layer 34 , located between the phase change layer 33 and the bit line 21 along the first direction D1 , with one end of the top electrode layer 34 electrically connected to the phase change layer 33 and the other end electrically connected to the bit line 21 ;

[0083] The first isolation layer 41 covers the sidewalls of the top electrode layer 34 , the sidewalls of the phase change layer 33 , and the sidewalls of the thermal insulation layer 32 .

[0084] Specifically, the phase change structure includes the heater 40, the phase change layer 33, and the top electrode layer 34 stacked in sequence along the first direction D1. The heater 40 is electrically connected to the transistor, and the top electrode layer 34 is electrically connected to the bit line 21. Figure 5 : This is a voltage-current diagram on the bit line of a memory cell during read and write operations in a specific embodiment of the present disclosure, wherein the first curve 50 represents the voltage-current diagram on the bit line 21 in the crystalline state, and the second curve 51 represents the voltage-current diagram on the bit line 21 in the amorphous state. The position indicated by the dotted line is the position when the memory cell is read. When performing a write operation on the memory cell 10, the transistor in the memory cell 10 is turned on and a heating signal is transmitted to the heater 40 via the common source line 20, so that the heater 40 heats the phase change layer 33, thereby causing the phase change layer 33 to transition between the crystalline state and the amorphous state, thereby achieving data writing. When performing a read operation on the memory cell 10, the transistor in the memory cell 10 is turned on and the data in the phase change structure is read via the bit line 21.

[0085] In one example, the thermal insulation layer 32 is distributed around the periphery of the heater 40, thereby further reducing the diffusion of heat generated by the heater 40 to the outside and preventing heat from the external environment from affecting the heater 40, thereby further improving the performance of the semiconductor structure. To further reduce the thermal conductivity of the thermal insulation layer 32 and further improve the performance of the semiconductor structure, in some embodiments, the thermal insulation layer 32 is made of zirconium dioxide.

[0086] In one example, the material of the first isolation layer 41 can be an insulating material with low thermal conductivity, such as a nitride material (such as silicon nitride), so that the first isolation layer 41 can, on the one hand, isolate the phase change structures in the two adjacent storage units 10, and on the other hand, further reduce the heat generated by the heater 40 from diffusing to the outside and avoid the heat in the external environment from affecting the heater 40, and can improve the reliability performance of the phase change memory, for example, improve the sustainability and recycling capabilities.

[0087] In some embodiments, the semiconductor structure further comprises:

[0088] a second isolation layer, located between adjacent memory cells 10 and covering the top surface of the word line 22 , wherein the top surface of the second isolation layer has a groove, and the thermal insulation layer 32 is further filled in the groove to improve the structural stability of the thermal insulation layer 32 ;

[0089] In the first direction D1, the top surface of the second isolation layer is located above the bottom surface of the heater 40, so as to further reduce heat dissipation from the heater 40 to the external environment. In one example, the material of the second isolation layer can also be a nitride material (such as silicon nitride).

[0090] This embodiment also provides a method for forming a semiconductor structure. Figure 6 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure, Figure 7-Figure 26 This is a schematic diagram of the main process structure in the process of forming a semiconductor structure in a specific embodiment of the present disclosure, wherein: Figure 7-Figure 26 (a) is the process of forming a semiconductor structure Figure 2 Schematic diagram of the cross section at the AA position in the figure. Figure 7-Figure 26 (b) is the process of forming a semiconductor structure Figure 2 The schematic diagram of the semiconductor structure formed in this embodiment can be found in Figure 1-Figure 4 .like Figure 1-Figure 4 ,as well as Figure 6-Figure 26 As shown, the method for forming the semiconductor structure includes the following steps:

[0091] Step S61, forming a substrate 30;

[0092] Step S62, forming a memory cell 10 located above the substrate 30 along a first direction D1, the memory cell 10 includes a transistor and a phase change structure, the transistor includes an active pillar 23 extending along the first direction D1, the phase change structure is located above the active pillar 23 along the first direction D1, the phase change structure includes a heater 40 located above the active pillar 23 along the first direction D1, a phase change layer 33 located above the heater 40 along the first direction D1, and a thermal insulation layer 32 covering the side wall of the heater 40, the heater 40 includes a first end 401 electrically connected to the active pillar 23, and a second end 402 opposite to the first end 401 along the first direction D1, the projected area of ​​the first end 401 on the top surface of the substrate 30 is smaller than the projected area of ​​the second end 402 on the top surface of the substrate 30, and the first direction D1 is perpendicular to the top surface of the substrate 30.

[0093] In some embodiments, the specific steps of forming the substrate 30 include:

[0094] Providing an initial substrate 70;

[0095] First dopant ions are implanted into the initial substrate 70 to form a plurality of common source lines 20 extending along the second direction D2 and arranged at intervals along the third direction D3. The initial substrate 70 remaining below the common source lines 20 serves as the substrate 30. The second direction D2 and the third direction D3 are both parallel to the top surface of the substrate 30, and the second direction D2 is orthogonal to the third direction D3.

[0096] Specifically, the first doping ions are implanted into the preset positions in the initial substrate 70 to form a plurality of the common source lines 20. In one example, second doping ions can also be implanted into the initial substrate 70 above the common source lines 20 to improve the conductivity of the initial substrate 70 above the common source lines 20, so as to facilitate the subsequent formation of the active pillars 23. Afterwards, the substrate 30, the common source lines 20, and the initial substrate 70 above the common source lines 20 are annealed to obtain the following: Figure 7 The structure shown.

[0097] In some embodiments, the specific steps of forming the memory cell 10 located above the substrate 30 along the first direction D1 include:

[0098] The initial substrate 70 above the common source line 20 is etched to form a plurality of first trenches 80 extending along the second direction D2 and spaced apart along the third direction D3 (eg, Figure 8), and forming a plurality of second grooves 100 extending along the third direction D3 and arranged at intervals along the second direction D2 (as shown in FIG. Figure 10 As shown), the plurality of first trenches 80 and the plurality of second trenches 100 separate the initial substrate 70 above the common source line 20 into the plurality of active pillars 23 arranged in an array along the second direction D2 and the third direction D3 (see Figure 2 );

[0099] A conductive contact layer 31 is formed above the active pillar 23. The conductive contact layer 31 is electrically connected to the active pillar 23. Figure 4 and Figure 17 As shown;

[0100] The phase change structure is formed above the conductive contact layer 31 along the first direction D1, and the phase change structure is electrically connected to the conductive contact layer 31. Figure 3 、 Figure 4 and Figure 26 shown.

[0101] In some embodiments, the active pillar 23 includes a channel region 101, a first source / drain region 102 located below the channel region 101 along the first direction D1, and a second source / drain region 103 located above the channel region 101 along the first direction D1. The common source line 20 is electrically connected to the first source / drain region 102. Before forming the phase change structure located above the active pillar 23 along the first direction D1, the following steps are further included:

[0102] Word lines 22 are formed in the first trench 80 and the second trench 100 . The word lines 22 extend along the third direction D3 and continuously cover the channel regions 101 in the plurality of active pillars 23 spaced apart along the third direction D3 .

[0103] For example, after forming the common source line 20, the initial substrate 70 above the common source line 20 is etched along the first direction D1 to form a plurality of first trenches 80 extending along the second direction D2 and spaced apart along the third direction D3, each of the first trenches 80 being aligned with the spaced region between two adjacent common source lines 20, as shown in FIG. Figure 8As shown. Next, dielectric materials such as oxide (such as silicon dioxide) are deposited on the inner wall of the first trench 80 and the top surface of the remaining initial substrate 70 to form a first liner layer. Then, dielectric materials such as oxide (such as silicon dioxide) are deposited in the first trench 80 again to form a second liner layer that fills the first trench 80, and the first liner layer and the second liner layer are used together as the first backfill layer 90. The two-step deposition process is used to form the first backfill layer 90 that fills the first trench 80, which can better cover the inner wall of the first trench 80 to better protect the active pillar 23. Afterwards, dielectric materials such as nitride (such as silicon nitride) are deposited on the surface of the first backfill layer to form a first covering layer; and dielectric materials such as oxide (such as silicon dioxide) are deposited on the first covering layer to form a second covering layer. Afterwards, a planarization process such as chemical mechanical polishing (CMP) is used to remove the second covering layer. Next, the first covering layer is removed to expose the first backfill layer 90, as shown. Figure 9 By forming the first covering layer and the second covering layer and removing the first covering layer and the second covering layer, it helps to improve the Figure 9 The flatness of the first backfill layer 90 in the structure shown. Afterwards, a first region and a second region may be defined in the initial substrate 70 remaining above the common source line 20, and ion doping may be performed on the first region and the second region, wherein the first region is subsequently used to form a first source / drain region, and the second region is subsequently used to form a second source / drain region. Next, the initial substrate 70 remaining above the common source line 20 is etched along the first direction D1 to form a plurality of second trenches 100 extending along the third direction D3 and spaced apart along the second direction D2, as shown in FIG. Figure 10 As shown. A plurality of first trenches 80 and a plurality of second trenches 100 separate the initial substrate 70 above the common source line 20 into a plurality of active pillars 23 arranged in an array along the second direction D2 and the third direction D3. Each active pillar 23 includes a channel region 101, a first source / drain region 102 located below the channel region 101 along the first direction D1, and a second source / drain region 103 located above the channel region 101 along the first direction D1. Figure 10 shown.

[0104] Part of the first backfill layer 90 is etched back to expose the second source and drain region 103. A dielectric material such as oxide (e.g., silicon dioxide) is deposited on the inner wall of the second trench 100, the top surface of the second source and drain region 103, and the top surface of the first backfill layer 90 to form a second backfill layer 110. Next, a nitride (e.g., silicon nitride) is deposited inside the second trench 100 and on the surface of the second backfill layer 110 to form a third isolation layer 111. A planarization process such as chemical mechanical polishing is used to remove the third isolation layer 111 and the second backfill layer 110 on the top surface of the second source and drain region 103 to expose the second source and drain region 103. Figure 11 A wet etching process is used to etch back part of the second backfill layer 110 to form a word line trench 120 exposing the channel region 101 in the active pillar 23, as shown. Figure 12 Next, a dielectric material such as silicon dioxide is deposited on the inner wall of the second trench 100 and the inner wall of the first trench 80 by an atomic layer deposition process to form a gate dielectric layer 130 that at least covers the top surface of the channel region 101 and the third isolation layer 111. Figure 13 Afterwards, a conductive material such as TiN is deposited in the first trench 80 and the second trench 100 to form the word line 22 that continuously covers the channel region 101 in the plurality of active pillars 23 spaced apart along the third direction D3, as shown. Figure 14 Next, a dielectric material such as silicon nitride is deposited in the first trench 80 and the second trench 100 to form a second isolation layer 150 that fills the first trench 80 and the second trench 100 and covers the gate dielectric layer 130. Figure 15 As shown. Figure 15 As shown, the second isolation layer 150 located above the word line 22 has a groove therein.

[0105] Afterwards, a portion of the second isolation layer 150 is removed, and a third trench 160 is formed in the second isolation layer 150 above the second source / drain region 103, as shown in FIG. Figure 16 As shown. Metal particles (such as cobalt ions) are implanted into the upper portion of the second source / drain region 103 along the third trench 160, and the second source / drain region 103 is annealed to form the conductive contact layer 31 made of metal silicide. Afterwards, the gate dielectric layer 130 above the conductive contact layer 31 is removed along the third trench 160 to expose the conductive contact layer 31, as shown. Figure 17 shown.

[0106] In some embodiments, the specific steps of forming the phase change structure above the conductive contact layer 31 along the first direction D1 include:

[0107] The thermal insulation layer 32 including the heater hole 230 is formed on the conductive contact layer 31. The heater hole 230 exposes the conductive contact layer 31. The bottom diameter of the heater hole 230 is smaller than the top diameter of the heater hole 230. The bottom of the heater hole 230 faces the conductive contact layer 31. The top of the heater hole 230 is distributed opposite to the bottom of the heater hole 230 along the first direction D1. Figure 23 As shown;

[0108] The heater 40 electrically connected to the conductive contact layer 31 is formed in the heater hole 230, such as Figure 24 As shown;

[0109] forming the phase change layer 33 on the heater 40;

[0110] A top electrode layer 34 is formed on the phase change layer 33, such as Figure 25 As shown;

[0111] A first isolation layer 41 is formed to cover the sidewalls of the top electrode layer 34, the sidewalls of the phase change layer 33 and the sidewalls of the heat insulation layer 32. Figure 26 shown.

[0112] In some embodiments, the specific steps of forming the thermal insulation layer 32 including the heater hole 230 on the conductive contact layer 31 include:

[0113] A heat insulation layer 32 is formed on the conductive contact layer 31, such as Figure 18 As shown;

[0114] A sacrificial layer covering the thermal insulation layer 32 is formed, wherein the sacrificial layer has a sacrificial hole 190 exposing the thermal insulation layer 32. Figure 20 As shown;

[0115] A filling layer 210 having an air gap 211 is formed in the sacrificial hole 190, as shown in FIG. Figure 21 As shown;

[0116] The filling layer 210 is etched back to form an etching hole 220 exposing the thermal insulation layer 32. Figure 22 As shown;

[0117] The heat insulating layer 32 is etched along the etched hole 220 to form the heater hole 230. Figure 23 shown.

[0118] In some embodiments, the specific steps of forming the filling layer 210 having the air gap 211 in the sacrificial hole 190 include:

[0119] Etching back a portion of the sacrificial layer along the sacrificial hole 190 so that the width of the bottom of the sacrificial hole 190 is greater than the width of the top of the sacrificial hole 190 , the bottom of the sacrificial hole 190 faces the thermal insulation layer 32 , and the top of the sacrificial hole 190 and the bottom of the sacrificial hole 190 are opposite to each other along the first direction D1;

[0120] The sacrificial hole 190 is backfilled to form the filling layer 210 having the air gap 211 .

[0121] In some embodiments, the sacrificial layer includes a first sacrificial layer 180 covering the thermal insulation layer 32, and a second sacrificial layer 181 located above the first sacrificial layer 180, and the sacrificial hole 190 continuously penetrates the first sacrificial layer 180 and the second sacrificial layer 181. Figure 18 and Figure 19 As shown; the specific steps of etching back part of the sacrificial layer along the sacrificial hole 190 include:

[0122] A portion of the first sacrificial layer 180 is etched back along the sacrificial hole 190 to increase the aperture of the sacrificial hole 190 in the first sacrificial layer 180. Figure 20 shown.

[0123] For example, a low thermal conductivity material such as zirconium dioxide is deposited on the surface of the conductive contact layer 31 and the surface of the second isolation layer 150 to form the thermal isolation layer 32. A dielectric material such as silicon dioxide is deposited on the surface of the isolation layer 32 to form the first sacrificial layer 180; and a dielectric material such as nitride is deposited on the surface of the first sacrificial layer 180 to form the second sacrificial layer 181. Figure 18 As shown. The first sacrificial layer 180 and the second sacrificial layer 181 should have a high etching selectivity (for example, an etching selectivity greater than 3) to facilitate the subsequent selective etching of the first sacrificial layer 180. Next, the second sacrificial layer 181 and the first sacrificial layer 180 are etched to form the sacrificial hole 190 that continuously penetrates the second sacrificial layer 181 and the first sacrificial layer 180 along the first direction D1 and exposes the thermal insulation layer 32, as shown. Figure 19 Afterwards, a wet etching process may be used to continue to laterally etch a portion of the first sacrificial layer 180 along the sacrificial hole 190 to increase the width of the sacrificial hole 190 (for example, increasing the width of the sacrificial hole 190 in the first sacrificial layer 180 along the second direction D2 and the width along the third direction D3), so that a step is formed in the sacrificial hole 190 and at the connection between the first sacrificial layer 180 and the second sacrificial layer 181, as shown in FIG. Figure 20As shown, a filling layer with an air gap can be formed in the sacrificial hole 190. Afterwards, the sacrificial hole 190 can be filled with a material with poor step coverage performance (such as polysilicon) to form the filling layer 210 with the air gap 211, as shown in FIG. Figure 21 The filling layer 210 is etched back using a dry etching process to form the etching hole 220 exposing the thermal insulation layer 32, as shown. Figure 22 As shown. Since the filling layer 210 has the air gap 211, the opening width of the top of the etched hole 220 is larger than the opening width of the bottom of the etched hole 220. The heat insulating layer 32 is etched along the etched hole 220 to form the heater hole 230 with a tapered cross section that exposes the conductive contact layer 31, as shown. Figure 23 Depositing TiN or other conductive materials in the heater hole 230 to form the heater 40, as shown. Figure 24 shown.

[0124] After forming the phase change structure, a conductive material such as metal tungsten is deposited on the top electrode layer 34 in the phase change structure to form the bit line 21. Figure 26 shown.

[0125] Some embodiments of this specific embodiment provide a semiconductor structure and a method for forming the same. By forming a memory cell comprising a transistor and a phase change structure, wherein the active pillar in the transistor extends in a direction perpendicular to the top surface of the substrate and the phase change structure is positioned above the transistor in a direction perpendicular to the top surface of the substrate, thereby forming a phase change memory cell with a vertical transistor structure, the size of the memory cell in the semiconductor structure is reduced, the storage density and storage efficiency of the semiconductor structure are significantly improved, and the storage performance of the semiconductor structure is improved. In some embodiments of this specific embodiment, the size of the first end (i.e., the bottom end) of the phase change structure heater is smaller than the size of the second end (i.e., the top end) of the heater, resulting in a tapered cross-section of the heater, thereby reducing the contact area between the heater and the transistor, increasing the thermal efficiency of the heater, and improving the response speed of the memory cell, thereby further improving the performance of the semiconductor structure. In some embodiments of this specific embodiment, the phase change structure further includes a thermal insulation layer covering the sidewalls of the heater, thereby preventing heat loss from the heater, further ensuring the thermal efficiency of the heater, and thus improving the performance of the semiconductor structure.

[0126] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: substrate; A memory cell is located on the top surface of the substrate, the memory cell includes a transistor and a phase change structure, the transistor includes an active pillar extending along a first direction, the phase change structure is located above the active pillar along the first direction, the phase change structure includes a heater located above the active pillar along the first direction, a phase change layer located above the heater along the first direction, and a thermal insulation layer covering the side wall of the heater, the heater includes a first end electrically connected to the active pillar, and a second end opposite to the first end along the first direction, the projected area of ​​the first end on the top surface of the substrate is smaller than the projected area of ​​the second end on the top surface of the substrate, and the first direction is perpendicular to the top surface of the substrate.

2. The semiconductor structure according to claim 1, wherein: Also includes: a common source line, located between the memory cell and the substrate along the first direction, and electrically connected to the active pillar; A bit line is located above the phase change structure along the first direction and is electrically connected to the phase change structure.

3. The semiconductor structure according to claim 2, wherein: The plurality of storage units are arranged in an array along a second direction and a third direction on the top surface of the substrate, the second direction and the third direction are both parallel to the top surface of the substrate, and the second direction is orthogonal to the third direction; The common source line extends along the second direction and is electrically connected to the active pillars in the plurality of memory cells arranged at intervals along the second direction; The bit line extends along the second direction and is electrically connected to the phase change structures in the plurality of memory cells arranged at intervals along the second direction.

4. The semiconductor structure according to claim 3, wherein: The active pillar includes a channel region, a first source / drain region located below the channel region along the first direction, and a second source / drain region located above the channel region along the first direction, and the common source line is electrically connected to the first source / drain region; The semiconductor structure further comprises: A word line extends along a third direction and continuously covers the channel regions in the plurality of active pillars spaced apart along the third direction.

5. The semiconductor structure according to claim 4, wherein: Also includes: A conductive contact layer is located between the heater and the second source and drain region along the first direction, wherein one end of the conductive contact layer is electrically connected to the heater, and the other end of the conductive contact layer is electrically connected to the second source and drain region. The semiconductor structure according to claim 4 , wherein: The phase change structure further includes: a top electrode layer, located between the phase change layer and the bit line along the first direction, one end of the top electrode layer being electrically connected to the phase change layer, and the other end being electrically connected to the bit line; A first isolation layer covers the sidewalls of the top electrode layer, the phase change layer, and the heat insulation layer.

7. The semiconductor structure according to claim 4, wherein: Also includes: a second isolation layer, located between adjacent memory cells and covering a top surface of the word line, wherein the top surface of the second isolation layer has a groove, and the thermal insulation layer is also filled in the groove; Along the first direction, a top surface of the second isolation layer is located above a bottom surface of the heater.

8. A method for forming a semiconductor structure, characterized in that: The steps include: forming a substrate; A memory cell is formed and located above the substrate along a first direction, the memory cell comprising a transistor and a phase change structure, the transistor comprising an active pillar extending along the first direction, the phase change structure being located above the active pillar along the first direction, the phase change structure comprising a heater located above the active pillar along the first direction, a phase change layer located above the heater along the first direction, and a thermal insulation layer covering a sidewall of the heater, the heater comprising a first end electrically connected to the active pillar, and a second end opposite to the first end along the first direction, a projected area of ​​the first end on the top surface of the substrate being smaller than a projected area of ​​the second end on the top surface of the substrate, and the first direction being perpendicular to the top surface of the substrate.

9. The method for forming a semiconductor structure according to claim 8, wherein: The specific steps of forming the substrate include: providing an initial substrate; First dopant ions are implanted into the initial substrate to form a plurality of common source lines extending along a second direction and spaced apart along a third direction, the initial substrate remaining below the common source lines serves as the substrate, the second direction and the third direction are both parallel to the top surface of the substrate, and the second direction is orthogonal to the third direction.

10. The method for forming a semiconductor structure according to claim 9, wherein: The specific steps of forming a memory cell located above the substrate along a first direction include: Etching the initial substrate above the common source line to form a plurality of first trenches extending along the second direction and arranged at intervals along the third direction, and forming a plurality of second trenches extending along the third direction and arranged at intervals along the second direction, wherein the plurality of first trenches and the plurality of second trenches separate the initial substrate above the common source line into a plurality of active pillars arranged in an array along the second direction and the third direction; forming a conductive contact layer above the active pillar, wherein the conductive contact layer is electrically connected to the active pillar; The phase change structure is formed above the conductive contact layer along the first direction, and the phase change structure is electrically connected to the conductive contact layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The active pillar includes a channel region, a first source / drain region located below the channel region along the first direction, and a second source / drain region located above the channel region along the first direction, the common source line being electrically connected to the first source / drain region. Before forming the phase change structure located above the active pillar along the first direction, the following steps are further included: Word lines are formed in the first trench and the second trench, the word lines extending along the third direction, and the word lines continuously cover the channel regions in the plurality of active pillars spaced apart and distributed along the third direction.

12. The method for forming a semiconductor structure according to claim 10, wherein: The specific steps of forming the phase change structure located above the conductive contact layer along the first direction include: forming a thermal insulation layer including a heater hole on the conductive contact layer, wherein the heater hole exposes the conductive contact layer, a hole diameter of a bottom portion of the heater hole is smaller than a hole diameter of a top portion of the heater hole, the bottom portion of the heater hole faces the conductive contact layer, and the top portion of the heater hole is opposite to the bottom portion of the heater hole along the first direction; forming the heater in the heater hole and electrically connected to the conductive contact layer; forming the phase change layer on the heater; forming a top electrode layer on the phase change layer; A first isolation layer is formed covering sidewalls of the top electrode layer, sidewalls of the phase change layer, and sidewalls of the heat insulation layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The specific steps of forming a heat-insulating layer including heater holes on the conductive contact layer include: forming a heat-insulating layer on the conductive contact layer; forming a sacrificial layer covering the thermal insulation layer, wherein the sacrificial layer has a sacrificial hole exposing the thermal insulation layer; forming a filling layer having an air gap in the sacrificial hole; Etching back the filling layer to form an etching hole exposing the thermal insulation layer; The heat insulation layer is etched along the etched hole to form the heater hole.

14. The method for forming a semiconductor structure according to claim 13, wherein: The specific steps of forming a filling layer with an air gap in the sacrificial hole include: Etching back a portion of the sacrificial layer along the sacrificial hole so that the width of the bottom of the sacrificial hole is greater than the width of the top of the sacrificial hole, the bottom of the sacrificial hole faces the thermal insulation layer, and the top of the sacrificial hole and the bottom of the sacrificial hole are oppositely distributed along the first direction; The sacrificial hole is backfilled to form the filling layer having the air gap.

15. The method for forming a semiconductor structure according to claim 14, wherein: The sacrificial layer includes a first sacrificial layer covering the thermal insulation layer, and a second sacrificial layer located above the first sacrificial layer, and the sacrificial hole continuously penetrates the first sacrificial layer and the second sacrificial layer; The specific steps of etching back a portion of the sacrificial layer along the sacrificial hole include: A portion of the first sacrificial layer is etched back along the sacrificial hole to increase the diameter of the sacrificial hole in the first sacrificial layer.

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