Display device

Abstract

A display device includes: a substrate including an emission area and a non-emission area; a via layer disposed on the substrate and including a recess toward the substrate; a pixel defining layer overlapping the non-emission region and disposed on the via layer; a first bank layer disposed on the pixel defining layer and defining a first opening; a second bank layer disposed on the first bank layer and including a tip protruding from a side surface of the first bank layer toward the first opening; a first pixel electrode overlapping the recessed portion of the via layer and disposed on the substrate; a first emission layer disposed in the first opening on the first pixel electrode; and a first common electrode disposed in the first opening, on the first emission layer, and in contact with the first bank layer. The side surface of the first bank layer and the tip of the second bank layer overlap the recess of the via layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0073923, filed on June 9, 2023, and all benefits derived therefrom, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of information-oriented society, various demands for display devices are increasing. For example, display devices are being adopted by various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Among such flat panel display devices, the light-emitting display device may include a light-emitting element capable of self-luminescence, so that each of the pixels of the display panel can self-luminesce. Accordingly, the light-emitting display device can display an image without a backlight unit that supplies light to the display panel. Summary of the invention

[0005] Aspects of the present disclosure provide display devices that reduce structural defects associated with some bank structures.

[0006] Aspects of the present disclosure provide a display device that improves an aperture ratio, for example, by preventing or eliminating a decrease in the aperture ratio due to a structural defect of a bank structure.

[0007] It should be noted that the objects of the present disclosure are not limited to the objects described above, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0008] An embodiment of a display device includes: a substrate including an emission area and a non-emission area; a through-hole layer disposed on the substrate and including a recessed portion facing the substrate; a pixel defining layer overlapping the non-emission area and disposed on the through-hole layer; a first embankment layer disposed on the pixel defining layer and defining a first opening; a second embankment layer disposed on the first embankment layer and including a tip protruding from a side surface of the first embankment layer toward the first opening; a first pixel electrode overlapping the recessed portion of the through-hole layer and disposed on the substrate; a first emission layer disposed in the first opening and on the first pixel electrode; and a first common electrode disposed in the first opening, on the first emission layer, and in contact with the first embankment layer, wherein the side surface of the first embankment layer and the tip of the second embankment layer may overlap with the recessed portion of the through-hole layer.

[0009] The first portion of the via layer may have a first thickness and may overlap the recessed portion; the second portion of the via layer may have a second thickness and may not overlap the recessed portion; and the first thickness may be different from the second thickness.

[0010] The first thickness may be smaller than the second thickness.

[0011] The first opening may overlap the recessed portion of the via layer.

[0012] A width of the first opening in a direction parallel to the substrate may be smaller than a width of the recessed portion of the via layer.

[0013] The via layer may further include: an inclined surface overlapping the non-emission region and not overlapping the recessed portion.

[0014] The first pixel electrode may be in contact with the inclined surface.

[0015] The pixel defining layer may be spaced apart from the first pixel electrode in a direction perpendicular to the substrate in the recessed portion of the via layer.

[0016] The display device may further include: a pattern layer disposed in a region where the first pixel electrode and the pixel defining layer are spaced apart from each other, wherein the pattern layer may overlap the recessed portion of the through hole layer and may contact the first emission layer.

[0017] The display device may further include: a first organic pattern disposed on the second embankment layer, wherein the first organic pattern may include a material that is the same as a material of the first emission layer and may be separated from the first emission layer; and a first electrode pattern disposed on the first organic pattern, wherein the first electrode pattern may include a material that is the same as a material of the first common electrode and may be separated from the first common electrode, wherein the first organic pattern and the first electrode pattern may overlap with the recessed portion of the through-hole layer.

[0018] The display device may further include: a second pixel electrode, separated from the first pixel electrode, wherein a through-hole layer may be interposed between the second pixel electrode and the first pixel electrode; a second emission layer, disposed on the second pixel electrode; a second common electrode, disposed on the second emission layer; and a second electrode pattern, disposed on the second embankment layer, wherein the second electrode pattern may include the same material as that of the second common electrode and may be separated from the second common electrode.

[0019] The display device may further include: a first inorganic layer covering the first common electrode and the first electrode pattern; and a second inorganic layer covering the second common electrode and the second electrode pattern, wherein the first inorganic layer and the second inorganic layer may be spaced apart from each other.

[0020] The display device may further include: an auxiliary through hole layer, arranged between the substrate and the through hole layer, wherein a surface of the auxiliary through hole layer may overlap with the recessed portion of the through hole layer and may be exposed through the recessed portion, and wherein the exposed surface of the auxiliary through hole layer may contact the first pixel electrode.

[0021] The via layer may further include: a first surface facing the auxiliary via layer; a second surface opposite to the first surface; and an inclined surface connecting the first surface with the second surface.

[0022] A width of the first surface may be greater than a width of the second surface, and wherein an angle formed by the first surface and the inclined surface may be an acute angle.

[0023] The via layer and the auxiliary via layer may include the same material.

[0024] The via layer and the auxiliary via layer may include different materials.

[0025] An embodiment of a display device includes: a substrate including an emission area and a non-emission area; a through-hole layer disposed on the substrate and including a recessed portion facing the substrate; a pixel defining layer overlapping the non-emission area, disposed on the through-hole layer and defining a first opening; a first embankment layer overlapping the non-emission area and disposed on the pixel defining layer; a second embankment layer disposed on the first embankment layer and including a tip protruding from a side surface of the first embankment layer toward the first opening; a first pixel electrode disposed in the recessed portion of the through-hole layer and on the through-hole layer; a first emission layer disposed in the first opening and on the first pixel electrode; and a first common electrode disposed in the first opening, on the first emission layer, and in contact with the first embankment layer, wherein the first opening may overlap with the recessed portion of the through-hole layer.

[0026] A width of the first opening may be smaller than a width of the recessed portion of the via layer.

[0027] A side surface of the pixel defining layer facing the first opening may be located in the recessed portion of the via layer, and the side surface of the pixel defining layer may overlap with the via layer in a direction parallel to the substrate.

[0028] According to an embodiment of the present disclosure, a display device having an improved electrical contact between a common electrode and a bank structure is described, wherein electrical contact failure between the common electrode and the bank structure is alleviated or reduced.

[0029] According to an embodiment of the present disclosure, a display device with improved lifespan and efficiency is described.

[0030] It should be noted that the effects of the present disclosure are not limited to those described herein, and other effects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] These and / or other features of the embodiments of the present invention will become more apparent and more easily understood from the following description of the embodiments in conjunction with the accompanying drawings.

[0032] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0033] Figure 2 is a perspective view illustrating a display device included in an electronic device according to an embodiment of the present disclosure.

[0034] Figure 3 Observed from the side Figure 2 A cross-sectional view of a display device.

[0035] Figure 4 is a plan view showing a display layer of a display device according to an embodiment of the present disclosure.

[0036] Figure 5 is a plan view showing the arrangement of emission areas in a first display area of ​​a display device according to an embodiment.

[0037] Figure 6 is along Figure 5 A cross-sectional view taken along line X1-X1'.

[0038] Figure 7 yes Figure 6 An enlarged cross-sectional view of region A.

[0039] Figure 8 yes Figure 7 An enlarged cross-sectional view of region T.

[0040] Fig. 9 is along Figure 5 A cross-sectional view of another example taken along line X1-X1'.

[0041] Fig.10 yes Fig. 9 An enlarged cross-sectional view of region P. DETAILED DESCRIPTION

[0042] The present invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments of the present invention are shown. However, the present invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the scope of the present invention to those skilled in the art. Throughout the specification, the same reference numerals indicate the same components. In the attached figures, the thickness of layers and zones is exaggerated for clarity.

[0043] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0044] It should be understood that although the terms "first", "second", or "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or are used to facilitate their description and explanation. For example, when discussing a "first element" in the description, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the teachings herein.

[0045] The terms used herein are only used to describe the purpose of specific embodiments, and are not intended to be limited. As used herein, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless otherwise clearly indicated in the context. For example, "an element" has the same meaning as "at least one element", unless otherwise clearly indicated in the context. "At least one" should not be interpreted as being limited to "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items. It will be further understood that when used in this specification, the term "includes" and / or its deformation or "comprising" and / or its deformation indicates the existence of stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their groups.

[0046] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship between one element and another element illustrated in the figure. It should be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figure. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other element will then be oriented to be on the "upper" side of the other element. Therefore, the term "lower" can cover both "lower" and "upper" orientations, which depends on the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the term "below" or "below" can cover both upper and lower orientations.

[0047] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0049] Embodiments are described herein with reference to schematically illustrated cross-sectional illustrations of idealized embodiments. Thus, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the zones illustrated herein, but should include deviations in shapes due to, for example, manufacturing. For example, a zone illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the claims.

[0050] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0051] Figure 1 is a perspective view of an electronic device 1 according to an embodiment of the present disclosure.

[0052] refer to Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 may refer to any electronic device that provides a display screen. For example, the electronic device 1 may include a television, a laptop computer, a monitor, an electronic billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display device, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera or a video camera, etc.

[0053] The electronic device 1 may include a display device 10 for providing a display screen (see Figure 2). Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting diode display device, a quantum dot light emitting display device, a plasma display device, and a field emission display device. In the description herein, an organic light emitting diode display device is used as an example of the display device 10, but the present disclosure is not limited thereto. Any other suitable display device may be used in association with the application of the technical idea of ​​the present disclosure.

[0054] The shape of the electronic device 1 may be modified in various ways. For example, in a plan view, the electronic device 1 may have a shape such as a rectangle with a longer horizontal side, a rectangle with a longer vertical side, a square, a quadrilateral with rounded corners (vertices), other polygons, and a circle. The shape of the display area DA of the electronic device 1 may also be similar to the overall shape of the electronic device 1. Figure 1 In the example shown in , the electronic device 1 has a rectangular shape having longer sides in the second direction (Y-axis direction).

[0055] The electronic device 1 may include a display area DA and a non-display area NDA. An image may be displayed in the display area DA. No image is displayed in the non-display area NDA. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may generally occupy the center of the electronic device 1.

[0056] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. Components for adding various functions to the electronic device 1 may be provided in the second display area DA2 and the third display area DA3. In other words, the second display area DA2 and the third display area DA3 may be referred to as component areas.

[0057] Figure 2 is a perspective view showing a display device 10 included in the electronic device 1 according to an embodiment of the present disclosure.

[0058] refer to Figure 2According to an embodiment of the present disclosure, an electronic device 1 may include a display device 10. The display device 10 may provide a display screen for displaying an image in the electronic device 1. When observed from the top, the display device 10 may have a shape similar to that of the electronic device 1. For example, similar to the rectangular shape of the electronic device 1, the display device 10 may have a rectangular shape having a shorter side in a first direction (X-axis direction) and a longer side in a second direction (Y-axis direction). The corner where the shorter side in the first direction (X-axis direction) intersects with the longer side in the second direction (Y-axis direction) may be rounded with a predetermined curvature. However, it should be understood that the present disclosure is not limited to this. The corner may be formed at a right angle. The shape of the display device 10 when observed from the top is not limited to a quadrilateral shape, but may be formed into a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0059] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0060] The display panel 100 may include a main area MA and a sub-area SBA (also referred to herein as an auxiliary area or a sub-area).

[0061] The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA located around the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may output light from a plurality of emission areas or a plurality of open areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0062] In an example, the self-luminous element may include but is not limited to at least one of a micro light emitting diode (micro LED), an organic light emitting diode including an organic emission layer, a quantum dot light emitting diode (quantum dot LED) including a quantum dot emission layer, and an inorganic light emitting diode (inorganic LED) including an inorganic semiconductor.

[0063] The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) that applies a gate signal to a gate line, and the non-display area NDA may include a fan-out line (not shown) that connects the display driver 200 to the display area DA.

[0064] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (third direction or Y-axis direction). The sub-area SBA may include a pad connected to the display driver 200 and the circuit board 300. According to another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad may be disposed in the non-display area NDA.

[0065] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may apply a power supply voltage to a voltage line, and may supply a gate control signal to a gate driver. The display driver 200 may be implemented as an integrated circuit (IC), and may be attached to the display panel 100 by a chip on glass (COG) technology, a chip on plastic (COP) technology, or ultrasonic bonding. For example, the display driver 200 may be disposed in a sub-area SBA, and may overlap with the main area MA in a thickness direction as the sub-area SBA is bent. In another example, the display driver 200 may be mounted on a circuit board 300.

[0066] The circuit board 300 may be attached to the pad area of ​​the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pads of the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as, for example, a chip on film (COF).

[0067] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to a touch sensing unit (e.g., a touch sensing layer) of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and may sense a change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal of a predetermined frequency. The touch driver 400 may determine whether there is an input, and may find out the coordinates of the input based on the amount of change in capacitance between the touch electrodes. The touch driver 400 may be implemented as an integrated circuit (IC).

[0068] Figure 3 is from Figure 2 A cross-sectional view of the display device 10 observed from the side of the display device 10.

[0069] refer to Figure 3, the display panel 100 may include a display layer DPL, a touch sensing layer 180 and a color filter layer 190. The display layer DPL may include a substrate 110, a thin film transistor layer 130, an emission material layer 150 and a thin film encapsulation layer 170.

[0070] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate 110 may include, but is not limited to, a polymer resin such as, for example, polyimide (PI). In another example, the substrate 110 may include a glass material or a metal material.

[0071] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may include a plurality of thin film transistors forming a pixel circuit in a pixel. The thin film transistor layer 130 may include a gate line, a data line, a voltage line, a gate control line, a fan-out line for connecting the display driver 200 to the data line, a lead for connecting the display driver 200 to the pad, and other components supporting the functions of the display device 10. Each of the thin film transistors may include a semiconductor layer, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of a non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0072] The thin film transistor layer 130 may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The gate lines, data lines, voltage lines, and thin film transistors in each of the pixels in the thin film transistor layer 130 may be disposed in the display area DA. The gate control lines and fan-out lines in the thin film transistor layer 130 may be disposed in the non-display area NDA. The leads of the thin film transistor layer 130 may be disposed in the sub-area SBA.

[0073] The emission material layer 150 may be disposed on the thin film transistor layer 130. The emission material layer 150 may include a plurality of light emitting elements each including a first electrode (or pixel electrode), a second electrode (or common electrode) and an emission layer to emit light, and a pixel defining layer for defining each pixel. The plurality of light emitting elements in the emission material layer 150 may be disposed in the display area DA.

[0074] According to an embodiment of the present disclosure, the emission layer may be an organic emission layer including an organic material. The emission layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer 130 and the second electrode receives a cathode voltage (or a common voltage or a low level voltage), holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, so that the holes and electrons are recombined in the organic light emitting layer to emit light.

[0075] According to another embodiment, the light emitting elements may include micro light emitting diodes, quantum dot light emitting diodes each including a quantum dot emission layer, or inorganic light emitting diodes each including an inorganic semiconductor.

[0076] The thin film encapsulation layer 170 may cover the upper surface and the side surface of the emission material layer 150 and may protect the emission material layer 150. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the emission material layer 150.

[0077] The touch sensing layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensing layer 180 may include a plurality of touch electrodes for sensing a user's touch through capacitive sensing, and the touch sensing layer 180 may include touch lines connecting the plurality of touch electrodes with the touch driver 400. For example, the touch sensing layer 180 may sense a user's touch through mutual capacitance sensing or self capacitance sensing.

[0078] In another example, the touch sensing layer 180 may be disposed on a separate substrate disposed on the display layer DPL. In this case, the substrate supporting the touch sensing layer 180 may be a base member encapsulating the display layer DPL.

[0079] A plurality of touch electrodes of the touch sensing layer 180 may be disposed in a touch sensor region overlapping the display area DA. A touch line of the touch sensing layer 180 may be disposed in a touch peripheral region overlapping the non-display area NDA.

[0080] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may output or receive infrared light, ultraviolet light, and / or light in the visible range. For example, the optical device 500 may be an optical sensor such as a proximity sensor, an illumination sensor, a camera sensor, and an image sensor that senses light incident on the display device 10.

[0081] The color filter layer 190 may be disposed on the thin film encapsulation layer 170 corresponding to the emission area. The color filter layer 190 may include a plurality of color filters respectively associated with the plurality of emission areas. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer 190 may absorb some of the light introduced from outside the display device 10 to reduce reflection of external light. Accordingly, the color filter layer 190 may prevent color distortion caused by reflection of external light.

[0082] In some embodiments, the color filter layer 190 is directly disposed on the thin film encapsulation layer 170, and the display device 10 may be implemented without a separate substrate for the color filter layer 190. Therefore, the thickness of the display device 10 may be relatively small.

[0083] Figure 4 1 is a plan view showing a display layer DPL of a display device 10 according to one or more embodiments. Figure 4 , the display layer DPL may include a main area MA and a sub-area SBA, and the main area MA may include a display area DA and a non-display area NDA.

[0084] The display area DA may be disposed at the center of the display device 10. A plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of voltage lines VL may be disposed in the display area DA. Each of the plurality of pixels PX may be defined as a minimum unit of outputting light.

[0085] The plurality of gate lines GL may supply gate signals received from the gate driver 210 to the plurality of pixels PX. The plurality of gate lines GL may extend in a first direction (X-axis direction) and may be spaced apart from each other in a second direction (Y-axis direction) crossing the first direction (X-axis direction).

[0086] The plurality of data lines DL may supply the plurality of pixels PX with data voltages received from the display driver 200. The plurality of data lines DL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction).

[0087] The plurality of voltage lines VL may apply a power supply voltage received from the display driver 200 to the plurality of pixels PX. The power supply voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low level voltage. The plurality of voltage lines VL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction).

[0088] The non-display area NDA may surround the display area DA. A gate driver 210, a fan-out line FOL, and a gate control line GCL may be disposed in the non-display area NDA. The gate driver 210 may generate a plurality of gate signals based on a gate control signal, and may sequentially supply the plurality of gate signals to a plurality of gate lines GL in a predetermined order.

[0089] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0090] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210.

[0091] The sub area SBA may include the display driver 200 and the pad area DPA.

[0092] The display driver 200 may output signals and voltages for driving the display panel 100 to the fan-out lines FOL. The display driver 200 may supply data voltages to the data lines DL through the fan-out lines FOL. The data voltages may be applied to the plurality of pixels PX in association with controlling the brightness of the plurality of pixels PX. The display driver 200 may supply gate control signals to the gate driver 210 through the gate control lines GCL.

[0093] The pad area DPA may be disposed at an edge of the sub-area SBA. The pad area DPA may be electrically connected to the circuit board 300 using a material such as, for example, an anisotropic conductive film and a self-assembly anisotropic conductive paste (SAP).

[0094] The pad area DPA may include a plurality of display pads DP. The display pads DP may be connected to a graphics system (not shown) through the circuit board 300. The plurality of display pads DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0095] Figure 5 is a plan view showing the arrangement of emission areas in the first display area DA1 of the display device 10 according to the embodiment.

[0096] refer to Figure 5 , the display device 10 may include a plurality of emission areas EA1 , EA2 , and EA3 and a non-emission area BA arranged in the display area DA. Figure 5 The display area shown in FIG. 1 is the first display area DA1, and the plurality of emission areas EA1, EA2, and EA3 may be located in the first display area DA1. However, it should be understood that the plurality of emission areas EA1, EA2, and EA3 may be located in the second and third display areas DA2 and DA3 of the display area DA.

[0097] The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. The first to third emission areas EA1, EA2, and EA3 may emit red light, green light, and blue light, respectively. The colors of the light emitted from the emission areas EA1, EA2, and EA3, respectively, may be based on the light emitting elements ED1, ED2, and ED3 (see FIG. 1 ) disposed in the emission material layer 150 described later herein. Figure 6 ) type. According to an embodiment of the present disclosure, the first emission area EA1 emits a red first light, the second emission area EA2 emits a green second light, and the third emission area EA3 emits a blue third light. However, it should be understood that the present disclosure is not limited to this. For example, the first emission area EA1, the second emission area EA2 and / or the third emission area EA3 can be configured to emit light different from the light described herein.

[0098] The emission areas EA1, EA2 and EA3 may be arranged as Matrix (e.g., diamond Matrix). For example, the first emission area EA1 and the third emission area EA3 may be spaced apart from each other in the first direction (X-axis direction), and may be alternately arranged in the first direction (X-axis direction) and the second direction (Y-axis direction). Regarding the arrangement of the emission areas EA1, EA2, and EA3, in the first row R1 and the third row R3, the first emission area EA1 and the third emission area EA3 may be alternately arranged in the first direction (X-axis direction). In the first column C1 and the third column C3, the first emission area EA1 and the third emission area EA3 may be alternately arranged in the second direction (Y-axis direction).

[0099] The second emission area EA2 may be spaced apart from another adjacent second emission area EA2 in the first direction (X-axis direction) and the second direction (Y-axis direction), and the second emission area EA2 may be spaced apart from the adjacent first emission area EA1 and the third emission area EA3 in the fourth direction DR4 or the fifth direction DR5. A plurality of second emission areas EA2 may be repeatedly arranged in the first direction (X-axis direction) and the second direction (Y-axis direction), and the second emission area EA2 and the first emission area EA1 or the second emission area EA2 and the third emission area EA3 may be alternately arranged in the fourth direction DR4 or the fifth direction DR5. With regard to the arrangement of the emission areas EA1, EA2, and EA3, in the second row R2 and the fourth row R4, the second emission area EA2 may be repeatedly arranged in the first direction (X-axis direction), and in the second column C2 and the fourth column C4, the second emission area EA2 may be repeatedly arranged in the second direction (Y-axis direction).

[0100] Each of the first to third emission areas EA1, EA2, and EA3 may be defined by a first opening OP1 and a second opening OP2 formed by an inorganic pixel defining layer 151 (see FIG. 1 ) described later herein of the emission material layer 150. Figure 6 ) and dike structure 160 (see Figure 6 )form.

[0101] The non-emission area BA may be located around the emission areas EA1, EA2, and EA3. For example, the non-emission area BA may surround the emission areas EA1, EA2, and EA3 (eg, referring to the XY plane). No light passes through the non-emission area BA. For example, the light blocking layer BM (see Figure 6 ) and the inorganic pixel defining layer 151 may overlap the non-emission area BA.

[0102] Figure 6 is a cross-sectional view of a portion of the display device 10 according to an embodiment, which shows cross sections of the display layer DPL, the touch sensing layer 180 , and the color filter layer 190 .

[0103] refer to Figure 6 , the display layer DPL may include a substrate 110 , a thin film transistor layer 130 , an emission material layer 150 , and a thin film encapsulation layer 170 .

[0104] The substrate 110 has been described herein, and for the sake of brevity, repeated description of the substrate 110 is omitted.

[0105] The thin film transistor layer 130 may include a first buffer layer 111, a bottom metal layer BML, a second buffer layer 113, a thin film transistor TFT, a gate insulating layer 131, a first interlayer dielectric layer 133, a capacitor electrode CPE, a second interlayer dielectric layer 135, a first connection electrode CNE1, a planarization layer 137, a second connection electrode CNE2, and a through hole layer 139.

[0106] The first buffer layer 111 may be disposed on the substrate 110. The first buffer layer 111 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the first buffer layer 111 may include a plurality of inorganic films stacked one by one.

[0107] The bottom metal layer BML may be disposed on the first buffer layer 111. For example, the bottom metal layer BML may be a single layer or a multilayer formed of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and alloys thereof.

[0108] The second buffer layer 113 may cover the first buffer layer 111 and the bottom metal layer BML. The second buffer layer 113 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the second buffer layer 113 may include a plurality of inorganic films stacked one by one.

[0109] The thin film transistor TFT may be disposed on the second buffer layer 113 and may form corresponding pixel circuits of a plurality of pixels PX. For example, each thin film transistor TFT may be a driving transistor or a switching transistor of a pixel circuit. Each thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0110] The semiconductor layer ACT may be disposed on the second buffer layer 113. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in a thickness direction and may be insulated from the gate electrode GE by the gate insulating layer 131. A material of a portion of the semiconductor layer ACT may be made conductive to form the source electrode SE and the drain electrode DE.

[0111] The gate electrode GE may be disposed on the gate insulating layer 131. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer 131 interposed therebetween.

[0112] The gate insulating layer 131 may be disposed on the semiconductor layer ACT. For example, the gate insulating layer 131 may cover the semiconductor layer ACT and the second buffer layer 113 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer 131 may include a contact hole through which the first connection electrode CNE1 passes.

[0113] The first interlayer dielectric layer 133 may cover the gate electrode GE and the gate insulating layer 131. The first interlayer dielectric layer 133 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer dielectric layer 133 may be connected to the contact hole of the gate insulating layer 131 and the contact hole of the second interlayer dielectric layer 135.

[0114] The capacitor electrode CPE may be disposed on the first interlayer dielectric layer 133. The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0115] The second interlayer dielectric layer 135 may cover the capacitor electrode CPE and the first interlayer dielectric layer 133. The second interlayer dielectric layer 135 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer dielectric layer 135 may be connected to the contact hole of the first interlayer dielectric layer 133 and the contact hole of the gate insulating layer 131.

[0116] The first connection electrode CNE1 may be disposed on the second interlayer dielectric layer 135. Each first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer dielectric layer 135, the first interlayer dielectric layer 133, and the gate insulating layer 131 to contact the drain electrode DE of the thin film transistor TFT.

[0117] The planarization layer 137 may cover the first connection electrode CNE1 and the second interlayer dielectric layer 135. The planarization layer 137 may protect the thin film transistor TFT. The planarization layer 137 may include a contact hole through which the second connection electrode CNE2 passes.

[0118] The second connection electrode CNE2 may be disposed on the planarization layer 137. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 with the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3, respectively. For example, each second connection electrode CNE2 may be inserted into a contact hole formed in the planarization layer 137 to contact the corresponding first connection electrode CNE1.

[0119] The via layer 139 may cover the second connection electrode CNE2 and the planarization layer 137. The via layer 139 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 pass.

[0120] The through-hole layer 139 may be formed of an insulating material. For example, the through-hole layer 139 may be formed of a single layer or multiple layers of an inorganic material, an organic material, or an organic / inorganic composite material, and may be formed by various deposition methods. In some embodiments, the through-hole layer 139 may be formed of any one or more of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, polyphenylene sulfide resin, and benzocyclobutene (BCB). In some embodiments, the through-hole layer 139 may be formed of one or more materials selected from the group consisting of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, polyphenylene sulfide resin, and benzocyclobutene (BCB). Additionally or alternatively, the through-hole layer 139 may include an organic protective film such as a planarization film that is transparent and has a flowability support for relieving and leveling the bending of the underlying structure.

[0121] The emission material layer 150 may be disposed on the thin film transistor layer 130. The emission material layer 150 may include light emitting elements ED1, ED2, and ED3, an inorganic pixel defining layer 151, and a plurality of embankment structures 160. The light emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, emission layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, respectively.

[0122] The display device 10 may include a plurality of emission areas EA1, EA2, and EA3 arranged in the display area DA. In some embodiments, the first to third emission areas EA1, EA2, and EA3 may have the same area or size. For example, the second opening OP2 formed by the embankment structure 160 in the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have the same diameter. However, it should be understood that the present disclosure is not limited thereto. For example, the respective areas or sizes of the first to third emission areas EA1, EA2, and EA3 of the display device 10 may be different from each other. For example, the area of ​​the second emission area EA2 may be greater than the area of ​​the first emission area EA1 and the area of ​​the third emission area EA3, and the area of ​​the third emission area EA3 may be greater than the area of ​​the first emission area EA1. The intensity of light emitted from the emission areas EA1, EA2, and EA3, respectively, may be based on the size of the emission areas EA1, EA2, and EA3. The color of the image displayed on the display device 10 or the electronic device 1 may be controlled by adjusting the size of the emission areas EA1, EA2, and EA3. That is, for example, the sizes of the emission areas EA1 , EA2 , and EA3 may be adjusted as needed according to the colors of images to be provided by the display device 10 and the electronic device 1 .

[0123] A first emission area EA1, a second emission area EA2, and a third emission area EA3 disposed adjacent to each other may form a pixel group. The pixel group may represent black and white or grayscale by emitting light of different colors from the emission areas EA1, EA2, and EA3. However, it should be understood that the present disclosure is not limited thereto. The combination of emission areas EA1, EA2, and EA3 forming a single pixel group may be modified depending on the arrangement of the emission areas EA1, EA2, and EA3 and the color of the light emitted from the emission areas EA1, EA2, and EA3.

[0124] The pixel electrodes AE1, AE2, and AE3 may be disposed on the via layer 139. The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2.

[0125] The pixel electrodes AE1, AE2, and AE3 may be disposed in the emission areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first emission area EA1, a second pixel electrode AE2 disposed in the second emission area EA2, and a third pixel electrode AE3 disposed in the third emission area EA3. The pixel electrodes AE1, AE2, and AE3 may be spaced apart from each other by the through-hole layer 139. Specifically, the pixel electrodes AE1, AE2, and AE3 may be disposed in different emission areas EA1, EA2, and EA3, respectively, to form light emitting elements ED1, ED2, and ED3 that emit light of different colors.

[0126] According to an embodiment of the present disclosure, the pixel electrodes AE1, AE2, and AE3 may have: a material layer having a high work function (e.g., greater than or equal to a target threshold work function) (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In 2 O 3 )) and a stacked structure of a reflective material layer (such as, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof). In some embodiments, for the pixel electrodes AE1, AE2 and AE3, a layer with a higher work function can be set at a layer higher than the reflective material layer, so that the layer with a higher work function is closer (for example, closer in the Y-axis direction) to the emission layers EL1, EL2 and EL3, respectively. Non-limiting examples of the pixel electrodes AE1, AE2 and AE3 include ITO / Mg, ITO / MgF 2 , ITO / Ag and ITO / Ag / ITO multilayer structures.

[0127] The inorganic pixel defining layer 151 may overlap the non-emission area BA, and may be disposed on the pixel electrodes AE1 , AE2 , and AE3 and the via hole layer 139 .

[0128] According to some embodiments, the inorganic pixel defining layer 151 may define a plurality of first openings OP1 for forming emission areas EA1, EA2, and EA3. The inorganic pixel defining layer 151 may expose the pixel electrodes AE1, AE2, and AE3 in a region overlapping the first openings OP1.

[0129] The inorganic pixel defining layer 151 (also referred to as an inorganic pixel defining film) may include an inorganic insulating material. For example, the inorganic pixel defining layer 151 may include any one or more of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0130] The embankment structure 160 may be disposed on the inorganic pixel defining layer 151. The embankment structure 160 may define a plurality of second openings OP2 forming emission areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3 of the display device 10 may correspond to the second openings OP2 of the embankment structure 160. The embankment structure 160 may include a first embankment layer 161 and a second embankment layer 163 including different metal materials and having different structures to perform different functions.

[0131] The emission layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3, respectively. The emission layers EL1, EL2, and EL3 may be organic emission layers formed of an organic material and may be formed on the pixel electrodes AE1, AE2, and AE3 by a deposition process. In an example in which the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons may move to the emission layers EL1, EL2, and EL3, respectively, through the hole transport layer and the electron transport layer, and the holes and electrons are recombined in the emission layers EL1, EL2, and EL3 to emit light.

[0132] The emission layers EL1, EL2, and EL3 may include a first emission layer EL1, a second emission layer EL2, and a third emission layer EL3, respectively, which are arranged in different emission areas EA1, EA2, and EA3. The first emission layer EL1 may be arranged on the first pixel electrode AE1 in the first emission area EA1, the second emission layer EL2 may be arranged on the second pixel electrode AE2 in the second emission area EA2, and the third emission layer EL3 may be arranged on the third pixel electrode AE3 in the third emission area EA3. The first to third emission layers EL1, EL2, and EL3 may be emission layers of the first to third light-emitting elements ED1, ED2, and ED3, respectively. The first emission layer EL1 may emit light of a first color (e.g., red light), the second emission layer EL2 may emit light of a second color (e.g., green light), and the third emission layer EL3 may emit light of a third color (e.g., blue light).

[0133] According to some embodiments of the present disclosure, the emission layers EL1, EL2, and EL3 may be partially disposed between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151. For example, corresponding portions of the emission layers EL1, EL2, and EL3 may be disposed between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151. The inorganic pixel defining layer 151 may be disposed on the pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the upper surfaces of the pixel electrodes AE1, AE2, and AE3. In some embodiments, the deposition process of the emission layers EL1, EL2, and EL3 may be performed in a manner such that the materials of the emission layers EL1, EL2, and EL3 are deposited in a direction inclined relative to the upper surface of the substrate 110 rather than in a direction perpendicular to the upper surface of the substrate 110 (or in a direction inclined relative to the upper surface of the substrate 110 in addition to a direction perpendicular to the upper surface of the substrate 110). By depositing the material of the emission layers EL1, EL2, and EL3 in an inclined direction, the emission layers EL1, EL2, and EL3 may be disposed on the upper surfaces of the pixel electrodes AE1, AE2, and AE3 exposed by the second openings OP2 of the embankment structure 160, and the emission layers EL1, EL2, and EL3 may fill the space between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151. The deposition process of the emission layers EL1, EL2, and EL3 is described in detail later herein.

[0134] The temporary protective layer may be disposed between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3, and may be partially removed in the process of preparing the display device 10. In an example, the emission layers EL1, EL2, and EL3 may be disposed in an area or gap corresponding to the position where the temporary protective layer is partially removed, and therefore, the lower surface of the inorganic pixel defining layer 151 may be spaced apart from the pixel electrodes AE1, AE2, and AE3. The unremoved portion of the temporary protective layer may be retained as a residual pattern layer (or pattern layer) 157 between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3. Accordingly, the area or gap between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3 may be filled with the residual pattern layer 157 and the emission layers EL1, EL2, and EL3.

[0135] Common electrodes CE1, CE2, and CE3 may be disposed on emission layers EL1, EL2, and EL3, respectively. Common electrodes CE1, CE2, and CE3 include transparent conductive materials to allow light generated in emission layers EL1, EL2, and EL3 to exit. Common electrodes CE1, CE2, and CE3 may receive a common voltage or a low-level voltage. When pixel electrodes AE1, AE2, and AE3 receive a voltage equal to the data voltage and common electrodes CE1, CE2, and CE3 receive a low-level voltage, a potential difference may be formed between pixel electrodes AE1, AE2, and AE3 and common electrodes CE1, CE2, and CE3, so that emission layers EL1, EL2, and EL3 may emit light.

[0136] For example, the common electrodes CE1, CE2, and CE3 may include, but are not limited to, silver (Ag). The common electrodes CE1, CE2, and CE3 may each include a material layer having a low work function (e.g., lower than a target threshold work function) such as, for example, Li, Ca, Al, Mg, Pt, Pd, Ni, Au, Nd, Ir, Cr, and Ba, or compounds thereof (e.g., LiF or BaF 2 ) or a mixture (for example, a mixture of Ag and Mg), or a multilayer material such as LiF / Ca or LiF / Al). The common electrodes CE1, CE2 and CE3 may each further include a transparent metal oxide layer disposed on the material layer having a low work function.

[0137] The common electrodes CE1, CE2 and CE3 may include a first common electrode CE1, a second common electrode CE2 and a third common electrode CE3 respectively disposed in different emission areas EA1, EA2 and EA3. The first common electrode CE1 may be disposed on the first emission layer EL1 in the first emission area EA1, the second common electrode CE2 may be disposed on the second emission layer EL2 in the second emission area EA2, and the third common electrode CE3 may be disposed on the third emission layer EL3 in the third emission area EA3.

[0138] In the display device 10 according to an embodiment of the present disclosure, the common electrodes CE1, CE2, and CE3 respectively disposed in different emission areas EA1, EA2, and EA3 may be indirectly connected. For example, the common electrodes CE1, CE2, and CE3 respectively disposed in different emission areas EA1, EA2, and EA3 are not directly connected, but may be electrically connected through the first bank layer 161 of the bank structure 160. Accordingly, a portion of the common electrodes CE1, CE2, and CE3 may be disposed on a side surface of the first bank layer 161 of the bank structure 160.

[0139] The capping layer 159 may be disposed on the common electrodes CE1, CE2, and CE3. The capping layer 159 may include an inorganic insulating material to cover the light emitting elements ED1, ED2, and ED3 and the pattern disposed on the embankment structure 160. The capping layer 159 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by the external air, and may prevent the pattern disposed on the embankment structure 160 from being delaminated during the process of preparing the display device 10. In an embodiment, the capping layer 159 may include any one or more of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0140] The thin film encapsulation layer 170 may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure 160, and may cover a plurality of light emitting elements ED1, ED2, and ED3 and the embankment structure 160. The thin film encapsulation layer 170 may include at least one inorganic film capable of reducing or preventing oxygen or moisture from penetrating into the emission material layer 150. The thin film encapsulation layer 170 may include at least one organic film capable of protecting the emission material layer 150 from foreign matter such as, for example, dust. According to an embodiment of the present disclosure, the thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 sequentially stacked one after another. In an example, the first encapsulation layer 171 and the third encapsulation layer 175 may be inorganic encapsulation layers, and the second encapsulation layer 173 disposed therebetween may be an organic encapsulation layer. Additionally or alternatively, the first encapsulation layer 171, the second encapsulation layer 173, and the third encapsulation layer 175 may include any suitable combination of inorganic encapsulation layers and / or organic encapsulation layers.

[0141] Each of the first encapsulation layer 171 and the third encapsulation layer 175 may include one or more inorganic insulating materials. The inorganic insulating material may include any one or more of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0142] The second encapsulation layer 173 may include a polymer material. The polymer material may include any one or more of acrylic resin, epoxy resin, polyimide, polyethylene, etc. For example, the second encapsulation layer 173 may include any one or more of acrylic resins such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer 173 may be formed by curing a monomer or by coating a polymer.

[0143] The first encapsulation layer 171 may include a first inorganic layer 171 - 1 , a second inorganic layer 171 - 2 , and a third inorganic layer 171 - 3 , respectively disposed in different emission areas EA1 , EA2 , and EA3 .

[0144] The touch sensing layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensing layer 180 may include a touch buffer layer 181, a touch insulating layer 183, a touch electrode TE, and a touch protection layer 185.

[0145] The touch buffer layer 181 may be disposed on the thin film encapsulation layer 170. The touch buffer layer 181 may be insulating and support optical functions. The touch buffer layer 181 may include at least one inorganic film. Optionally, the touch buffer layer 181 may be omitted. Although not shown in the drawings, in some embodiments, a connection electrode for electrically connecting between the touch electrodes TE may be disposed on the touch buffer layer 181. The connection electrode may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO). Additionally or alternatively, the connection electrode may be formed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0146] The touch insulating layer 183 may cover the touch buffer layer 181. The touch insulating layer 183 may have an insulating function. For example, the touch insulating layer 183 may be an inorganic layer including any one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. In some examples, the touch insulating layer 183 may be an inorganic layer including at least one selected from the group consisting of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0147] In some aspects, some of the touch electrodes TE may be disposed on the touch insulating layer 183. In an example, the touch electrode TE may not overlap the first to third emission areas EA1, EA2, and EA3. The touch electrode TE may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO). Additionally or alternatively, the touch electrode TE may be formed of a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0148] The touch protection layer 185 may cover the touch electrode TE and the touch insulating layer 183. The touch protection layer 185 may have insulating properties and optical functions. The touch protection layer 185 may be formed of any material described herein with reference to forming the touch insulating layer 183.

[0149] The light blocking layer BM may be disposed on the touch sensing layer 180. The light blocking layer BM may overlap the non-emission area BA. In some examples, the light blocking layer BM may partially overlap the non-emission area BA. Accordingly, for example, the light blocking layer BM may overlap the through-hole layer 139, the inorganic pixel defining layer 151, and the embankment structure 160. The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be, but is not limited to, carbon black, and the organic black pigment may include, but is not limited to, at least one of lactam black, perylene black, and aniline black. The light blocking layer BM may prevent visible light from passing between the first to third emission areas EA1, EA2, and EA3 to improve the color gamut of the display device 10. For example, the light blocking layer BM may prevent the mixing of the colors of the light emitted by the first to third emission areas EA1, EA2, and EA3, respectively.

[0150] The color filter layer 190 may overlap the emission areas EA1, EA2, and EA3, and may be disposed on the touch protection layer 185 and the light blocking layer BM.

[0151] The color filter layer 190 may include a first color filter 191, a second color filter 193, and a third color filter 195, which are respectively arranged in different emission areas EA1, EA2, and EA3. The color filters 191, 193, and 195 may each include a colorant such as, for example, a dye and a pigment that absorbs light in a wavelength range other than light in a specific wavelength range, and may be arranged in association with the light emitted from the emission areas EA1, EA2, and EA3. For example, the first color filter 191 may be a red color filter that transmits a red first light (e.g., only transmits a red first light), and the first color filter 191 is arranged so that the first color filter 191 overlaps the first emission area EA1. The second color filter 193 may be a green color filter that transmits a green second light (e.g., only transmits a green second light), and the second color filter 193 is arranged so that the second color filter 193 overlaps the second emission area EA2. The third color filter 195 may be a blue color filter that transmits blue third light (eg, transmits only blue third light), and is disposed such that the third color filter 195 overlaps the third emission area EA3.

[0152] Color filters 191, 193, and 195 may partially overlap each other, for example, in a region that does not overlap with the light blocking layer BM, for example, in a direction that intersects the Y-axis direction. Different color filters 191, 193, and 195 may not overlap with other emission regions among emission regions EA1, EA2, and EA3, and may overlap with each other on the light blocking layer BM. In an example embodiment, the second color filter 193 overlaps with the second emission region EA2, but does not overlap with another emission region (e.g., the first emission region EA1, the third emission region EA3).

[0153] The overcoat layer OC may be disposed over the color filter layer 190 and the light blocking layer BM to provide a flat surface over the color filters 191, 193, and 195. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as, for example, an acrylic resin.

[0154] Figure 7 yes Figure 6 An enlarged cross-sectional view of region A.

[0155] refer to Figure 7 , the through hole layer 139 may include a recessed portion R recessed toward the substrate 110 corresponding to the emission areas EA1, EA2, and EA3. Figure 7 , the center of the recessed portion R may be aligned with the center of the first emission area EA1, and the recessed portion R may completely overlap with the first emission area EA1. Alternatively or additionally, the through-hole layer 139 may include a protrusion P protruding toward the embankment structure 160 corresponding to the non-emission area BA. For example, the center of the protrusion P may be aligned with the center of the embankment structure 160, and the protrusion P may overlap with a portion of the embankment structure 160. In other words, the through-hole layer 139 may include the recessed portion R and the protrusion P repeated in a direction parallel to the substrate 110 (for example, in a direction perpendicular to the Y-axis direction).

[0156] In some embodiments, the thickness H1 of the recessed portion R of the via layer 139 may be smaller than the thickness H2 of other portions (e.g., the protrusion P) of the via layer 139. In other words, the thickness H2 of the protrusion P of the via layer 139 may be greater than the thickness H1 of other portions (e.g., the recessed portion R) of the via layer 139.

[0157] In some embodiments, the through-hole layer 139 may include a flat surface 139r overlapping the recessed portion R and in contact with the first pixel electrode AE1, and a flat surface 139p overlapping the protrusion P and in contact with the first pixel electrode AE1 and the inorganic pixel defining layer 151. The flat surface 139r overlapping the recessed portion R and the flat surface 139p overlapping the protrusion P may include a step difference. Accordingly, the flat surface 139r overlapping the recessed portion R and the flat surface 139p overlapping the protrusion P may be connected by an inclined surface 139i located therebetween.

[0158] In some embodiments, the first pixel electrode AE1 may be located in the recess R of the via layer 139 and contact the flat surface 139r of the via layer 139. In addition, the first pixel electrode AE1 may overlap the non-emission area BA, cover the inclined surface 139i, and at least partially cover the flat surface 139p of the via layer 139. Accordingly, the first pixel electrode AE1 may overlap the stepped portion along the inclined surface 139i of the via layer 139.

[0159] like Figure 7 As shown in , the second pixel electrode AE2 may be spaced apart from the first pixel electrode AE1 in a direction parallel to the substrate 110 (e.g., a direction perpendicular to the Y-axis direction) by the through-hole layer 139. For example, the first pixel electrode AE1 and the second pixel electrode AE2 may be spaced apart from each other on the flat surface 139p of the through-hole layer 139. Although the first pixel electrode AE1 is described for ease of explanation, the corresponding structures of the pixel electrodes AE2 and AE3 may include aspects of the structure of the described first pixel electrode AE1. For example, the pixel electrodes AE1, AE2, and AE3 may all have the same structure. Additionally or alternatively, the corresponding structures of the pixel electrodes AE1, AE2, and AE3 may be at least partially different.

[0160] The inorganic pixel defining layer 151 may overlap the non-emission area BA and may be disposed on the through-hole layer 139. The inorganic pixel defining layer 151 may cover the first pixel electrode AE1 and the second pixel electrode AE2 on the through-hole layer 139. Accordingly, for example, the inorganic pixel defining layer 151 may include a step along the inclined surface 139i of the through-hole layer 139. The inorganic pixel defining layer 151 may contact a portion of the flat surface 139p of the through-hole layer 139 where the first pixel electrode AE1 is spaced apart from the second pixel electrode AE2 (e.g., a portion located in a region where the first pixel electrode AE1 is spaced apart from the second pixel electrode AE2).

[0161] The first opening OP1 defined by the inorganic pixel defining layer 151 may overlap the recessed portion R of the through-hole layer 139. In an example, the width of the first opening OP1 defined by the inorganic pixel defining layer 151 may be smaller than the width of the recessed portion R of the through-hole layer 139. Accordingly, for example, the first emission layer EL1, the first common electrode CE1, and the capping layer 159 located in the first opening OP1 may overlap the recessed portion R of the through-hole layer 139. According to one or more embodiments of the present disclosure, the emission layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer 159 located in the first opening OP1, the second opening OP2, and the third opening OP3 may overlap the corresponding recessed portions R of the through-hole layer 139.

[0162] In some embodiments, a side surface 151 c of the inorganic pixel defining layer 151 facing the first opening OP1 may overlap the recessed portion R of the via layer 139. In some aspects, the side surface 151 c of the inorganic pixel defining layer 151 may overlap the protrusion P of the via layer in the recessed portion R of the via layer 139 in a direction parallel to the substrate 110.

[0163] refer to Figure 6 and Figure 7 , the residual pattern layer 157 may be disposed between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3. As described herein, in the display device 10, the temporary protective layer may be disposed between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3, and then partially removed during the preparation process. The unremoved portion of the temporary protective layer may be retained in the display device 10 in the form of a residual pattern layer 157. Accordingly, the residual pattern layer 157 disposed in the emission areas EA1, EA2, and EA3, respectively, may be positioned to contact the emission layers EL1, EL2, and EL3 and be located between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3. In other words, the residual pattern layer 157 may overlap with the recessed portion R of the through-hole layer 139, and may contact the emission layers EL1, EL2, and EL3.

[0164] In some embodiments, the residual pattern layer 157 may cover the pixel electrodes AE1 , AE2 , and AE3 or be disposed along the pixel electrodes AE1 , AE2 , and AE3 . Accordingly, the residual pattern layer 157 may include a step along the inclined surface 139 i of the via layer 139 .

[0165] like Figure 7 As shown in , the residual pattern layer 157 overlapping the second emission area EA2 may be spaced apart from the residual pattern layer 157 overlapping the first emission area EA1 in a direction parallel to the substrate 110 on the flat surface 139 p of the via layer 139 .

[0166] The first bank layer 161 included in the bank structure 160 may be disposed on the inorganic pixel defining layer 151. The first bank layer 161 may include a first surface 161a in contact with the inorganic pixel defining layer 151 and a side surface 161c positioned in a direction toward the first opening OP1. For example, the side surface 161c may face the first opening OP1. The first surface 161a of the first bank layer 161 may cover the inorganic pixel defining layer 151 along the shape (e.g., curved portion, stepped portion) of the inorganic pixel defining layer 151. Accordingly, the first surface 161a of the first bank layer 161 may include a step along the through-hole layer 139.

[0167] The side surface 161c of the first bank layer 161 may be inclined in a direction between a direction parallel to the substrate 110 and a third direction (Y-axis direction). In some embodiments, the bank structure 160 may be formed by a deposition process and an etching process instead of a mask process, and the first bank layer 161 may be formed by a wet etching process. Accordingly, the side surface 161c of the first bank layer 161 may be recessed more than the inorganic pixel defining layer 151 in a direction perpendicular to the substrate 110, so that the side surface 161c may be formed as a surface inclined from the third direction (Y-axis direction) toward a direction parallel to the substrate 110. In an embodiment, the side surface 161c of the first bank layer 161 may overlap with the recessed portion R of the through-hole layer 139.

[0168] The first bank layer 161 may include a metal having high conductivity (eg, conductivity equal to or greater than a threshold value). For example, the first bank layer 161 may include aluminum (Al) having high conductivity. Accordingly, the first bank layer 161 may be electrically connected to the common electrodes CE1, CE2, and CE3.

[0169] The second opening OP2 defined by the first bank layer 161 may overlap the recessed portion R of the through-hole layer 139. For example, the width of the second opening OP2 defined by the first bank layer 161 may be smaller than the width of the recessed portion R of the through-hole layer 139. Accordingly, for example, the first emission layer EL1, the first common electrode CE1, and the capping layer 159 located in the second opening OP2 may overlap the recessed portion R of the through-hole layer 139. According to one or more embodiments of the present disclosure, the emission layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer 159 located in the first opening OP1, the second opening OP2, and the third opening OP3 may overlap the corresponding recessed portions R of the through-hole layer 139.

[0170] The second bank layer 163 may be disposed on the first bank layer 161. The second bank layer 163 may include a material having an etch rate lower than that of the first bank layer 161, and, for example, may include titanium (Ti).

[0171] In some embodiments, the second bank layer 163 may include a first surface 163a facing the first bank layer 161 and a side surface 163c facing the first opening OP1. Figure 7In the example illustrated in , the side surface 163c may be included in the first opening OP1. Like the first bank layer 161, the second bank layer 163 is formed by a wet etching process. The second bank layer 163 includes a material that is relatively stable during the wet etching process compared to the first bank layer 161, and therefore, the side surface 163c of the second bank layer 163 may have a shape that protrudes toward the first opening OP1 more than the side surface 161c of the first bank layer 161. In other words, the side surface 161c of the first bank layer 161 may have a shape that is recessed inward from the side surface 163c of the second bank layer 163. Expressed in another way, the side surface 161c of the first bank layer 161 may be further recessed away from the first opening OP1 compared to the side surface 163c. Accordingly, the second bank layer 163 of the bank structure 160 may include a tip TIP protruding toward the first opening OP1, and an undercut may be formed between the tip TIP of the second bank layer 163 and the side surface 161c of the first bank layer 161. In an embodiment, the tip TIP of the second bank layer 163 may correspond to and be disposed in the recess R of the via layer 139. For example, the tip TIP may at least partially overlap the recess R.

[0172] In some embodiments, the deposition technology can alleviate or prevent the situation where the material is not fully deposited under the tip TIP of the embankment structure 160 of the display device 10. Accordingly, the material of the emission layers EL1, EL2 and EL3 and the common electrodes CE1, CE2 and CE3 can be deposited in an inclined direction rather than in a third direction (Y-axis direction) perpendicular to the upper surface of the substrate 110. For example, the deposition process for forming the emission layers EL1, EL2 and EL3 can be performed in a manner that allows the material to be deposited in a direction that is not perpendicular to the upper surface of the pixel electrodes AE1, AE2 and AE3 (for example, in an inclined direction between a direction parallel to the substrate 110 and the third direction (Y-axis direction)). In this way, the material can even be deposited under the tip TIP of the embankment structure 160.

[0173] According to an embodiment of the present disclosure, the angle of the deposition process for forming the emission layers EL1, EL2, and EL3 is defined as a first angle. The deposition process for forming the emission layers EL1, EL2, and EL3 may be performed at an angle of 45° to 50° to the upper surfaces of the pixel electrodes AE1, AE2, and AE3. That is, in some embodiments, the first angle may be in the range of 45° to 50°. Accordingly, for example, by forming the emission layers EL1, EL2, and EL3 according to the first angle, the emission layers EL1, EL2, and EL3 may fill the corresponding spaces between the pixel electrodes AE1, AE2, and AE3 and the inorganic pixel defining layer 151, and the emission layers EL1, EL2, and EL3 may be formed on the sidewalls of the second opening OP2 that are blocked by the protruding tip TIP of the embankment structure 160.

[0174] The deposition process for forming the common electrodes CE1, CE2 and CE3 may be performed in a manner that allows the material to be deposited in a direction that is not perpendicular to the upper surfaces of the pixel electrodes AE1, AE2 and AE3 (for example, in a direction that is inclined between a direction parallel to the substrate 110 and a third direction (Y-axis direction)). According to an embodiment of the present disclosure, the angle of the deposition process for forming the common electrodes CE1, CE2 and CE3 is defined as a second angle. The deposition process for forming the common electrodes CE1, CE2 and CE3 may be performed obliquely (for example, at an angle other than 90 degrees) relative to the upper surfaces of the pixel electrodes AE1, AE2 and AE3. For example, the deposition process for forming the common electrodes CE1, CE2 and CE3 may be performed at an angle of 30° or less relative to the upper surfaces of the pixel electrodes AE1, AE2 and AE3, respectively.

[0175] In other words, the deposition process for forming the common electrodes CE1, CE2, and CE3 may be performed in a relatively horizontal direction compared to the deposition process for forming the emission layers EL1, EL2, and EL3. Accordingly, for example, the contact area between the common electrodes CE1, CE2, and CE3 and the side surface 161c of the first bank layer 161 may be greater than the contact area between the emission layers EL1, EL2, and EL3 and the side surface 161c of the first bank layer 161. Accordingly, the deposition process for forming the common electrodes CE1, CE2, and CE3 may have a higher step coverage characteristic (e.g., achieve a higher step coverage) compared to the deposition process for forming the emission layers EL1, EL2, and EL3. That is, for example, the common electrodes CE1, CE2, and CE3 may be deposited to a position higher than the emission layers EL1, EL2, and EL3 on the side surface 161c of the first bank layer 161.

[0176] According to one or more embodiments of the present disclosure, the tip TIP of the second bank layer 163 may be formed to be parallel to the first pixel electrode AE1 overlapping the first opening OP1. In other words, the tip TIP of the second bank layer 163 may be formed to be parallel to the inorganic pixel defining layer 151 overlapping the second opening OP2. That is, the tip TIP of the second bank layer 163 may not overlap with the step included in the inorganic pixel defining layer 151 in the third direction (Y-axis direction). Figure 8 yes Figure 7 An enlarged cross-sectional view of region T.

[0177] refer to Figure 6 and Figure 8 , the display device 10 may include organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and capping patterns 159-1, 159-2, and 159-3 disposed on the bank structure 160.

[0178] The organic patterns ELP1, ELP2 and ELP3, the electrode patterns CEP1, CEP2 and CEP3, and the capping patterns 159-1, 159-2 and 159-3 may be disposed on the embankment structure 160 and may surround the first opening OP1. During the process of preparing the display device 10, the stacked structure of the organic patterns ELP1, ELP2 and ELP3, the electrode patterns CEP1, CEP2 and CEP3, and the capping patterns 159-1, 159-2 and 159-3 around the first opening OP1 may be partially etched so that the pattern shapes of these stacked structures may be changed. Accordingly, for example, when the pattern shapes of these stacked structures are changed, a portion of the upper surface of the second embankment layer 163 of the embankment structure 160 may not be covered by the organic patterns ELP1, ELP2 and ELP3, and the uncovered portion may be partially etched. Figure 8 Also, a portion of the organic patterns ELP1, ELP2, and ELP3, a portion of the electrode patterns CEP1, CEP2, and CEP3, and a portion of the capping patterns 159-1, 159-2, and 159-3 may form a trench TP.

[0179] A plurality of organic patterns ELP1, ELP2, and ELP3 may be disposed on the second bank layer 163 such that the organic patterns ELP1, ELP2, and ELP3 at least partially overlap the second bank layer 163. The organic patterns ELP1, ELP2, and ELP3 may include the same material as the emission layers EL1, EL2, and EL3 of the light emitting elements ED1, ED2, and ED3, respectively. The first organic pattern ELP1 may include the same material as the first emission layer EL1 of the first light emitting element ED1. The second organic pattern ELP2 may include the same material as the second emission layer EL2 of the second light emitting element ED2. The third organic pattern ELP3 may include the same material as the third emission layer EL3 of the third light emitting element ED3.

[0180] Since the tip TIP included in the embankment structure 160 provides physical and electrical separation between the organic patterns ELP1, ELP2, and ELP3 and the emission layers EL1, EL2, and EL3, the organic patterns ELP1, ELP2, and ELP3 can be formed into traces disconnected from the emission layers EL1, EL2, and EL3. The organic patterns ELP1, ELP2, and ELP3 can be formed in the first opening OP1 and the second opening OP2, and the organic patterns ELP1, ELP2, and ELP3 and the emission layers EL1, EL2, and EL3 can be disconnected from each other by the tip TIP of the embankment structure 160, respectively.

[0181] The first organic pattern ELP1 may include a side surface ELP1c. In a region where the first organic pattern ELP1 overlaps the second opening OP2, the side surface ELP1c of the first organic pattern ELP1 covers the side surface 163c of the second bank layer 163. Figure 7 and Figure 8 , the first organic pattern ELP1 overlapping the second opening OP2 may overlap the recessed portion R of the through-hole layer 139. Accordingly, the side surface ELP1c of the first organic pattern ELP1 may also overlap the recessed portion R of the through-hole layer 139. Although the first organic pattern ELP1 is described for ease of explanation, it should be understood that the organic patterns ELP2 and ELP3 may include various aspects of the described first organic pattern ELP1. For example, the organic patterns ELP1, ELP2, and ELP3 may all have the same structure.

[0182] The electrode patterns CEP1, CEP2, and CEP3 may be disposed on the organic patterns ELP1, ELP2, and ELP3, respectively. The electrode patterns CEP1, CEP2, and CEP3 may include a first electrode pattern CEP1, a second electrode pattern CEP2, and a third electrode pattern CEP3. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may include the same material as the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3, respectively. For example, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be disposed directly on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively.

[0183] In some embodiments, the arrangement relationship between the electrode patterns CEP1, CEP2, and CEP3 and the organic patterns ELP1, ELP2, and ELP3 may be the same as the arrangement relationship between the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 and the emission layers EL1, EL2, and EL3. For example, since the tip TIP included in the embankment structure 160 provides physical and electrical separation between the electrode patterns CEP1, CEP2, and CEP3 and the common electrodes CE1, CE2, and CE3, the electrode patterns CEP1, CEP2, and CEP3 may be traces formed due to the disconnection of the deposited material from the common electrodes CE1, CE2, and CE3. In the display device 10, even in a deposition process without a mask, the technology described herein supports the separate formation of the common electrodes CE1, CE2, and CE3 in different regions by the tip TIP of the embankment structure 160.

[0184] The first electrode pattern CEP1 may be located on the first organic pattern ELP1 in a region where the first electrode pattern CEP1 overlaps the second opening OP2. In a region where the first electrode pattern CEP1 overlaps the second opening OP2, the first electrode pattern CEP1 may include a side surface CEP1c of the first electrode pattern CEP1 covering a side surface ELP1c of the first organic pattern ELP1. Figure 7 and Figure 8 , the first electrode pattern CEP1 overlapping with the second opening OP2 may overlap with the recessed portion R of the through-hole layer 139. Accordingly, the side surface CEP1c of the first electrode pattern CEP1 may also overlap with the recessed portion R of the through-hole layer 139. Although the first electrode pattern CEP1 is described for ease of explanation, it should be understood that the electrode patterns CEP2 and CEP3 may include various aspects of the described first electrode pattern CEP1. For example, the electrode patterns CEP1, CEP2, and CEP3 may all have the same structure. Additionally or alternatively, the corresponding structures of the electrode patterns CEP1, CEP2, and CEP3 may be partially different.

[0185] The capping patterns 159-1, 159-2, and 159-3 may be disposed on the electrode patterns CEP1, CEP2, and CEP3. The capping patterns 159-1, 159-2, and 159-3 may include the same material as the material of the capping layer 159 disposed on the common electrodes CE1, CE2, and CE3. The capping patterns 159-1, 159-2, and 159-3 may be directly disposed on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3, respectively. In some embodiments, the arrangement relationship between the capping patterns 159-1, 159-2, and 159-3 and the electrode patterns CEP1, CEP2, and CEP3 may be the same as the arrangement relationship between the capping layer 159 and the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3. Since the tip TIP included in the bank structure 160 provides physical and electrical separation between the capping patterns 159 - 1 , 159 - 2 , and 159 - 3 and the capping layer 159 , the capping patterns 159 - 1 , 159 - 2 , and 159 - 3 may be traces formed due to the disconnection of the deposited material from the capping layer 159 .

[0186] The first capping pattern 159-1 may include a side surface 159-1c. The side surface 159-1c of the first capping pattern 159-1 covers the side surface CEP1c of the first electrode pattern CEP1 in a region where the first capping pattern 159-1 overlaps the second opening OP2. Figure 7 and Figure 8, the first capping pattern 159-1 overlapping with the second opening OP2 may overlap with the recessed portion R of the through-hole layer 139. Accordingly, the side surface 159-1c of the first capping pattern 159-1 may also overlap with the recessed portion R of the through-hole layer 139. Although the first capping pattern 159-1 is described for ease of explanation, it should be understood that the capping patterns 159-2 and 159-3 may include various aspects of the first capping pattern 159-1 described herein. For example, the capping patterns 159-1, 159-2, and 159-3 may all have the same structure. Additionally or alternatively, the corresponding structures of the capping patterns 159-1, 159-2, and 159-3 may be partially different.

[0187] In some embodiments, the first to third inorganic layers 171-1, 171-2, and 171-3 included in the first encapsulation layer 171 may cover the common electrodes CE1, CE2, and CE3 and the electrode patterns CEP1, CEP2, and CEP3, respectively. In other words, the first to third inorganic layers 171-1, 171-2, and 171-3 may be provided to cover the light emitting elements ED1, ED2, and ED3 in the emission areas EA1, EA2, and EA3 or in the second opening OP2 of the embankment structure 160. In some embodiments, the first to third inorganic layers 171-1, 171-2, and 171-3 may overlap with the non-emission area BA to cover a plurality of lower layer patterns (organic patterns, electrode patterns, and capping patterns).

[0188] The first to third inorganic layers 171-1, 171-2 and 171-3 can prevent the light emitting elements ED1, ED2 and ED3 from being exposed to the outside air. The first to third inorganic layers 171-1, 171-2 and 171-3 can prevent the light emitting elements ED1, ED2 and ED3 from being damaged by the outside air, and can prevent the pattern set on the embankment structure 160 from being delaminated during the process of preparing the display device 10. Since the first to third inorganic layers 171-1, 171-2 and 171-3 can be formed by a chemical vapor deposition method, the formed first to third inorganic layers 171-1, 171-2 and 171-3 can have a uniform thickness along the steps of the deposited layers. For example, the first to third inorganic layers 171-1, 171-2 and 171-3 can be formed as a thin film even on the undercut of the tip TIP of the embankment structure 160.

[0189] Although aspects of the present disclosure support the first to third inorganic layers 171-1, 171-2, and 171-3 being disposed in the same layer in the display device 10, the technology described herein supports forming the first to third inorganic layers 171-1, 171-2, and 171-3 by different processes during the process of preparing the display device 10. For example, in some embodiments, the emission layers EL1, EL2, and EL3 of the first to third light-emitting elements ED1, ED2, and ED3 may not be formed at the same time, but may be formed by different processes. According to an embodiment of the present disclosure, the first inorganic layer 171-1 may be formed after forming the first light-emitting element ED1, the second inorganic layer 171-2 may be formed after forming the second light-emitting element ED2, and the third inorganic layer 171-3 may be formed after forming the third light-emitting element ED3. That is, the first inorganic layer 171-1 may be formed prior to the second light-emitting element ED2 and the third light-emitting element ED3, and the second inorganic layer 171-2 may be formed prior to the third light-emitting element ED3.

[0190] In other words, the first inorganic layer 171-1 may be formed so that the first inorganic layer 171-1 completely covers the second emission area EA2 and the third emission area EA3, and then the first inorganic layer 171-1 may be removed from the second emission area EA2 and the third emission area EA3 by a dry etching process. In some embodiments, after the first inorganic layer 171-1 is formed, the second inorganic layer 171-2 may be formed so that the second inorganic layer 171-2 completely covers the first emission area EA1 and the third emission area EA3, and then the second inorganic layer 171-2 may be removed from the first emission area EA1 and the third emission area EA3 by a dry etching process. In some embodiments, after the first inorganic layer 171-1 and the second inorganic layer 171-2 are formed, the third inorganic layer 171-3 may be formed so that the third inorganic layer 171-3 completely covers the first emission area EA1 and the second emission area EA2, and then the third inorganic layer 171-3 may be removed from the first emission area EA1 and the second emission area EA2 by a dry etching process.

[0191] The first inorganic layer 171-1 and the second inorganic layer 171-2 formed by different processes may be spaced apart from each other on the second bank layer 163 of the bank structure 160. In some embodiments, the lower layer patterns ELP1, CEP1, and 159-1 covered by the first inorganic layer 171-1 and the lower layer patterns ELP2, CEP2, and 159-2 covered by the second inorganic layer 171-2 may be spaced apart from each other on the bank structure 160. Therefore, a portion of the second bank layer 163 of the bank structure 160 between the first inorganic layer 171-1 and the second inorganic layer 171-2 spaced apart from each other may be exposed, and the exposed portion of the second bank layer 163 may be in direct contact with the second encapsulation layer 173 of the thin film encapsulation layer 170. Although the relationship between the first inorganic layer 171-1 and the second inorganic layer 171-2 is described for ease of explanation, it should be understood that the relationship between the third inorganic layer 171-3 and the second inorganic layer 171-2 may include aspects of the relationship between the first inorganic layer 171-1 and the second inorganic layer 171-2. For example, the third inorganic layer 171-3 and the second inorganic layer 171-2 may be spaced apart from each other, and an exposed portion of the second bank layer 163 between the third inorganic layer 171-3 and the second inorganic layer 171-2 may be in direct contact with the second encapsulation layer 173.

[0192] Fig. 9 is along Figure 5 A cross-sectional view of a display device 30 according to another example taken along line X1 - X1 ′.

[0193] Fig. 9 The display device 30 of the embodiment is different from the display device 10 in that the thin film transistor layer 130 further includes an auxiliary via layer 138 on the planarization layer 137, and a via layer 139 is disposed on the auxiliary via layer 138 corresponding to the non-emission area BA. For example, the via layer 139 may at least partially overlap the non-emission area BA. Fig. 9 , unlike the display device 10 in which the through-hole layer 139 includes the recessed portion R or the protruding portion P and the recessed portion R and the protruding portion P are prepared by a single process, in the display device 30, the auxiliary through-hole layer 138 is formed, and then, the through-hole layer 139 is separately formed corresponding to the non-emission area BA.

[0194] In some embodiments, the auxiliary via layer 138 may overlap the emission areas EA1, EA2, and EA3 and the non-emission area BA, and may cover the second connection electrode CNE2 and the planarization layer 137. The auxiliary via layer 138 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting elements ED1, ED2, and ED3 pass. The auxiliary via layer 138 may be formed of an insulating material.

[0195] In some embodiments, the via layer 139 may be located on the auxiliary via layer 138 so that the via layer 139 overlaps the non-emission area BA. The via layer 139 may be prepared by the same process as the auxiliary via layer 138, or may be prepared by a different process. In some aspects, the via layer 139 may include the same material as the auxiliary via layer 138, or may include a material different from the material of the auxiliary via layer 138.

[0196] In some embodiments, the through-hole layer 139 of the display device 30 may form an opening OP0. The opening OP0 formed by the through-hole layer 139 may overlap with the first opening OP1 formed by the inorganic pixel defining layer 151 and the second opening OP2 formed by the first bank layer 161. For example, the width of the opening OP0 formed by the through-hole layer 139 may be greater than the width of the first opening OP1 formed by the inorganic pixel defining layer 151 and the width of the second opening OP2 formed by the first bank layer 161. That is, for example, the first opening OP1 formed by the inorganic pixel defining layer 151 and the second opening OP2 formed by the first bank layer 161 may be located within the opening OP0 formed by the through-hole layer 139.

[0197] Fig.10 yes Fig. 9 An enlarged cross-sectional view of region P.

[0198] refer to Fig.10 , the via layer 139 may include a first surface 139a in contact with the auxiliary via layer 138 and a second surface 139b opposite to the first surface 139b. The first surface 139a and the second surface 139b of the via layer 139 may be parallel to each other. The width of the first surface 139a of the via layer 139 may be greater than the width of the second surface 139b. In some aspects, the via layer 139 may include a first inclined surface 139c and a second inclined surface 139d connecting the first surface 139a of the via layer 139 to the second surface 139b of the via layer 139. For example, the inclination angle θ1 formed between the first surface 139a of the via layer 139 and the first inclined surface 139c of the via layer 139 may be an acute angle. Although not shown in the drawings, the inclination angle formed between the first surface 139a of the via layer 139 and the second inclined surface 139d of the via layer 139 may also be an acute angle. In some examples, an inclination angle formed between the first surface 139 a and the second inclined surface 139 d may be equal to the inclination angle θ1 .

[0199] The first pixel electrode AE1 located in the first emission area EA1 and the second pixel electrode AE2 located in the second emission area EA2 may be spaced apart from each other by the via layer 139. Expressed in another way, the via layer 139 may be located between the first pixel electrode AE1 and the second pixel electrode AE2.

[0200] In some embodiments, the first pixel electrode AE1 may include a first portion AE11 in contact with the auxiliary via layer 138, a second portion AE12 overlapping the non-emission area BA and in contact with the first inclined surface 139c of the via layer 139, and a third portion AE13 in contact with the second surface 139b of the via layer 139. In some embodiments, the second pixel electrode AE2 may include a first portion AE21 in contact with the auxiliary via layer 138, a second portion AE22 overlapping the non-emission area BA and in contact with the second inclined surface 139d of the via layer 139, and a third portion AE23 in contact with the second surface 139b of the via layer 139. Fig.10 As illustrated in the example of , the first pixel electrode AE1 and the second pixel electrode AE2 may be included in the non-emission area BA.

[0201] In some embodiments, the first portion AE11 and the second portion AE12 of the first pixel electrode AE1 may extend in a direction away from each other, and the second portion AE12 and the third portion AE13 of the first pixel electrode AE1 may extend in a direction away from each other. In some embodiments, the first portion AE21 and the second portion AE22 of the second pixel electrode AE2 may extend in a direction away from each other, and the second portion AE22 and the third portion AE23 of the second pixel electrode AE2 may extend in a direction away from each other. Fig.10 As shown in FIG. 1 , the third portion AE13 of the first pixel electrode AE1 and the third portion AE23 of the second pixel electrode AE2 may be spaced apart from each other on the second surface 139 b of the via layer 139 .

[0202] In some embodiments, the first pixel electrode AE1 may include a step along the first inclined surface 139c of the through-hole layer 139. As described herein, the step included in the first pixel electrode AE1 may be formed so that the step does not overlap with the tip TIP of the second bank layer 163. Although the first pixel electrode AE1 is described for ease of explanation, the second pixel electrode AE2 and the third pixel electrode AE3 may include aspects of the first pixel electrode AE1 described herein. For example, the pixel electrodes AE1, AE2, and AE3 of the display device 30 may all have the same structure. Additionally or alternatively, the corresponding structures of the pixel electrodes AE1, AE2, and AE3 may be partially different.

[0203] The inorganic pixel defining layer 151 may cover the first pixel electrode AE1 and the second pixel electrode AE2 corresponding to the non-emission area BA. For example, the inorganic pixel defining layer 151 may cover along the first to third portions AE11, AE12, and AE13 of the first pixel electrode AE1 and the first to third portions AE21, AE22, and AE23 of the second pixel electrode AE2. It should be noted that the inorganic pixel defining layer 151 may contact the second surface 139b of the through-hole layer 139 between the first pixel electrode AE1 and the second pixel electrode AE2 that are spaced apart from each other.

[0204] In some embodiments, the inorganic pixel defining layer 151 may include a step along the first inclined surface 139c of the through hole layer 139. In some embodiments, the inorganic pixel defining layer 151 may include a step along the third portion AE13 of the first pixel electrode AE1. As described herein, the step included in the inorganic pixel defining layer 151 may be formed so that the step does not overlap with the tip TIP of the second bank layer 163.

[0205] The residual pattern layer 157 may be disposed between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3. As described herein, in the display device 30, a temporary protective layer may be disposed between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3, and then partially removed during the preparation process. The unremoved portion of the temporary protective layer may be retained in the display device 30 in the form of a residual pattern layer 157. Accordingly, the residual pattern layer 157, which is respectively disposed in the emission areas EA1, EA2, and EA3, may be positioned to contact the emission layers EL1, EL2, and EL3 and be located between the inorganic pixel defining layer 151 and the pixel electrodes AE1, AE2, and AE3.

[0206] In some embodiments, the residual pattern layer 157 may cover along the pixel electrodes AE1, AE2, and AE3. Fig.10 The residual pattern layer 157 may include a first portion 157a overlapping the first portion AE11 of the first pixel electrode AE1, a second portion 157b overlapping the second portion AE12 of the first pixel electrode AE1, and a third portion 157c overlapping the third portion AE13 of the first pixel electrode AE1.

[0207] In some embodiments, the residual pattern layer 157 disposed on the first pixel electrode AE1 and the residual pattern layer 157 disposed on the second pixel electrode AE2 may be spaced apart from each other on the second surface 139 b of the via layer 139 .

[0208] In some embodiments, the residual pattern layer 157 may include a step along the first inclined surface 139c of the via layer 139. As described herein, the step included in the residual pattern layer 157 may be formed such that the step does not overlap with the tip end TIP of the second bank layer 163.

[0209] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, include: a substrate including an emitting region and a non-emitting region; a through-hole layer disposed on the substrate and comprising a recessed portion facing the substrate; a pixel defining layer, overlapping the non-emitting area and disposed on the through-hole layer; A first bank layer is disposed on the pixel defining layer and defines a first opening; a second bank layer disposed on the first bank layer and including a tip protruding from a side surface of the first bank layer toward the first opening; a first pixel electrode, overlapping the recessed portion of the through-hole layer and disposed on the substrate; A first emission layer is disposed in the first opening and on the first pixel electrode; as well as a first common electrode disposed in the first opening, on the first emission layer, and in contact with the first bank layer; The side surface of the first bank layer and the tip of the second bank layer overlap with the recessed portion of the via layer.

2. The display device according to claim 1, in, The first portion of the via layer has a first thickness and overlaps the recessed portion; The second portion of the via layer has a second thickness and does not overlap the recessed portion; and The first thickness is different from the second thickness.

3. The display device according to claim 2, in, The first thickness is smaller than the second thickness.

4. The display device according to claim 3, in, The first opening overlaps the recessed portion of the via layer.

5. The display device according to claim 4, in, The width of the first opening in a direction parallel to the substrate is smaller than the width of the recessed portion of the via layer.

6. The display device according to claim 1, in, The through-hole layer further comprises: An inclined surface overlaps the non-emitting area and does not overlap the recessed portion.

7. The display device according to claim 6, in, The first pixel electrode is in contact with the inclined surface.

8. The display device according to claim 1, in, The pixel defining layer is spaced apart from the first pixel electrode in the recessed portion of the via layer in a direction perpendicular to the substrate.

9. The display device according to claim 8, further comprising: include: a pattern layer, disposed in a region where the first pixel electrode and the pixel defining layer are spaced apart from each other, The pattern layer overlaps with the recessed portion of the through-hole layer and contacts with the first emission layer.

10. The display device according to claim 1, further comprising: include: a first organic pattern disposed on the second bank layer, wherein the first organic pattern includes a same material as that of the first emission layer and is spaced apart from the first emission layer; and a first electrode pattern disposed on the first organic pattern, wherein the first electrode pattern comprises a material that is the same as that of the first common electrode and is spaced apart from the first common electrode, The first organic pattern and the first electrode pattern overlap with the recessed portion of the through-hole layer.

11. The display device according to claim 10, further comprising: include: a second pixel electrode, spaced apart from the first pixel electrode, wherein the through-hole layer is interposed between the second pixel electrode and the first pixel electrode; A second emission layer is arranged on the second pixel electrode; A second common electrode is disposed on the second emission layer; and A second electrode pattern is disposed on the second bank layer, wherein the second electrode pattern includes a material that is the same as that of the second common electrode and is spaced apart from the second common electrode.

12. The display device according to claim 11, further comprising: include: a first inorganic layer, covering the first common electrode and the first electrode pattern; as well as a second inorganic layer, covering the second common electrode and the second electrode pattern, The first inorganic layer and the second inorganic layer are spaced apart from each other.

13. The display device according to claim 1, further comprising: include: an auxiliary through-hole layer, arranged between the substrate and the through-hole layer, wherein a surface of the auxiliary via layer overlaps with the recessed portion of the via layer and is exposed through the recessed portion, and Wherein, the exposed surface of the auxiliary through-hole layer contacts the first pixel electrode.

14. The display device according to claim 13, in, The through-hole layer further comprises: a first surface facing the auxiliary via layer; a second surface, opposite to the first surface; and An inclined surface connects the first surface to the second surface.

15. The display device according to claim 14, in, The width of the first surface is greater than the width of the second surface, and Wherein, the angle formed by the first surface and the inclined surface is an acute angle.

16. The display device according to claim 15, in, The via layer and the auxiliary via layer include the same material.

17. The display device according to claim 15, in, The via layer and the auxiliary via layer include different materials.

18. A display device, include: a substrate including an emitting region and a non-emitting region; a through-hole layer disposed on the substrate and comprising a recessed portion facing the substrate; a pixel defining layer, overlapping the non-emitting area, disposed on the through-hole layer, and defining a first opening; a first bank layer overlapping the non-emitting region and disposed on the pixel defining layer; a second bank layer disposed on the first bank layer and including a tip protruding from a side surface of the first bank layer toward the first opening; A first pixel electrode is disposed in the recessed portion of the through-hole layer and on the through-hole layer; A first emission layer is disposed in the first opening and on the first pixel electrode; as well as a first common electrode disposed in the first opening, on the first emission layer, and in contact with the first bank layer; Wherein, the first opening overlaps with the recessed portion of the through-hole layer.

19. The display device according to claim 18, in, The width of the first opening is smaller than the width of the recessed portion of the via layer.

20. The display device according to claim 19, in, A side surface of the pixel defining layer facing the first opening is located in the recessed portion of the through-hole layer, and The side surface of the pixel defining layer overlaps the via layer in a direction parallel to the substrate.

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