Display device manufacturing method and display device

Abstract

The invention provides a method for manufacturing a display device and a display device capable of suppressing reduction of reliability. In a method of manufacturing a display device according to an embodiment, a lower electrode is formed, an inorganic insulating layer covering the lower electrode is formed, and a partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion is formed on the inorganic insulating layer. A resist patterned using a photomask provided with an opening having a pair of first linear portions extending in a first direction, a pair of second linear portions extending in a second direction intersecting the first direction, and four arcuate corner portions connecting the first linear portions and the second linear portions adjacent to each other is formed on the inorganic insulating layer. A rib having a pixel opening overlapping the lower electrode is formed by removing a portion of the inorganic insulating layer exposed from the resist.

Description

[0001] This application is based on Japanese Patent Application No. 2023-094156 (filing date: June 7, 2023) and claims priority from the aforementioned application. The present application incorporates the entire contents of the aforementioned application by reference. Technical Field

[0002] Embodiments of the present invention relate to a method for manufacturing a display device and a display device. Background Art

[0003] In recent years, a display device using an organic light emitting diode (OLED) as a display element has been put into practical use. The display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0004] When manufacturing such a display device as described above, a technique for suppressing a decrease in reliability is required. Summary of the invention

[0005] An object of the present invention is to provide a method for manufacturing a display device and a display device capable of suppressing a decrease in reliability.

[0006] In a manufacturing method of a display device involved in one embodiment, a lower electrode is formed, an inorganic insulating layer covering the above-mentioned lower electrode is formed, and a partition wall is formed on the above-mentioned inorganic insulating layer, wherein the partition wall includes a conductive lower portion and an upper portion having an end protruding from the side surface of the above-mentioned lower portion; a resist patterned using a photomask is formed on the above-mentioned inorganic insulating layer, wherein the photomask has an opening, and the opening has a pair of first straight line portions extending in a first direction, a pair of second straight line portions extending in a second direction intersecting the above-mentioned first direction, and four arc-shaped corner portions connecting adjacent first straight line portions and second straight line portions, and a rib portion having a pixel opening overlapping the above-mentioned lower electrode is formed by removing a portion of the above-mentioned inorganic insulating layer exposed from the above-mentioned resist.

[0007] A display device involved in one embodiment comprises: a lower electrode; a rib having a pixel opening overlapping the above-mentioned lower electrode; a partition wall comprising a conductive lower portion arranged on the above-mentioned rib, and an upper portion having an end protruding from the side surface of the above-mentioned lower portion; a laminated film comprising an organic layer in contact with the above-mentioned lower electrode through the above-mentioned pixel opening and an upper electrode covering the above-mentioned organic layer; and a sealing layer covering the above-mentioned laminated film, wherein the above-mentioned rib has a tapered end over the entire circumference of the above-mentioned pixel opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a diagram showing a configuration example of a display device according to an embodiment.

[0009] Figure 2This is a diagram showing an example of a sub-pixel layout.

[0010] Figure 3 It is along Figure 2 Schematic cross-sectional view of the display panel taken along line III-III.

[0011] Figure 4 It is a schematic plan view showing the planar shape of a pixel opening according to this embodiment.

[0012] Figure 5 FIG. 1 is a diagram showing an example of a structure of a rib having a pixel opening that can be applied to the present embodiment.

[0013] Figure 6 It is a schematic plan view showing a part of the photomask according to this embodiment.

[0014] Figure 7 It is a schematic plan view showing a part of the photomask according to this embodiment.

[0015] Figure 8 It is a diagram for explaining the step of forming a pixel opening in the manufacturing method involved in this embodiment.

[0016] Fig. 9 It is a diagram for explaining the step of forming a pixel opening in the manufacturing method according to this embodiment.

[0017] Fig.10 It is a schematic plan view showing a part of a photomask used in a production method according to a comparative example.

[0018] Fig.11 It is a diagram for explaining a step of forming a pixel opening in a manufacturing method according to a comparative example.

[0019] Fig.12 It is a schematic cross-sectional view showing a part of a display device manufactured by a manufacturing method according to a comparative example. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments will be described with reference to the drawings.

[0021] It should be noted that the disclosed content is only an example, and the invention is not limited to the content described in the following embodiments. Deformations that are easy for a person skilled in the art to think of are of course included in the scope of the disclosure. In order to make the description clearer, the size, shape, etc. of each part are sometimes changed relative to the actual embodiment in the drawings and schematically represented. In multiple drawings, the same reference numerals are marked for corresponding elements, and detailed descriptions are sometimes omitted.

[0022] In the drawings, as needed, for easy understanding, mutually orthogonal X-axis, Y-axis and Z-axis are recorded. The direction along the X-axis is called the first direction, the direction along the Y-axis is called the second direction, and the direction along the Z-axis is called the third direction. The third direction Z is a normal direction relative to a plane including the first direction X and the second direction Y. In addition, the situation of observing various elements parallel to the third direction Z is called top view.

[0023] The display device involved in this embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, vehicle-mounted equipment, tablet terminals, smartphones, mobile phone terminals, wearable terminals, etc.

[0024] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to the present embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL includes a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0025] In the present embodiment, the shape of the substrate 10 when viewed from above is a rectangle. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0026] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. It should be noted that the pixel PX may also include sub-pixels SP of other colors such as white together with the sub-pixels SP1, SP2, and SP3, or may include sub-pixels SP of other colors such as white instead of any of the sub-pixels SP1, SP2, and SP3.

[0027] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0028] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0029] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0030] Figure 2 is a schematic top view showing an example of the layout of sub-pixels SP1, SP2, and SP3. Figure 2 In the example of FIG. 1 , the sub-pixels SP2 and SP3 are arranged in the sub-pixel SP1 and in the first direction X, respectively. In addition, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the second direction Y.

[0031] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y and columns in which a plurality of sub-pixels SP1 are repeatedly arranged in the second direction Y are formed in the display area DA. These columns are alternately arranged in the first direction X. It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 Example.

[0032] The rib 5 is disposed in the display area DA. The rib 5 has pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3.

[0033] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 respectively overlapping with the pixel opening AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping with the pixel opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping with the pixel opening AP3.

[0034] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cover layer described later. The ribs 5 surround each of these display elements DE1, DE2, and DE3.

[0035] The lower electrode LE1 is connected to the pixel circuit 1 (refer to Figure 1The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0036] The partition wall 6 is arranged on the rib 5. The partition wall 6 overlaps with the rib 5 as a whole and has the same planar shape as the rib 5. That is, the partition wall 6 has openings AP61, AP62, and AP63 in the sub-pixels SP1, SP2, and SP3, respectively. From another point of view, the rib 5 and the partition wall 6 are arranged between the display elements DE1, DE2, and DE3, and are in a lattice shape when viewed from above.

[0037] Figure 3 It is along Figure 2 A schematic cross-sectional view of a display panel PNL (display device DSP) taken along line III-III in FIG. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 The illustrated pixel circuit 1, scanning lines GL, signal lines SL, power supply lines PL and other various circuits and wirings.

[0038] The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes the unevenness generated by the circuit layer 11. Figure 3 Although not shown in the cross section, the contact holes CH1 , CH2 , and CH3 are provided in the organic insulating layer 12 .

[0039] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The ribs 5 are disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5.

[0040] The partition wall 6 includes a conductive lower portion 61 disposed on the rib 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Thus, both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever shape.

[0041] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower portion 61 of the partition wall 6.

[0042] exist Figure 3In the example, a cap layer CP1 is arranged on the upper electrode UE1, a cap layer CP2 is arranged on the upper electrode UE2, and a cap layer CP3 is arranged on the upper electrode UE3. The cap layers CP1, CP2, and CP3 respectively function as optical adjustment layers for improving the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3.

[0043] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0044] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 located below the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL2 located below the partition wall 6 (the portion constituting the display element DE2). In addition, a portion of the laminate film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL3 located below the partition wall 6 (the portion constituting the display element DE3).

[0045] Sealing layers SE1, SE2, and SE3 are respectively arranged in sub-pixels SP1, SP2, and SP3. Sealing layer SE1 continuously covers laminated film FL1 and partition walls 6 around sub-pixel SP1. Sealing layer SE2 continuously covers laminated film FL2 and partition walls 6 around sub-pixel SP2. Sealing layer SE3 continuously covers laminated film FL3 and partition walls 6 around sub-pixel SP3.

[0046] exist Figure 3 In the example, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0047] The sealing layers SE1, SE2, and SE3 are covered by the resin layer 13. The resin layer 13 is covered by the sealing layer 14. The sealing layer 14 is covered by the resin layer 15. The resin layers 13, 15, and the sealing layer 14 are continuously provided at least in the entire display area DA, and a part of them also reaches the peripheral area SA.

[0048] A cover member such as a polarizing plate, a touch panel, a protective film or a cover glass may be further disposed on the resin layer 15. Such a cover member may be bonded to the resin layer 15 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0049] The organic insulating layer 12 is formed of an organic insulating material. The rib 5 and the sealing layers 14, SE1, SE2, and SE3 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the rib 5 is formed of silicon oxynitride, and the sealing layers 14, SE1, SE2, and SE3 are formed of silicon nitride. The resin layers 13 and 15 are formed of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0050] The lower electrodes LE1, LE2, and LE3 include, for example, a reflective layer formed of silver (Ag) and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. Each conductive oxide layer may be formed of, for example, a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0051] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0052] The organic layers OR1, OR2, and OR3 may have a stacked structure of a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The organic layers OR1, OR2, and OR3 may have a so-called tandem structure including a plurality of light emitting layers.

[0053] The cover layers CP1, CP2, and CP3, for example, have a stacked structure formed by overlapping multiple transparent thin films. The multiple thin films may include thin films formed by inorganic materials and thin films formed by organic materials. In addition, the multiple thin films have different refractive indices. The materials of these thin films are different from the materials of the upper electrodes UE1, UE2, and UE3, and are also different from the materials of the sealing layers SE1, SE2, and SE3. It should be noted that at least one of the cover layers CP1, CP2, and CP3 can be omitted.

[0054] The lower portion 61 of the partition wall 6 is formed of, for example, aluminum. The lower portion 61 may be formed of an aluminum alloy such as an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi), or may have a laminated structure of an aluminum layer and an aluminum alloy layer. In addition, the lower portion 61 may have a bottom layer formed of a metal material different from aluminum or an aluminum alloy under the aluminum layer or the aluminum alloy layer. As a metal material forming such a bottom layer, for example, molybdenum (Mo), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb) may be used.

[0055] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. As the metal material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used. As the conductive oxide forming the upper layer, for example, ITO or IZO can be used. It should be noted that the upper portion 62 can have a single-layer structure of a metal material.

[0056] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 respectively in contact with the side surface of the lower portion 61. The pixel voltage is supplied to the lower electrodes LE1, LE2, LE3 through the pixel circuit 1 included in each of the sub-pixels SP1, SP2, SP3.

[0057] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength region. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength region.

[0058] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may include a layer including quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0059] Figure 4 It is a schematic plan view showing the planar shape of the pixel opening AP1 of the sub-pixel SP1. It should be noted that although the pixel opening AP1 of the sub-pixel SP1 is shown in this figure, the pixel opening AP2 of the sub-pixel SP2 and the pixel opening AP3 of the sub-pixel SP3 also have the same planar shape.

[0060] like Figure 4 As shown, the pixel opening AP1 has a pair of first straight line portions LX1 extending along the first direction X, a pair of second straight line portions LY1 extending along the second direction Y, and four corner portions CN1 formed in an arc shape. Each of the corner portions CN1 connects the adjacent first straight line portion LX1 and second straight line portion LY1. The pixel opening AP1 has the same planar shape as the mask opening formed in the photomask for patterning the resist configured when forming the pixel opening AP1, and the details will be described later.

[0061] It should be noted that if Figure 4 As shown, the opening AP61 of the partition wall 6 surrounding the pixel opening AP1 is rectangular. That is, the pixel opening AP1 of the sub-pixel SP1 and the opening AP61 of the partition wall 6 surrounding the sub-pixel SP1 have different planar shapes.

[0062] Figure 5 This is a diagram showing an example of a structure that can be applied to the rib 5 having a pixel opening. It should be noted that, although the rib 5 having the pixel opening AP1 is shown in this figure, the same structure can also be applied to the rib 5 having the pixel opening AP2 of the sub-pixel SP2 and the rib 5 having the pixel opening AP3 of the sub-pixel SP3.

[0063] exist Figure 5 In the example of FIG. 5 , the end of the lower electrode LE1 is located below the lower portion 61 . Accordingly, the step difference of the rib 5 caused by the lower electrode LE1 is covered by the lower portion 61 .

[0064] exist Figure 5 , the details are omitted in the figure. As mentioned above, the side surface of the lower portion 61 is in contact with the upper electrode UE1 included in the laminate film FL1. It should be noted that the organic layer OR1 included in the laminate film FL1 is not in contact with the side surface of the lower portion 61 but is covered by the upper electrode UE1 as a whole. In addition, the cover layer CP1 included in the laminate film FL1 may not be in contact with the side surface of the lower portion 61, or may be in contact with the side surface.

[0065] like Figure 5 As shown in the area V surrounded by the dotted line, the end 51 of the rib 5 near the pixel opening AP1 is gently inclined at an angle θ1 relative to the upper surface of the lower electrode LE1. In other words, the end 51 of the rib 5 has a tapered shape (more specifically, a positive tapered shape in which the width of the rib 5 decreases as it moves upward along the third direction Z).

[0066] It should be noted that the angle θ1 (more specifically, the inclination angle θ1 of the end 51 relative to the upper surface of the lower electrode LE1) is preferably a value of 45° or less. In other words, the length L1 of the end 51 of the rib 5 in the horizontal direction is preferably longer than the film thickness L2 of the rib 5. According to such a structure, in the end 51 of the rib 5 near the pixel opening AP1, the stacked film FL1 (upper electrode UE1, organic layer OR1 and cover layer CP1) can be prevented from being stepped and the sealing layer SE1 is disconnected (defects such as cracks are generated in the sealing layer SE1).

[0067] The end portion 51 of the rib portion 5 has a Figure 5 That is, the end portion 51 of the rib 5 has a shape near the first straight line portion LX1, near the second straight line portion LY1, and near the corner portion CN1 of the pixel opening AP1. Figure 5 It should be noted that, as described above, the end portion 51 of the rib 5 has the same structure also around the entire circumference of the pixel opening AP2 of the sub-pixel SP2 and the entire circumference of the pixel opening AP3 of the sub-pixel SP3.

[0068] Figure 6 1 is a schematic top view showing a portion of a photomask PM for patterning a resist disposed when forming a pixel opening. The photomask PM is formed of, for example, chromium (Cr). It should be noted that the portion of the photomask PM corresponding to the pixel opening AP1 of the sub-pixel SP1 (i.e., the portion corresponding to the pixel opening AP1 of the sub-pixel SP1) is shown in the figure. Figure 4 The same is true for the portion corresponding to the pixel opening AP1 of the sub-pixel SP2 and the portion corresponding to the pixel opening AP3 of the sub-pixel SP3.

[0069] like Figure 6 As shown, the photomask PM has a mask opening AP1m corresponding to the pixel opening AP1. The mask opening AP1m has a pair of first straight line portions LX1m extending along the first direction X, a pair of second straight line portions LY1m extending along the second direction Y, and four corner portions CN1m formed in an arc shape. Each of the corner portions CN1m connects the adjacent first straight line portions LX1m and second straight line portions LY1m.

[0070] To achieve Figure 5 In the structure shown, i.e., the length L1 of the end 51 of the rib 5 is longer than the film thickness L2 of the rib 5 (in other words, the end 51 of the rib 5 is gently inclined at an angle of less than 45° relative to the upper surface of the lower electrode LE1), it is preferred that the curvature radius R1 of each corner CN1m is set to a value greater than 3μm. It is more preferred that the curvature radius R1 of each corner CN1m is set to a value greater than 5μm. Thus, it is possible to achieve Figure 5 The structure shown will be described in detail later.

[0071] exist Figure 6 The example shows that the corners CN1m of the mask opening AP1m are R surfaces (curved surfaces) that have been R-chamfered, but the corners CN1m can also be C surfaces that have been C-chamfered (a surface that connects the first straight line portion LX1m and the second straight line portion LY1m using a straight line portion that is inclined 45° relative to the first straight line portion LX1m or the second straight line portion LY1m, and is along the straight line portion).

[0072] It should be noted that the value of the R surface (curvature radius) and the value of the C surface (dimension) are set based on the height of the partition wall 6 (lower portion 61 and upper portion 62 ) surrounding the pixel opening AP1 and the distance from the opening AP61 of the partition wall 6 to the pixel opening AP1 .

[0073] Figure 7 It is a schematic plan view showing a portion of another photomask PM for patterning a resist disposed when forming a pixel opening. Figure 7 The photomask PM shown is Figure 6 The photomask PM shown in the figure is different in that it includes a first region r where the chromium film formed of chromium is arranged. Cr and a second region r in which a halftone film is disposed instead of the chrome film HT .

[0074] Figure 7 The shaded area is equivalent to the first area r Cr , Figure 7 The dotted area is equivalent to the second area r HT .like Figure 7 As shown, the second region r HT The first region r where the chromium film is disposed corresponds to each of the corners CN1m of the mask opening AP1m. Cr The light transmittance of the second region r is 0%. HT The light transmittance of the first region r is about 30% to 40%. The resist arranged at the position overlapping with the mask opening AP1m is removed by patterning, and the resist arranged at the position overlapping with the first region r Cr The resist at the overlapping position is not removed by patterning, but is arranged at the position corresponding to the second region r. HT The resist at the overlapping position is partially removed by patterning.

[0075] To achieve Figure 5 The structure shown in FIG. 1 , i.e., the structure in which the length L1 of the end portion 51 of the rib 5 is longer than the film thickness L2 of the rib 5 (in other words, the structure in which the end portion 51 of the rib 5 is gently inclined at an angle of less than 45° relative to the upper surface of the lower electrode LE1), is preferably configured with Figure 7The second region r of the halftone film shown HT The width W1 is set to a value greater than 4 μm. Figure 6 Similarly, the photomask PM shown in FIG. Figure 5 The structure shown.

[0076] It should be noted that each of the corners CN1m of the mask opening AP1m may be an R surface (curved surface) that has been R-chamfered or a C surface that has been C-chamfered. Figure 6 The photomasks PM shown are identical.

[0077] Next, refer to Figure 8 as well as Fig. 9 The process of forming the pixel opening AP1 in the manufacturing method according to the present embodiment is described. It should be noted that, although the pixel opening AP1 of the sub-pixel SP1 is shown in these figures, the pixel opening AP2 of the sub-pixel SP2 and the pixel opening AP3 of the sub-pixel SP3 are also formed in the same process.

[0078] Although the detailed illustration is omitted here, in the manufacture of the display device DSP, the circuit layer 11 and the organic insulating layer 12 are first formed on the substrate 10. Next, the lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. Then, the inorganic insulating layer 5a for processing into the rib 5 is formed in a manner that covers the lower electrodes LE1, LE2, and LE3 as a whole. In addition, the conductive first layer 61a for processing into the lower part 61 is formed on the inorganic insulating layer 5a, and the second layer 62a for processing into the upper part 62 is formed on the first layer 61a.

[0079] Next, the first layer 61a and the second layer 62a are patterned. The patterning includes etching to process the second layer 62a into the shape of the upper portion 62 and etching to process the first layer 61a into the shape of the lower portion 61. By these etchings, the partition wall 6 including the lower portion 61 and the upper portion 62 is formed on the inorganic insulating layer 5a.

[0080] After forming the partition wall 6, as Figure 8 As shown, Figure 6 or Figure 7 The photomask PM shown in FIG. 1 is used to arrange the resist RG1 patterned into the planar shape of the rib 5 on the inorganic insulating layer 5a. Figure 6 or Figure 7 The photomask PM shown is Figure 8 As shown, the resist RG1 is patterned into an inclined shape near the portion where the pixel opening AP1 is formed. Although not shown here, the shape of the resist RG1 near the portion where the pixel opening AP2 is formed and near the portion where the pixel opening AP3 is formed is similar.

[0081] Then, if Fig. 9 As shown in FIG. 1 , the portion of the inorganic insulating layer 5a used for processing into the rib portion 5 exposed from the resist RG1 is removed by etching. Fig. 9 As shown, the rib 5 having the pixel opening AP1 (and the pixel openings AP2 and AP3 ) and the end portion 51 having a gently tapered shape is formed.

[0082] After that, the steps for forming the display elements DE1, DE2, and DE3 are sequentially performed. Figure 5 That is, a display device DSP having a structure that extends over the entire circumference of the pixel opening AP1 (and the pixel openings AP2 and AP3) and in which the length L1 of the end 51 of the rib 5 is longer than the film thickness L2 of the rib 5 (in other words, a structure in which the end 51 of the rib 5 is gently inclined at an angle of less than 45° relative to the upper surface of the lower electrode LE1).

[0083] The following uses comparative examples to illustrate the effects of the manufacturing method and the display device DSP involved in this embodiment. It should be noted that the comparative examples are used to illustrate a part of the effects that can be achieved by the manufacturing method and the display device DSP involved in this embodiment, and do not exclude the effects common to the present embodiment and the comparative examples from the scope of the present invention.

[0084] Fig.10 This is a schematic top view showing a portion of the photomask PM' used in the manufacturing method involved in the comparative example. It should be noted that, although the portion of the photomask PM' corresponding to the pixel opening AP1 of the sub-pixel SP1 is shown in this figure, the portion corresponding to the pixel opening AP2 of the sub-pixel SP2 and the portion corresponding to the pixel opening AP3 of the sub-pixel SP3 are also the same.

[0085] like Fig.10 As shown, the difference between the photomask PM′ involved in the comparative example and the photomask PM involved in this embodiment is that the planar shape of the mask opening AP1m is a rectangle having a pair of first straight line portions LX1m extending along the first direction X and a pair of second straight line portions LY1m extending along the second direction Y.

[0086] Fig.11 It is a diagram for explaining a step of forming the pixel opening AP1 in the manufacturing method according to the comparative example. Fig.12 1 is a schematic cross-sectional view showing a part of a display device DSP' manufactured by a manufacturing method according to a comparative example.

[0087] In the manufacturing method according to the comparative example, when the partition wall 6 is formed by the same steps as the manufacturing method according to the present embodiment, Fig.10The resist RG1 patterned by the photomask PM′ shown is disposed on the inorganic insulating layer 5a. Fig.11 As shown, the resist RG1 mainly arranged at a position overlapping with the corner of the rectangular mask opening AP1m is patterned into a steep shape, not an inclined shape. Therefore, the end 51 of the rib 5 formed as a result of patterning the resist RG1 as a mask also has a steep shape.

[0088] According to this, if Fig.12 As shown in FIG. 1 , the stacked film FL1 (organic layer OR1, upper electrode UE1, and cap layer CP1) deposited on the lower electrode LE1 in the process of forming the display element DE1 may be stepped at the end 51 of the rib 5. Fig.12 As shown, the sealing layer SE1 covering the laminated film FL1 may be disconnected at the end 51 of the rib 5 (that is, cracks or other defects may occur in the sealing layer SE1). Such step disconnection of the laminated film FL1 and defects in the sealing layer SE1 may reduce the brightness of the display device or reduce the resistance of the display device to moisture, thereby reducing the reliability of the display device.

[0089] In contrast, in the manufacturing method according to the present embodiment, it is possible to use Figure 6 or Figure 7 The photomask PM shown is used to pattern the resist RG1, and the resist RG1 arranged at a position overlapping with the corner CN1m of the mask opening AP1m is patterned into an inclined shape (see FIG. 1 ). Figure 8 ), therefore, the end 51 of the rib 5 formed by patterning the resist RG1 as a mask can be made as Fig. 9 As shown in the figure, the rib 5 has an inclined shape throughout the entire periphery of the pixel opening AP1. Thus, at the end 51 of the rib 5, it is possible to prevent the stacked film FL1 (upper electrode UE1, organic layer OR1, and cover layer CP1) from being stepped or the sealing layer SE1 from being disconnected (causing defects such as cracks in the sealing layer SE1). That is, it is possible to suppress the reduction in the reliability of the display device.

[0090] According to one embodiment described above, it is possible to provide a method for manufacturing a display device and a display device capable of suppressing a decrease in reliability.

[0091] It should be noted that several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A method for manufacturing a display device, wherein: forming a lower electrode, forming an inorganic insulating layer covering the lower electrode, forming a partition wall on the inorganic insulating layer, wherein the partition wall includes a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, A resist patterned by using a photomask is formed on the inorganic insulating layer, wherein the photomask has an opening, the opening having a pair of first straight line portions extending along a first direction, a pair of second straight line portions extending along a second direction intersecting the first direction, and four arc-shaped corner portions connecting adjacent first straight line portions and second straight line portions, A rib having a pixel opening overlapping with the lower electrode is formed by removing a portion of the inorganic insulating layer exposed from the resist.

2. The method for manufacturing a display device according to claim 1, wherein: The rib has a tapered end portion throughout the entire circumference of the pixel opening.

3. The method for manufacturing a display device according to claim 2, wherein: The inclination angle of the end of the rib is less than or equal to 45 degrees.

4. The method for manufacturing a display device according to claim 1, wherein: The radius of curvature of each of the corners is 3 μm or more.

5. The method for manufacturing a display device according to claim 1, wherein: The photomask is formed of a halftone film and a chrome film, wherein the halftone film is arranged in regions respectively corresponding to the corners, and the chrome film is arranged in regions respectively corresponding to the corners and other regions other than the openings.

6. The method for manufacturing a display device according to claim 5, wherein: The width of the halftone film is 4 μm or more.

7. The method for manufacturing a display device according to claim 1, further comprising: forming an organic layer covering the lower electrode and emitting light in response to application of a voltage, An upper electrode covering the organic layer and contacting the lower portion is formed.

8. The method for manufacturing a display device according to claim 7, further comprising: A sealing layer is formed to continuously cover the stacked film including the organic layer and the upper electrode and the partition wall.

9. A display device comprising: Lower electrode; a rib having a pixel opening overlapping the lower electrode; a partition wall including a conductive lower portion disposed on the rib portion and an upper portion having an end portion protruding from a side surface of the lower portion; a laminate film comprising an organic layer in contact with the lower electrode through the pixel opening and an upper electrode covering the organic layer; and a sealing layer covering the laminated film, The rib has a tapered end portion throughout the entire circumference of the pixel opening.

10. The display device according to claim 9, wherein: The inclination angle of the end of the rib is less than or equal to 45 degrees.

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