Spinning electronic device, manufacturing method thereof and storage unit

Abstract

The invention discloses a spinning electronic device, a manufacturing method thereof and a storage unit, and relates to the technical field of storage. The spin electronic device includes: a substrate; the spin orbit moment layer is arranged on the top surface of the substrate, the material of the spin orbit moment layer at least comprises MnPd3, and the crystal face of the MnPd3 is (114); the magnetic layer is arranged on the top surface of the spin orbit moment layer; the first insulating layer is arranged on the top surface of the magnetic layer; and the electrode layer is arranged on the top layer of the spinning electronic device. According to the spinning electronic device and the manufacturing method thereof disclosed by the embodiment of the invention, the out-of-plane damping torque is formed by the current of the MnPd3 layer in the direction perpendicular to the MnPd3 layer, so that the non-external-field overturning of the spinning electronic device is realized; by adopting the storage unit composed of the two spintronic devices, a reading window is enlarged, and the reading precision of the magnetic storage device is further improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a spin electronic device and a manufacturing method thereof, and a storage unit. Background Art

[0002] Magnetic random access memory is a storage device made of spin electronic devices. It has the advantages of high read and write speed, low power consumption, high life, good miniaturization and compatibility with CMOS process. It is gradually replacing eFlash and becoming a new type of storage unit in microcontroller units. The core structure of magnetic random access memory is the magnetic tunnel junction, which is a "sandwich" structure consisting of two layers of magnetic materials and an insulating layer. When the magnetization directions of the two magnetic layers are parallel or anti-parallel, the magnetic tunnel junction presents a low resistance state or a high resistance state, realizing the function of storing binary "0" or "1". A serious problem faced by magnetic memory is that when the write current flips the magnetization direction of the magnetic layer, an external magnetic field is required to obtain a deterministic flip, and the existence of the external magnetic field seriously restricts the integration and practical use of spin electronic devices as storage units. Therefore, it is urgent to solve the problem of external magnetic field when magnetic memory is working. Summary of the invention

[0003] In order to solve the problem that the magnetic memory needs to rely on an external magnetic field to obtain deterministic flipping when working, the present application provides the following technical solutions:

[0004] In a first aspect, a spin electronic device is provided, comprising:

[0005] Substrate.

[0006] The spin-orbit moment layer is arranged on the top surface of the substrate and is used to generate a damping-like torque perpendicular to the spin-orbit moment layer, so that the magnetization direction of the magnetic layer is reversed under the action of current without the help of an external magnetic field. The material of the spin-orbit moment layer includes at least MnPd3, wherein the crystal plane of MnPd3 is (114).

[0007] The magnetic layer is disposed on the top surface of the spin-orbit moment layer.

[0008] The first insulating layer is arranged on the top surface of the magnetic layer.

[0009] The electrode layer is arranged on the top layer of the spintronic device.

[0010] Furthermore, the spin electronic device further comprises:

[0011] The second insulating layer is arranged on the top surface of the first insulating layer.

[0012] The protection layer is arranged on the top surface of the second insulating layer.

[0013] Furthermore, the spin electronic device further comprises:

[0014] The reference layer is arranged on the top surface of the first insulating layer.

[0015] The pinning layer is disposed on the top surface of the reference layer.

[0016] Furthermore, the material of the substrate includes at least one of silicon dioxide, sapphire, and MgO single crystal.

[0017] The material of the magnetic layer includes at least one of Co, CoFe and CoFeB.

[0018] The material of the first insulating layer includes at least one of MgO and Al 2 O 3 .

[0019] The electrode layer is made of at least one of Ti / Au alloy, W, Ta, Pt and TiN.

[0020] In a second aspect, a method for manufacturing a spintronic device is provided, comprising:

[0021] A spin-orbit moment layer with MnPd3 as the main component is formed on the top surface of the substrate, wherein the crystal plane of MnPd3 is (114).

[0022] A magnetic layer is formed on the top surface of the spin-orbit moment layer.

[0023] A first insulating layer is formed on the top surface of the magnetic layer.

[0024] The electrode layer is formed into a film.

[0025] Furthermore, after forming a first insulating layer on the top surface of the magnetic layer, the method further comprises:

[0026] Forming a second insulating layer on the top surface of the first insulating layer;

[0027] A protective layer is formed on the top surface of the second insulating layer.

[0028] Furthermore, after forming a first insulating layer on the top surface of the magnetic layer, the method further comprises:

[0029] Forming a reference layer on the top surface of the first insulating layer;

[0030] On top of the reference layer, a pinning layer is formed into a film.

[0031] In a third aspect, a storage unit is provided, comprising:

[0032] substrate;

[0033] A spin-orbit moment layer is disposed on the top surface of the substrate;

[0034] At least one spin electronic device according to the first aspect;

[0035] When the number of the spin electronic devices in the memory cell is greater than 1, at least one of the spin electronic devices shares a substrate and a spin-orbit moment layer.

[0036] Further, the storage unit includes two spin electronic devices, and the magnetic tunnel junctions of the two spin electronic devices are separated by a preset distance, wherein the magnetic tunnel junction includes: a magnetic layer, a first insulating layer, a reference layer, and a pinning layer;

[0037] The directions of magnetic moments between the reference layers of the two magnetic tunnel junctions in the memory cell are antiparallel;

[0038] The magnetic moments of the magnetic layers of any magnetic tunnel junction in the memory cell are in parallel.

[0039] Further, the memory cell further comprises: a first transistor, a second transistor, a third transistor, a comparator, a power supply line, a write word line, a read word line, a write bit line, and a read bit line;

[0040] The first transistor comprises: a first transistor first electrode, a first transistor second electrode and a first transistor third electrode;

[0041] The second transistor comprises: a second transistor first electrode, a second transistor second electrode and a second transistor third electrode;

[0042] The third transistor comprises: a third transistor first electrode, a third transistor second electrode and a third transistor third electrode;

[0043] The comparator has: a comparator first input terminal, a comparator second input terminal and a comparator output terminal;

[0044] The first electrode of the first transistor is electrically connected to the write word line, the second electrode of the first transistor is electrically connected to the spin orbit moment layer of the memory cell, the spin orbit moment layer of the memory cell is also electrically connected to the power line, and the third electrode of the first transistor is electrically connected to the write bit line;

[0045] A first electrode of the second transistor is electrically connected to a read word line, a second electrode of the second transistor is electrically connected to an electrode layer of a spin electronic device in the memory cell, and a third electrode of the second transistor is electrically connected to a first input terminal of the comparator;

[0046] A first electrode of the third transistor is electrically connected to the read word line, a second electrode of the third transistor is electrically connected to an electrode layer of another spin electronic device in the memory cell, and a third electrode of the third transistor is electrically connected to the second input terminal of the comparator;

[0047] The comparator output terminal is electrically connected to the read bit line;

[0048] The memory cell is configured such that, in response to a reversal of the magnetic moment of a magnetic layer of any magnetic tunnel junction in the memory cell, a logic signal outputted from an output terminal of the comparator is reversed.

[0049] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0050] By implementing a spin electronic device and a manufacturing method thereof disclosed in an embodiment of the present application, the out-of-plane damping-like torque formed by the current flowing through the MnPd3 layer in a direction perpendicular to the MnPd3 layer can cause the magnetic moment of CoFeB to undergo a directional reversal, thereby achieving external field-free reversal of the spin electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 is a schematic diagram of a spin electronic device provided in an embodiment of the present application;

[0053] Figure 2 is a schematic diagram of another spin electronic device provided in an embodiment of the present application;

[0054] Figure 3 It is a schematic diagram of a method for manufacturing a spin electronic device provided in an embodiment of the present application;

[0055] Figure 4 This is a schematic diagram of a spin electronic device Hall bar provided in an embodiment of the present application;

[0056] Figure 5 is a schematic diagram of another method for manufacturing a spin electronic device provided in an embodiment of the present application;

[0057] Figure 6 is a schematic diagram of a storage unit provided in an embodiment of the present application;

[0058] Figure 7 is a schematic diagram of a storage unit composed of two spin electronic devices provided in an embodiment of the present application;

[0059] Figure 8 It is a schematic diagram of a storage unit composed of a spin electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in the implementation mode of this application will be clearly and completely described below in conjunction with the drawings in the implementation mode of this application. Obviously, the described implementation mode is only a part of the embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0061] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "one" or "the" do not indicate a quantity limitation, but indicate that there is at least one. The numbers in the drawings of the specification only indicate the distinction between various functional components or modules, and do not indicate the logical relationship between components or modules. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] Hereinafter, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the accompanying drawings, the same reference numerals are given to components having substantially the same or similar structures and functions, and repeated descriptions thereof will be omitted.

[0063] In order to solve the problem that the magnetic memory needs to rely on an external magnetic field to obtain deterministic switching when working, the present application provides the following embodiments.

[0064] In some embodiments, Figure 1 As shown, a spin electronic device comprises:

[0065] Substrate 000.

[0066] The material of the substrate 000 includes at least one of silicon dioxide, sapphire, and MgO single crystal.

[0067] The spin-orbit moment layer 100 is arranged on the top surface of the substrate and is used to generate a damping-like torque perpendicular to the spin-orbit moment layer 100, so that the magnetization direction of the magnetic layer 200 is reversed under the action of current without the help of an external magnetic field. The material of the spin-orbit moment layer 100 includes at least MnPd3, wherein the crystal plane of MnPd3 is (114).

[0068] Preferably, the spin-orbit moment layer 100 having MnPd3 as a main component has a thickness of 10-12 nm (nanometers).

[0069] When MnPd3 is used as the material of the spin-orbit moment layer 100, when a current is passed in a direction parallel to the spin-orbit moment layer 100, due to the effect of the spin-orbit moment, a first spin current will be generated in a direction perpendicular to the spin-orbit moment layer 100, which is similar to heavy metals such as W, Pt, and Ta. However, unlike heavy metals such as W, Pt, and Ta, MnPd3 will also generate a second spin current with a spin direction opposite to the first spin current, and a third spin current with a spin direction perpendicular to the first spin current. The third spin current further generates an out-of-plane damping torque, and the out-of-plane damping torque generated by the third spin current can be used to cause the CoFeB magnetic moment to be directionally flipped. The magnetization directions of CoFeB are different, so that the device Hall voltages read are different. Different Hall voltages indicate that the device is in different resistance states. By applying a voltage to the electrode layer 600, the potential barrier of the magnetic layer 200 can be reduced, the required flip current density can be reduced, and thus the power consumption can be reduced.

[0070] When the crystal plane of MnPd3 is (114), current is passed through the spin-orbit moment layer 100 to achieve a field-free switching effect on the magnetic layer 200. When the thickness of the spin-orbit moment layer 100 reaches 10-12 nm, the field-free switching effect of the spin-orbit moment layer 100 is better.

[0071] The relationship between magnetization direction and magnetic moment is: when a material is magnetized, its internal magnetic moment tends to align along the direction of the external magnetic field, causing the entire material to exhibit macroscopic magnetism.

[0072] The magnetic layer 200 is disposed on the top surface of the spin-orbit moment layer 100 .

[0073] The magnetic layer 200 is used to record the magnetization direction. Corresponding to different magnetization directions, the spin electronic device presents different resistances. The material of the magnetic layer 200 includes at least one of Co, CoFe and CoFeB.

[0074] Preferably, CoFeb is used as the material of the magnetic layer 200 .

[0075] Preferably, the thickness of the magnetic layer 200 is 1-1.4 nm.

[0076] The first insulating layer 300 is disposed on the top surface of the magnetic layer 200 .

[0077] The first insulating layer 300 is used to protect the magnetic layer 200 , and the material of the first insulating layer 300 includes at least one of MgO and Al 2 O 3 .

[0078] Preferably, MgO is used as the material of the first insulating layer 300 .

[0079] Preferably, the thickness of the first insulating layer 300 is 1-2 nm.

[0080] Spintronic devices also include:

[0081] The second insulating layer 400 is disposed on the top surface of the first insulating layer 300 .

[0082] The material of the second insulating layer 400 is a high dielectric constant material, which can provide stronger voltage regulation capability at the same thickness.

[0083] Optionally, the material of the second insulating layer 400 includes ZrO x , HfO x And at least one of Al2O3.

[0084] Preferably, ZrO x As the material of the second insulating layer 400 .

[0085] Preferably, the thickness of the second insulating layer 400 is 10 nm.

[0086] The protection layer 500 is disposed on the top surface of the second insulating layer.

[0087] The protective layer 500 is used to protect the spin electronic device; the material of the protective layer 500 includes TaO x And at least one of Al2O3. TaO x It can be formed by natural oxidation of Ta; Al2O3 can be formed by natural oxidation of Al. x Or Al2O3 can provide good protection for the spin electronic device.

[0088] Preferably, the thickness of the protective layer 500 is 2-3 nm.

[0089] The electrode layer 600 is disposed on the top layer of the spin electronic device and is connected to a corresponding voltage through a pin. The material of the electrode layer 600 includes at least one of Ti / Au alloy, W, Ta, Pt and TiN.

[0090] The electrode layer 600 is manufactured by photolithography and ion beam evaporation technology.

[0091] In other embodiments, Figure 2 As shown, another spin electronic device comprises:

[0092] Substrate 000.

[0093] The thickness of the silicon dioxide of the substrate 000 is at least 500 nm.

[0094] The spin-orbit moment layer 100 is arranged on the top surface of the substrate 000 and is used to generate a damping-like torque perpendicular to the spin-orbit moment layer 100, so that the magnetization direction of the magnetic layer 200 is reversed under the action of current without the help of an external magnetic field. The material of the spin-orbit moment layer 100 includes at least MnPd3, wherein the crystal plane of MnPd3 is (114).

[0095] Preferably, the spin-orbit moment layer 100 having MnPd 3 as a main component has a thickness of 10 nm.

[0096] The magnetic layer 200 is disposed on the top surface of the spin-orbit moment layer 100. In this embodiment, the magnetic layer 200 may also be referred to as a free layer. To ensure the consistency of technical terms, the magnetic layer is uniformly described in this application.

[0097] The magnetic layer 200 is used to record the magnetization direction. Corresponding to different magnetization directions, the spin electronic device presents different resistances. The material of the magnetic layer 200 includes at least one of Co, CoFe and CoFeB.

[0098] Preferably, CoFeb is used as the material of the magnetic layer 200 .

[0099] Preferably, the thickness of the magnetic layer 200 is 1 nm.

[0100] The first insulating layer 300 is disposed on the top surface of the magnetic layer 200 .

[0101] Preferably, MgO is used as the material of the first insulating layer 300 .

[0102] Preferably, the thickness of the first insulating layer 300 is 1 nm.

[0103] The reference layer 700 is disposed on the top surface of the first insulating layer 300 .

[0104] The reference layer 700 is used to provide a magnetic moment reference direction of the spin electronic device. The material of the reference layer 700 includes at least one of Co, CoFe and CoFeB.

[0105] Preferably, the material of the reference layer 700 is CoFeB.

[0106] Preferably, the thickness of the reference layer 700 is 1.2 nm.

[0107] The pinning layer 800 is disposed on the top surface of the reference layer 700 and is used to fix the magnetic moment direction of the reference layer 700 .

[0108] The material of the pinning layer 800 includes at least one of IrMn, FeMn, PtMn, a Pt / Co composite material, and a Ni / Co composite material.

[0109] The electrode layer is arranged on the top layer of the spin electronic device and is connected to the corresponding voltage through the pins. The material of the electrode layer includes at least one of Ti / Au alloy, W, Ta, Pt and TiN.

[0110] The electrode layer is manufactured by photolithography and ion beam evaporation technology.

[0111] Preferably, the material of the electrode layer is W.

[0112] Preferably, the thickness of the electrode layer is 8 nm.

[0113] When current is injected into the spin-orbit moment layer 100, the magnetization direction of the material CoFeB of the magnetic layer 200 is deterministically flipped due to the effect of the damping torque. The magnetization direction of the reference layer 700 is difficult to change due to the coupling effect with the pinning layer 800. When the magnetization direction of the magnetic layer 200 is parallel or anti-parallel to the magnetization direction of the reference layer 700, the spin electronic device is in a low resistance or high resistance state, realizing the function of storing binary "0" and "1".

[0114] In other embodiments, corresponding to Figure 1 The spin electronic device shown, and the corresponding spin electronic device manufacturing method, such as Figure 3 As shown, including:

[0115] S100: forming a spin-orbit moment layer with MnPd3 as the main component on the top surface of the substrate, wherein the crystal plane of MnPd3 is (114).

[0116] Optionally, the material of the substrate includes at least one of silicon dioxide, sapphire, and MgO single crystal.

[0117] Preferably, a spin-orbit moment layer having MnPd3 as a main component is formed on the top surface of the substrate by magnetron sputtering, and the substrate is offset from the magnetron sputtering source by an angle of 10°-15°.

[0118] S200: forming a magnetic layer on the top surface of the spin-orbit moment layer.

[0119] Preferably, the magnetic layer is grown by magnetron sputtering using a DC power supply, and the thickness of the magnetic layer is precisely controlled to be 1-1.4 nm.

[0120] S300: forming a first insulating layer on the top surface of the magnetic layer.

[0121] Preferably, the first insulating layer is grown by magnetron sputtering using a radio frequency power supply, and the thickness of the first insulating layer is precisely controlled to be 1-2 nm.

[0122] S310: forming a second insulating layer on the top surface of the first insulating layer.

[0123] Preferably, the second insulating layer is grown by magnetron sputtering using a radio frequency power supply, and the thickness of the second insulating layer is precisely controlled to be 10 nm. x For example, ZrO x When the second insulating layer is used as the main component, the second insulating layer is grown by magnetron sputtering using a radio frequency power supply, and the thickness of the second insulating layer is precisely controlled to be 10nm, so that the spin electronic device has a stronger voltage regulation capability.

[0124] S320: forming a protective layer on the top surface of the second insulating layer.

[0125] Preferably, a DC power supply is used to magnetron sputter and grow the Ta layer, and the thickness of the Ta layer is precisely controlled to be 2-3 nm, and a dense TaO is formed through natural oxidation. x layer to protect the spin electronic device.

[0126] S400: forming an electrode layer into a film.

[0127] The electrode layer is manufactured by photolithography and ion beam evaporation technology.

[0128] After the electrode layer is manufactured, the spin electronic device is placed in a magnetic field perpendicular to the spin electronic device, annealed at 350-400°C for 20 minutes, and the shape of the spin electronic device is manufactured into a Hall bar shape by using photolithography and etching technology, such as Figure 4 As shown. The CoFeB magnetization of this spin electronic device is in the z direction, and a current I is passed through the MnPd3 layer. x Due to the effect of the spin-orbit moment, a spin current with a spin direction of y is generated in the z direction, which is similar to heavy metals such as W, Pt, and Ta. However, the current in the MnPd3 layer will not only generate a spin current with a spin direction of y, but also a spin current with spin directions of x and z, thereby generating an in-plane (x direction) and out-of-plane (z direction) damping-like torque. The out-of-plane damping-like torque can be used to determine the reversal of the CoFeB magnetic moment. The different magnetization directions of CoFeB result in different read Hall voltages, and the device is in different resistance states. By applying voltage to the electrode layer, the potential barrier of the magnetic layer can be lowered, the required reversal current density can be reduced, and thus the power consumption can be reduced.

[0129] In other embodiments, corresponding to Figure 2The spintronic device and the corresponding method for manufacturing the spintronic device are as follows: Figure 5 As shown, including:

[0130] S100: forming a spin-orbit moment layer with MnPd3 as the main component on the top surface of the substrate, wherein the crystal plane of MnPd3 is (114).

[0131] The substrate comprises at least 500 nm thick silicon dioxide.

[0132] Preferably, a spin-orbit moment layer with MnPd3 as the main component is formed on the top surface of the above-mentioned silicon dioxide by magnetron sputtering, and the angle between the substrate and the magnetron sputtering source is 10°-15°.

[0133] S200: forming a magnetic layer on the top surface of the spin-orbit moment layer.

[0134] Preferably, the magnetic layer is grown by magnetron sputtering using a DC power supply, and the thickness of the magnetic layer is precisely controlled to be 1 nm.

[0135] S300: forming a first insulating layer on the top surface of the magnetic layer;

[0136] Preferably, the first insulating layer is grown by magnetron sputtering using a radio frequency power supply, and the thickness of the first insulating layer is precisely controlled to be 1 nm.

[0137] S310′: forming a reference layer on the top surface of the first insulating layer;

[0138] Preferably, the reference layer is grown by magnetron sputtering, and the thickness of the reference layer is precisely controlled to be 1.2 nm.

[0139] S320′: forming a pinning layer on the top surface of the reference layer.

[0140] Preferably, the pinned layer is a Pt / Co multilayer synthetic antiferromagnetic layer.

[0141] S400: forming an electrode layer into a film.

[0142] It should be understood that although Figure 3 as well as Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3 as well as Figure 5At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0143] In some other embodiments, a storage unit such as Figure 6 As shown, including:

[0144] substrate;

[0145] A spin-orbit moment layer is disposed on the top surface of the substrate;

[0146] At least one spintronic device as described above;

[0147] When the number of the spin electronic devices in the memory cell is greater than 1, at least one of the spin electronic devices shares a substrate and a spin-orbit moment layer.

[0148] Take the example of a memory cell including two spintronic devices, such as Figure 7 As shown, the magnetic tunnel junctions of the two spin electronic devices are separated by a preset distance L. The magnetic tunnel junction includes: a magnetic layer, a first insulating layer, a reference layer and a pinning layer.

[0149] Optionally, the preset distance L is 50nm-1000nm.

[0150] The directions of magnetic moments between the reference layers of the two magnetic tunnel junctions in the memory cell are antiparallel;

[0151] The magnetic moment direction of the reference layer in the magnetic tunnel junction is fixed by the pinning layer. In the memory cell described in this embodiment, the magnetic moment directions between the reference layers of the two magnetic tunnel junctions are fixed to be antiparallel by the pinning layers in the respective magnetic tunnel junctions.

[0152] The magnetic moments of the magnetic layers of any magnetic tunnel junction in the memory cell are in parallel.

[0153] The memory cell further includes: a first transistor T1, a second transistor T2, a third transistor T3, a comparator CMP, a power line SL, a write word line WWL, a read word line RWL, a write bit line WBL, and a read bit line RBL.

[0154] The first transistor T1 has: a first transistor first electrode T 11 , the second electrode T of the first transistor 12 and the third electrode T of the first transistor 13 .

[0155] The second transistor T2 has: a first electrode T21 , the second transistor second electrode T 22 and the third electrode T of the second transistor 23 .

[0156] The third transistor T3 has: a first electrode T 31 , the second electrode T of the third transistor 32 and the third electrode T of the third transistor 33 .

[0157] The comparator CMP comprises: a comparator first input terminal CMP1 , a comparator second input terminal CMP2 , and a comparator output terminal CMP0 .

[0158] The first transistor first electrode T 11 The first transistor second electrode T is electrically connected to the write word line WWL. 12 The first transistor third electrode T is electrically connected to the spin-orbit moment layer of the memory cell, and the spin-orbit moment layer of the memory cell is also electrically connected to the power line SL. 13 Electrically connected to the write bit line WBL.

[0159] The first electrode T of the second transistor 21 The second transistor second electrode T is electrically connected to the read word line RWL. 22 The third electrode T of the second transistor is electrically connected to an electrode layer of a spin electronic device in the storage unit. 23 The comparator is electrically connected to the first input terminal CMP1.

[0160] The first electrode T of the third transistor 31 The second electrode T of the third transistor is electrically connected to the read word line. 32 The third transistor T is electrically connected to the electrode layer of another spin electronic device in the memory cell. 33 The comparator is electrically connected to the second input terminal CMP2.

[0161] The comparator output terminal CMP0 is electrically connected to the read bit line RBL.

[0162] The memory cell is configured such that: in response to a reversal of the magnetic moment of a magnetic layer of any magnetic tunnel junction in the memory cell, a logic signal outputted by the comparator output terminal CMP0 is reversed.

[0163] When reading, the read word line RWL is set to a high level, the second transistor T2 and the third transistor T3 are turned on, and a read current is applied through the power line SL. The read current passes through the two spin electronic devices respectively, and the read voltages V1 and V2 are respectively sent to the first input terminal CMP1 and the second input terminal CMP2 of the comparator. If the magnetic moment of the spin electronic device connected to the second transistor T2 is in a parallel state, the voltage at the first input terminal CMP1 of the comparator is VP The magnetic moment of the spin electronic device connected to the third transistor T3 is in an antiparallel state, and the voltage at the second input terminal CMP2 of the comparator is V AP . Usually, V AP Greater than V P The voltage difference is: V2-V1=V AP -V P ; Compared with a single device, the voltage at the first input terminal CMP1 of the comparator is generally V AP and V P The average value, V1=(V AP +V P ) / 2. Compared with the reading voltage difference of a single spin electronic device, the reading window of the storage unit is increased, solving the problem of a small reading window of a single device. A small reading window is prone to the problem of misreading. Therefore, the above embodiment can improve the reading accuracy.

[0164] When writing, the first transistor T1 is turned on and a write current is applied from the power line SL. The current flows through the spin-orbit moment layer. Due to the action of the spin-orbit moment and the damping-like moment, the magnetic layer is flipped to achieve the binary "1" and "0" write operation.

[0165] In some other embodiments, a storage unit such as Figure 8 As shown, a spin electronic device is included.

[0166] The memory cell further includes: a fourth transistor T4, a fifth transistor T5, a power line SL, a write word line WWL, a read word line RWL, and a bit line BL.

[0167] The fourth transistor T4 has: a first electrode T 41 , the second electrode T of the fourth transistor 42 , the third electrode T of the fourth transistor 43 .

[0168] The first electrode T of the fourth transistor 41 is the gate, the second electrode T of the fourth transistor 42 is the source, the third electrode T 43 For the drain.

[0169] The fifth transistor T5 has: a first electrode T 51 , the second electrode T of the fifth transistor 52 , the third electrode T of the fifth transistor 53 .

[0170] The first electrode T of the fifth transistor 51 is the gate, the second electrode T of the fifth transistor 52 is the source, the third electrode T 53 For the drain.

[0171] The first electrode T of the fourth transistor 41 The second electrode T of the fourth transistor is electrically connected to the write word line WWL. 42 The third electrode T of the fourth transistor is electrically connected to the power line SL. 43 The spin-track moment layer of the memory cell is electrically connected to the spin-track moment layer of the memory cell, and the spin-track moment layer of the memory cell is also electrically connected to the bit line BL.

[0172] The first electrode T of the fifth transistor 51 The second electrode T of the fifth transistor is electrically connected to the read word line RWL. 52 The third electrode T53 of the fifth transistor is electrically connected to the power line SL, and the third electrode T53 of the fifth transistor is electrically connected to the electrode layer of the spin electronic device in the memory unit.

[0173] When the fourth transistor T4 is turned on, current flows from the fourth transistor T4 into the spin-orbit moment layer, changing the magnetization state of the magnetic layer, and realizing the writing function. When the fifth transistor T5 is turned on, current flows through the spin electronic device, and the resistance state of the spin electronic device is read. When it is higher than the reference voltage, the reading result is "1"; when it is lower than the reference voltage, the reading result is "0", realizing the function of reading binary "1" and "0".

[0174] By implementing a spin electronic device and a manufacturing method thereof disclosed in an embodiment of the present application, the out-of-plane damping-like torque formed by the current flowing through the MnPd3 layer in a direction perpendicular to the MnPd3 layer can cause a directional reversal of the magnetic moment of CoFeB, thereby realizing external field-free reversal of the spin electronic device; by applying voltage to the electrode layer, the potential barrier of the magnetic layer can be lowered, the required reversal current density can be reduced, and thus power consumption can be reduced; by adopting a storage unit composed of two spin electronic devices, the reading window is increased, further increasing the reading accuracy of the magnetic storage device.

[0175] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present application, which will not be described one by one here.

[0176] Embodiment 1

[0177] A spintronic device, such as Figure 1 As shown, including:

[0178] Substrate.

[0179] The spin-orbit moment layer is arranged on the top surface of the substrate and is used to generate a damping-like torque perpendicular to the spin-orbit moment layer, so that the magnetization direction of the magnetic layer is reversed under the action of current without the help of an external magnetic field. The material of the spin-orbit moment layer includes at least MnPd3, wherein the crystal plane of MnPd3 is (114).

[0180] The magnetic layer is disposed on the top surface of the spin-orbit moment layer.

[0181] The material of the magnetic layer is CoFeb.

[0182] The thickness of the magnetic layer is 1-1.4 nm.

[0183] The first insulating layer is arranged on the top surface of the magnetic layer.

[0184] The material of the first insulating layer is MgO.

[0185] The thickness of the first insulating layer is 1-2 nm.

[0186] The second insulating layer is arranged on the top surface of the first insulating layer.

[0187] The material of the second insulating layer is ZrO x .

[0188] The thickness of the second insulating layer is 10 nm.

[0189] The protection layer is arranged on the top surface of the second insulating layer.

[0190] The material of the protective layer is TaO x .

[0191] The thickness of the protective layer is 2-3 nm.

[0192] The electrode layer is arranged on the top layer of the spin electronic device and is connected to the corresponding voltage through the pins. The material of the electrode layer includes at least one of Ti / Au alloy, W, Ta, Pt and TiN.

[0193] Embodiment 2

[0194] A spintronic device, such as Figure 2 As shown, including:

[0195] Substrate.

[0196] The thickness of the substrate silicon dioxide is at least 500 nm.

[0197] The spin-orbit moment layer is arranged on the top surface of the substrate and is used to generate a damping-like torque perpendicular to the spin-orbit moment layer, so that the magnetization direction of the magnetic layer is reversed under the action of current without the help of an external magnetic field. The material of the spin-orbit moment layer includes at least MnPd3, wherein the crystal plane of MnPd3 is (114).

[0198] The thickness of the spin-orbit moment layer is 10 nm.

[0199] The magnetic layer is disposed on the top surface of the spin-orbit moment layer.

[0200] The material of the magnetic layer is CoFeb.

[0201] The thickness of the magnetic layer is 1 nm.

[0202] The first insulating layer is arranged on the top surface of the magnetic layer.

[0203] The material of the first insulating layer is MgO.

[0204] The thickness of the first insulating layer is 1 nm.

[0205] The reference layer is arranged on the top surface of the first insulating layer.

[0206] The material of the reference layer is CoFeB.

[0207] The thickness of the reference layer is 1.2 nm.

[0208] The pinning layer is disposed on the top surface of the reference layer.

[0209] The material of the pinning layer includes at least one of IrMn, FeMn, PtMn, a Pt / Co composite material, and a Ni / Co composite material.

[0210] The electrode layer is arranged on the top layer of the spin electronic device and is connected to the corresponding voltage through the pins. The material of the electrode layer includes at least one of Ti / Au alloy, W, Ta, Pt and TiN.

[0211] The material of the electrode layer is W.

[0212] The thickness of the electrode layer is 8 nm.

[0213] Embodiment 3

[0214] A method for manufacturing a spin electronic device, such as Figure 3 As shown, including:

[0215] S100: forming a spin-orbit moment layer with MnPd3 as the main component on the top surface of the substrate, wherein the crystal plane of MnPd3 is (114).

[0216] S200: forming a magnetic layer on the top surface of the spin-orbit moment layer.

[0217] S300: forming a first insulating layer on the top surface of the magnetic layer.

[0218] S310: forming a second insulating layer on the top surface of the first insulating layer.

[0219] S320: forming a protective layer on the top surface of the second insulating layer.

[0220] S400: forming an electrode layer into a film.

[0221] Embodiment 4

[0222] A method for manufacturing a spin electronic device, such as Figure 5 As shown, including:

[0223] S100: forming a spin-orbit moment layer with MnPd3 as the main component on the top surface of the substrate, wherein the crystal plane of MnPd3 is (114).

[0224] S200: forming a magnetic layer on the top surface of the spin-orbit moment layer.

[0225] S300: forming a first insulating layer on the top surface of the magnetic layer;

[0226] S310′: forming a reference layer on the top surface of the first insulating layer;

[0227] S320′: forming a pinning layer on the top surface of the reference layer.

[0228] S400: forming an electrode layer into a film.

[0229] Embodiment 5

[0230] substrate;

[0231] A spin-orbit moment layer is disposed on the top surface of the substrate;

[0232] At least one spintronic device as described above;

[0233] When the number of the spin electronic devices in the memory cell is greater than 1, at least one of the spin electronic devices shares a substrate and a spin-orbit moment layer.

[0234] Take the example of a memory cell including two spintronic devices, such as Figure 7 As shown, the magnetic tunnel junctions of the two spin electronic devices are separated by a preset distance L, wherein the magnetic tunnel junction includes: a magnetic layer, a first insulating layer, a reference layer, and a pinning layer;

[0235] The directions of magnetic moments between the reference layers of the two magnetic tunnel junctions in the memory cell are antiparallel;

[0236] The magnetic moments of the magnetic layers of any magnetic tunnel junction in the memory cell are in parallel.

[0237] The memory cell further includes: a first transistor T1, a second transistor T2, a third transistor T3, a comparator CMP, a power line SL, a write word line WWL, a read word line RWL, a write bit line WBL, and a read bit line RBL.

[0238] The first transistor T1 has: a first transistor first electrode T 11 , the second electrode T of the first transistor 12 and the third electrode T of the first transistor 13 .

[0239] The second transistor T2 has: a first electrode T 21 , the second transistor second electrode T 22 and the third electrode T of the second transistor 23 .

[0240] The third transistor T3 has: a first electrode T 31 , the second electrode T of the third transistor 32 and the third electrode T of the third transistor 33 .

[0241] The comparator CMP comprises: a comparator first input terminal CMP1 , a comparator second input terminal CMP2 , and a comparator output terminal CMP0 .

[0242] The first transistor first electrode T 11 The first transistor second electrode T is electrically connected to the write word line WWL. 12 The first transistor third electrode T is electrically connected to the spin-orbit moment layer of the memory cell, and the spin-orbit moment layer of the memory cell is also electrically connected to the power line SL. 13 Electrically connected to the write bit line WBL.

[0243] The first electrode T of the second transistor 21 The second transistor second electrode T is electrically connected to the read word line RWL. 22 The third electrode T of the second transistor is electrically connected to an electrode layer of a spin electronic device in the storage unit. 23 The comparator is electrically connected to the first input terminal CMP1.

[0244] The first electrode T of the third transistor 31 The second electrode T of the third transistor is electrically connected to the read word line. 32 The third transistor T is electrically connected to the electrode layer of another spin electronic device in the memory cell. 33 The comparator is electrically connected to the second input terminal CMP2.

[0245] The comparator output terminal CMP0 is electrically connected to the read bit line RBL.

[0246] The memory cell is configured such that: in response to a reversal of the magnetic moment of a magnetic layer of any magnetic tunnel junction in the memory cell, a logic signal outputted by the comparator output terminal CMP0 is reversed.

[0247] Embodiment 6

[0248] A storage unit, such as Figure 8 As shown, a spin electronic device is included.

[0249] The memory cell further includes: a fourth transistor T4, a fifth transistor T5, a power line SL, a write word line WWL, a read word line RWL, and a bit line BL.

[0250] The fourth transistor T4 has: a first electrode T 41 , the second electrode T of the fourth transistor 42 , the third electrode T of the fourth transistor 43 .

[0251] The first electrode T of the fourth transistor 41 is the gate, the second electrode T of the fourth transistor 42 is the source, the third electrode T 43 For the drain.

[0252] The fifth transistor T5 has: a first electrode T 51 , the second electrode T of the fifth transistor 52 , the third electrode T of the fifth transistor 53 .

[0253] The first electrode T of the fifth transistor 51 is the gate, the second electrode T of the fifth transistor 52 is the source, the third electrode T 53 For the drain.

[0254] The first electrode T of the fourth transistor 41 The second electrode T of the fourth transistor is electrically connected to the write word line WWL. 42 The third electrode T of the fourth transistor is electrically connected to the power line SL. 43 The spin-track moment layer of the memory cell is electrically connected to the spin-track moment layer of the memory cell, and the spin-track moment layer of the memory cell is also electrically connected to the bit line BL.

[0255] The first electrode T of the fifth transistor 51 The second electrode T of the fifth transistor is electrically connected to the read word line RWL. 52 The third electrode T53 of the fifth transistor is electrically connected to the power line SL, and the third electrode T53 of the fifth transistor is electrically connected to the electrode layer of the spin electronic device in the memory unit.

[0256] When the fourth transistor T4 is turned on, current flows from the fourth transistor T4 into the spin-orbit moment layer, changing the magnetization state of the magnetic layer, and realizing the writing function. When the fifth transistor T5 is turned on, current flows through the spin electronic device, and the resistance state of the spin electronic device is read. When it is higher than the reference voltage, the reading result is "1"; when it is lower than the reference voltage, the reading result is "0", realizing the function of reading binary "1" and "0".

[0257] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made to those skilled in the art without departing from the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A spintronic device, It is characterized in that include: substrate; The spin-orbit moment layer is arranged on the top surface of the substrate, and is used to generate a damping-like moment perpendicular to the spin-orbit moment layer, so that the magnetization direction of the magnetic layer is reversed under the action of current without the help of an external magnetic field. The material of the spin-orbit moment layer at least includes MnPd 3 , wherein the MnPd 3 The crystal face is 114; A magnetic layer, disposed on the top surface of the spin-orbit moment layer; A first insulating layer, disposed on the top surface of the magnetic layer; The electrode layer is arranged on the top layer of the spin electronic device.

2. The spintronic device according to claim 1, It is characterized in that Also includes: A second insulating layer, disposed on a top surface of the first insulating layer; The protection layer is arranged on the top surface of the second insulating layer.

3. The spintronic device according to claim 1, It is characterized in that Also includes: A reference layer, disposed on a top surface of the first insulating layer; The pinning layer is arranged on the top surface of the reference layer.

4. The spintronic device according to any one of claims 1 to 3, It is characterized in that The material of the substrate includes at least one of silicon dioxide, sapphire, and MgO single crystal; The material of the magnetic layer includes at least one of Co, CoFe and CoFeB; The material of the first insulating layer includes MgO and Al 2 O 3 At least one of; The electrode layer, the material of the electrode layer includes at least one of Ti / Au alloy, W, Ta, Pt and TiN.

5. A method for manufacturing a spintronic device, It is characterized in that include: On the top surface of the substrate will be MnPd 3 As the main component of the spin orbit moment layer, MnPd 3 The crystal face is 114; Forming a magnetic layer on the top surface of the spin-orbit moment layer; forming a first insulating layer on the top surface of the magnetic layer; The electrode layer is formed into a film.

6. The method for manufacturing a spintronic device according to claim 5, It is characterized in that After forming the first insulating layer on the top surface of the magnetic layer, the method further comprises: forming a second insulating layer on the top surface of the first insulating layer; A protective layer is formed on the top surface of the second insulating layer.

7. The method for manufacturing a spintronic device according to claim 5, It is characterized in that After forming the first insulating layer on the top surface of the magnetic layer, the method further comprises: Forming a reference layer on the top surface of the first insulating layer; A pinning layer is formed on top of the reference layer.

8. A storage unit, It is characterized in that include: substrate; A spin-orbit moment layer is disposed on the top surface of the substrate; At least one spintronic device according to any one of claims 1 to 4; When the number of the spin electronic devices in the memory cell is greater than 1, at least one spin electronic device shares a substrate and a spin-orbit moment layer.

9. The storage unit according to claim 8, It is characterized in that The storage unit includes two spin electronic devices, the magnetic tunnel junctions of the two spin electronic devices are separated by a preset distance, wherein the magnetic tunnel junction includes: a magnetic layer, a first insulating layer, a reference layer and a pinning layer; The magnetic moment directions between the reference layers of the two magnetic tunnel junctions in the memory cell are antiparallel; The magnetic moment directions between the magnetic layers of any magnetic tunnel junction in the memory cell are parallel.

10. The storage unit according to claim 9, It is characterized in that The memory cell further comprises: a first transistor, a second transistor, a third transistor, a comparator, a power supply line, a write word line, a read word line, a write bit line and a read bit line; The first transistor comprises: a first transistor first electrode, a first transistor second electrode and a first transistor third electrode; The second transistor comprises: a second transistor first electrode, a second transistor second electrode and a second transistor third electrode; The third transistor comprises: a third transistor first electrode, a third transistor second electrode and a third transistor third electrode; The comparator comprises: a first comparator input terminal, a second comparator input terminal and a comparator output terminal; The first electrode of the first transistor is electrically connected to the write word line, the second electrode of the first transistor is electrically connected to the spin orbit moment layer of the memory cell, the spin orbit moment layer of the memory cell is also electrically connected to the power line, and the third electrode of the first transistor is electrically connected to the write bit line; The first electrode of the second transistor is electrically connected to the read word line, the second electrode of the second transistor is electrically connected to an electrode layer of a spin electronic device in the memory cell, and the third electrode of the second transistor is electrically connected to the first input terminal of the comparator; The first electrode of the third transistor is electrically connected to the read word line, the second electrode of the third transistor is electrically connected to the electrode layer of another spin electronic device in the memory cell, and the third electrode of the third transistor is electrically connected to the second input terminal of the comparator; The comparator output terminal is electrically connected to the read bit line; The storage unit is configured such that, in response to a reversal of the magnetic moment of a magnetic layer of any magnetic tunnel junction in the storage unit, a logic signal outputted from an output terminal of the comparator is reversed.

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