Magnetic memory and memory system

Abstract

To provide a magnetic memory with a small number of error bits.SOLUTION: A flow of data reading by a magnetic memory includes: setting a temporary value at a first bit of temporarily read data in a data latch 31; shifting a magnetic wall and moving a next reading target memory cell to a reading position when the acquisition of temporarily read data for all reading target memory cells has not been completed yet; determining the presence or absence of a magnetic wall between the memory cells; setting, at the first bit of the temporarily read data, the same value as a second bit; shifting the bit of the temporarily read data towards an upper bit side by one bit when the magnetic wall has been detected; setting, at the first bit, a value opposite to the value of the second bit; and using magnetization information to update a value of a magnetization information latch with a value based on a type of a change in the detected magnetic wall. When the acquisition of the temporarily read data has been completed for all the reading target memory cells, magnetization resolution is performed.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments relate generally to magnetic memories and memory systems. [Background technology]

[0002] A memory system including a memory and a memory controller is known. An example of the memory is a magnetic memory using a magnetic material. The memory system is required to store and output data accurately. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0101901 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a magnetic memory and a memory system with a reduced number of error bits. [Means for solving the problem]

[0005] A magnetic memory according to an embodiment includes a magnetic body, a first circuit, a first storage circuit, a second storage circuit, and a second circuit. The magnetic body extends in a first direction and includes a plurality of portions aligned in the first direction. The first circuit outputs first information indicating the presence or absence of a domain wall between each two adjacent ones of the plurality of portions, and second information based on a combination of each of the two magnetization states. The first storage circuit stores a plurality of first bits corresponding to the plurality of portions, respectively. The most significant bit of the plurality of first bits has a value independent of the corresponding magnetization state of one of the plurality of portions. Each of the plurality of first bits has a value based on the first information. The second storage circuit stores the second information in a second bit. The second circuit outputs the first bits from the first memory circuit when the value of the least significant bit of the first bits matches the value of the second information stored in the second memory circuit, and outputs a plurality of third bits from the first memory circuit, each bit having a value opposite to that of the first bits, when the value of the least significant bit differs from the value of the second information stored in the second memory circuit. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 shows an example of functional blocks of an information processing system including a memory system according to the first embodiment. [Diagram 2] FIG. 2 illustrates an example of functional blocks of the memory system according to the first embodiment. [Diagram 3] FIG. 3 shows an example of functional blocks of the magnetic memory of the memory system of the first embodiment. [Figure 4] FIG. 4 shows an example of components of a memory cell array of the memory system of the first embodiment. [Diagram 5] FIG. 5 shows an example of the structure of a part of the memory cell array of the memory system of the first embodiment. [Figure 6] FIG. 6 shows an example of the structure of the magnetic body and the stacked body of the memory system of the first embodiment. [Figure 7] FIG. 7 shows an example of components of a read circuit of the memory system of the first embodiment. [Figure 8] FIG. 8 shows a flow of data writing by the magnetic memory of the memory system of the first embodiment. [Figure 9] FIG. 9 shows the state of some elements during operation in the memory system of the first embodiment. [Figure 10] FIG. 10 shows the state of some elements during operation in the memory system of the first embodiment. [Figure 11] FIG. 11 shows the state of some elements during operation in the memory system of the first embodiment. [Figure 12] FIG. 12 shows the state of some elements during operation in the memory system of the first embodiment. [Figure 13] FIG. 13 shows the state of some elements during operation in the memory system of the first embodiment. [Figure 14] FIG. 14 shows the state of some elements during operation in the memory system of the first embodiment. [Figure 15] FIG. 15 shows a flow of reading data from the magnetic memory of the memory system of the first embodiment. [Figure 16] FIG. 16 shows a flow of data reading by the memory system of the first embodiment. [Figure 17] FIG. 17 shows the unintended reversal of the magnetization state of a unit magnetization. [Figure 18] FIG. 18 illustrates an example of functional blocks of a memory controller in a memory system according to the second embodiment. [Figure 19] FIG. 19 shows a flow of reading data from the magnetic memory of the memory system of the second embodiment. [Figure 20] FIG. 20 shows a flow of data reading by the memory system of the second embodiment. [Figure 21] FIG. 21 shows an example of functional blocks of a magnetic memory in a memory system according to the third embodiment. [Figure 22] FIG. 22 shows the state of some elements during operation in the memory system of the third embodiment. [Diagram 23]FIG. 23 shows a flow of reading data from the magnetic memory of the memory system of the third embodiment. [Figure 24] FIG. 24 shows a flow of reading data from the magnetic memory of the memory system of the third embodiment. [Diagram 25] FIG. 25 shows a flow of data reading by the memory system of the third embodiment. [Figure 26] FIG. 26 shows a flow of data reading by the memory system of the third embodiment. [Figure 27] FIG. 27 shows an example of data generated during operation in the memory system of the third embodiment. [Figure 28] FIG. 28 shows a flow of reading data from the magnetic memory of the memory system of the fourth embodiment. [Figure 29] FIG. 29 shows a flow of data reading by the memory system of the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In an embodiment or different embodiments, a plurality of components having substantially the same functions and configurations may be distinguished from each other by adding an additional number or letter to the end of the reference numeral. In the embodiment following a certain described embodiment, the differences from the described embodiment will be mainly described. All descriptions of one embodiment are applicable to the description of another embodiment, unless expressly or obviously excluded.

[0008] Each functional block may be realized as either hardware, computer software, or a combination of both, and thus will be described generally in terms of their functionality so as to make it clear that each functional block may be either.

[0009] Any steps in the method flows of the embodiments are not limited to the order illustrated and may occur in an order different from the order illustrated and / or in parallel with other steps, unless otherwise indicated.

[0010] In this specification and claims, when a first element is "connected" to another second element, it includes the first element being connected to the second element directly or via an element that is constantly or selectively conductive.

[0011] 1. First embodiment 1.1.Configuration (Structure) 1.1.1. Information Processing System 1 shows an example of functional blocks of an information processing system including a memory system according to the first embodiment. The information processing system 100 includes a memory system 1 and a host device 5.

[0012] The host device 5 requests the memory system 1 to read and write data.

[0013] The memory system 1 is a system for storing data. The memory system 1 receives a data write request from the host device 5 and stores the requested data. The memory system 1 receives a data read request from the host device 5 and transmits the requested data to the host device 5.

[0014] Memory System 2 shows an example of functional blocks of the memory system 1 according to the first embodiment. As shown in FIG. 2, the memory system 1 includes a magnetic memory 2 and a memory controller 3.

[0015] The magnetic memory 2 is a device that uses magnetization to store data in a nonvolatile manner. The magnetic memory 2 includes a magnetic body having a plurality of magnetic domains, and stores data using the magnetization directions of the magnetic domains.

[0016] The memory controller 3 is a device that controls the magnetic memory 2. The memory controller 3 controls the magnetic memory 2 to read and write data based on a request from a host device 5.

[0017] The memory controller 3 includes functional blocks such as a host interface 11, a read only memory (ROM) 12, a random access memory (RAM) 13, a central processing unit (CPU) 14, a memory interface 15, and an error correction circuit 16.

[0018] The memory controller 3 functions as sub-parts such as an error correction control unit, a write control unit, a read control unit, a signal transmission control unit, and a signal reception control unit based on the operation being performed. The error correction control unit controls the entire process performed for error correction, and performs data division, data combination, temporary storage of data, data supply, control of the encoding control unit, and control of the decoding control unit. The write control unit controls the process for writing data to the magnetic memory 2, prepares data to be written to the magnetic memory 2, and generates a command CMD and address information ADD for writing. The read control unit controls the process for reading data from the magnetic memory 2, and generates a command CMD for reading and address information ADD for identifying data based on data read from the magnetic memory 2. The signal transmission control unit controls the transmission of signals including data DAT, command CMD, address information ADD, and control signal CNT to the magnetic memory 2, and controls the memory interface 15. The signal reception control unit controls the reception of signals including data DAT and control signal CNT from the magnetic memory 2, and controls the memory interface 15.

[0019] The host interface 11 is an interface through which the memory controller 3 communicates with the host device 5. The host interface 11 can be made up of hardware or a combination of hardware and software. The host interface 11 is connected to the host device 5 by wiring that enables communication in a format (or standard) that the host interface 11 and the host device 5 comply with.

[0020] The ROM 12 is a non-volatile memory. The ROM 12 stores a program including firmware. The program is configured to cause the memory controller 3 to perform the operations described in this specification by being executed by the CPU 14. The ROM 12 may be realized as one semiconductor chip, may be realized as a plurality of independent semiconductor chips, or may be a circuit formed on a semiconductor substrate.

[0021] The RAM 13 is a volatile memory. The RAM 13 temporarily stores data and stores the programs stored in the ROM 12 while the memory system 1 is powered. Examples of the RAM 13 include a dynamic random access memory (DRAM) and a static RAM (SRAM). The RAM 13 also functions as a working memory and a data buffer while the memory controller 3 is operating. The RAM 13 may be realized as one semiconductor chip, may be realized as a plurality of independent semiconductor chips, or may be a circuit formed on a semiconductor substrate.

[0022] The CPU 14 is a circuit that controls the overall operation of the memory controller 3. The memory controller 3 executes various operations and functions as various sub-portions by executing a program stored in the ROM 12 and loaded onto the RAM 13 by the CPU 14. The CPU 14 may be realized as one semiconductor chip, or as multiple independent semiconductor chips, or may be a circuit formed on a semiconductor substrate.

[0023] The memory interface 15 is an interface through which the memory controller 3 communicates with the magnetic memory 2. The memory interface 15 can be made of hardware or a combination of hardware and software. The memory interface 15 is connected to the magnetic memory 2 by wiring to enable communication in a format conforming to the magnetic memory 2 and the memory controller 3. The memory interface 15 transmits a command CMD and address information ADD to the magnetic memory 2. The memory interface 15 transmits a control signal CNT and data DAT to the magnetic memory 2, and receives the control signal CNT and data DAT from the magnetic memory 2.

[0024] The command CMD indicates an operation to be performed by the magnetic memory 2. The address information ADD specifies an area in the magnetic memory 2 from which data is to be read or written. The control signal CNT is a signal for controlling the operation timing between the magnetic memory 2 and the memory controller 3 and the operation timing inside the magnetic memory 2.

[0025] The error correction circuit 16 uses an error correction code (ECC) to detect and correct errors in data read from the magnetic memory 2. The error correction circuit 16 generates an error correction code from data (actual write data) to be written to the magnetic memory 2. The actual write data and the error correction code generated from the actual write data are written to the magnetic memory 2. The error correction circuit 16 uses the error correction code to detect errors in the data read from the magnetic memory 2, and corrects the error when an error is detected. The error correction circuit 16 may be realized as an independent dedicated semiconductor chip, may be a circuit formed on a semiconductor substrate, or may be realized by the CPU 14 executing firmware.

[0026] Magnetic Memory Fig. 3 shows functional blocks of the magnetic memory of the memory system of the first embodiment. As shown in Fig. 3, the magnetic memory 2 includes functional blocks such as a memory cell array 21, an input / output circuit 22, a control circuit 23, a row selection circuit 24, a column selection circuit 25, a write circuit 26, a read circuit 27, a shift control circuit 29, a data latch 31, a magnetization information latch 32, and a magnetization solving circuit 33.

[0027] The memory cell array 21 includes a plurality of strings STR. Each string STR includes a plurality of memory cells MC. Each memory cell MC can store one bit of data in a non-volatile manner and includes a magnetic material. In the memory cell array 21, wiring such as a plurality of source lines SL, a plurality of bit lines BL, and a plurality of field lines EL are also located. The wiring is not shown in FIG. 3.

[0028] The input / output circuit 22 is a circuit that inputs signals to the magnetic memory 2 and outputs signals from the magnetic memory 2. The input / output circuit 22 is connected to the memory controller 3 by wiring. The input / output circuit 22 receives a control signal CNT, a command CMD, address information ADD, and data DAT from the memory controller 3. The input / output circuit 22 transmits the control signal CNT and the data DAT to the memory controller 3. In the case of writing data to the magnetic memory 2, the data DAT includes write data. In the case of reading data from the magnetic memory 2, the data DAT includes read data.

[0029] The row selection circuit 24 is a circuit that selects a row of memory cells MC. The row selection circuit 24 receives address information ADD from the input / output circuit 22. The row selection circuit 24 obtains a row address from the address information ADD. The row selection circuit 24 sets a row specified by a row address in the memory cell array 21 to a selected state. The row selection circuit 24 includes circuits such as a multiplexer, a switch circuit, and a driver circuit.

[0030] The column selection circuit 25 is a circuit that selects a column of memory cells MC. The column selection circuit 25 receives address information ADD from the input / output circuit 22. The column selection circuit 25 obtains a column address from the address information ADD. The row selection circuit 24 selects a column (e.g., a bit line BL) specified by a column address in the memory cell array 21. The column selection circuit 25 includes circuits such as a multiplexer, a switch circuit, and a driver circuit.

[0031] The write circuit 26 is a circuit that controls writing of data to the memory cells MC. The write circuit 26 supplies a write current or a write voltage to the memory cell array 21 during data writing. This causes data to be written to a selected memory cell MC. For example, the write circuit 26 is connected to the memory cell array 21 via the row selection circuit 24. The write circuit 26 includes a voltage source and / or a current source.

[0032] The read circuit 27 is a circuit that controls the reading of data from the memory cells MC. The read circuit 27 is a circuit that controls the reading of data from the memory cells MC. The read circuit 27 supplies a read current or voltage to the memory cell array 21, senses a signal output from the memory cells MC, and outputs data related to the state of the memory cells MC from which data is read. The data related to the state of the memory cells MC from which data is read includes domain wall existence information and magnetization information. The domain wall existence information indicates, by at least one bit, whether the magnetizations of two adjacent memory cells MC are determined to be different. The magnetization information indicates, by at least one bit, the combination of the magnetizations of two adjacent memory cells MC. The magnetization information expresses how the state of the memory cell MC to be determined has changed from the state of the memory cell MC adjacent to the memory cell MC to be determined.

[0033] The shift control circuit 29 is a circuit that controls the movement of the memory cells MC. The shift control circuit 29 shifts the domain walls to store data in the memory cells MC at the specified addresses and to read data from the memory cells MC at the specified addresses. The shift control circuit 29 supplies a current or voltage to the memory cell array 21, thereby moving the domain walls. For example, the shift control circuit 29 is connected to the memory cell array 21 via the column selection circuit 25.

[0034] The data latch 31 is a circuit that stores data. When writing data, the data latch 31 receives write data from the input / output circuit and transmits the received write data to the write circuit 26. When reading data, the data latch 31 stores read data and temporary read data. The temporary read data is used to generate read data. The data latch 31 also has a function of a shift register and a function of storing data in which the value of one or more specified bits of the stored data is inverted. The data latch 31 transmits the read data to the input / output circuit 22.

[0035] The magnetization information latch 32 is a circuit that stores magnetization information. The magnetization information latch 32 can store one or more bits. The magnetization information latch 32 receives the magnetization information from the magnetization solving circuit 33.

[0036] The magnetization resolution circuit 33 is a circuit that generates read data from the domain wall existence information and the magnetization information. The magnetization resolution circuit 33 stores the latest received magnetization information in the magnetization information latch 32. The magnetization resolution circuit 33 generates information indicating data determined to be stored in the memory cell MC to be read based on the received domain wall existence information, and generates provisional read data. The magnetization resolution circuit 33 refers to the magnetization information in the magnetization information latch 32, and uses the magnetization information to generate read data determined to be stored in the memory cell MC to be read from the provisional read data.

[0037] The control circuit 23 is a circuit that controls the entire magnetic memory 2. The control circuit 23 receives a control signal CNT and a command CMD from the input / output circuit 22. The control circuit 23 generates a control signal based on the control indicated by the control signal CNT and the command CMD. The control circuit 23 controls the write circuit 26, the read circuit 27, the shift control circuit 29, and the magnetization solving circuit 33 using the generated control signals.

[0038] Memory Cell Array 4 shows an example of components of a memory cell array of the memory system of the first embodiment. As shown in FIG. 4, each string STR includes N memory cells MC_0 to MC_N-1, where N is a positive integer. In each string STR, the memory cells MC of this string STR are made of one magnetic body portion extending in a certain direction as a whole.

[0039] Fig. 5 shows an example of the structure of a portion of the memory cell array of the memory system of the first embodiment. As shown in Fig. 5, the memory cell array 21 includes a plurality of magnetic bodies UT and a plurality of laminated bodies LS. In addition, a plurality of conductors 41, a plurality of conductors 42, and a plurality of conductors 43 are located in the memory cell array 21.

[0040] The magnetic bodies UT are arranged in the X and Y directions, which are perpendicular to each other. Each magnetic body UT has a linear shape and extends in the Z direction. The Z direction is perpendicular to the X and Y directions. Hereinafter, a position in the Z direction from a certain position may be referred to as "upper", and a position in the opposite direction to the Z direction (-Z direction) from a certain position may be referred to as "lower". In one example, each magnetic body UT includes a thin film of magnetic material on the surface and a non-magnetic material inside. Each magnetic body UT functions as one string STR. The magnetic body UT includes a plurality of unit parts ML. Each unit part ML is arranged one by one in the extension direction of the magnetic body UT and is in contact with the adjacent unit part ML.

[0041] Each laminate LS includes a plurality of magnetic bodies and a plurality of insulators. The plurality of magnetic bodies and the plurality of insulators each have a layer shape and are aligned in the Z direction. Each laminate LS includes a structure that functions as a switching element and a structure that functions as an MTJ (Magnetic Tunneling Junction) element. The structure that functions as an MTJ element is located on the upper surface of the structure that functions as a switching element. The upper surface of each laminate LS contacts the lower surface of one magnetic body UT. The structure that functions as an MTJ element includes an MTJ, two ferromagnetic bodies, and an insulator between the two ferromagnetic bodies. The structure that functions as a switching element controls electrical conduction and non-conduction between both ends of the switching element.

[0042] The conductor 41 is located in the -Z direction from the pair of stacked bodies LS. The conductors 41 extend in the X direction and are aligned in the Y direction. Each conductor 41 functions as one source line SL. Each conductor 41 is connected to the lower surfaces of the multiple stacked bodies LS aligned in the X direction.

[0043] The conductor 42 is located in the Z direction from the set of magnetic bodies UT. The conductors 42 are aligned along an XY plane consisting of the X and Y directions, and in a direction intersecting the X and Y directions, for example, a direction intersecting the direction in which the conductors 42 extend. Each conductor 42 functions as one bit line BL. Each conductor 42 is connected to the upper surface of each of the multiple magnetic bodies UT that are different from the multiple magnetic bodies UT connected to one conductor 41.

[0044] The conductors 43 extend in the X direction. Each conductor 43 extends along a unit part ML located at the upper end of each of the multiple magnetic bodies UT aligned in the X direction. Each conductor 43 has a gap between it and the unit part ML located at the upper end of each of the multiple magnetic bodies UT aligned in the X direction. Each conductor 43 functions as one field line EL. When a current flows through the conductor 43 during data writing, a magnetic field is generated around the conductor 43. This magnetic field magnetizes the unit parts ML aligned at a gap from the conductor 43 in a direction based on the direction of the magnetic field.

[0045] FIG. 6 shows an example of the structure of the magnetic body and the laminate of the memory system of the first embodiment. The magnetic body UT includes a plurality of unit parts ML as described above with reference to FIG. 5, and includes N unit parts ML_0 to ML_N-1 as an example. The boundary between each two adjacent unit parts ML has an XY area smaller than the XY area at other positions. The XY area is the area in a plane along the XY plane. Since the XY area at each boundary of the unit parts ML is small, the domain wall is more likely to remain at the boundary of the unit parts ML than at other positions. A magnetic domain is formed in each unit part ML based on the fact that the domain wall is more likely to remain at the boundary of the unit parts ML. Each magnetic domain has magnetization. The magnetization can have one of two different directions. The direction of the magnetization is variable by control by the magnetic memory 2. For the purpose of ease of understanding, FIG. 6 shows a form in which each unit part ML has one magnetic domain. However, when two or more adjacent unit parts ML have magnetization in the same direction, the area consisting of these unit parts ML has a single magnetic domain and does not include a domain wall. The magnetic memory 2 stores one bit of data according to the direction of magnetization in each unit part ML. That is, each unit part ML functions as one memory cell MC.

[0046] The conductor 43 is aligned with the uppermost unit part ML_0. Data is written to the memory cell MC located in the unit part ML_0. The unit part ML_0 may be referred to as a write position.

[0047] The stacked body LS includes an MTJ element MTJ and a variable resistance material SEL. The variable resistance material SEL functions as a switching element. The variable resistance material SEL is a material that exhibits a dynamically variable resistance, and has, for example, the shape of a layer. The variable resistance material SEL is a two-terminal switching element, where a first terminal of the two terminals is one of the upper surface and the lower surface of the variable resistance material SEL, and a second terminal of the two terminals is the other of the upper surface and the lower surface of the variable resistance material SEL. When a voltage applied between the two terminals is less than a certain threshold voltage, the variable resistance material is in a "high resistance" state, for example, an electrically non-conductive state. When the voltage applied between the two terminals increases and becomes equal to or greater than the threshold voltage, the variable resistance material becomes in a "low resistance" state, for example, an electrically conductive state. When a voltage applied between the two terminals of the variable resistance material SEL in the low resistance state decreases and becomes less than the threshold voltage, the variable resistance material becomes in a high resistance state.

[0048] In one example, the variable resistance material SEL includes an insulator and a dopant introduced into the insulator by ion implantation. The insulator includes, for example, an oxide, and includes a material consisting essentially of SiO2. In one example, the dopant includes arsenic (As) and germanium (Ge). The phrase "consists essentially of" and similar phrases mean that the "consist essentially of" component is allowed to contain unintentional impurities.

[0049] The MTJ element MTJ includes a ferromagnetic layer RL, an insulating layer TB, and a ferromagnetic layer FL. In one example, as shown in FIG. 6, the insulating layer TB is located on the top surface of the ferromagnetic layer RL, and the ferromagnetic layer FL is located on the top surface of the insulating layer TB.

[0050] The ferromagnetic layer RL is a layer of material exhibiting ferromagnetism. The ferromagnetic layer RL has an easy axis of magnetization along a certain direction. The magnetization orientation of the ferromagnetic layer RL is intended to be unchanged by application of a voltage or current for reading and writing data in the memory cell MC and for shifting the domain walls. The ferromagnetic layer RL functions as a so-called reference layer. The ferromagnetic layer RL may include multiple layers.

[0051] The insulating layer TB is an insulating layer that contains, for example, magnesium oxide (MgO) or is substantially made of MgO, and functions as a so-called tunnel barrier.

[0052] The ferromagnetic layer FL is a layer of a material exhibiting ferromagnetism. The ferromagnetic layer FL includes, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or is substantially composed of CoFeB or FeB. The ferromagnetic layer FL has an easy axis of magnetization in a direction parallel to the easy axis of magnetization of the ferromagnetic layer RL. The magnetization direction of the ferromagnetic layer FL is variable and is linked to the magnetization direction of the bottom unit part ML_N-1, and has a magnetization direction parallel to the magnetization direction of the bottom unit part ML_N-1, for example. The ferromagnetic layer FL functions as a so-called memory layer.

[0053] When the magnetization direction of the memory layer FL is parallel to the magnetization direction of the reference layer RL, the MTJ element MTJ has a certain low resistance. When the magnetization direction of the memory layer FL is antiparallel to the magnetization direction of the reference layer RL, the MTJ element MTJ has a resistance higher than the resistance when the magnetization direction of the memory layer FL and the magnetization direction of the reference layer RL are parallel. Based on the resistance of the MTJ element, the magnetization direction of the memory layer FL and the magnetization direction of the unit part ML_N-1 can be determined. The data stored in the memory cell MC located in the unit part ML_N-1 can be determined based on the magnetization direction of the unit part ML_N-1. The bottom unit part ML_N-1 may be referred to as a read position.

[0054] Hereinafter, when a certain unit part has magnetization in one and the other of two mutually opposite directions, the unit part is referred to as being in a north pole state and a south pole state, respectively.

[0055] To read data from a certain memory cell MC, the domain wall of the magnetic body UT is shifted toward the stack LS until the memory cell MC to be read is located in the unit part ML_N-1. That is, data is written in the unit part ML_0, and data is read in the unit part ML_N-1. Such a data writing and reading method is a FIFO (First In First Out) method.

[0056] The stack LS may include further layers, such as electrical conductors.

[0057] 1.1.5.Readout Circuit 7 shows an example of components of the read circuit of the memory system of Embodiment 1. As shown in FIG. 7, the read circuit 27 includes information retention circuits 271 and 272 and a sense amplifier 273.

[0058] The information retention circuits 271 and 272 each retain a physical value reflecting the magnetization orientation of the memory cell MC, i.e., whether it is in the N-pole state or the S-pole state. That is, based on the magnetization orientation of the memory cell MC, the MTJ element MTJ is in a high resistance state or a low resistance state, and thus a physical value based on the resistance state of the MTJ element MTJ can be obtained. The physical value reflects the magnetization state of the memory cell MC at the read position, i.e., whether it is in the N-pole state or the S-pole state. Examples of the physical value include a voltage based on the resistance of the memory cell MC, and in this example, the information retention circuits 271 and 272 are capacitors.

[0059] One of the information retention circuits 271 and 272 retains a value based on the state of the memory cell MC at the read position. The memory cell MC at the read position may be referred to as the read position cell MC. The other of the information retention circuits 271 and 272 retains a value based on the state of the memory cell MC adjacent to the read position cell MC in the -Z direction, for example, retains a value based on the state of the memory cell MC that was at the read position before the domain wall shifted. The memory cell MC adjacent to the read position cell MC in the -Z direction may be referred to as the previous read position cell MC.

[0060] The sense amplifier 273 outputs domain wall existence information and magnetization information based on the respective values ​​of the information retention circuits 271 and 272, that is, the value for the read position cell MC and the value for the previous read position cell MC.

[0061] If the value for the read position cell MC and the value for the previous read position cell MC are substantially the same, for example, if the difference between the two values ​​is within a certain range, this means that the read position cell MC and the previous read position cell MC have the same magnetization state. In this case, there is no magnetic domain wall between the read position cell MC and the previous read position cell MC, and therefore the sense amplifier 273 outputs magnetic domain wall presence information, for example, "0" data, indicating that there is no magnetic domain wall.

[0062] On the other hand, if the value for the read position cell MC is different from the value for the previous read position cell MC, for example, if the difference between the two values ​​exceeds a certain range, this means that the read position cell MC and the previous read position cell MC have different magnetization states. In this case, a magnetic domain wall exists between the read position cell MC and the previous read position cell MC, and therefore the sense amplifier 273 outputs magnetic domain wall existence information, for example, "1" data, indicating that a magnetic domain wall exists.

[0063] When the previous read position cell MC is in the N-pole state and the read position cell MC is in the S-pole state, the magnetization information has a value indicating this, for example, data "0". On the other hand, when the previous read position cell MC is in the S-pole state and the read position cell MC is in the N-pole state, the magnetization information has a value indicating this, for example, data "1". The value of the magnetization information may be the opposite of this example.

[0064] 1.2.Operation The following description is based on an example in which the magnetic memory 2 treats memory cells MC in the S-pole state as storing data "0" and memory cells MC in the N-pole state as storing data "1." The magnetic memory 2 may store "1" data using memory cells MC in the S-pole state and store "0" data using memory cells MC in the N-pole state.

[0065] 1.2.1. Data writing 8 shows a flow of data writing by the magnetic memory of the memory system of the first embodiment. The flow of FIG. 8 starts when the magnetic memory 2 receives a write command instructing data writing and write data. The write command includes or is accompanied by address information ADD that identifies the memory cell MC to which the write data is to be written.

[0066] The magnetic memory 2 sets write data in the data latch 31 (ST1). The write data includes one or more bits. When writing data of multiple bits, the data is written one bit at a time.

[0067] The magnetic memory 2, for example, the write circuit 26, selects bits (write bits) to be written to the memory cells MC in the write data (ST2). The write bits are selected one by one, for example, from the most significant bit to the least significant bit of the bit string of the write data.

[0068] The magnetic memory 2, for example, the control circuit 23 controls the shift control circuit 29 to shift the memory cell MC of the write destination to the write position (ST3). If the memory cell MC at the write position is unwritten, step ST3 is skipped.

[0069] If the bit to be written has “0” data (ST4_Yes), the magnetic memory 2, for example, the write circuit 26, puts the memory cell MC to be written into the S-pole state (ST5). If the bit to be written has “1” data (ST4_No), the magnetic memory 2, for example, the write circuit 26, puts the memory cell MC to be written into the N-pole state (ST6).

[0070] Steps ST5 and ST6 are continued to step ST7. The magnetic memory 2, for example, the write circuit 26, judges whether all bits of the write data have been written (ST7). If all bits have been written (ST7_Yes), the flow of FIG. 8 ends. If all bits have not been written (ST7_No), the flow proceeds to step ST2.

[0071] 1.2.2. Data Reading Data reading uses a magnetization solution. The principle of the magnetization solution is described with reference to FIG. 9 to FIG. 14. FIG. 9 to FIG. 14 sequentially show the states of several elements during operation in the memory system of the first embodiment. Each of FIG. 9 to FIG. 14 shows different times in the left-right direction of the figure. Each of FIG. 9 to FIG. 14 shows a unit part ML of the read position and several unit parts ML aligned with this unit part in the top row of the figure. Each of FIG. 9 to FIG. 14 shows the domain wall existence information, the provisional read data, and the value of the magnetization information latch in the second, third, and bottom rows from the top, respectively. The provisional read data is a string of bits with the same number as the number of memory cells MC to be read. The provisional read data indicates the magnetization state of a certain memory cell MC in each bit. The bits of the provisional read data are shown in order from the most significant bit to the least significant bit for the memory cells MC located from the beginning to the end in the direction of the shift of the domain wall during reading. The bits of the provisional read data are referred to as the first, second, third, fourth, and fifth most significant bit, from the least significant bit (or last bit) to the most significant bit (or first bit). Hereinafter, the state in which each bit has an invalid data value is indicated by the symbol "-".

[0072] 9, as an example, the read target is five memory cells MC, and unit parts ML_N-1, ML_N-2, ML_N-3, ML_N-4, and ML_N-5 are in state 0. In state 0, unit parts ML_N-1, ML_N-2, ML_N-3, ML_N-4, and ML_N-5 are occupied by memory cells MC1, MC2, MC3, MC4, and MC5, respectively. Memory cells MC1, MC2, MC4, and MC5 are in the N pole state, and memory cell MC3 is in the S pole state.

[0073] The magnetization state of the memory cell MC1 is unknown, and therefore, as shown in FIG. 10, the magnetization solving circuit 33 stores a tentative value data in the first bit of the tentative read data. Thus, the tentative read data has "----0" in the fifth to first bits, respectively. The tentative value data may be "0" data (i.e., data indicating a south pole state) or "1" data (i.e., data indicating a north pole state). First, an example of inputting "0" data, i.e., an example in which a magnetization state opposite to that of the memory cell MC1 is assumed, will be described. That is, the memory cell MC1 is assumed to be in a south pole state, and subsequent processing occurs under this assumption.

[0074] Since no change in magnetization has been detected, the magnetization solving circuit 33 does not update the value of the magnetization information latch 32 regardless of the value of the magnetization information.

[0075] 11, the domain walls are shifted to obtain state 1. In state 1, memory cells MC2 to MC5 are located in unit portions ML_N-1, ML_N-2, ML_N-3, and ML_N-4, respectively.

[0076] Since the memory cell MC2 has the same magnetization state as the memory cell MC1, the domain wall existence information has data "0". The magnetization resolution circuit 33 shifts the bit of the provisional read data by one bit toward the more significant bit side, and stores a value based on the domain wall existence information in the first order bit. If the domain wall existence information indicates the absence of a domain wall, the magnetization resolution circuit 33 sets the same value as the second order bit (i.e., the first order bit before the domain wall shift) in the first order bit of the provisional read data based on this. That is, the memory cell MC2 is treated as having the same S pole state as the S pole state assumed to be possessed by the memory cell MC1. The provisional read data has "---00" in the fifth order bit to the first order bit, respectively.

[0077] Since no change in magnetization has occurred, the magnetization solving circuit 33 does not update the value of the magnetization information latch 32 regardless of the value of the magnetization information.

[0078] 12, the domain walls are shifted to obtain state 2. In state 2, memory cells MC3 to MC5 are located in unit portions ML_1, ML_2, and ML_3, respectively.

[0079] Since the memory cell MC3 has a different magnetization state from the memory cell MC2, the domain wall existence information has data "1". The magnetization resolution circuit 33 shifts the bit of the provisional read data by one bit toward the more significant bit side, and stores a value based on the domain wall existence information in the first order bit. If the domain wall existence information indicates the existence of a domain wall, the magnetization resolution circuit 33 stores a value opposite to that of the second order bit in the first order bit of the provisional read data based on this. In other words, the memory cell MC3 is treated as having an N pole state opposite to the S pole state assumed to be possessed by the memory cell MC2. Therefore, the provisional read data has "--001" in the fifth to first order bits, respectively.

[0080] Since a change in magnetization has occurred, the magnetization solving circuit 33 updates the value of the magnetization information latch 32 with a value indicating a change in the pole of the memory cell MC3 based on the magnetization state assumed to be possessed by the memory cell MC2, whose magnetization state was determined before the domain wall shift. In the current example, since the memory cell MC3 has changed from the north pole state of the memory cell MC2 to the south pole state, "0" data is set in the magnetization information latch 32.

[0081] As shown in FIG. 13, the same process as that described above with reference to FIG. 11 and FIG. 12 is performed continuously. In state 3, memory cells MC4 and MC5 are located in unit parts ML_0 and ML_1, respectively. The memory cell MC4 has a magnetization state different from that of the memory cell MC3. Therefore, the domain wall existence information has data "1". The magnetization solving circuit 33 shifts the bit of the provisional read data by one bit to the higher bit side, and sets a value different from that of the second bit, i.e., data "0", in the first bit. Therefore, the provisional read data has "-0010" in the fifth to first bits, respectively. Since the memory cell MC4 has changed from the S state of the memory cell MC3 to the N pole state, data "1" is set in the magnetization information latch 32.

[0082] In state 4, the memory cell MC5 is located in the unit portion ML_1. The memory cell MC5 has the same magnetization state as the memory cell MC4. Therefore, the domain wall existence information has data "0". The magnetization solving circuit 33 shifts the bit of the provisional read data by one bit to the higher bit side, and sets the same value as the second bit, i.e., data "0", in the first bit. Therefore, the provisional read data has "00100" in the fifth to first bits, respectively. Since no change in magnetization has occurred, the magnetization information latch 32 maintains data "1".

[0083] When the magnetic domain wall shift is performed from state 4, the magnetic domain wall shift is completed. Then, the magnetic domain resolution circuit 33 performs magnetic domain resolution. The magnetic domain resolution refers to generating read data from the provisional read data based on the value of the most significant bit of the provisional read data.

[0084] The magnetization solution circuit 33 generates read data based on the value of the magnetization information latch 32 and the value of the most significant bit of the provisional read data. If the value of the magnetization information latch 32 and the value of the most significant bit of the provisional read data match, the magnetization solution circuit 33 uses the provisional read data as it is as read data.

[0085] On the other hand, if the value of the magnetization information latch 32 does not match the value of the first bit of the provisional read data, this means that the assumed magnetization state of the first memory cell MC to be read (i.e., memory cell MC1) does not match the actual magnetization state. Based on this, a set of opposite values ​​of all bits of the provisional read data is used as the read data. In the current example, the value of the magnetization information latch 32 does not match the value of the first bit of the provisional read data. For this reason, the magnetization solving circuit 33 uses the bit string of "11011" as the read data.

[0086] 9 to 13, Fig. 14 shows a case where the assumed magnetization state of the first memory cell MC to be read (i.e., memory cell MC1) coincides with the actual magnetization state. The magnetization states of memory cells MC1 to MC5 are the same as those in Figs. 9 to 13.

[0087] In state 0, the tentative read data has "----1" in the 5th to 1st bit, respectively.

[0088] In state 1, the tentative read data has "---11" from the 5th to 1st bit, respectively.

[0089] In state 2, the tentative read data has "--110" from the fifth bit to the first bit, respectively, and the magnetic information latch 32 has "0" data.

[0090] In state 3, the tentative read data has "-1101" from the fifth bit to the first bit, respectively, and the magnetic information latch 32 has data "1".

[0091] In states 4 and 5, the tentative read data has "11011" from the 5th to 1st bit, respectively.

[0092] The value of the magnetization information latch 32 and the value of the first bit of the provisional read data match, so the magnetization solving circuit 33 uses the provisional read data as it is, as the read data.

[0093] Fig. 15 shows a flow of data reading by the magnetic memory of the memory system of the first embodiment. The flow of Fig. 15 starts when the magnetic memory 2 receives a read command instructing data reading. The read command is accompanied by or includes address information ADD that identifies the memory cell MC from which data is to be read.

[0094] First, the magnetic memory 2 acquires provisional read data and magnetization information in steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, and ST19.

[0095] The magnetic memory 2, for example the magnetization solving circuit 33, sets a provisional value in the first bit of the provisional read data in the data latch 31 according to the control of the control circuit 23 (ST11).

[0096] If acquisition of tentative read data for all read target memory cells MC is not complete (ST12_No), the magnetic memory 2, for example the control circuit 23, shifts the domain wall (ST13) and moves the next read target memory cell MC to the read position.

[0097] The magnetic memory 2, for example, the magnetization resolution circuit 33, determines whether or not there is a domain wall between the memory cell MC at the read position and the memory cell MC that was at the read position before the previous domain wall shift. If no domain wall is detected (ST14_No), the magnetization resolution circuit 33 shifts the bit of the provisional read data by one bit toward the higher bit side (ST15). Next, the magnetization resolution circuit 33 sets the same value as the second most significant bit in the first most significant bit of the provisional read data (ST16). Step ST16 continues to step ST12.

[0098] If a magnetic domain wall is detected (ST14_Yes), the magnetization resolution circuit 33 shifts the bits of the provisional read data one bit to the more significant bit side (ST17). Next, the magnetization resolution circuit 33 sets the value of the first bit of the provisional read data to the opposite value of the second bit (ST18).

[0099] The magnetization solving circuit 33 uses the magnetization information to update the value of the magnetization information latch 32 with a value based on the type of domain wall change detected as step ST14 (ST19). Step ST19 is a continuation of step ST12.

[0100] If the acquisition of tentative read data has been completed for all of the memory cells MC to be read (ST12_Yes), the process proceeds to step ST21. The magnetic memory 2 performs magnetization solution in ST21, ST22, and ST23.

[0101] If the value of the first bit of the provisional read data matches the value of the magnetization information latch 32 (ST21_Yes), the magnetization solution circuit 33 uses the provisional read data as it is as read data (ST22). The flow of FIG. 15 ends when the read data is obtained.

[0102] If the value of the most significant bit of the provisional read data does not match the value of the magnetization information latch 32 (ST21_No), the magnetization solution circuit 33 generates, as read data, a set of bits having opposite values ​​for all bits of the provisional read data (ST23).

[0103] Fig. 16 shows a flow of reading data by the memory system of the first embodiment. The flow of Fig. 16 starts when the host device 5 decides to read data from the memory system 1.

[0104] The host device 5 transmits a read request command instructing data reading (ST31). The read request command is accompanied by or includes an address specifying the target area from which data is read.

[0105] Upon receiving the read request command, the memory system 1 transmits a read command to the magnetic memory 2 based on the received read request command (ST32). The transmission of the read command includes the generation of the read command. The generation of the read command includes obtaining information (e.g., physical address) that identifies the memory cell MC storing the target data of the data read request from the target area (e.g., logical address) of the data read request. The read command includes or is accompanied by address information ADD that identifies the target memory cell MC from which data is read.

[0106] When the magnetic memory 2 receives the read command, it performs data reading using the magnetization solution (ST33). Data reading using the magnetization solution includes execution of steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, ST19, ST21, ST22, and ST23 of the flow shown in Fig. 15. Upon completion of step ST33, read data is obtained.

[0107] The magnetic memory 2, for example the control circuit 23, transmits the read data to the memory controller 3 (ST34).

[0108] When the memory controller 3 receives the read data, it uses the error correction circuit 16 to perform error correction on the read data (ST35). If the error correction is successful (ST36_Yes), the memory controller 3 transmits the error-corrected data to the host device 5 as the data subject to the read request (ST37). Successful error correction includes a case where the data subject to error correction does not contain an error. When the host device 5 receives the data subject to the read request (ST38), the flow of FIG. 16 ends.

[0109] If the error correction fails (ST36_No), the memory controller 3 transmits a signal indicating a read error status to the host device 5 (ST39). When the host device 5 receives the status (ST40), the flow in FIG. 16 ends.

[0110] 1.3. Advantages (Effects) According to a first embodiment, as described below, a magnetic memory and a memory system having fewer error bits in read data are provided.

[0111] It is possible to store 1-bit data in the unit parts. Such a type is hereinafter referred to as a magnetization-data correspondence type. The difference between the resistance of the MTJ element when the magnetizations of the two ferromagnetic layers of the MTJ element are parallel and the resistance of the MTJ element when the magnetizations of the two ferromagnetic layers are antiparallel is small. For this reason, it is difficult to store data in the magnetization-data correspondence type and read the data using the difference in resistance. For this reason, memories using domain wall shift generally store 1-bit data between the unit parts. For example, when there is no domain wall between two adjacent unit parts, it is treated as storing "0" data between these unit parts, and when there is a domain wall between two unit parts, it is treated as storing "1" data between these unit parts. Such a type is hereinafter referred to as a domain wall-data correspondence type.

[0112] The magnetization state of the unit part may change unintentionally after data writing, as shown in FIG. 17. Also, data writing may fail, and data different from the written data may be written. As an example, assume that "1010" data was written or was to be written by the magnetic wall by making the unit parts ML_1, ML_2, ML_3, ML_4, and ML_5 into S-pole, N-pole, N-pole, S-pole, and S-pole states, respectively, but when reading, the unit part ML_N-2 is in the S-pole state. In this case, the data that was to be written or was written is "1010", but "0110" data is read. This means that the reversal of the magnetization state of one unit part has produced a two-bit error. Furthermore, when reading data, the magnetic wall shift may fail. In this case, the magnetization in many unit parts is misjudged, and the number of bit errors is large.

[0113] According to the first embodiment, the magnetic memory 2 generates provisional read data by using the difference between the magnetization state of the memory cell MC to be read and the magnetization state of the memory cell MC adjacent to the memory cell MC to be read and the magnetization state of which has been determined before. The magnetic memory 2 continues to update the magnetization information indicating the type of change in magnetization of the two adjacent memory cells MC, and generates read data using the magnetization information and the provisional read data. Although the magnetization state of the first memory cell MC to be read is unknown, it is possible to generate correct read data even if the provisional value is different by using the magnetization change and the change type of the adjacent memory cells. With this method, data can be read even in the magnetization-data compatible type.

[0114] The magnetization-data correspondence type limits the number of error bits caused by reversal of the magnetization state of one unit portion to 1 bit, thereby realizing a magnetic memory 2 with a small number of error bits.

[0115] Furthermore, the memory system and magnetic memory of the first embodiment are of the magnetization-data corresponding type, and therefore can read data with low latency and have a large storage capacity. As is clear from FIG. 17, the magnetic domain wall-data corresponding type can store 4 bits of data using five unit parts ML, whereas the magnetic domain wall-data corresponding type of the first embodiment can store 5 bits of data. Thus, reading of a certain number of bits of data is completed faster in the case of the magnetic domain wall-data corresponding type than in the case of the magnetic domain wall-data corresponding type. The magnetic domain wall-data corresponding type can realize more bits using a certain number of unit parts than the case of using the same number of unit parts ML in the case of the magnetic domain wall-data corresponding type.

[0116] Furthermore, the memory system and magnetic memory of the first embodiment are of the magnetization-data compatible type, and therefore data can be added to unwritten unit portions of a magnetic body to which data has already been written. The domain wall-data compatible type stores data that differs depending on the presence or absence of a domain wall, and therefore when determining the magnetization state of a unit portion for data writing, it is necessary to know the state of an adjacent unit portion. For this reason, data cannot be added to unwritten unit portions of a magnetic body to which data has already been written. On the other hand, according to the first embodiment, being of the magnetization-data compatible type, it is not necessary to know the magnetization state of an adjacent unit portion ML, and therefore data can be added to unwritten unit portions ML of a magnetic body to which data has already been written.

[0117] 1.4. Variations The above description is based on an example in which data writing and data reading are of the FIFO type, but the first embodiment can also adopt a LIFO (Last In First Out) type. The direction of the domain wall shift when reading data is the same as the direction of the domain wall shift when writing data in the FIFO type, whereas the direction of the domain wall shift when reading data is opposite to the direction of the domain wall shift when writing data in the LIFO type. In the LIFO type, a structure in which the stack LS is inverted with respect to the Z direction is located between the unit part ML_0 and the conductor 42.

[0118] When all bits of data requested by the host device 5 have the same value, the set of unit parts ML to which the data is written does not include a magnetic wall. In such a case, an error bit can be created by deliberately inverting the value of, for example, one bit in the bit string written to the memory cell. The error bit can be created by the memory controller 3 or the magnetic memory 2.

[0119] 2. Second embodiment The second embodiment differs from the first embodiment in terms of the components that perform the magnetization solution.

[0120] FIG. 18 shows an example of a functional block of a memory controller of a memory system of the second embodiment. As shown in FIG. 18, the memory controller 3b further includes a magnetization resolver 18 in addition to the functional blocks included in the memory controller 3 of the first embodiment. The magnetization resolver 18 is a functional block that generates read data from provisional read data using magnetization information. The magnetization resolver 18 may be realized as one or more dedicated semiconductor chips or circuits, or may be a circuit formed on a semiconductor substrate. Alternatively, the magnetization resolver 18 may be realized as a sub-part that is stored in the ROM 12 and is realized by the CPU 14 executing a program loaded on the RAM 13.

[0121] The magnetization resolver 18 executes part of the functions of the magnetization resolver circuit 33 of the memory system of the first embodiment. That is, the magnetization resolver 18 receives tentative read data and magnetization information from the magnetic memory 2b in response to a data read command sent by the memory controller 3b. The magnetization resolver 18 generates read data based on the received tentative read data and magnetization information.

[0122] The magnetic memory 2b includes the same functional blocks as those of the magnetic memory 2 of the first embodiment. As in the first embodiment, the magnetization solving circuit 33b of the magnetic memory 2b generates provisional read data based on the domain wall existence information and updates the value in the magnetization information latch 32. On the other hand, the magnetization solving circuit 33b does not perform magnetization solving.

[0123] Fig. 19 shows a flow of data read by the magnetic memory of the memory system of the second embodiment. The flow of Fig. 19 starts when the magnetic memory 2b receives a read command. The flow of Fig. 19 differs from the flow of Fig. 15 of the first embodiment in that the flow ends when acquisition of tentative read data for all memory cells MC to be read is completed (ST12_Yes).

[0124] Fig. 20 shows a flow of data reading by the memory system of the second embodiment. The flow of Fig. 20 starts when the host device 5 decides to read data from the memory system 1b.

[0125] 20, step ST32 is followed by step ST41. In step ST41, the magnetic memory 2b acquires the provisional read data and the magnetization information. The acquisition of the provisional read data and the magnetization information includes the execution of steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, and ST19 of the flow shown in FIG.

[0126] The magnetic memory 2b transmits the provisional read data and the magnetization information in the magnetization information latch 32b to the memory controller 3b (ST42).

[0127] When the memory controller 3b receives the tentative read data and the magnetization information, it uses the magnetization resolver 18 to perform magnetization resolution (ST43). The magnetization resolution includes the execution of steps ST21, ST22, and ST23 of the flow shown in FIG. 15 of the first embodiment. The read data is obtained by the magnetization resolution. Step ST43 continues to step ST35. The subsequent operations including step ST35 are the same as those in the first embodiment (FIG. 16).

[0128] According to the second embodiment, the magnetic memory 2b generates the tentative read data and the magnetization information in the same manner as in the first embodiment, and the memory controller 3b performs magnetization solving to generate the read data, thereby obtaining the same advantages as in the first embodiment.

[0129] 3. Third embodiment The third embodiment differs from the first embodiment in the method of storing magnetization information.

[0130] The memory controller 3c of the third embodiment has the same functional blocks as the functional blocks of the memory controller 3 of the first embodiment. On the other hand, the error correction circuit 16c of the memory controller 3c is configured to be able to perform the operation described below.

[0131] Fig. 21 shows an example of functional blocks of a magnetic memory in a memory system according to the third embodiment. As shown in Fig. 21, the magnetic memory 2c includes a domain wall existence information latch 37 in addition to the functional blocks included in the magnetic memory 2 according to the first embodiment. The domain wall existence information latch 37 has a function of a shift register. The magnetization information latch 32c also has a function of a shift register.

[0132] 22 shows the states of several elements during operation in the memory system of the third embodiment, similar to Fig. 9 to Fig. 14 of the first embodiment. The second, third, fourth, and bottom rows of Fig. 22 show the domain wall existence information, the provisional read data, the value of the domain wall existence information latch, and the value of the magnetization information latch, respectively.

[0133] The domain wall existence information latch 37 stores the domain wall existence information by performing the same operation as a shift register. That is, every time the domain wall existence information latch 37 receives new domain wall existence information, it shifts the bit of the domain wall existence information already stored by one bit toward the most significant bit, and sets the domain wall existence information last received to the most significant bit.

[0134] Unlike the first embodiment, the magnetization information latch 32c stores magnetization information by performing the same operation as a shift register. That is, every time the magnetization information latch 32c receives new magnetization information, it shifts the bit of the magnetization information already stored by one bit to the higher-order bit side and sets the magnetization information last received to the most significant bit.

[0135] The magnetization resolution is performed by comparing the value of the most significant bit of the provisional read data with the value of the bit of the magnetization information latch 32c that is the same as the least significant bit of all bits having "1" data in the domain wall presence information latch 37. That is, when the value of the most significant bit of the provisional read data matches the value of the bit of the magnetization information latch 32c that is the same as the least significant bit of all bits having "1" data in the domain wall presence information latch 37, the magnetization resolution circuit 33c uses the provisional read data as it is as read data. Hereinafter, the least significant bit of all bits having "1" data in the domain wall presence information latch 37 may be referred to as the least significant bit of "1" data.

[0136] On the other hand, if the value of the most significant bit of the provisional read data does not match the value of the bit of the magnetization information latch 32c that is at the same position as the least significant bit of the “1” data of the magnetic wall existence information latch 37, the magnetization solution circuit 33c uses a set of opposite values ​​of all bits of the provisional read data as the read data.

[0137] 3.2.Operation 23 and 24 show the flow of data read by the magnetic memory of the memory system of the third embodiment. As shown in FIG. 23 and FIG. 24, after step ST16, the magnetization solution circuit 33c shifts the bit of the magnetic domain wall existence information latch 37 by one bit to the higher bit side (ST51). The magnetization solution circuit 33c sets the most significant bit of the magnetic domain wall existence information latch 37 to "0" (ST52). The magnetization solution circuit 33c shifts the bit of the magnetic domain wall existence information latch 32c by one bit to the higher bit side (ST53). The magnetization solution circuit 33c sets the most significant bit of the magnetic domain wall existence information latch 32c to "0" (ST54). Step ST54 is continued to step ST12.

[0138] After step ST18, the magnetization solution circuit 33c shifts the bit of the magnetic domain wall presence information latch 37 by one bit to the more significant bit side (ST55). The magnetization solution circuit 33c sets the most significant bit of the magnetic domain wall presence information latch to "1" (ST56). The magnetization solution circuit 33c shifts the bit of the magnetic domain wall presence information latch 32c by one bit to the more significant bit side (ST57). The magnetization solution circuit 33c sets the value of the magnetic information to the most significant bit of the magnetic domain wall presence information latch 32c (ST58). Step ST58 continues to step ST12.

[0139] If the acquisition of tentative read data has been completed for all of the read target memory cells MC (ST12_Yes), the process proceeds to step ST59. The magnetic memory 2 performs magnetization solution in ST59, ST22, and ST23.

[0140] If the value of the most significant bit of the provisional read data matches the value of the bit of the magnetization information latch 32c that is at the same order as the least significant bit of the “1” data of the domain wall existence information latch 37 (ST59_Yes), the process proceeds to step ST22. If the value of the most significant bit of the provisional read data does not match the value of the most significant bit of the magnetization information latch 32c that is at the same order as the least significant bit of the “1” data of the domain wall existence information latch 37 (ST59_No), the process proceeds to step ST23.

[0141] The set of steps ST15 and ST16, the set of steps ST51 and ST52, and the set of steps ST53 and ST54 can be performed in any order. The set of steps ST17 and ST18, the set of steps ST55 and ST56, and the set of steps ST57 and ST58 can be performed in any order.

[0142] Figures 25 and 26 show the flow of data reading by the memory system of the third embodiment. The flow of Figures 25 and 26 starts when the host device 5 decides to read data from the memory system 1c.

[0143] As shown in Fig. 25 and Fig. 26, step ST32 continues to step ST61. As step ST61, the magnetic memory 2c performs data reading using the magnetization solution. The data reading using the magnetization solution includes the execution of steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, ST22, ST23, ST51, ST52, ST53, ST54, ST55, ST56, ST57, ST58, and ST59 of the flow shown in Fig. 23 and Fig. 24. Upon completion of step ST61, read data is obtained. Step ST61 continues to step ST34.

[0144] If the error correction fails (ST36_No), the memory controller 3c sends a command to the magnetic memory 2c instructing it to output the bit string of the magnetic wall presence information in the magnetic wall presence information latch 37 and the bit string of the magnetization information in the magnetic information latch 32c (ST62).

[0145] Upon receiving the command, the magnetic memory 2c transmits the domain wall existence information and the magnetization information to the memory controller 3c (ST63).

[0146] The memory controller 3c, for example, the error correction circuit 16c, inverts the values ​​of a plurality of bits in the read data determined using the domain wall existence information and the magnetization information, thereby generating one or a plurality of candidates of the read data in which the error due to the domain wall misdetection is estimated to have been corrected (ST64). The details of the generation of the read data candidates in which the error due to the domain wall misdetection is estimated to have been corrected will be described later with reference to FIG.

[0147] The memory controller 3c uses the error correction circuit 16c to perform error correction on the read data candidate in which the error due to the domain wall misdetection is estimated to have been corrected (ST65). By correcting the error due to the domain wall misdetection, the error correction in step ST65 of the read data in which the error correction in step ST36 fails may be successful. If the error correction is successful (ST66_Yes), the process proceeds to step ST37. If the error correction fails (ST66_No), the process proceeds to step ST39.

[0148] Fig. 27 shows an example of data generated during operation in the memory system of the third embodiment. Specifically, Fig. 27 shows an example of data generated during correction of an error caused by a domain wall erroneous detection by the memory system of the third embodiment.

[0149] Consider an example in which data written to a memory cell MC to be read, and thus read data to be obtained, has "11000010" in order from the first read bit (most significant bit). Even though no domain wall exists between a memory cell MC storing the fourth most significant bit and a memory cell MC storing the fifth most significant bit, a domain wall is mistakenly detected. As a result, the obtained provisional read data has "11001101" in order from the most significant bit. The domain wall existence information has "0101011" from the seventh most significant bit to the first most significant bit, respectively. The magnetization information latch has "0001010" from the seventh most significant bit to the first most significant bit, respectively.

[0150] The magnetization solution generates read data of "00110010". The read data is different from the expected (or correct) read data, and all bits on the higher-order bit side of the erroneously detected domain wall are different from the bit values ​​of the correct read data. Based on this phenomenon, the error correction circuit 16c performs the following process to generate several candidates of read data that are estimated to be obtained if there is no domain wall erroneous detection.

[0151] When a magnetic domain wall exists, the magnetization states of the memory cells MC on both sides of the magnetic domain wall are different. Therefore, the magnetic domain information latch should have opposite values ​​for the memory cells MC on both sides of the magnetic domain wall. Based on this, for example, the error correction circuit 16c refers to the same bits of the magnetic domain wall existence information latch 32c as the bits having "1" data in the magnetic domain wall existence information latch 37. The values ​​of the sixth and fourth bits are inverted. However, the values ​​of the fourth and second bits are the same. Since the magnetization alternates between two states, it should not happen that the magnetization changes in the same direction in both the first and second magnetic domain walls adjacent to each other. Based on this, for example, the error correction circuit 16c estimates that a magnetic domain wall has been erroneously detected at the boundary on the upper bit side of each of the two bits that indicate the existence of a magnetic domain wall in the magnetic domain wall existence information latch 37 and hold the same value in the magnetic domain wall existence information latch 32c, and at all boundaries between these boundaries. 27, it is estimated that a domain wall has been erroneously detected at any of the boundaries between the 5th and 4th most significant bits of the provisional read data, the boundary between the 4th and 3rd most significant bits, and the boundary between the 3rd and 2nd most significant bits. Based on this estimation, multiple read data in which the values ​​of all bits from the most significant bit to the boundary are inverted are generated as candidates for each of all boundaries.

[0152] According to the third embodiment, the magnetic memory 2c generates provisional read data and magnetization information, and performs magnetization solving to generate read data, in the same manner as in the first embodiment, thereby obtaining the same advantages as in the first embodiment.

[0153] According to the third embodiment, the magnetic memory 2c accumulates the domain wall existence information and the magnetization information over the entire memory cell MC to be read. Then, when the memory controller 3c fails to correct the error of the read data received first in response to the read command, it receives the bit string of the domain wall existence information and the bit string of the magnetization information from the magnetic memory 2c, and attempts to correct the error of the read data received first based on the bit string. Therefore, the memory system 1c can achieve fewer read errors by having another error correction mechanism in addition to the error correction using the error correction code.

[0154] 4. Fourth embodiment The fourth embodiment differs from the third embodiment in terms of the components that perform the magnetization solution.

[0155] A memory controller 3d of a memory system 1d of the fourth embodiment has the same configuration as the memory controller 3b of the second embodiment, except that the memory controller 3d is configured to perform the operations described below.

[0156] A magnetic memory 2d of a memory system 1d of the fourth embodiment includes the same functional blocks as the magnetic memory 2c of the third embodiment. A magnetization solving circuit 33d of the magnetic memory 2d generates provisional read data based on domain wall existence information as in the first embodiment, and stores domain wall existence information in a domain wall existence information latch 37d and magnetization information in a magnetization information latch 32d as in the third embodiment. On the other hand, the magnetization solving circuit 33d does not perform magnetization solving.

[0157] Fig. 28 shows a flow of data read by the magnetic memory of the memory system of the fourth embodiment. The flow of Fig. 28 starts when the magnetic memory 2d receives a read command. The flow of Fig. 28 differs from the flow of Fig. 23 of the third embodiment in that the flow ends when acquisition of tentative read data for all memory cells MC to be read is completed (ST12_Yes).

[0158] Fig. 29 shows a flow of data reading by the memory system of the fourth embodiment. The flow of Fig. 29 starts when the host device 5 decides to read data from the memory system 1d.

[0159] As shown in Fig. 29, step ST32 is followed by step ST71. In step ST71, the magnetic memory 2d acquires the provisional read data, the bit string of the domain wall existence information, and the bit string of the magnetization information. The acquisition of the provisional read data, the bit string of the domain wall existence information, and the bit string of the magnetization information includes the execution of steps ST11, ST12, ST13, ST14, ST15, ST16, ST17, ST18, ST51, ST52, ST53, ST54, ST55, ST56, ST57, and ST58 of the flow shown in Fig. 28.

[0160] The magnetic memory 2d transmits the provisional read data, the bit string of the domain wall existence information in the domain wall existence information latch 37, and the bit string of the domain wall existence information in the magnetization information latch 32d to the memory controller 3d (ST72).

[0161] When the memory controller 3d receives the tentative read data, the bit string of the domain wall existence information, and the bit string of the magnetization information, it uses the magnetization solver 18d to perform magnetization solution (ST73). The magnetization solution includes the execution of steps ST59, ST22, and ST23 of the flow shown in FIG. 23 and FIG. 24 of the third embodiment. The read data is obtained by the magnetization solution. Step ST73 continues to step ST35. The subsequent operations including step ST35 are the same as those in the third embodiment (FIG. 26).

[0162] According to the fourth embodiment, the magnetic memory 2d generates the tentative read data and the magnetization information in the same manner as in the third embodiment, and the memory controller 3d performs magnetization resolution to generate the read data, thereby obtaining the same advantages as in the third embodiment.

[0163] Furthermore, according to the fourth embodiment, similarly to the third embodiment, domain wall existence information and magnetization information are stored throughout the entire memory cell MC to be read, and if an error correction of the read data received first in response to a read command fails, an attempt is made to correct the error of the read data received first based on the bit string of the domain wall existence information and the bit string of the magnetization information, thereby obtaining the same advantages as the third embodiment.

[0164] In step ST72, only the provisional read data and the magnetization information may be transmitted, and immediately before step ST64, the memory controller 3d may obtain the bit string of the domain wall existence information in the domain wall existence information latch 37 from the magnetic memory 2d by transmitting a command.

[0165] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0166] 100...Information processing systems, 1...Memory system, 5...host device, 2...Magnetic memory, 3...Memory controller, 11...host interface, 12…ROM, 13…RAM, 14…CPU, 15...Memory interface, 16...Error correction circuit, 21...Memory cell array, STR: String, MC: memory cell, SL…Source line, BL...bit line, EL: Field line, 22...input / output circuit, 23...Control circuit, 24...row selection circuit, 25...column selection circuit, 26...write circuit, 27...Readout circuit, 29...shift control circuit, 31...Data latch, 32...Magnetic information latch, 33...Magnetization solution circuit, UT...magnetic material, LS: Laminated body, 41...conductor, 42...Conductor, 43...Conductor, ML: unit part, 271...information retention circuit, 272...information retention circuit, 273...Sense amplifier, 18...Magnetization solution section, 37…Magnetic wall presence information latch

Claims

1. A magnetic body extending in a first direction and including a plurality of portions aligned in the first direction; a first circuit that outputs first information indicating the presence or absence of a domain wall between each two adjacent portions of the plurality of portions, and second information based on a combination of the each two magnetization states; a first storage circuit that stores a plurality of first bits respectively corresponding to the plurality of portions, a most significant bit of the plurality of first bits having a value independent of a magnetization state of a corresponding one of the plurality of portions, and each of the plurality of first bits having a value based on the first information; a second storage circuit for storing the second information in a second bit; a second circuit that outputs the first bits from the first storage circuit when a value of a least significant bit of the first bits matches a value of the second information stored in the second storage circuit, and outputs a plurality of third bits, each of which has a value opposite to that of the first bits, from the first storage circuit when a value of the least significant bit differs from a value of the second information stored in the second storage circuit; A magnetic memory comprising:

2. Each of the plurality of first bits has a value equal to a value of an adjacent bit of the plurality of first bits arranged on a side of the most significant bit when it is determined that a magnetization state between a corresponding one of the plurality of parts and an adjacent part arranged on a side of the corresponding one part in the first direction is the same, and has a value different from a value of the adjacent bit when it is determined that a magnetization state between the corresponding one part and the adjacent part is different.

2. The magnetic memory according to claim 1.

3. the first storage circuit moves a value of each of the plurality of first bits to an adjacent bit each time the first information is received, and stores a value based on the received first information in the least significant bit of the plurality of first bits; 3. The magnetic memory according to claim 2.

4. the second information has a first value when a first portion of the plurality of portions has a first magnetization state and the first portion has a second magnetization state before a domain wall in the plurality of portions moves in the first direction, and has a second value when the first portion has the second magnetization state and the first portion has the first magnetization state before the movement of the domain wall.

2. The magnetic memory according to claim 1.

5. the first magnetization state is a state of magnetization oriented in a second direction, the second magnetization state is a state of magnetization oriented in a third direction, The third direction is different from the second direction.

5. The magnetic memory according to claim 4.

6. each time a domain wall in the plurality of portions moves in the first direction, the first circuit sequentially outputs the first information and sequentially outputs the second information based on a magnetization state of a first portion of the plurality of portions and a magnetization state of the first portion before the movement of the domain wall.

2. The magnetic memory according to claim 1.

7. the second storage circuit updates the value of the second bit with the received second information each time the second information is received; 2. The magnetic memory according to claim 1.

8. the magnetic memory further comprising a third storage circuit configured to store a plurality of fourth bits; the third storage circuit moves a value of each of the plurality of fourth bits to an adjacent bit each time the third storage circuit receives the first information, and stores a value based on the received first information in the least significant bit of the plurality of fourth bits; the first information has a third value when it is determined that a domain wall exists; the second storage circuit stores a plurality of fifth bits; the second storage circuit moves a value of each of the plurality of fifth bits to an adjacent bit each time the second information is received, and stores a value based on the received second information in the least significant bit of the plurality of fifth bits; the second bit is a bit having the same order as a least significant bit having the third value among the plurality of fourth bits; 2. The magnetic memory according to claim 1.

9. A magnetic body extending in a first direction and including a plurality of portions aligned in the first direction; a first circuit that outputs first information indicating the presence or absence of a domain wall between each two adjacent portions of the plurality of portions, and second information based on a combination of the each two magnetization states; a first storage circuit that stores a plurality of first bits respectively corresponding to the plurality of portions, a most significant bit of the plurality of first bits having a value independent of a magnetization state of a corresponding one of the plurality of portions, and each of the plurality of first bits having a value based on the first information; a second storage circuit for storing the second information in a second bit; a second circuit that outputs the first bits from the first storage circuit when a value of a least significant bit of the first bits matches a value of the second information stored in the second storage circuit, and outputs a plurality of third bits, each of which has a value opposite to that of the first bits, from the first storage circuit when a value of the least significant bit differs from a value of the second information stored in the second storage circuit; A memory system comprising:

10. Each of the plurality of first bits has a value equal to a value of an adjacent bit of the plurality of first bits arranged on a side of the most significant bit when it is determined that a magnetization state between a corresponding one of the plurality of parts and an adjacent part arranged on a side of the corresponding one part in the first direction is the same, and has a value different from a value of the adjacent bit when it is determined that a magnetization state between the corresponding one part and the adjacent part is different.

10. The memory system of claim 9.

11. the first storage circuit moves a value of each of the plurality of first bits to an adjacent bit each time the first information is received, and stores a value based on the received first information in the least significant bit of the plurality of first bits; The memory system of claim 10.

12. the second information has a first value when a first portion of the plurality of portions has a first magnetization state and the first portion has a second magnetization state before a domain wall in the plurality of portions moves in the first direction, and has a second value when the first portion has the second magnetization state and the first portion has the first magnetization state before the movement of the domain wall.

10. The memory system of claim 9.

13. the first magnetization state is a state of magnetization oriented in a second direction, the second magnetization state is a state of magnetization oriented in a third direction, The third direction is different from the second direction.

13. The memory system of claim 12.

14. each time a domain wall in the plurality of portions moves in the first direction, the first circuit sequentially outputs the first information and sequentially outputs the second information based on a magnetization state of a first portion of the plurality of portions and a magnetization state of the first portion before the movement of the domain wall.

10. The memory system of claim 9.

15. the second storage circuit updates the value of the second bit with the received second information each time the second information is received; 10. The memory system of claim 9.

16. the memory system further comprising a third storage circuit configured to store a plurality of fourth bits; the third storage circuit moves a value of each of the plurality of fourth bits to an adjacent bit each time the third storage circuit receives the first information, and stores a value based on the received first information in the least significant bit of the plurality of fourth bits; the first information has a third value when it is determined that a domain wall exists; the second storage circuit stores a plurality of fifth bits; the second storage circuit moves a value of each of the plurality of fifth bits to an adjacent bit each time the second information is received, and stores a value based on the received second information in the least significant bit of the plurality of fifth bits; the second bit is a bit having the same order as a least significant bit having the third value among the plurality of fourth bits; 10. The memory system of claim 9.

17. The memory system includes a magnetic memory and a memory controller. the magnetic memory includes the magnetic body, the first circuit, the first storage circuit, and the second storage circuit; the memory controller comprises the second circuit; the memory controller receives read data including the plurality of first bits or the plurality of third bits, and when an error correction of the read data fails, causes the magnetic memory to output the plurality of fourth bits and the plurality of fifth bits; 17. The memory system of claim 16.

18. The memory system includes a magnetic memory and a memory controller. the magnetic memory includes the magnetic body, the first circuit, the first storage circuit, and the second storage circuit; The memory controller sends a first command to the magnetic memory; when the magnetic memory receives the first command, the magnetic memory outputs the first bits, the fourth bits, and the fifth bits.

17. The memory system of claim 16.

19. The memory system includes a magnetic memory and a memory controller. the magnetic memory includes the magnetic body, the first circuit, the first storage circuit, the second storage circuit, and the second circuit.

10. The memory system of claim 9.

20. The memory system includes a magnetic memory and a memory controller. the magnetic memory includes the magnetic body, the first circuit, the first storage circuit, and the second storage circuit; the memory controller comprises the second circuit; 10. The memory system of claim 9.

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