Array substrate, shift register unit and display device

Abstract

An array substrate, a shift register unit and a display device. The array substrate comprises a data line, a gate line, a first control signal line and a sub-pixel. The sub-pixel comprises a first sub-pixel part and a second sub-pixel part, the first sub-pixel part comprises a first pixel electrode, and the second sub-pixel part comprises a second pixel electrode; the first sub-pixel part comprises a first transistor connected with the first pixel electrode, and the second sub-pixel part comprises a second transistor and a third transistor connected with the second pixel electrode; the first transistor and the second transistor are connected with the same gate line and the same data line, and the third transistor is connected with the first control signal line; the array substrate further comprises a second control signal line, and the second sub-pixel part further comprises an adjustable capacitor connected with the third transistor; the second control signal line is connected with the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor, which is conducive to relieving color cast phenomenon under large viewing angle.

Description

Technical Field

[0001] This disclosure relates to an array substrate, a shift register unit, and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are currently the most widely used display products. An LCD consists of two stacked substrates and a liquid crystal layer located between them. With technological advancements, people have increasingly higher demands for the display functions and effects of LCD devices, such as high-low refresh rate compatibility, low-temperature startup capability, and wide viewing angles. Summary of the Invention

[0003] This disclosure provides an array substrate, a shift register unit, and a display device.

[0004] This disclosure provides an array substrate, comprising: a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; a plurality of data lines located on the substrate and arranged along the first direction; a plurality of gate lines located on the substrate and arranged along the second direction; and a plurality of first control signal lines located on the substrate and arranged along the second direction. Each sub-pixel in at least a portion of the sub-pixels includes a first sub-pixel portion and a second sub-pixel portion arranged along the second direction. The first sub-pixel portion includes a first pixel electrode, and the second sub-pixel portion includes a second pixel electrode. The first pixel electrode and the second pixel electrode are spaced apart, and the first sub-pixel portion and the second sub-pixel portion share a common electrode. The first sub-pixel portion includes a first transistor, and the first electrode of the first transistor is connected to the first pixel electrode. The second sub-pixel portion includes a second transistor and a third transistor, and the first electrodes of the second transistor and the third transistor are both connected to the second pixel electrode. The control electrodes of the first transistor and the second transistor are both connected to the same gate line. The second electrodes of the first transistor and the second transistor are both connected to the same data line. The control electrode of the third transistor is connected to the first control signal line. The array substrate further includes a second control signal line, and the second sub-pixel portion further includes an adjustable capacitor. The first terminal of the adjustable capacitor is connected to the second terminal of the third transistor. The second control signal line is connected to the second terminal of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor. A semiconductor layer and an insulating layer are disposed between the first terminal and the second terminal of the adjustable capacitor. The semiconductor layer, the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor are all disposed in the same layer. A first protrusion is disposed on the side of the second pixel electrode near the first pixel electrode, and a second protrusion is disposed on the side of the second terminal of the adjustable capacitor near the second pixel electrode. The first control signal line includes a bent portion located between the first protrusion and the second protrusion.

[0005] For example, according to an embodiment of this disclosure, the active layer of the first transistor, the active layer of the second transistor, the active layer of the third transistor, and the first and second electrodes of the adjustable capacitor are all located between the first pixel electrode and the second pixel electrode.

[0006] For example, according to an embodiment of this disclosure, the same gate line electrically connected to the control electrode of both the first transistor and the control electrode of the second transistor is located between the first pixel electrode and the second pixel electrode.

[0007] For example, according to an embodiment of this disclosure, the first control signal line is located between the first pixel electrode and the second pixel electrode.

[0008] For example, according to an embodiment of this disclosure, the second control signal line is located between the same gate line and the first control signal line.

[0009] For example, according to an embodiment of this disclosure, the plurality of gate lines are located between the plurality of data lines and the substrate, the second electrode of the adjustable capacitor and the control electrode of each transistor are disposed on the same layer as the plurality of gate lines, and the first electrode of the adjustable capacitor is disposed on the same layer as the plurality of data lines.

[0010] For example, according to an embodiment of this disclosure, a straight line extending along the second direction passes through the active layer of the second transistor and the semiconductor layer of the adjustable capacitor.

[0011] For example, according to an embodiment of this disclosure, a straight line extending along the first direction passes through the control electrode of the third transistor and the second electrode of the adjustable capacitor.

[0012] For example, according to an embodiment of this disclosure, the first electrode of the second transistor and the first electrode of the third transistor are integrally disposed, and the first electrode of the third transistor is disposed on the same layer as the plurality of data lines.

[0013] For example, according to an embodiment of this disclosure, the second electrode of the third transistor is integrally disposed with the first electrode of the adjustable capacitor, and the second electrode of the third transistor is located between at least a portion of the first electrode of the second transistor and the second pixel electrode.

[0014] For example, according to an embodiment of this disclosure, the plurality of sub-pixels are arranged as multi-row, multi-column sub-pixels, the multi-row sub-pixels are arranged along the second direction, the second pole of the adjustable capacitor in each row of sub-pixels is connected to the same second control signal line, and the plurality of second control signal lines connected to the adjustable capacitors of the multi-row sub-pixels are arranged along the second direction.

[0015] For example, according to an embodiment of this disclosure, the array substrate further includes: at least one third control signal line and at least one pin electrically connected to the at least one third control signal line. The at least one third control signal line extends in the same direction as the data line, and the plurality of second control signal lines are connected to the at least one third control signal line.

[0016] For example, according to an embodiment of this disclosure, the array substrate further includes a plurality of pins. Each second control signal line is connected to a pin such that each second control signal line is configured to input a separate control signal.

[0017] This disclosure provides an array substrate, comprising: a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; a plurality of data lines located on the substrate and arranged along the first direction; and a plurality of gate lines located on the substrate and arranged along the second direction. Each sub-pixel includes a transistor and a pixel electrode and a common electrode stacked thereon. The first electrode of the transistor is connected to the data line, the second electrode of the transistor is connected to the pixel electrode, and the control electrode of the transistor is connected to the gate line. The array substrate further includes at least one control signal line. At least some sub-pixels also include an adjustable capacitor. The adjustable capacitor includes a first electrode, a semiconductor layer, and a second electrode stacked sequentially along a direction perpendicular to the substrate. The semiconductor layer is co-layered with and spaced apart from the active layer of the transistor. The first electrode of the adjustable capacitor is connected to the pixel electrode. The control signal line is connected to the second electrode of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor. The straight line extending along the first direction passes through the active layer and the semiconductor layer.

[0018] For example, according to an embodiment of this disclosure, at least one gate line is multiplexed as the control signal line.

[0019] For example, according to an embodiment of this disclosure, the gate line is spaced apart from the control signal line, and the second electrode of the adjustable capacitor is located entirely between the control signal line and the pixel electrode connected to the first electrode of the adjustable capacitor.

[0020] For example, according to an embodiment of this disclosure, the control electrode of the transistor is disposed on the same layer as the gate line, and the control electrode includes two parts located on both sides of the gate line. The portion of the two parts closer to the adjustable capacitor has a first dimension in the second direction, and the portion of the two parts farther from the adjustable capacitor has a second dimension in the second direction. The first dimension is larger than the second dimension.

[0021] For example, according to an embodiment of this disclosure, the second electrode of the transistor is spaced apart from the first electrode of the adjustable capacitor.

[0022] For example, according to an embodiment of this disclosure, the control signal line is disposed on the same layer as the gate line; the plurality of sub-pixels are arranged as multi-row and multi-column sub-pixels, the multi-row sub-pixels are arranged along the second direction, the second pole of the adjustable capacitor in each row of sub-pixels is connected to the same control signal line, and the plurality of control signal lines connected to the adjustable capacitors of the multi-row sub-pixels are arranged along the second direction.

[0023] For example, according to an embodiment of this disclosure, the array substrate further includes: at least one control signal connection line and at least one pin electrically connected to the at least one control signal connection line. The at least one control signal connection line extends in the same direction as the data line, and the plurality of control signal lines are connected to the at least one control signal connection line.

[0024] For example, according to an embodiment of this disclosure, the array substrate further includes a plurality of pins, wherein each control signal line is connected to a pin such that each control signal line is configured to input a separate control signal.

[0025] For example, according to an embodiment of this disclosure, the array substrate further includes: a multi-row shift register unit located on the substrate. The shift register unit includes an input circuit, an output circuit, and a node noise reduction circuit; the input circuit is connected to a first node and configured to provide an input signal to the first node; the node noise reduction circuit is connected to both the first node and a second node and configured to perform noise reduction on the first node under the control of the level of the second node; the output circuit is connected to the first node and an output terminal and configured to output an output signal at the output terminal under the control of the level of the first node. Each control signal line is connected to the second node of the shift register unit located in the same row.

[0026] This disclosure provides a shift register unit, including an input circuit, an output circuit, and a reset circuit. The input circuit is connected to a first node and configured to provide an input signal to the first node. The reset circuit is connected to the first node and a reset terminal and configured to reset the first node in response to a reset signal provided by the reset terminal. The output circuit is connected to the first node and an output terminal and configured to output an output signal at the output terminal under the control of the voltage level of the first node. The output circuit includes an adjustable capacitor, with a first terminal connected to the output terminal, and the first node connected to a second terminal of the adjustable capacitor to change the capacitance value of the adjustable capacitor when the voltage of the first node changes. The output circuit also includes a transistor electrically connected to the adjustable capacitor, with the control terminal of the transistor connected to the first node, and a first terminal of the transistor connected to the second terminal of the adjustable capacitor. A semiconductor layer and an insulating layer are disposed between the first and second terminals of the adjustable capacitor, and the active layer of the transistor is disposed on the same layer as the semiconductor layer of the adjustable capacitor.

[0027] For example, according to an embodiment of this disclosure, the input circuit includes a first transistor, the first terminal of which is connected to a first power supply terminal, the second terminal of which is connected to the first node, and the gate of which is connected to a first signal control terminal; the reset circuit includes a second transistor, the first terminal of which is connected to the first node, the second terminal of which is connected to the second power supply terminal, and the gate of which is connected to a second signal control terminal; the output circuit further includes a third transistor, the first terminal of which is connected to a clock signal terminal, the second terminal of which is connected to the first terminal of the adjustable capacitor, and the gate of which is connected to the first node; the shift register unit further includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, wherein the first terminal of the fourth transistor is connected to the first node, the second terminal of the fourth transistor is connected to a third voltage terminal, and the gate of the fourth transistor is connected to a frame reset signal terminal; the first terminal of the fifth transistor is connected to the fourth voltage terminal, and the second terminal of the fifth transistor is connected to a second signal control terminal. The second node is connected; the first terminal of the sixth transistor is connected to the second node, the second terminal of the sixth transistor is connected to the third voltage terminal, and the gate of the sixth transistor is connected to the first node; the first terminal of the seventh transistor is connected to the first node, the second terminal of the seventh transistor is connected to the third voltage terminal, and the gate of the seventh transistor is connected to the frame reset signal terminal; the first terminal of the eighth transistor is connected to the gate of the fifth transistor, the second terminal of the eighth transistor is connected to the third voltage terminal, and the gate of the eighth transistor is connected to the first node; the first terminal of the ninth transistor is connected to the fourth voltage terminal, the second terminal of the ninth transistor is connected to the first terminal of the eighth transistor, and the gate of the ninth transistor is connected to the fourth voltage terminal; the first terminal of the tenth transistor is connected to the first node, the second terminal of the tenth transistor is connected to the third signal terminal, and the gate of the tenth transistor is connected to the second node; the first terminal of the eleventh transistor is connected to the second terminal of the third transistor, the second terminal of the eleventh transistor is connected to the third voltage terminal, and the gate of the eleventh transistor is connected to the first node.

[0028] This disclosure provides a display device including any of the array substrates or shift register units described above. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0030] Figure 1 This is a partial planar structure schematic diagram of an array substrate provided according to an embodiment of the present disclosure.

[0031] Figure 2 for Figure 1 A schematic diagram showing the partial structure of a sub-pixel in the array substrate and the connection relationship between the sub-pixel and the signal line.

[0032] Figure 3 for Figure 2 The diagram shows the circuit structure of the sub-pixel.

[0033] Figure 4 For along Figure 2 The diagram shows a cross-sectional view of the adjustable capacitor cut by AA'.

[0034] Figure 5 and Figure 6 This is a schematic diagram of a partial planar structure of an array substrate provided according to different examples of embodiments of the present disclosure.

[0035] Figure 7 This is a partial planar structure schematic diagram of an array substrate provided according to another embodiment of the present disclosure.

[0036] Figure 8 for Figure 7 The diagram shows a partial structure of two adjacent sub-pixels in the array substrate and the connection relationship between the sub-pixels and the signal lines.

[0037] Figure 9 for Figure 8 The diagram shows the circuit structure of the sub-pixel.

[0038] Figure 10 For along Figure 8 The diagram shows the cross-sectional structure of the adjustable capacitor intercepted by line BB'.

[0039] Figure 11 This is a partial planar structure schematic diagram of an array substrate provided according to another example of an embodiment of the present disclosure.

[0040] Figures 12 to 14 This is a schematic diagram of a partial planar structure of an array substrate provided according to different examples of embodiments of the present disclosure.

[0041] Figure 15 for Figure 14 A circuit diagram of a shift register unit in the array substrate shown.

[0042] Figure 16 This is a schematic diagram of a shift register unit provided according to another embodiment of the present disclosure.

[0043] Figure 17 for Figure 16 The circuit diagram shows a specific implementation example of the shift register unit.

[0044] Figure 18 for Figure 17 The circuit layout shown.

[0045] Figure 19 for Figure 17 The timing diagram of the shift register unit shown is shown. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Features such as “parallel,” “perpendicular,” and “identical” used in embodiments of this disclosure include features in the strict sense of “parallel,” “perpendicular,” and “identical,” as well as cases where “substantially parallel,” “substantially perpendicular,” and “substantially identical” include a certain degree of error, taking into account measurement and errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), indicating a range of acceptable deviations for a particular value as determined by one of ordinary skill in the art. For example, “substantially” can mean within one or more standard deviations, or within 10% or 5% of said value. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component means that the component may be one or more, or can be understood as at least one. “At least one” means one or more, and “more” means at least two. The term "same-layer arrangement" as used in this disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, wherein their materials may be the same or different. The term "integrated arrangement structure" as used in this disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, wherein their materials may be the same or different.

[0048] In their research, the inventors of this application discovered that the display effect of a display device is limited by the capacitance in the panel. For example, a fixed pixel storage capacitor makes it difficult for the display panel to be compatible with high and low refresh rates. Or, if the capacitance in the shift register unit of the display device is too small, it will cause the voltage of the pull-up node, such as the PU point, to be unable to be maintained, resulting in poor display. If the capacitance in the shift register unit is too large, it will cause the pull-up node to be difficult to charge and discharge, and poor low-temperature start-up capability.

[0049] This disclosure provides an array substrate, including a substrate and multiple data lines, multiple gate lines, and multiple first control signal lines located on the substrate. Multiple sub-pixels are arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; multiple data lines are arranged along the first direction; multiple gate lines are arranged along the second direction; and multiple first control signal lines are arranged along the second direction. Each sub-pixel, at least a portion thereof, includes a first sub-pixel portion and a second sub-pixel portion arranged along the second direction. The first sub-pixel portion includes a first pixel electrode, and the second sub-pixel portion includes a second pixel electrode. The first pixel electrode and the second pixel electrode are spaced apart, and the first sub-pixel portion and the second sub-pixel portion share a common electrode. The first sub-pixel portion includes a first transistor, the first electrode of which is connected to the first pixel electrode. The second sub-pixel portion includes a second transistor and a third transistor, the first electrodes of the second transistor and the first electrodes of the third transistor are both connected to the second pixel electrode. The control electrodes of the first transistor and the second transistor are both connected to the same gate line, the second electrodes of the first transistor and the second transistor are both connected to the same data line, and the control electrode of the third transistor is connected to the first control signal line. The array substrate further includes a second control signal line, and the second sub-pixel portion further includes an adjustable capacitor. The first terminal of the adjustable capacitor is connected to the second terminal of the third transistor, and the second control signal line is connected to the second terminal of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor. A semiconductor layer and an insulating layer are disposed between the first terminal and the second terminal of the adjustable capacitor. The semiconductor layer, the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor are all disposed in the same layer. A first protrusion is disposed on the side of the second pixel electrode near the first pixel electrode, and a second protrusion is disposed on the side of the second terminal of the adjustable capacitor near the second pixel electrode. The first control signal line includes a bent portion located between the first protrusion and the second protrusion. The array substrate provided in this disclosure, by providing an adjustable capacitor in the second sub-pixel portion and providing protrusions in both the adjustable capacitor and the second pixel electrode, and by including a bent portion between the two protrusions in the first control signal line, helps to alleviate color shift at large viewing angles while maximizing the storage capacitance of the first sub-pixel portion and the adjustable capacitance value range of the adjustable capacitor, and avoids interference from the first control signal line to the storage capacitor and the adjustable capacitor.

[0050] This disclosure also provides an array substrate, including a substrate and multiple gate lines and multiple data lines located on the substrate. Multiple sub-pixels are arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; multiple data lines are arranged along the first direction; multiple gate lines are arranged along the second direction. Each sub-pixel includes a transistor and a pixel electrode and a common electrode stacked together. The first electrode of the transistor is connected to the data line, the second electrode of the transistor is connected to the pixel electrode, and the control electrode of the transistor is connected to the gate line. The array substrate also includes at least one control signal line. At least some sub-pixels also include an adjustable capacitor. The adjustable capacitor includes a first electrode, a semiconductor layer, and a second electrode stacked sequentially along a direction perpendicular to the substrate. The semiconductor layer and the active layer of the transistor are co-layered and spaced apart. The first electrode of the adjustable capacitor is connected to the pixel electrode. The control signal line is connected to the second electrode of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor, and the straight line extending along the first direction passes through the active layer and the semiconductor layer. The array substrate provided in this disclosure achieves compatibility with high and low refresh rates by setting adjustable capacitors in sub-pixels and setting the positional relationship between the active layer of the transistor and the semiconductor layer of the adjustable capacitors, while maximizing the aperture ratio of the sub-pixels by setting the position of the adjustable capacitors.

[0051] This disclosure also provides a shift register unit, including an input circuit, an output circuit, and a reset circuit. The input circuit is connected to a first node and configured to provide an input signal to the first node; the reset circuit is connected to the first node and a reset terminal and configured to reset the first node in response to a reset signal provided by the reset terminal; the output circuit is connected to the first node and an output terminal and configured to output an output signal at the output terminal under the control of the level of the first node. The output circuit includes an adjustable capacitor, the first node is connected to the second terminal of the adjustable capacitor to change the capacitance value of the adjustable capacitor when the voltage of the first node changes; the output circuit includes a transistor electrically connected to the adjustable capacitor, the control terminal of the transistor is connected to the first node, one terminal of the transistor is connected to the second terminal of the adjustable capacitor, a semiconductor layer and an insulating layer are disposed between the first terminal and the second terminal of the adjustable capacitor, and the active layer of the transistor is disposed on the same layer as the semiconductor layer of the adjustable capacitor. The shift register unit provided in this disclosure uses an adjustable capacitor, whose capacitance value increases as the voltage of the first node increases. For example, to rapidly increase the voltage of the first node to improve low-temperature start-up capability, the capacitance value of the adjustable capacitor increases after the voltage of the first node rises. When this shift register unit is applied to a touch display device, the voltage at the first node can be better maintained during the touch phase. When the first node discharges, the capacitance value of the adjustable capacitor decreases accordingly, allowing the first node to discharge quickly.

[0052] The array substrate, shift register unit, and display device provided in this disclosure are described below with reference to the accompanying drawings.

[0053] Figure 1 This is a partial planar structure schematic diagram of an array substrate provided according to an embodiment of the present disclosure. Figure 2 for Figure 1 A schematic diagram showing the partial structure of a sub-pixel in the array substrate and the connection relationship between the sub-pixel and the signal line. Figure 3 for Figure 2 The diagram shows the circuit structure of the sub-pixel. Figure 4 For along Figure 2 The diagram shows a cross-sectional view of the adjustable capacitor cut by AA'.

[0054] like Figures 1 to 3 As shown, the array substrate includes a substrate 10 and a plurality of sub-pixels 100, a plurality of data lines 210, a plurality of gate lines 220, and a plurality of first control signal lines 310 located on the substrate 10. The plurality of sub-pixels 100 are arranged in an array along a first direction and a second direction, the first direction intersecting the second direction. For example, Figure 1 The diagram schematically shows the first direction as the X direction and the second direction as the Y direction, but is not limited to this; the first and second directions can be interchanged. For example, the first and second directions can be perpendicular. However, it is not limited to this; the angle between the first and second directions can be 80 to 100 degrees, such as 85 to 95 degrees. For example, the area where multiple sub-pixels 100 are located is a display area for displaying images, and the array substrate may also include a peripheral area surrounding the display area.

[0055] like Figures 1 to 3 As shown, multiple data lines 210 are arranged along a first direction, multiple gate lines 220 are arranged along a second direction, and multiple first control signal lines 310 are arranged along the second direction. For example, the multiple data lines 210 and the multiple gate lines 220 are arranged intersectingly. For example, the gate lines 220 are located between the data lines 210 and the substrate 10.

[0056] like Figures 1 to 3 As shown, at least some of the sub-pixels 100 include a first sub-pixel portion 110 and a second sub-pixel portion 120 arranged along a second direction. The first sub-pixel portion 110 includes a first pixel electrode 111, and the second sub-pixel portion 120 includes a second pixel electrode 121. The first pixel electrode 111 and the second pixel electrode 121 are spaced apart, and the first sub-pixel portion 110 and the second sub-pixel portion 120 share a common electrode 113. For example, each sub-pixel 100 is a display unit, and the first sub-pixel portion 110 and the second sub-pixel portion 120 are two parts of the display unit. These two parts are adjacent to each other and are used to display the same color sub-pixel 100.

[0057] like Figures 2 to 3As shown, the first sub-pixel section 110 includes a first transistor 114, the first electrode 1141 of the first transistor 114 is connected to the first pixel electrode 111, the second sub-pixel section 120 includes a second transistor 123 and a third transistor 124, the first electrode 1231 of the second transistor 123 and the first electrode 1241 of the third transistor 124 are both connected to the second pixel electrode 121, the control electrode 1143 of the first transistor 114 and the control electrode 1233 of the second transistor 123 are both connected to the same gate line 220, the second electrode 1142 of the first transistor 114 and the second electrode 1232 of the second transistor 123 are both connected to the same data line 210, and the control electrode 1243 of the third transistor 124 is connected to the first control signal line 310.

[0058] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure all use thin-film transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal, and the other as the second terminal.

[0059] like Figures 2 to 3 As shown, the array substrate also includes a second control signal line 320, and the second sub-pixel portion 120 also includes an adjustable capacitor 125. The first terminal 1251 of the adjustable capacitor is connected to the second terminal 1242 of the third transistor 124. The second control signal line 320 is connected to the second terminal 1252 of the adjustable capacitor 125 to apply a voltage to change the capacitance value of the adjustable capacitor 125.

[0060] The array substrate provided in this disclosure helps to alleviate large viewing angle distortion when the array substrate is used for display by providing an adjustable capacitor in the second sub-pixel section.

[0061] For example, Figures 1 to 3 The array substrate shown can be applied to liquid crystal display devices employing multi-domain vertical alignment (VA) mode. For example, the multi-domain mode can be an 8-domain mode.

[0062] For example, such as Figures 2 to 3As shown, the first sub-pixel portion 110 can be a bright sub-pixel portion, and the second sub-pixel portion 120 can be a dark sub-pixel portion. By adjusting the voltage on the pixel electrodes of the two pixel portions of the same sub-pixel, the deflection angle of the liquid crystal can be adjusted to achieve brightness adjustment, thereby achieving color shift correction at large viewing angles. For example, the first pixel electrode 111 and the second pixel electrode 121 are both plate-shaped structures, and the common electrode 113 can include a strip-shaped structure. For example, a row of sub-pixels 100 is arranged between two adjacent data lines 210.

[0063] In some examples, such as Figures 1 to 3 As shown, the same gate line 220, which is electrically connected to the control electrode of the first transistor 114 and the control electrode of the second transistor 123, is located between the first pixel electrode 111 and the second pixel electrode 121. By placing the gate line between the first pixel electrode and the second pixel electrode, it is convenient to electrically connect the control electrodes of the first transistor and the second transistor to the gate line, while also saving space to improve the aperture ratio of the sub-pixel.

[0064] For example, such as Figures 2 to 3 As shown, the first pixel electrode 111 and the common electrode 113 form the storage capacitor 115 of the first sub-pixel portion 110, and the second pixel electrode 121 and the common electrode 113 form the storage capacitor 126 of the second sub-pixel portion 210.

[0065] For example, such as Figures 2 to 3 As shown, when the voltage of gate line 220 is high, the first transistor 114 and the second transistor 123 are turned on. Data line 210 simultaneously charges the storage capacitor 115 of the first sub-pixel section 110 and the storage capacitor 126 of the second sub-pixel section 120. At this time, the voltages of the storage capacitors of the first sub-pixel section 110 and the second sub-pixel section 120 are the same, and the brightness of the first sub-pixel section 110 and the second sub-pixel section 120 is the same. After the storage capacitors of the first sub-pixel section 110 and the second sub-pixel section 120 are fully charged, the voltage of gate line 220 is low, and the first transistor 114 and the second transistor 123 are turned off. Then, the voltage of the first control signal line 310 is high, the third transistor 124 is turned on, and the charge in the storage capacitor 126 of the second sub-pixel section 120 charges the adjustable capacitor 125 through the third transistor 124. The voltage of the second electrode (control electrode) of the adjustable capacitor 125 is adjusted via the second control signal line 320. This adjusts the capacitance value of the adjustable capacitor 125, thereby changing the voltage on the second pixel electrode 121 in the second sub-pixel section 120, thus adjusting the deflection angle of the liquid crystal until the large viewing angle color shift problem is resolved. Finally, the voltage of the second control signal line is lowered, and the third transistor 124 is turned off, completing the adjustment.

[0066] For example, such as Figure 4As shown, the adjustable capacitor 125 includes a first metal layer 01, an insulating layer 02, a semiconductor layer 03, and a second metal layer 04. The first metal layer 01 is located between the second metal layer 02 and the substrate. When the first metal layer 01 and the second metal layer 04 are energized, the actual capacitance value of the adjustable capacitor 125 changes with the voltage of the first metal layer 01. For example, when the adjustable capacitor 125 is an N-type capacitor, the capacitance value of the adjustable capacitor 125 increases as the input voltage to the first metal layer 01 increases; when the adjustable capacitor 125 is a P-type capacitor, the capacitance value of the adjustable capacitor 125 decreases as the voltage of the first metal layer 01 increases.

[0067] In some examples, such as Figure 2 and Figure 3 As shown, the active layer 1140 of the first transistor 114, the active layer 1230 of the second transistor 123, the active layer 1240 of the third transistor 124, and the first electrode 1251 and the second electrode 1252 of the adjustable capacitor 125 are all located between the first pixel electrode 111 and the second pixel electrode 121. By placing the active layers of each transistor and the adjustable capacitor between the first pixel electrode and the second pixel electrode, space can be saved and the aperture ratio of the sub-pixel can be improved.

[0068] For example, such as Figure 2 As shown, the active layer 1140 of the first transistor 114 and the active layer 1230 of the second transistor 123 are arranged along a first direction. For example, the active layer 1140 of the first transistor 114 and the active layer 1230 of the second transistor 123 can be an integrated structure to further save space between the two sub-pixel portions.

[0069] like Figure 2 and Figure 3 As shown, the second pixel electrode 121 has a first protrusion 121-1 on the side near the first pixel electrode 111, and the second electrode 1252 of the adjustable capacitor 125 has a second protrusion 125-1 on the side near the second pixel electrode 121. The first control signal line 310 includes a bent portion 311 located between the first protrusion 121-1 and the second protrusion 125-1. Therefore, in this display substrate, while maximizing the increase in the storage capacitance of the first sub-pixel portion and the adjustable capacitance value range of the adjustable capacitor, interference from the first control signal line to the storage capacitor and the adjustable capacitor is avoided.

[0070] For example, such as Figure 2As shown, the second protrusion 125-1 includes a second inclined side, and the first protrusion 121-1 includes a first inclined side. The first inclined side and the second inclined side are substantially parallel, and the two side edges of the bent portion 311 of the first control signal line 310 located between the two protrusions are substantially parallel to the first inclined side and the second inclined side, respectively. For example, the extending directions of both the first inclined side and the second inclined side intersect with the first direction and with the second direction.

[0071] For example, such as Figure 2 As shown, a straight line extending along the X direction passes through the second protrusion 125-1 and the gate of the third transistor.

[0072] like Figure 2 As shown, the second protrusion 125-1 of the second electrode 1252 of the adjustable capacitor 125 refers to the portion of it that protrudes toward the second pixel electrode 121 relative to the second control signal line 320.

[0073] For example, such as Figure 2 As shown, the distance D1 between the active layers (such as active layer 1140 and active layer 1230) of the first transistor 114 and the second transistor 123 and the first pixel electrode 111 is smaller than the distance D2 between the active layer and the second pixel electrode 121. Furthermore, the edge of the first pixel electrode 111 near the active layer includes a protrusion 111-1, which does not overlap with the orthographic projection of the active layer onto a plane extending in the first direction and perpendicular to the XY plane. By providing a protrusion in the first pixel electrode that protrudes towards the second pixel electrode, and ensuring that the protrusion does not overlap with the orthographic projection of the active layer onto a plane extending in the first direction and perpendicular to the XY plane, it is beneficial to maximize the storage capacitance of the first sub-pixel while preventing interference between the first pixel electrode and the active layers of the first and second transistors.

[0074] For example, the ratio of distance D1 to distance D2 can be 0.5 to 5. For example, the ratio of distance D1 to distance D2 can be 1 to 4. For example, the ratio of distance D1 to distance D2 can be 2 to 3.5. For example, the ratio of distance D1 to distance D2 can be 2 to 3.

[0075] For example, such as Figure 2 As shown, the control electrode of the first transistor 114 and the control electrode of the second transistor are integrated into a single structure to save space. For example, the second electrode of the first transistor 114 and the second electrode of the second transistor 123 are integrated into a single structure to save space.

[0076] In some examples, such as Figures 1 to 4 As shown, multiple gate lines 220 are located between multiple data lines 210 and the substrate 10, and the second electrode 1252 of the adjustable capacitor 125 (as shown) Figure 4 The first metal layer 01 shown) and the control electrode of each transistor are all arranged on the same layer as multiple gate lines 220. The first electrode 1251 of the adjustable capacitor 125 (as shown) Figure 4 The second metal layer 04 shown is disposed on the same layer as multiple data lines 210, and a semiconductor layer 03 and an insulating layer 02 are disposed between the first electrode 1251 and the second electrode 1252 of the adjustable capacitor 125. The semiconductor layer 03 is disposed on the same layer as the active layers of each transistor (such as active layer 1140 and active layer 1230) and spaced apart.

[0077] For example, such as Figure 2 As shown, the control electrode of the first transistor 114, the control electrode of the second transistor 123, and the gate line 220 can be integrated into a single structure.

[0078] In some examples, such as Figure 2 As shown, the first control signal line 310 is located between the first pixel electrode 111 and the second pixel electrode 121. In some examples, such as Figure 2 As shown, the second control signal line 320 is located between the same gate line 220 and the first control signal line 310. By setting the positions of the gate line, the first control signal line, and the second control signal line, it is beneficial to save layout space and improve layout utilization.

[0079] For example, such as Figure 2 As shown, among the gate line 220, the first control signal line 310, and the second control signal line 320 located between the first pixel electrode 111 and the second pixel electrode 121, the distance between the gate line 220 (such as a position other than the control electrode of the first transistor 114 and the second transistor 123) and the second control signal line 320 (such as a position other than the second electrode 1252 of the adjustable capacitor) is greater than the distance between the second control signal line 320 and the first control signal line 310 (such as a position other than the control electrode of the third transistor 124).

[0080] For example, such as Figure 2 As shown, the extension directions of the gate line 220, the first control signal line 310, and the second control signal line 320 are generally along the first direction. For example, the edge of the second control signal line 320 facing the gate line 220 can be a straight edge extending along the first direction.

[0081] In some examples, such as Figure 2 and Figure 4 As shown, a straight line extending along the second direction passes through the active layer 1230 of the second transistor 123 and the semiconductor layer 03 of the adjustable capacitor 125. For example, the orthographic projections of the active layer 1230 of the second transistor 123 and the semiconductor layer 03 of the adjustable capacitor 125 on a plane extending along the first direction and perpendicular to the XY plane overlap.

[0082] In some examples, such as Figure 2 As shown, a straight line extending along the first direction passes through the control electrode of the third transistor 124 and the second electrode of the adjustable capacitor 125. For example, the orthographic projections of the control electrode of the third transistor 124 and the second electrode of the adjustable capacitor 125 on a plane extending along the second direction and perpendicular to the XY plane overlap.

[0083] The array substrate provided in this disclosure, by setting the positional relationship of the second transistor, the adjustable capacitor and the third transistor in the first direction and the second direction, helps to prevent interference between the active layer of each transistor and the semiconductor layer of the adjustable capacitor, while maximizing the area of ​​the active layer of each transistor and the semiconductor layer of the adjustable capacitor, preventing the film layer from overlapping with the common electrode, reducing interference between the film layers, improving the layout utilization, and maximizing the aperture ratio of the sub-pixels.

[0084] For example, such as Figure 2 As shown, the second pole of the adjustable capacitor 125 includes a protrusion that protrudes toward the first control signal line 310, and the first control signal line 310 is bent at the position corresponding to the protrusion.

[0085] In some examples, such as Figure 2 As shown, the first electrode of the second transistor 123 and the first electrode of the third transistor 124 are integrated into a structure, and the first electrode of the third transistor 124 is arranged on the same layer as multiple data lines 210.

[0086] In some examples, such as Figure 2 As shown, the second electrode of the third transistor 124 and the first electrode of the adjustable capacitor 125 are integrally formed, and the second electrode of the third transistor 124 is located between at least a portion of the first electrode of the second transistor 123 and the second pixel electrode 121.

[0087] When the second transistor, the third transistor, and the adjustable capacitor are all located between the first pixel electrode and the second pixel electrode and are set to be close together, by setting the first electrode of the second transistor and the first electrode of the third transistor as an integrated structure, and setting the second electrode of the third transistor and the first electrode of the adjustable capacitor as an integrated structure, it is beneficial to save layout space and improve the aperture ratio of the sub-pixel.

[0088] In some examples, such as Figure 1 and Figure 2As shown, multiple sub-pixels 100 are arranged in multiple rows and columns, with the multiple rows of sub-pixels 100 arranged along a second direction. For example, the first direction can be a row direction, and the second direction can be a column direction. The second terminal of the adjustable capacitor 125 in each row of sub-pixels 100 is connected to the same second control signal line 320, and the multiple second control signal lines 320 connected to the adjustable capacitors 125 of the multiple rows of sub-pixels 100 are arranged along the second direction.

[0089] Figure 5 and Figure 6 This is a schematic diagram of a partial planar structure of an array substrate provided according to different examples of embodiments of the present disclosure.

[0090] For example, such as Figure 6 As shown, the array substrate also includes at least one third control signal line 330 and at least one pin 331 electrically connected to the at least one third control signal line 330. The extension direction of the at least one third control signal line 330 is the same as the extension direction of the data line 210. Multiple second control signal lines 320 are connected to the at least one third control signal line 330. Figure 6 A third control signal line 330 is schematically shown, to which all second control signal lines 320 are electrically connected to transmit control signals. Of course, the number of third control signal lines is not limited to one; for example, there can be two, three, or more third control signal lines to divide multiple rows of subpixels into multiple groups, with different third control signal lines configured to transmit control signals to adjustable capacitors of different groups.

[0091] For example, such as Figure 5 As shown, the third control signal line 330 and the data line 210 can be arranged on the same layer. Of course, the embodiments disclosed herein are not limited to this; for example, the third control signal line can be located on the side of the data line away from the substrate.

[0092] For example, such as Figure 5 As shown, multiple data lines 210 are electrically connected to the circuit board via multiple pins 211. The circuit board may include a chip-on-film (COF) substrate, and the COF may include a source IC. For example, a third control signal line 330 may be electrically connected to the source IC via pin 331. For instance, if no third control signal line is provided in the array substrate, the aforementioned pin 331 may be a dummy pin, i.e., a pin that is not input with electrical signals. After the third control signal line is provided, this pin is electrically connected to the third control signal line and receives the corresponding control signal.

[0093] In some examples, such as Figure 6As shown, the array substrate also includes multiple pins 321, with each second control signal line 320 connected to one pin 321 such that each second control signal line 320 is configured to input a separate control signal. For example, the second control signal line 320 is electrically connected to a gate control chip (Gate IC) via pin 321, and the gate line 220 is electrically connected to the Gate IC via pin 321. The Gate IC is configured to transmit signals to the gate line and the second control signal line 320.

[0094] For example, such as Figure 6 As shown, the first control signal line 310 is connected to pin 321 for electrical connection with the Gate IC.

[0095] Figure 7 This is a partial planar structure schematic diagram of an array substrate provided according to another embodiment of the present disclosure. Figure 8 for Figure 7 The diagram shows a partial structure of two adjacent sub-pixels in the array substrate and the connection relationship between the sub-pixels and the signal lines. Figure 9 for Figure 8 The diagram shows the circuit structure of the sub-pixel. Figure 10 For along Figure 8 The diagram shows the cross-sectional structure of the adjustable capacitor intercepted by line BB'.

[0096] like Figure 7 As shown, the array substrate includes a substrate 10 and a plurality of sub-pixels 100, a plurality of data lines 210, and a plurality of gate lines 220 located on the substrate 10. The plurality of sub-pixels 100 are arranged in an array along a first direction and a second direction, the first direction intersecting the second direction. For example, Figure 7 The diagram schematically shows the first direction as the X direction and the second direction as the Y direction, but is not limited to this; the first and second directions can be interchanged. For example, the first and second directions can be perpendicular. However, it is not limited to this; the angle between the first and second directions can be 80 to 100 degrees, such as 85 to 95 degrees. For example, the area where multiple sub-pixels 100 are located is a display area for displaying images, and the array substrate may also include a peripheral area surrounding the display area.

[0097] like Figure 7 As shown, multiple data lines 210 are arranged along a first direction, and multiple gate lines 220 are arranged along a second direction. For example, the multiple data lines 210 and the multiple gate lines 220 are intersected to define the area where each sub-pixel 100 is located. For example, the gate lines 220 are located between the data lines 210 and the substrate 10.

[0098] like Figures 8 to 9As shown, each sub-pixel 100 includes a transistor 101 and a pixel electrode 102 and a common electrode 103 stacked together. The first electrode 1011 of the transistor 101 is connected to the data line 210, the second electrode 1012 of the transistor 101 is connected to the pixel electrode 102, and the control electrode 1013 of the transistor 101 is connected to the gate line 220. For example, the pixel electrode 102 can be a plate-like structure, and the common electrode 103 can be a strip-like structure.

[0099] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure all use thin-film transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal, and the other as the second terminal.

[0100] like Figures 7 to 10 As shown, the array substrate also includes at least one control signal line 410, and at least some sub-pixels 100 also include adjustable capacitors 104. The adjustable capacitor 104 includes a first electrode 1041, a semiconductor layer 03, and a second electrode 1042 sequentially stacked along a direction perpendicular to the substrate 10. The semiconductor layer 03 is co-layered with and spaced apart from the active layer 1010 of the transistor 101. The first electrode 1041 of the adjustable capacitor 104 is connected to the pixel electrode 102, and the control signal line 410 is connected to the second electrode 1042 of the adjustable capacitor 104 to apply a voltage to change the capacitance value of the adjustable capacitor 104. The straight line extending along the first direction passes through the active layer 1010 and the semiconductor layer 03. For example, the capacitor 105 formed between the pixel electrode 102 and the common electrode 103, together with the adjustable capacitor 104, forms the storage capacitor of the sub-pixel 100.

[0101] The array substrate provided in this disclosure can achieve the following: at high refresh rates, the storage capacitance of the sub-pixels is small to enable fast charging; at low refresh rates, the storage capacitance of the sub-pixels is large, and the pixel voltage can be better maintained to achieve high-low refresh rate compatibility. At the same time, by setting the positional relationship between the transistors and the adjustable capacitors, the layout can be made more compact, which is beneficial to improving the aperture ratio of the sub-pixels.

[0102] For example, such as Figure 8 and Figure 9As shown, when the display device including the array substrate uses a high refresh rate, a smaller storage capacitor is needed for better charging. In this case, the voltage input to the adjustable capacitor is adjusted via the control signal line to minimize the capacitor's capacitance. The smaller storage capacitance of the sub-pixels facilitates charging, enabling a high refresh rate. Conversely, when the display device including the array substrate uses a low refresh rate, the charging time is longer, and the sub-pixels require better voltage retention. This necessitates a larger storage capacitor. Therefore, the voltage input to the adjustable capacitor is adjusted via the control signal line to maximize the capacitor's capacitance. In this case, the larger storage capacitance of the sub-pixels enables a low refresh rate.

[0103] In some examples, such as Figure 7 and Figure 8 As shown, the gate line 220 and the control signal line 410 are spaced apart, and the second pole 1042 of the adjustable capacitor 104 is located entirely between the control signal line 410 and the pixel electrode 102 connected to the first pole 1041 of the adjustable capacitor 104.

[0104] In some examples, such as Figure 7 and Figure 8 As shown, the control electrode 1013 of transistor 101 is disposed on the same layer as the gate line 220. For example, the control electrode 1013 and the gate line 220 of transistor 101 can be an integrated structure, such as a part of the gate line 220 being a part of the control electrode 1013. The control electrode 1013 includes two parts located on both sides of the gate line 220. The part closer to the adjustable capacitor 104 has a dimension of a first dimension S1 in the second direction, and the part farther from the adjustable capacitor 104 has a dimension of a second dimension S2 in the second direction. The first dimension S1 is larger than the second dimension S2.

[0105] For example, such as Figure 8 As shown, the ratio of the first dimension S1 to the second dimension S2 can be 1.5 to 10. For example, the ratio of the first dimension S1 to the second dimension S2 can be 2 to 3. For example, the ratio of the first dimension S1 to the second dimension S2 can be 2.5 to 8. While ensuring the gate area of ​​the transistor, setting the ratio of the first dimension to the second dimension as large as possible is beneficial to maximizing the overlap area between the semiconductor layer and the second electrode in the adjustable capacitor.

[0106] For example, such as Figure 8 As shown, the second electrode 1042 of the adjustable capacitor 104 and the control electrode 1013 of the transistor 101 overlap in their orthographic projections onto a plane extending along the Y direction and perpendicular to the XY plane. For example, the second electrode 1042 of the adjustable capacitor 104 and the control electrode 1013 of the transistor 101 are arranged in the same layer.

[0107] By placing most of the control electrode of the transistor between the gate line and the control signal line, and placing the second electrode of the adjustable capacitor between the gate line and the control signal line, it is possible to achieve a large channel region for the transistor and a large overlap area between the first and second electrodes of the adjustable capacitor, while saving space in the second direction of the layout, thereby improving the aperture ratio of the sub-pixel.

[0108] For example, such as Figure 8 As shown, the first electrode 1011 and the second electrode 1012 of transistor 101, the first electrode 1041 of adjustable capacitor 104, and data line 210 are arranged on the same layer.

[0109] In some examples, such as Figure 8 As shown, the second electrode 1012 of transistor 101 and the first electrode 1041 of adjustable capacitor 104 are spaced apart, which helps to save space in the second direction of the layout while preventing interference between the first electrode of adjustable capacitor and the second electrode of transistor.

[0110] For example, such as Figure 8 As shown, the distance between the second electrode 1012 of transistor 101 and the first electrode 1041 of adjustable capacitor 104 is greater than the dimension of the first electrode 1041 of adjustable capacitor 104 in the first direction.

[0111] In some examples, such as Figure 7 and Figure 8 As shown, the control signal line 410 and the gate line 220 are arranged on the same layer; multiple sub-pixels 100 are arranged in multiple rows and multiple columns, with the multiple rows of sub-pixels 100 arranged along a second direction. The second terminal of the adjustable capacitor 104 in each row of sub-pixels 100 is connected to the same control signal line 410, and the multiple control signal lines 410 connected to the adjustable capacitors 104 of the multiple rows of sub-pixels 100 are arranged along the second direction. For example, the first direction can be a row direction, and the second direction can be a column direction.

[0112] For example, such as Figure 7 As shown, multiple control signal lines 410 and multiple gate lines 220 are arranged alternately along the second direction.

[0113] Figure 11 This is a partial planar structure schematic diagram of an array substrate provided according to another example of an embodiment of the present disclosure. Figure 11 The array substrate shown and Figure 7 The difference in the array substrate shown is that at least one gate line 220 is multiplexed as a control signal line 410. For example, each gate line 220 is multiplexed as a control signal line 410. For example, the gate signal transmitted by the gate line 220 can be multiplexed as the control signal transmitted by the control signal line 410.

[0114] The array substrate provided in this example saves layout space by multiplexing the gate lines as control signal lines connected to the adjustable capacitor.

[0115] Figures 12 to 14 This is a schematic diagram of a partial planar structure of an array substrate provided according to different examples of embodiments of the present disclosure.

[0116] For example, such as Figure 12 As shown, the array substrate also includes at least one control signal connection line 420 and at least one pin 411 electrically connected to the at least one control signal connection line 420. The extension direction of the at least one control signal connection line 420 is the same as the extension direction of the data line 210, and multiple control signal lines 410 are connected to the at least one control signal connection line 420. Figure 12 A control signal connection line 420 is schematically shown, to which all control signal lines 410 are electrically connected to transmit control signals. Of course, the number of control signal connection lines is not limited to one; for example, there can be two, three, or more control signal connection lines to divide multiple rows of subpixels into multiple groups, with different control signal connection lines configured to transmit control signals to adjustable capacitors of different groups.

[0117] For example, such as Figure 12 As shown, the control signal connection line 420 and the data line 210 can be arranged on the same layer. Of course, the embodiments disclosed herein are not limited to this; for example, the control signal connection line can be located on the side of the data line away from the substrate.

[0118] For example, such as Figure 12 As shown, multiple data lines 210 are electrically connected to the circuit board via multiple pins 211. The circuit board may include a chip-on-film (COF) substrate, and the COF may include a source IC. For example, a control signal connection line 420 may be electrically connected to the source IC via pin 411. For instance, if no control signal connection line is provided in the array substrate, the aforementioned pin 411 may be a dummy pin, meaning it is not input with any electrical signal. After a control signal connection line is provided, this pin is electrically connected to the control signal connection line and is input with the corresponding control signal.

[0119] In some examples, such as Figure 13 As shown, the array substrate also includes multiple pins 321, with each control signal line 410 connected to one pin 321 such that each control signal line 410 is configured to input a separate control signal. For example, the control signal line 410 is electrically connected to a gate control chip (Gate IC) via pin 321, and the gate line 220 is electrically connected to the Gate IC via pin 321. The Gate IC is configured to transmit signals to the gate line and the control signal line 410.

[0120] Figure 15 for Figure 14 A circuit diagram of a shift register unit in the array substrate shown.

[0121] In some examples, such as Figure 14 and Figure 15 As shown, the array substrate also includes a multi-row shift register unit 510 located on the substrate 10. The shift register unit 510 includes an input circuit 511, an output circuit 512, and a node noise reduction circuit 513. The input circuit 511 is connected to a first node N1 and configured to provide an input signal to the first node N1. The node noise reduction circuit 513 is connected to the first node N1 and a second node N2 and configured to reduce noise in the first node N1 under the control of the level of the second node N2. The output circuit 512 is connected to the first node N1 and the output terminal OUT and configured to output an output signal at the output terminal OUT under the control of the level of the first node N1. Each control signal line 410 is connected to the second node N2 of the shift register unit 510 located in the same row.

[0122] For example, the control signal line 410 can be transferred to the location of the second node N2 through a film layer disposed in the same layer as the pixel electrode.

[0123] For example, such as Figure 14 and Figure 15 As shown, the output terminal OUT of the shift register unit 510 is connected to the gate line 220 to transmit the gate signal to the gate line 220. For example, the output circuit 512 is connected to the clock signal terminal CLK.

[0124] For example, such as Figure 15 As shown, the node noise reduction circuit 513 may include a transistor whose gate is connected to the second node N2, whose first terminal is connected to node N1, and whose second terminal is connected to the voltage terminal VGL. Under the control of the second node N2, the transistor pulls down the first node N1 to achieve noise reduction. For example, the shift register unit 510 may also include a pull-down circuit 514, which is connected to the second node N2 and the voltage terminal VGL. Under the control of the second node N2, the pull-down circuit 514 outputs a low-level voltage from the voltage terminal VGL to the output terminal OUT.

[0125] Figure 15 The shift register unit shown can be used Figure 17 The specific implementation circuit diagram shown is an example of the 11T1C circuit, where T represents a transistor and C represents a capacitor. However, it is not limited to this. Figure 15 The shift register unit shown can also use other circuits, such as 9T1C, 10T1C, etc.

[0126] Figure 16This is a schematic diagram of a shift register unit provided according to another embodiment of the present disclosure. Figure 17 for Figure 16 The circuit diagram shows a specific implementation example of the shift register unit. Figure 18 for Figure 17 The circuit layout shown. Figure 19 for Figure 17 The timing diagram of the shift register unit shown is shown.

[0127] like Figure 16 As shown, the shift register unit includes an input circuit 610, an output circuit 620, and a reset circuit 630. The input circuit 610 is connected to the first node N1 and configured to provide an input signal to the first node N1. The reset circuit 630 is connected to the first node N1 and the reset terminal RST, and configured to reset the first node N1 in response to a reset signal provided by the reset terminal RST. The output circuit 620 is connected to the first node N1 and the output terminal OUT, and configured to output an output signal at the output terminal OUT under the control of the voltage level of the first node N1. The output circuit 620 includes an adjustable capacitor C. The first terminal of the adjustable capacitor C is connected to the output terminal OUT, and the first node N1 is connected to the second terminal of the adjustable capacitor C to change the capacitance value of the adjustable capacitor C when the voltage of the first node N1 changes.

[0128] like Figures 16 to 18 As shown, the output circuit 610 includes a transistor 621 electrically connected to the adjustable capacitor C, such as the third transistor M3 mentioned later. The control electrode of the transistor 621 is connected to the first node N1, and one electrode of the transistor 621 is connected to the second electrode of the adjustable capacitor C. A semiconductor layer and an insulating layer are disposed between the first electrode and the second electrode of the adjustable capacitor C. The active layer of the transistor 621 is disposed on the same layer as the semiconductor layer of the adjustable capacitor C.

[0129] For example, the films in an adjustable capacitor can be arranged as follows: Figure 4 As shown, it includes a first metal layer 01, an insulating layer 02, a semiconductor layer 03, and a second metal layer 04 stacked sequentially. For example, the first electrode of the adjustable capacitor can be on the same layer as the source or drain of the transistor M3 and electrically connected, or the two can be integrated into one structure; the second electrode of the adjustable capacitor can be on the same layer as the gate of the transistor M3 and electrically connected, or the two can be integrated into one structure; the semiconductor layer of the adjustable capacitor can be on the same layer as the active layer of the transistor M3 and spaced apart.

[0130] In the shift register provided in this disclosure, the control terminal of the adjustable capacitor is connected to the first node. The capacitance value of the adjustable capacitor increases as the voltage of the first node increases. When the first node is charging, the initial capacitance value of the adjustable capacitor is small, which can quickly increase the voltage at the first node to improve the low-temperature start-up capability. After the voltage of the first node rises, the capacitance value of the adjustable capacitor increases, and when the display device including this shift register is applied to the touch stage, the voltage of the first node can be better maintained. When the first node discharges, the capacitance value of the adjustable capacitor decreases accordingly, thereby allowing the first node to discharge quickly.

[0131] In some examples, such as Figure 16 and Figure 17 As shown, the input circuit 610 includes a first transistor M1. The first terminal of the first transistor M1 is connected to the first power supply terminal VDD, the second terminal of the first transistor M1 is connected to the first node N1, and the gate of the first transistor M1 is connected to the first signal control terminal INT. When the first signal control terminal INT outputs a high level, the first transistor M1 is turned on, outputting the voltage of the first power supply terminal VDD to the first node N1 to charge the first node N1. The first node N1 can be called a pull-up node. When the first power supply terminal VDD provides voltage to the first node N1, the capacitance value of the adjustable capacitor increases as the voltage of the first node increases.

[0132] In some examples, such as Figure 16 and Figure 17 As shown, the reset circuit 630 includes a second transistor M2. The first terminal of the second transistor M2 is connected to the first node N1, the second terminal of the second transistor M2 is connected to the second power supply terminal VSS, and the gate of the second transistor M2 is connected to the second signal control terminal RST. For example, under the control of the second signal control terminal RST, the second transistor M2 outputs the voltage of the second power supply terminal VSS to the first node N1 to reset the first node N1.

[0133] In some examples, such as Figure 16 and Figure 17 As shown, the output circuit 620 also includes a third transistor M3. The first terminal of the third transistor M3 is connected to the clock signal terminal CLK, the second terminal of the third transistor M3 is connected to the first terminal of the adjustable capacitor C, and the gate of the third transistor M3 is connected to the first node N1. When the first node N1 is at a high potential, the third transistor M3 is turned on, outputting the low level of the clock signal segment CLK to the output terminal OUT.

[0134] In some examples, such as Figure 16 and Figure 17As shown, the shift register unit also includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.

[0135] In some examples, such as Figure 16 and Figure 17 As shown, the fourth transistor M4 can be part of a pull-up node reset circuit. This circuit, under the control of the frame reset signal STV, outputs the voltage of the third voltage terminal VGL to the first node N1. The first terminal of the fourth transistor M4 is connected to the first node N1, the second terminal is connected to the third voltage terminal VGL, and the gate is connected to the frame reset signal STV. For example, when the frame reset signal STV outputs a high level, the fourth transistor M4 is turned on, causing it to input a low level of the third voltage terminal VGL to the first node N1 to reset it. Conversely, when the frame reset signal STV outputs a low level, the fourth transistor M4 is turned off.

[0136] In some examples, such as Figure 16 and Figure 17 As shown, transistors M5, M9, M8, and M6 form the structure of a pull-down control circuit. The first terminal of transistor M5 is connected to the fourth voltage terminal GCH, the second terminal of transistor M5 is connected to the second node N2, the gate of transistor M5 is connected to the second terminal of transistor M9, the first terminal of transistor M9 is connected to the fourth voltage terminal GCH, and the gate of transistor M9 is connected to the fourth voltage terminal GCH. The first terminal of transistor M6 is connected to the second node N2, the second terminal of transistor M6 is connected to the third voltage terminal VGL, and the gate of transistor M6 is connected to the first node N1. The first terminal of transistor M8 is connected to the gate of transistor M5, the second terminal of transistor M8 is connected to the third voltage terminal VGL, and the gate of transistor M8 is connected to the first node N1.

[0137] For example, such as Figure 17As shown, the pull-down control circuit can control the potential of the second node N2, so that the second node N2 can control the noise reduction circuit (hereinafter described including the tenth transistor M10) to pull down the potential of the first node N1 to the potential of the fourth voltage terminal GCH, so as to reduce noise in the first node N1. For example, under the control of the high potential of the first node N1, the sixth transistor M6 is turned on, and under the control of the high level of the fourth voltage terminal GCH, the fifth transistor M5 is turned on. However, since the width-to-length ratio of the channel of the sixth transistor M6 is greater than that of the channel of the fifth transistor M5, the potential of the second node N2 will still be pulled down to the low level of the third voltage terminal VGL through the sixth transistor M6. For example, under the control of the high potential of the first node N1, the sixth transistor M6 and the eighth transistor M8 are turned on. Under the control of the high level of the fourth voltage terminal GCH, the ninth transistor M9 is turned on. However, since the width-to-length ratio of the channel of the eighth transistor M8 is greater than that of the channel of the ninth transistor M9, the gate of the fifth transistor M5 is at a low level, which controls the fifth transistor M5 to be turned off. The potential of the second node N2 will still be pulled down to the low level of the third voltage terminal VGL through the sixth transistor M6.

[0138] In some examples, such as Figure 16 and Figure 17 As shown, the seventh transistor M7 is part of the output reset circuit. The signal output reset circuit connects the frame reset signal terminal STV, the third voltage terminal VGL, and the output terminal OUT. Under the control of the frame reset signal terminal STV, it outputs the voltage of the third voltage terminal VGL to the signal output terminal OUT. The first terminal of the seventh transistor M7 is connected to the first node N1, the second terminal of the seventh transistor M7 is connected to the third voltage terminal VGL, and the gate of the seventh transistor M7 is connected to the frame reset signal terminal STV.

[0139] For example, such as Figure 17 As shown, a low level input to the frame reset signal terminal STV turns off the seventh transistor M7. For example, a high level input to the frame reset signal terminal STV turns on the seventh transistor M7, causing it to input a low level from the third voltage terminal VGL to the output terminal OUT to reset the output terminal OUT.

[0140] In some examples, such as Figure 16 and Figure 17 As shown, the tenth transistor M10 is part of the noise reduction circuit structure. The noise reduction circuit connects the second node N2, the third voltage terminal VGL, and the first node N1, and is used to output the voltage of the third voltage terminal VGL to the first node N1 under the control of the second node N2. The first terminal of the tenth transistor M10 is connected to the first node N1, the second terminal of the tenth transistor M10 is connected to the third signal terminal VGL, and the gate of the tenth transistor M10 is connected to the second node N2.

[0141] In some examples, such as Figure 16 and Figure 17 As shown, the eleventh transistor M11 is part of a pull-down circuit. The pull-down circuit connects the second node N2, the third voltage terminal VGL, and the output terminal OUT. Under the control of the second node N2, it outputs the voltage from the third voltage terminal VGL to the signal output terminal OUT. The first terminal of the eleventh transistor M11 is connected to the second terminal of the third transistor M3, the second terminal of the eleventh transistor M11 is connected to the third voltage terminal VGL, and the gate of the eleventh transistor M11 is connected to the first node N1.

[0142] For example, such as Figure 17 As shown, under the control of the low potential of the first node N1, the sixth transistor M6 is turned off, and the fifth transistor M5 is turned on under the control of the high level of the fourth voltage terminal GCH, and outputs the high level of the fourth voltage terminal GCH to the second node N2. Under the control of the high potential of the second node N2, the tenth transistor M10 and the eleventh transistor M11 are both turned on. The tenth transistor M10 pulls down the potential of the first node N1 to the low level of the third voltage terminal VGL, and the eleventh transistor M11 pulls down the potential of the signal output terminal OUT to the low level of the third voltage terminal VGL.

[0143] In embodiments of this disclosure, for example, when the circuits are implemented as N-type transistors, the term "pull-up" refers to charging a node or an electrode of a transistor to raise the absolute value of the voltage level of that node or electrode, thereby enabling the operation of the corresponding transistor (e.g., turning it on); "pull-down" refers to discharging a node or an electrode of a transistor to lower the absolute value of the voltage level of that node or electrode, thereby enabling the operation of the corresponding transistor (e.g., turning it off).

[0144] For example, when the circuits are implemented as P-type transistors, the term "pull-up" means discharging a node or an electrode of a transistor to lower the absolute value of the voltage level of that node or electrode, thereby enabling the corresponding transistor to operate (e.g., turn on); "pull-down" means charging a node or an electrode of a transistor to raise the absolute value of the voltage level of that node or electrode, thereby enabling the corresponding transistor to operate (e.g., turn off).

[0145] It should be noted that in the description of the various embodiments of this disclosure, the first node N1 and the second node N2 do not represent actual components, but rather represent the junction of related electrical connections in the circuit diagram.

[0146] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure all use thin-film transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal, and the other as the second terminal.

[0147] Furthermore, the transistors in the embodiments of this disclosure are all described using N-type transistors as an example. In this case, the first terminal of the transistor is the drain, and the second terminal is the source. It should be noted that this disclosure includes, but is not limited to, this. For example, one or more transistors in the shift register unit provided in the embodiments of this disclosure can also be P-type transistors. In this case, the first terminal of the transistor is the source, and the second terminal is the drain. It is only necessary to connect the terminals of the selected type of transistor according to the terminals of the corresponding transistors in the embodiments of this disclosure, and provide the corresponding high voltage or low voltage at the corresponding voltage terminals. When using N-type transistors, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin-film transistor. Compared with using low-temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin-film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0148] For example, such as Figure 19 As shown, the frame reset signal STV enables 4 rows of dummy shift register units, and the OUT output signal corresponds to the clock signal CLK5-6. Subsequently, each row of shift register units is enabled and matched with the corresponding CLK output. Figure 19 The diagram illustrates the Nth and N+1th frames and the blank time between them. N can be a positive integer greater than or equal to 1.

[0149] This disclosure also provides a gate driving circuit including multiple cascaded shift register units, wherein any one or more shift register units can adopt the structure of the shift register unit provided in any embodiment of this disclosure or a variation thereof. For example, it can adopt... Figure 17 The shift register unit shown is an example. For instance, the gate drive circuit can be directly integrated onto the array substrate of the display device using the same semiconductor process as thin-film transistors to achieve progressive or interlaced scan drive functions.

[0150] This disclosure provides a display device, including any of the array substrates or the shift register units described above.

[0151] The display device in this embodiment can be any product or component with display function, such as a liquid crystal panel, liquid crystal television, monitor, mobile phone, tablet computer, laptop computer, digital photo frame, or navigator. The display device may also include other conventional components such as a display panel; however, the embodiments disclosed herein are not limited in this regard.

[0152] The technical effects of the display device provided by the embodiments of this disclosure can be referred to the corresponding descriptions of the array substrate and shift register unit in the above embodiments, which will not be repeated here.

[0153] The following points need to be explained:

[0154] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0155] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0156] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. An array substrate, comprising: a substrate; a plurality of sub-pixels on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; a plurality of data lines on the substrate, the plurality of data lines being arranged along the first direction; a plurality of gate lines on the substrate, the plurality of gate lines being arranged along the second direction; a plurality of first control signal lines on the substrate, the plurality of first control signal lines being arranged along the second direction; wherein each of at least some of the plurality of sub-pixels comprises a first sub-pixel portion and a second sub-pixel portion arranged along the second direction, the first sub-pixel portion comprising a first pixel electrode, the second sub-pixel portion comprising a second pixel electrode, the first pixel electrode and the second pixel electrode being spaced apart, and the first sub-pixel portion and the second sub-pixel portion sharing a common electrode; the first sub-pixel portion comprising a first transistor, a first electrode of the first transistor being connected to the first pixel electrode, the second sub-pixel portion comprising a second transistor and a third transistor, a first electrode of the second transistor and a first electrode of the third transistor being connected to the second pixel electrode, a control electrode of the first transistor and a control electrode of the second transistor being connected to a same gate line, a second electrode of the first transistor and a second electrode of the second transistor being connected to a same data line, a control electrode of the third transistor being connected to the first control signal line; wherein the array substrate further comprises a second control signal line, the second sub-pixel portion further comprises an adjustable capacitor, a first electrode of the adjustable capacitor being connected to a second electrode of the third transistor, the second control signal line being connected to a second electrode of the adjustable capacitor to apply a voltage to change a capacitance value of the adjustable capacitor; a semiconductor layer and an insulating layer being arranged between the first electrode of the adjustable capacitor and the second electrode of the adjustable capacitor, the semiconductor layer, an active layer of the first transistor, an active layer of the second transistor, and an active layer of the third transistor being arranged in the same layer; the second pixel electrode being provided with a first protruding portion on a side close to the first pixel electrode, the second electrode of the adjustable capacitor being provided with a second protruding portion on a side close to the second pixel electrode, the first control signal line comprising a bent portion between the first protruding portion and the second protruding portion.

2. The array substrate according to claim 1, wherein, the active layer of the first transistor, the active layer of the second transistor, the active layer of the third transistor, and the first electrode and the second electrode of the adjustable capacitor are all located between the first pixel electrode and the second pixel electrode.

3. The array substrate according to claim 2, wherein, the same gate line, to which the control electrode of the first transistor and the control electrode of the second transistor are both electrically connected, is located between the first pixel electrode and the second pixel electrode.

4. The array substrate according to claim 3, wherein, the first control signal line is located between the first pixel electrode and the second pixel electrode.

5. The array substrate according to claim 4, wherein, the second control signal line is located between the same gate line and the first control signal line.

6. The array substrate of claim 1, wherein, The plurality of gate lines are located between the plurality of data lines and the substrate, the second poles of the adjustable capacitors and the control poles of the transistors are arranged in the same layer as the plurality of gate lines, and the first poles of the adjustable capacitors are arranged in the same layer as the plurality of data lines.

7. The array substrate of claim 1, wherein, A straight line extending along the second direction passes through the active layer of the second transistor and the semiconductor layer of the adjustable capacitor.

8. The array substrate of claim 6, wherein, A straight line extending along the first direction passes through the control pole of the third transistor and the second pole of the adjustable capacitor.

9. The array substrate of claim 1, wherein, The first pole of the second transistor is arranged in an integrated structure with the first pole of the third transistor, and the first pole of the third transistor is arranged in the same layer as the plurality of data lines.

10. The array substrate of claim 1, wherein, The second pole of the third transistor is arranged in an integrated structure with the first pole of the adjustable capacitor, and the second pole of the third transistor is located between at least part of the first pole of the second transistor and the second pixel electrode.

11. The array substrate according to any one of claims 1-10, wherein, The plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns of sub-pixels, a plurality of rows of sub-pixels are arranged along the second direction, the second poles of the adjustable capacitors in each row of sub-pixels are connected to the same second control signal line, and a plurality of second control signal lines connected to the adjustable capacitors of the plurality of rows of sub-pixels are arranged along the second direction.

12. The array substrate of claim 11, further comprising: at least one third control signal line and at least one pin electrically connected to the at least one third control signal line, wherein the at least one third control signal line extends in the same direction as the data lines, and the plurality of second control signal lines are connected to the at least one third control signal line.

13. The array substrate of claim 11, further comprising a plurality of pins, wherein, Each second control signal line is connected to one pin so that each second control signal line is configured to individually input a control signal.

14. An array substrate, comprising: a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; a plurality of data lines located on the substrate and arranged along the first direction; a plurality of gate lines located on the substrate and arranged along the second direction; wherein each sub-pixel includes a transistor and a pixel electrode and a common electrode arranged in a stack, a first pole of the transistor is connected to the data line, a second pole of the transistor is connected to the pixel electrode, and a control pole of the transistor is connected to the gate line; the array substrate further comprises at least one control signal line, and at least part of the sub-pixels further comprise an adjustable capacitor, the adjustable capacitor comprises a first pole, a semiconductor layer, and a second pole arranged in a stack in a direction perpendicular to the substrate, the semiconductor layer is arranged in the same layer as and spaced apart from the active layer of the transistor, the first pole of the adjustable capacitor is connected to the pixel electrode, the control signal line is connected to the second pole of the adjustable capacitor to apply a voltage to change the capacitance value of the adjustable capacitor, and a straight line extending along the first direction passes through the active layer and the semiconductor layer.

15. The array substrate of claim 14, wherein, At least one gate line is multiplexed as the control signal line.

16. The array substrate of claim 14, wherein, The gate line and the control signal line are arranged in a spaced manner, and the second pole of the adjustable capacitor is located between the control signal line and the pixel electrode connected with the first pole of the adjustable capacitor.

17. The array substrate of claim 16, wherein, The control pole of the transistor is arranged in the same layer as the gate line, the control pole includes two parts located on both sides of the gate line, the part close to the adjustable capacitor in the two parts has a first size in the second direction, and the part away from the adjustable capacitor in the two parts has a second size in the second direction, and the first size is greater than the second size.

18. The array substrate according to any one of claims 14-17, wherein, The second pole of the transistor is arranged in a spaced manner with the first pole of the adjustable capacitor.

19. The array substrate of claim 16, wherein, The control signal line is arranged in the same layer as the gate line. The plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns of sub-pixels, a plurality of rows of sub-pixels are arranged along the second direction, the second pole of the adjustable capacitor in each row of sub-pixels is connected with the same control signal line, and a plurality of control signal lines connected with the adjustable capacitors of the plurality of rows of sub-pixels are arranged along the second direction.

20. The array substrate of claim 19, further comprising: at least one control signal connection line and at least one pin electrically connected with the at least one control signal connection line, wherein the extension direction of the at least one control signal connection line is the same as the extension direction of the data line, and the plurality of control signal lines are connected with the at least one control signal connection line.

21. The array substrate of claim 19, further comprising a plurality of pins, wherein, Each control signal line is connected with one pin so that each control signal line is configured to input a control signal individually.

22. The array substrate of claim 19, further comprising: a plurality of shift register units located on the substrate, wherein the shift register unit includes an input circuit, an output circuit, and a node noise reduction circuit; the input circuit is connected with a first node and configured to provide an input signal to the first node; the node noise reduction circuit is connected with the first node and a second node, and configured to reduce noise of the first node under the control of the level of the second node; the output circuit is connected with the first node and an output terminal, and configured to output an output signal at the output terminal under the control of the level of the first node, wherein each control signal line is connected with the second node of the shift register unit in the same row.

23. A shift register unit, comprising an input circuit, an output circuit, and a reset circuit, wherein, the input circuit is connected with a first node and configured to provide an input signal to the first node; the reset circuit is connected with the first node and a reset terminal, and configured to reset the first node in response to a reset signal provided by the reset terminal; the output circuit is connected with the first node and an output terminal, and configured to output an output signal at the output terminal under the control of the level of the first node, wherein the output circuit includes an adjustable capacitor, a first pole of the adjustable capacitor is connected with the output terminal, and a second pole of the adjustable capacitor is connected with the first node to change the capacitance value of the adjustable capacitor when the voltage of the first node changes. The output circuit comprises a transistor electrically connected with the adjustable capacitor, a control electrode of the transistor is connected with the first node, one pole of the transistor is connected with a second pole of the adjustable capacitor, a semiconductor layer and an insulating layer are arranged between a first pole of the adjustable capacitor and the second pole of the adjustable capacitor, and an active layer of the transistor is arranged in the same layer as the semiconductor layer of the adjustable capacitor.

24. The shift register cell of claim 23, wherein, The input circuit comprises a first transistor, a first pole of the first transistor is connected with a first power supply end, a second pole of the first transistor is connected with the first node, and a gate electrode of the first transistor is connected with a first signal control end; The reset circuit comprises a second transistor, a first pole of the second transistor is connected with the first node, a second pole of the second transistor is connected with a second power supply end, and a gate electrode of the second transistor is connected with a second signal control end; The output circuit further comprises a third transistor, a first pole of the third transistor is connected with a clock signal end, a second pole of the third transistor is connected with the first pole of the adjustable capacitor, and a gate electrode of the third transistor is connected with the first node; The shift register unit further comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor, wherein a first pole of the fourth transistor is connected with the first node, a second pole of the fourth transistor is connected with a third voltage end, a gate electrode of the fourth transistor is connected with a frame reset signal end; a first pole of the fifth transistor is connected with a fourth voltage end, a second pole of the fifth transistor is connected with a second node; a first pole of the sixth transistor is connected with the second node, a second pole of the sixth transistor is connected with the third voltage end, and a gate electrode of the sixth transistor is connected with the first node; a first pole of the seventh transistor is connected with the first node, a second pole of the seventh transistor is connected with the third voltage end, and a gate electrode of the seventh transistor is connected with the frame reset signal end; a first pole of the eighth transistor is connected with a gate electrode of the fifth transistor, a second pole of the eighth transistor is connected with the third voltage end, and a gate electrode of the eighth transistor is connected with the first node; a first pole of the ninth transistor is connected with the fourth voltage end, a second pole of the ninth transistor is connected with the first pole of the eighth transistor, and a gate electrode of the ninth transistor is connected with the fourth voltage end; a first pole of the tenth transistor is connected with the first node, a second pole of the tenth transistor is connected with a third signal end, and a gate electrode of the tenth transistor is connected with the second node; a first pole of the eleventh transistor is connected with the second pole of the third transistor, a second pole of the eleventh transistor is connected with the third voltage end, and a gate electrode of the eleventh transistor is connected with the first node.

25. A display device comprising the array substrate of any one of claims 1-22 or the shift register unit of claim 23 or 24.

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