Display substrate and display device

Abstract

The invention discloses a display substrate and a display device, the display substrate comprises a substrate, and a plurality of sub-pixels, a plurality of first signal lines and a plurality of second signal lines which are arranged on the substrate, each sub-pixel comprises a pixel circuit, the pixel circuit is electrically connected with the first signal lines, the first signal lines comprise at least one initial signal line, and the second signal lines comprise at least one second signal line; the second signal line comprises at least one initial connecting line; the initial signal line extends along a first direction (D1), the initial connecting line extends along a second direction (D2), and the first direction (D1) and the second direction (D2) intersect; the at least one initial signal line is in one-to-one correspondence with the at least one initial connecting line, and the initial signal line is electrically connected with the corresponding initial connecting line.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising: a substrate, and a plurality of sub-pixels, a plurality of first signal lines, and a plurality of second signal lines disposed on the substrate, wherein the sub-pixels include pixel circuits electrically connected to the first signal lines, the first signal lines include at least one initial signal line, and the second signal lines include at least one initial connection line; the initial signal lines extend along a first direction, and the initial connection lines extend along a second direction, the first direction intersecting the second direction;

[0006] The at least one initial signal line corresponds to the at least one initial connection line in a one-to-one manner, and the initial signal line is electrically connected to the corresponding initial connection line.

[0007] In an exemplary embodiment, the at least one initial signal line includes a first initial signal line and a second initial signal line, the second initial signal line being located on a side of the first initial signal line away from the substrate.

[0008] In an exemplary embodiment, further comprising: a plurality of reset signal lines, the reset signal lines at least partially extending along the first direction;

[0009] The orthographic projection of the first initial signal line on the substrate is located between the orthographic projection of the second initial signal line on the substrate and the orthographic projection of the reset signal line on the substrate, and does not overlap with the orthographic projection of the second initial signal line on the substrate and the orthographic projection of the reset signal line on the substrate.

[0010] In an exemplary embodiment, the further comprising: a plurality of light emitting signal lines, the light emitting signal lines at least partially extending along the first direction;

[0011] The orthographic projection of the second initial signal line on the substrate is between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the luminous signal line on the substrate, and does not overlap with the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the luminous signal line on the substrate.

[0012] In an exemplary embodiment, the at least one initial connection line includes: a first initial connection line and a second initial connection line, the first initial connection line and the second initial connection line are arranged in the same layer, a plurality of first initial connection lines are arranged along a first direction, and a plurality of second initial connection lines are arranged along the first direction;

[0013] The first initial connection lines and the second initial connection lines are alternately arranged along the first direction, and the midlines of the two first initial connection lines along the second direction pass through the signal main line of the second initial connection line located between the two first initial connection lines;

[0014] The first initial connection line is electrically connected to the first initial signal line through a via hole, and the second initial connection line is electrically connected to the second initial signal line through a via hole.

[0015] In an exemplary embodiment, the pixel circuit includes: a capacitor, the capacitor including: a first plate and a second plate, the second plate of the capacitor being located on a side of the first plate of the capacitor away from the substrate;

[0016] An orthographic projection of the first initial signal line on the substrate at least partially overlaps with an orthographic projection of the second plate of the capacitor on the substrate.

[0017] In an exemplary embodiment, the second initial connection line includes: a signal main line, a plurality of first signal connection parts, and a plurality of second signal connection parts; the signal main line extends along the second direction, the first signal connection parts and the second signal connection parts extend along the first direction, the first signal connection parts and the second signal connection parts are respectively connected to the signal main line, and the signal main line is connected to the second initial signal line;

[0018] The first signal connection portion and the second signal connection portion are respectively located on both sides of the signal main line and are symmetrically arranged relative to the signal main line.

[0019] In an exemplary embodiment, an orthographic projection of the signal main line on the substrate at least partially overlaps an orthographic projection of the second plate of the capacitor on the substrate.

[0020] In an exemplary embodiment, orthographic projections of the first and second signal connecting portions on the substrate at least partially overlap with an orthographic projection of the second initial signal line on the substrate, and do not overlap with an orthographic projection of the reset signal line on the substrate.

[0021] In an exemplary embodiment, the pixel structures of the pixel circuits of adjacent sub-pixels located in the same row are symmetrically arranged along a virtual straight line extending in the second direction.

[0022] In an exemplary embodiment, the method further includes: a plurality of data signal lines extending along the second direction, wherein the data signal lines connecting adjacent sub-pixels are symmetrically arranged with respect to a virtual straight line extending along the second direction;

[0023] The orthographic projection of the first signal connection line on the substrate or the orthographic projection of the signal main line of the second signal connection line on the substrate is located between the orthographic projections of two adjacent data signal lines on the substrate.

[0024] In an exemplary embodiment, the present invention further includes: a plurality of first scan signal lines, wherein at least a portion of the first scan signal lines extends along the first direction;

[0025] The orthographic projection of the reset signal line on the substrate is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the first initial signal line on the substrate;

[0026] The reset signal line includes: a first sub-reset signal line and a second sub-reset signal line electrically connected to each other;

[0027] The first sub-reset signal line is provided on the same layer as the first initial signal line, the second sub-reset signal line is provided on the same layer as the second initial signal line, and an orthographic projection of the first sub-reset signal line on the substrate at least partially overlaps with an orthographic projection of the second sub-reset signal line on the substrate.

[0028] In an exemplary embodiment, further comprising: a plurality of second scan signal lines, the second scan signal lines at least partially extending along the first direction;

[0029] The orthographic projection of the second scanning signal line on the substrate is located between the orthographic projections of the first scanning signal line and the light emitting signal line on the substrate;

[0030] The second scanning signal line includes: a first sub-scanning signal line and a second sub-scanning signal line electrically connected to each other;

[0031] The first sub-scanning signal line is arranged on the same layer as the first initial signal line, the second sub-scanning signal line is arranged on the same layer as the second initial signal line, and the orthographic projection of the first sub-scanning signal line on the substrate at least partially overlaps with the orthographic projection of the second sub-scanning signal line on the substrate.

[0032] In an exemplary embodiment, the present invention further comprises: a plurality of first power supply lines and a plurality of flat portions, the sub-pixel further comprises: a light emitting device, the light emitting device comprises a first electrode, and the pixel circuit comprises: an oxide transistor;

[0033] The flat portion is disposed between adjacent first power lines and connected to the adjacent first power lines;

[0034] The orthographic projection of the flat portion on the substrate at least partially overlaps with the orthographic projections of the reset signal line, the first scan signal line, the second scan signal line, the active layer of the oxide transistor, and the first electrode of the light emitting device on the substrate;

[0035] An orthographic projection of the at least one flat portion on the substrate also at least partially overlaps with an orthographic projection of the first initial signal line on the substrate.

[0036] In an exemplary embodiment, a plurality of annular areas are formed between the plurality of first power lines and the plurality of flat portions;

[0037] At least two of the annular regions have different shapes.

[0038] In an exemplary embodiment, the display device includes: a display area and a non-display area, and further includes: a third signal line located in the non-display area, the sub-pixel, the first signal line, and the second signal line are located in the display area, and the third signal line includes: at least one initial power supply line, the initial power supply line at least partially extending along the second direction;

[0039] At least one initial power supply line corresponds to at least one initial signal line on a one-to-one basis, and the initial power supply line is electrically connected to the corresponding initial signal line.

[0040] In an exemplary embodiment, the display area includes a first side and a second side opposite to each other, and the third signal line is located on at least one of the first side and the second side of the display area.

[0041] In an exemplary embodiment, the present invention further comprises: a driving structure layer sequentially stacked on the substrate; the driving structure layer comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked;

[0042] The first conductive layer at least includes: a first scanning signal line, a light emitting signal line, and a first plate of a capacitor located in at least one sub-pixel;

[0043] The second conductive layer at least includes: a first initial signal line, a first sub-reset signal line of the reset signal line, a first sub-scanning signal line of the second scan signal line, and a second plate of a capacitor located in at least one sub-pixel;

[0044] The third conductive layer at least includes: a second sub-reset signal line of the reset signal line, a second sub-scanning signal line of the second scan signal line, and a second initial signal line;

[0045] The fourth conductive layer at least includes: a first initial connection line and a second initial connection line;

[0046] The fifth conductive layer at least includes: a data signal line, a first power line and a flat portion.

[0047] In a second aspect, the present disclosure further provides a display device comprising the above-mentioned display substrate.

[0048] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0049] Summary of the Figures

[0050] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0051] FIG1 is a schematic structural diagram of a display device;

[0052] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0053] FIG3 is a schematic diagram of a planar structure of another display substrate;

[0054] FIG4A is a schematic diagram of an equivalent circuit of a pixel circuit;

[0055] FIG4B is an operation timing diagram of the pixel circuit provided in FIG4A ;

[0056] FIG5 is a schematic plan view of a display substrate provided in an embodiment of the present disclosure;

[0057] FIG6 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0058] FIG7 is a schematic diagram of a portion of film layers of a display substrate provided in accordance with an exemplary embodiment;

[0059] FIG8 is a second schematic diagram of a partial film layer of a display substrate provided in an exemplary embodiment;

[0060] FIG9 is a third schematic diagram of a partial film layer of a display substrate provided in an exemplary embodiment;

[0061] FIG10 is a schematic diagram after forming a light shielding layer pattern;

[0062] FIG11 is a schematic diagram of a pattern of a first semiconductor layer;

[0063] FIG12 is a schematic diagram after forming a first semiconductor layer pattern;

[0064] FIG13 is a schematic diagram of a first conductive layer pattern;

[0065] FIG14 is a schematic diagram after forming a first conductive layer pattern;

[0066] FIG15 is a schematic diagram of a second conductive layer pattern;

[0067] FIG16 is a schematic diagram after forming a second conductive layer pattern;

[0068] FIG17 is a schematic diagram of a second semiconductor layer pattern;

[0069] FIG18 is a schematic diagram showing a second semiconductor layer after patterning;

[0070] FIG19 is a schematic diagram of a pattern of a third conductive layer;

[0071] FIG20 is a schematic diagram after forming a third conductive layer pattern;

[0072] FIG21 is a schematic diagram after forming a seventh insulating layer pattern;

[0073] FIG22 is a schematic diagram of a fourth conductive layer pattern;

[0074] FIG23 is a schematic diagram after forming a fourth conductive layer pattern;

[0075] FIG24 is a schematic diagram after forming a first planar layer pattern;

[0076] FIG25 is a schematic diagram of a fifth conductive layer pattern;

[0077] FIG. 26 is a schematic diagram showing a fifth conductive layer after patterning is formed.

[0078] Details

[0079] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings below. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0080] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0081] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0082] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0083] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0084] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0085] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0086] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0087] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0088] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0089] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0090] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0091] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0092] The display substrate uses low-temperature polysilicon (LTPS) technology, which has advantages such as high resolution, high response speed, high brightness, and high aperture ratio. Although it is popular in the market, LTPS technology also has some defects, such as high production cost and high power consumption. At this time, the backplane (Low Temperature Poly-Silicon+Oxide, LTPO) technology solution formed by combining low-temperature polysilicon transistors with oxide transistors came into being. Compared with LTPS technology, LTPO technology has lower leakage current and faster pixel response. The display substrate adds an extra layer of oxide, which reduces the energy consumption required to excite the pixels, thereby reducing the power consumption when the screen is displayed. Display products using LTPO technology have multiple initial signals to facilitate the adjustment of multiple nodes of the pixel circuit in the display product, but multiple initial signals require the setting of multiple signal lines. The voltage drop of the signal lines will affect the display uniformity and reduce the display effect of the display substrate.

[0093] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel circuit. The pixel circuit may be respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0094] Figure 2 is a schematic diagram of a planar structure of a display substrate, and Figure 3 is a schematic diagram of a planar structure of another display substrate. As shown in Figures 2 and 3, the display substrate may include a plurality of pixel units P arranged in a matrix. The plurality of pixel units P include a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and at least one third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel circuit and a light-emitting device. The pixel circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel circuit of the subpixel in which they are located. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the subpixel in which they are located.

[0095] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0096] In an exemplary embodiment, as shown in FIG2 , a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a triangular pattern, which is not limited in this disclosure. FIG2 illustrates the arrangement in a horizontal parallel pattern as an example.

[0097] In an exemplary embodiment, as shown in FIG3 , a pixel unit may include four sub-pixels, which may be a first sub-pixel, a second sub-pixel, and two third sub-pixels. The four sub-pixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure. FIG3 illustrates an example of a square arrangement of four sub-pixels.

[0098] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a stacked electrode (anode), an organic light emitting layer, and a second electrode (cathode).

[0099] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0100] FIG4A is a schematic diagram of an equivalent circuit of a pixel circuit. In an exemplary embodiment, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG4A , the pixel circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one capacitor C.

[0101] As shown in FIG4A , a gate electrode of the first transistor T1 is electrically connected to the reset signal line Reset, a first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and a second electrode of the first transistor T1 is electrically connected to the first node N1; a gate electrode of the second transistor T2 is electrically connected to the second scan signal line Gate2, a first electrode of the second transistor T2 is electrically connected to the first node N1, and a second electrode of the second transistor T2 is electrically connected to the third node N3; a gate electrode of the third transistor T3 is electrically connected to the first node N1, a first electrode of the third transistor T3 is electrically connected to the second node N2, and a second electrode of the third transistor T3 is electrically connected to the third node N3; a gate electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, a first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and a gate electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate2. A second electrode of the transistor T4 is electrically connected to the second node N2; a gate electrode of the fifth transistor T5 is electrically connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2; a gate electrode of the sixth transistor T6 is electrically connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; a gate electrode of the seventh transistor T7 is electrically connected to the first scanning signal line Gate1, a first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; a first plate C1 of the capacitor C is electrically connected to the first node N1, and a second plate C2 of the capacitor C is electrically connected to the first power supply line VDD.

[0102] In an exemplary embodiment, the first transistor T1 may be referred to as a node reset transistor, and writes the initial signal of the first initial signal line INIT1 into the first node N1 when the signal of the reset signal line Reset is an active level signal.

[0103] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, and when the signal of the second scan signal line Gate2 is an active level signal, writes the signal of the third node N3 into the first node N1 to compensate for the signal of the first node N1.

[0104] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines a driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between a gate electrode and the first electrode thereof.

[0105] In an exemplary embodiment, the fourth transistor T4 may be referred to as a write transistor, and writes an initial signal of the data signal line Data into the second node N2 when the signal of the first scan signal line Gate1 is an active level signal.

[0106] In an exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When the signal of the light emitting signal line EM is an active level signal, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to enable the light emitting device to emit light.

[0107] In an exemplary embodiment, the seventh transistor T7 may be referred to as an anode reset transistor, and writes the initial signal of the second initial signal line INIT2 into the first electrode of the light emitting device L when the signal of the first scan signal line Gate1 is an active level signal.

[0108] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0109] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form an LTPO display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0110] In an exemplary embodiment, the first transistor T1 and the second transistor T2 are of opposite transistor types to the third transistor T3 to the seventh transistor T7. For example, the first transistor T1 and the second transistor T2 may be N-type transistors, and the third transistor T3 to the seventh transistor T7 may be P-type transistors.

[0111] In example embodiments, the first and second transistors T1 and T2 may be oxide transistors, and the third to seventh transistors T3 to T7 may be low-temperature polysilicon transistors.

[0112] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT1 may be -2.5 volts to -3.5 volts. Exemplarily, the voltage value of the signal of the first initial signal line INIT1 may be -3 volts.

[0113] In an exemplary embodiment, the voltage value of the signal of the second initial signal line INIT2 may be -3.5 volts to -4.5 volts, and illustratively, the voltage value of the signal of the first initial signal line INIT1 may be -4 volts.

[0114] In the present disclosure, the arrangement of the first initial signal line INIT1 and the second initial signal line INIT2 can achieve both the required brightness of 0 grayscale and the required brightness in the high brightness mode.

[0115] In an exemplary embodiment, the light emitting device L′ may be electrically connected to the fourth node N4 and the second power line VSS, respectively.

[0116] In an exemplary embodiment, the first power line VDD continuously provides a high level signal, and the second power line VSS continuously provides a low level signal.

[0117] FIG4B is an operating timing diagram of the pixel circuit provided in FIG4A . The following illustrates an exemplary embodiment of the present disclosure through the operating process of the pixel circuit illustrated in FIG4A during the display phase. FIG4B is illustrated by taking the first transistor T1 and the second transistor T2 as N-type transistors, and the third transistor T3 to the seventh transistor T7 as P-type transistors as an example. The pixel circuit in FIG4B includes the first transistor T1 to the seventh transistor T7, a capacitor C, and eight signal lines (a data signal line Data, a first scan signal line Gate1, a second scan signal line Gate2, a reset signal line Reset, a first initial signal line INIT1, a second initial signal line INIT2, an emission signal line EM, and a first power line VDD).

[0118] 4A and 4B , the operation process of the pixel circuit may include:

[0119] The first stage P1 is called the initialization stage. The signal of the reset signal line Reset is a high-level signal, the first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is written into the first node N1 through the turned-on first transistor T1, initializing (resetting) the first node N1, clearing the pre-stored voltage inside it, and completing the initialization.

[0120] In the second phase P2, also known as the data writing phase or the threshold compensation phase, the first scanning signal line Gate1 is a low-level signal, the second scanning signal line Gate2 is a low-level signal, and the data signal line Data outputs a data voltage. During this phase, the third transistor T3 is turned on because the first node N1 is a low-level signal. The signal of the first scan signal line Gate1 is a low-level signal, the fourth transistor T4 is turned on, and the seventh transistor T7 is turned on. The signal of the second scan signal line Gate2 is a high-level signal, and the second transistor T2 is turned on. The data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor T7, thereby initializing (resetting) the first electrode of the light-emitting device L, clearing the pre-stored voltage therein, and completing the initialization.

[0121] In the third stage P3, called the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, thereby driving the light-emitting device L to emit light.

[0122] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth)2=K*[(Vdd-Vd+|Vth|)-Vth]2=K*[(Vdd-Vd]2

[0123] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0124] Figure 5 is a planar schematic diagram of a display substrate provided in an embodiment of the present disclosure, Figure 6 is a structural schematic diagram of a display substrate provided in an embodiment of the present disclosure, Figure 7 is a partial membrane layer schematic diagram 1 of a display substrate provided in an exemplary embodiment, Figure 8 is a partial membrane layer schematic diagram 2 of a display substrate provided in an exemplary embodiment, and Figure 9 is a partial membrane layer schematic diagram 3 of a display substrate provided in an exemplary embodiment. As shown in Figures 5 to 9, the display substrate provided in an embodiment of the present disclosure may include: a substrate and a plurality of sub-pixels, a plurality of first signal lines, and a plurality of second signal lines arranged on the substrate, the sub-pixels including: a pixel circuit electrically connected to the first signal line, the first signal line including at least one initial signal line, the second signal line including at least one initial connection line; the initial signal line extends along a first direction D1, the initial connection line extends along a second direction, and the first direction D1 intersects with the second direction D2. Figures 6 to 9 are described using two rows and four columns of sub-pixels as an example.

[0125] In an exemplary embodiment, the number of initial signal lines may be two, three or more, which may be determined according to the circuit structure of the pixel circuit of the sub-pixel. FIG. 5 to FIG. 9 illustrate the example in which the first signal line includes: a first initial signal line INIT1 and a second initial signal line INIT2.

[0126] In an exemplary embodiment, the number of initial connection lines may be two, three, or more, and the number of initial connection lines may be the same as the number of initial signal lines. Figures 5 to 9 illustrate an example in which the second signal line includes a first initial connection line CL1 and a second initial connection line CL2.

[0127] In an exemplary embodiment, as shown in Figures 5 to 9, at least one initial signal line corresponds to at least one initial connection line, and the initial signal line is electrically connected to the corresponding initial connection line. For example, the first initial signal line INIT1 corresponds to the first initial connection line CL1 and is connected to the corresponding first initial connection line CL1. The second initial signal line INIT2 corresponds to the second initial connection line CL2 and is connected to the corresponding second initial connection line CL2.

[0128] In an exemplary embodiment, the signals between at least one initial signal line may be the same or different, and this disclosure does not make any limitation thereto.

[0129] In example embodiments, the display substrate may be an LTPO display substrate.

[0130] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0131] 5 , the display substrate includes a display region 100 and a non-display region 200 surrounding at least one side of the display region. A plurality of sub-pixels, a plurality of first signal lines, and a plurality of second signal lines may be located in the display region 100 .

[0132] In an exemplary embodiment, the shape of the display area may be a square or a rounded rectangle, or may be other shapes, which is not limited in the present disclosure.

[0133] The display substrate provided by the embodiment of the present disclosure includes: a substrate and a plurality of sub-pixels, a plurality of first signal lines, and a plurality of second signal lines arranged on the substrate, the sub-pixels including: a pixel circuit, the pixel circuit being electrically connected to the first signal line, the first signal line including at least one initial signal line, and the second signal line including at least one initial connection line; the initial signal line extending along a first direction, the initial connection line extending along a second direction, the first direction intersecting the second direction; at least one initial signal line corresponding to at least one initial connection line, and the initial signal line being electrically connected to the corresponding initial connection line. The present disclosure, by setting at least one initial signal line corresponding to at least one initial connection line in a one-to-one manner, and the initial signal line being electrically connected to the corresponding initial connection line, can enable any initial signal line and the corresponding initial connection line to form a mesh structure, thereby reducing the voltage drop between the signal lines, improving the display uniformity of the display substrate, and improving the display effect of the display substrate.

[0134] In an exemplary embodiment, as shown in FIG6 to FIG9 , the at least one initial signal line may include a first initial signal line INIT1 and a second initial signal line INIT2. The second initial signal line INIT2 may be located on a side of the first initial signal line INIT1 that is away from the substrate. This location of the second initial signal line INIT2 on a side of the first initial signal line INIT1 that is away from the substrate can reduce the area occupied by the subpixels and optimize the layout of the display substrate.

[0135] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the display substrate may further include a plurality of reset signal lines Reset, wherein the reset signal lines Reset at least partially extend along the first direction D1.

[0136] In an exemplary embodiment, as shown in Figures 6 to 9, the orthographic projection of the first initial signal line INIT1 on the substrate is located between the orthographic projection of the second initial signal line INIT2 on the substrate and the orthographic projection of the reset signal line Reset on the substrate, and does not overlap with the orthographic projection of the second initial signal line INIT2 on the substrate and the orthographic projection of the reset signal line Reset on the substrate. The non-overlapping orthographic projections of the first initial signal line INIT1 and the second initial signal line INIT2 on the substrate and the orthographic projection of the reset signal line Reset on the substrate can reduce the overlapping area between film layers, thereby reducing parasitic capacitance.

[0137] In an exemplary embodiment, the reset signal line Reset may have a double-layer structure.

[0138] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the display substrate may further include a plurality of light emitting signal lines EM, the light emitting signal lines EM at least partially extending along the first direction D1 .

[0139] In an exemplary embodiment, as shown in Figures 6 to 9, the orthographic projection of the second initial signal line INIT2 on the substrate is between the orthographic projection of the first initial signal line INIT1 on the substrate and the orthographic projection of the light-emitting signal line EM on the substrate, and does not overlap with the orthographic projection of the first initial signal line INIT1 on the substrate and the orthographic projection of the light-emitting signal line EM on the substrate. The fact that the orthographic projection of the second initial signal line INIT2 on the substrate does not overlap with the orthographic projection of the first initial signal line INIT1 on the substrate and the orthographic projection of the light-emitting signal line EM on the substrate can reduce the overlapping area between film layers, thereby reducing parasitic capacitance.

[0140] 6 to 9 , the at least one preliminary connection line includes a first preliminary connection line CL1 and a second preliminary connection line CL2 . The first preliminary connection line CL1 and the second preliminary connection line CL2 are disposed in the same layer.

[0141] In an exemplary embodiment, the plurality of first preliminary connection lines CL2 are arranged along the first direction D1, and the plurality of second preliminary connection lines CL2 are arranged along the first direction D1.

[0142] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the first preliminary connection lines CL1 and the second preliminary connection lines CL2 are alternately arranged, that is, one second preliminary connection line is located between two first preliminary connection lines.

[0143] In exemplary embodiments, as shown in FIG. 6 to FIG. 9 , midlines of the two first preliminary connection lines CL1 in the second direction D2 may pass through the signal main line CL2A of the second preliminary connection line CL2 located between the two first preliminary connection lines.

[0144] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the first initial connection line CL1 is electrically connected to the first initial signal line INIT1 through a via hole, and the second initial connection line CL2 is electrically connected to the second initial signal line INIT2 through a via hole.

[0145] In an exemplary embodiment, as shown in FIG6 to FIG9 , the pixel circuit includes a capacitor including a first plate and a second plate. The second plate C2 of the capacitor is located on a side of the first plate of the capacitor away from the substrate.

[0146] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , an orthographic projection of the first initial signal line INIT1 on the substrate at least partially overlaps with an orthographic projection of the second plate C2 of the capacitor on the substrate.

[0147] In an exemplary embodiment, as shown in Figures 6 to 9, at least one second initial connection line CL2 may include a signal main line CL2A, a plurality of first signal connection parts CL2B, and a plurality of second signal connection parts CL2C. The signal main line CL2A extends along the second direction D2, and the first signal connection parts CL2B and the second signal connection parts CL2C extend along the first direction D1. The first signal connection parts CL2B and the second signal connection parts CL2C are respectively connected to the signal main line CL2A, and the signal main line CL2A is connected to the second initial signal line INIT2.

[0148] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the first signal connection portion CL2B and the second signal connection portion CL2C are respectively located on both sides of the signal main line CL2A and are symmetrically arranged with respect to the signal main line CL2A.

[0149] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the orthographic projection of the signal main line CL2A on the substrate at least partially overlaps with the orthographic projection of the second plate C2 of the capacitor on the substrate.

[0150] In an exemplary embodiment, the orthographic projections of the first and second signal connection parts CL2B and CL2C on the substrate at least partially overlap with the orthographic projection of the second initial signal line INIT2 on the substrate, and do not overlap with the orthographic projection of the reset signal line Reset on the substrate.

[0151] The orthographic projections of the first signal connection part CL2B and the second signal connection part CL2C in the present disclosure on the substrate at least partially overlap with the orthographic projection of the second initial signal line INIT2 on the substrate, which can increase the area ratio of the blank area without signal lines in the display substrate and improve the visible light transmittance of the display substrate.

[0152] The first signal connection part CL2B and the second signal connection part CL2C in the present disclosure do not overlap with the orthographic projection of the reset signal line Reset on the substrate, which reduces the area of ​​the overlapping region between the film layer where the first signal connection part CL2B and the second signal connection part CL2C are located and the film layer where the reset signal line Reset is located, thereby avoiding the risk of short circuit between the reset signal line and the second initial connection line due to the protrusion of the reset signal line caused by dust particles when the second initial connection line is set on the reset signal line, thereby avoiding poor display caused by short circuit and improving the reliability of the display substrate.

[0153] In exemplary embodiments, as shown in Figures 6 to 9 , the pixel structures of pixel circuits of adjacent sub-pixels in the same row are symmetrically arranged along a virtual line extending in the second direction D2. This symmetrical arrangement of the pixel structures of pixel circuits of adjacent sub-pixels in the same row along a virtual line extending in the second direction D2 allows the adjacent sub-pixels to share portions of their structures, thereby reducing the space occupied by the pixel circuits and increasing lateral space, providing space for the second signal lines and optimizing the wiring space of the display substrate.

[0154] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the display substrate may further include a plurality of data signal lines Data extending along the second direction D2 .

[0155] In an exemplary embodiment, as shown in FIG6 to FIG9 , the data signal lines Data connected to adjacent sub-pixels are symmetrically arranged with respect to a virtual straight line extending along the second direction D2;

[0156] In an exemplary embodiment, as shown in Figures 6 to 9, the orthographic projection of the first signal connection line CL1 on the substrate or the orthographic projection of the signal main line CL2A of the second signal connection line CL2 on the substrate is located between the orthographic projections of two adjacent data signal lines Data on the substrate. That is, the signal main line CL2A of the first signal connection line CL1 and the second signal connection line CL2 are interspersed between the data signal lines Data, which can ensure the integrity of the structure included in the film layer where the data signal lines are located (such as the first and second electrodes of the first transistor, the second transistor and the third transistor), and can improve the shielding and covering effects, and is suitable for high-resolution display substrates.

[0157] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the display substrate may further include a plurality of first scan signal lines Gate1 , the first scan signal lines Gate1 at least partially extending along the first direction D1 .

[0158] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the orthographic projection of the reset signal line Reset on the substrate is located between the orthographic projection of the first scan signal line Gate1 and the orthographic projection of the first initial signal line INIT1 on the substrate.

[0159] 6 to 9 , the reset signal line Reset may include a first sub-reset signal line ResetA and a second sub-reset signal line ResetB electrically connected to each other. For example, the first sub-reset signal line ResetA and the second sub-reset signal line ResetB may be connected in the non-display area.

[0160] In an exemplary embodiment, as shown in Figures 6 to 9, the first sub-reset signal line ResetA can be provided on the same layer as the first initial signal line INIT1, the second sub-reset signal line ResetB can be provided on the same layer as the second initial signal line INIT2, and the orthographic projection of the first sub-reset signal line ResetA on the substrate at least partially overlaps with the orthographic projection of the second sub-reset signal line ResetB on the substrate.

[0161] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the display substrate may further include a plurality of second scan signal lines Gate2 , the second scan signal lines Gate2 at least partially extending along the first direction D1 .

[0162] In an exemplary embodiment, the second scan signal line Gate2 may have a double-layer structure.

[0163] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , an orthographic projection of the second scan signal line Gate2 on the substrate is located between orthographic projections of the first scan signal line Gate1 and the emission signal line EM on the substrate.

[0164] 6 to 9 , the second scan signal line Gate2 may include a first sub-scan signal line Gate2A and a second sub-scan signal line Gate2B electrically connected to each other. For example, the first sub-scan signal line Gate2A and the second sub-scan signal line Gate2B may be connected in the non-display area.

[0165] In an exemplary embodiment, as shown in Figures 6 to 9, the first sub-scanning signal line Gate2A is arranged on the same layer as the first initial signal line INIT1, the second sub-scanning signal line Gate2B is arranged on the same layer as the second initial signal line INIT2, and the orthographic projection of the first sub-scanning signal line Gate2A on the substrate at least partially overlaps with the orthographic projection of the second sub-scanning signal line Gate2B on the substrate.

[0166] 6 to 9 , the display substrate may further include a plurality of first power lines VDD and a plurality of flat portions BL. The sub-pixel may further include a light emitting device including a first electrode, and the pixel circuit may include an oxide transistor.

[0167] In an exemplary embodiment, an oxide transistor includes a first transistor and a second transistor.

[0168] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the first power lines to which adjacent sub-pixels are connected are symmetrical with respect to a virtual straight line extending along the second direction D2 .

[0169] In an exemplary embodiment, the first power line VDD is connected to one of the adjacent power lines and is spaced apart from the other adjacent power line. Two data signal lines Data are disposed between the two spaced apart first power lines VDD.

[0170] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , the flat portion BL is disposed between adjacent first power lines VDD and is connected to the adjacent first power lines VDD.

[0171] In exemplary embodiments, as shown in Figures 6 to 9 , the orthographic projection of the flat portion BL on the substrate at least partially overlaps with the orthographic projections of the reset signal line Reset, the first scan signal line Gate1, the second scan signal line Gate2, the active layer of the oxide transistor, and the first electrode of the light-emitting device on the substrate. By providing the flat portion, the present disclosure can improve the flatness of the first electrode of the light-emitting device, thereby enhancing the display quality of the display substrate.

[0172] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , an orthographic projection of the at least one flat portion BL on the substrate also at least partially overlaps with an orthographic projection of the first initial signal line INIT1 on the substrate.

[0173] In an exemplary embodiment, as shown in FIG. 6 to FIG. 9 , a plurality of ring-shaped areas are formed between the plurality of first power lines VDD and the plurality of flat portions BL.

[0174] In an exemplary embodiment, as shown in Figures 6 to 9, at least two of the annular regions have different shapes.

[0175] In an exemplary embodiment, the light emitting device may include a first light emitting device emitting red light, a second light emitting device emitting blue light, and a third light emitting device and a fourth light emitting device emitting green light.

[0176] In an exemplary embodiment, the area of ​​the first electrode of the second light emitting device is larger than that of the first light emitting device, and the areas of the first electrodes of the third and fourth light emitting devices are smaller than that of the first electrode of the first light emitting device.

[0177] In an exemplary embodiment, as shown in FIG5 , a display substrate includes a display area 100 and a non-display area 200, and further includes third signal lines located in the non-display area. Subpixels, first signal lines, and second signal lines are located in the display area. The third signal lines include at least one initial power supply line, extending at least partially along a second direction D2. The at least one initial power supply line corresponds one-to-one with at least one initial signal line and is electrically connected to the corresponding initial signal line. FIG5 illustrates an example in which the third signal lines include a first initial power supply line INITL1 and a second initial power supply line INITL2. Exemplarily, the first initial power supply line INITL1 corresponds to and is connected to the first initial signal line INIT1. The second initial power supply line INITL2 corresponds to and is connected to the second initial signal line INIT2.

[0178] In an exemplary embodiment, as shown in Figure 5 , the display area 100 includes a first side and a second side opposite to each other, and the third signal line is located on at least one of the first and second sides of the display area. Figure 5 illustrates the third signal line located on the first and second sides as an example.

[0179] In an exemplary embodiment, the display substrate may further include: a driving structure layer sequentially stacked on the base; the driving structure layer includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked;

[0180] The first conductive layer at least includes: a first scanning signal line Gate1, a light emitting signal line EM, and a first plate of a capacitor located in at least one sub-pixel;

[0181] The second conductive layer at least includes: a first initial signal line INIT1, a first sub-reset signal line ResetA of the reset signal line Reset, a first sub-scanning signal line Gate2A of the second scan signal line Gate2, and a second plate C2 of the capacitor located in at least one sub-pixel;

[0182] The second semiconductor layer includes at least: an active layer of an oxide transistor;

[0183] The third conductive layer at least includes: a second sub-reset signal line ResetB of the reset signal line Reset, a second sub-scanning signal line Gate2B of the second scan signal line Gate2, and a second initial signal line INIT2;

[0184] The fourth conductive layer includes at least: a first initial connection line CL1 and a second initial connection line CL2;

[0185] The fifth conductive layer at least includes a data signal line Data, a first power line VDD, and a flat portion BL.

[0186] In an exemplary embodiment, the driving structure layer may further include: a shielding layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, an eighth insulating layer, a first planar layer, and a second planar layer. The light shielding layer is located on the side of the first semiconductor layer close to the substrate, the first insulating layer is located between the substrate and the light shielding layer, the second insulating layer is located between the light shielding layer and the first semiconductor layer, the third insulating layer is located between the first semiconductor layer and the first conductive layer, the fourth insulating layer is located between the first conductive layer and the second conductive layer, the fifth insulating layer is located between the second conductive layer and the second semiconductor layer, the sixth insulating layer is located between the second semiconductor layer and the third conductive layer, the seventh insulating layer is located between the third conductive layer and the fourth conductive layer, the eighth insulating layer and the first planar layer are located between the fourth conductive layer and the fifth conductive layer, the first planar layer is located on the side of the eighth insulating layer away from the substrate, and the second planar layer is located on the side of the fifth conductive layer away from the substrate.

[0187] In an exemplary embodiment, as shown in Figure 6, there is a parasitic capacitance between the active layer of the oxide transistor located in the second semiconductor layer (exemplarily, the active layer of the first transistor and the active layer of the second transistor) of the pixel circuit of the sub-pixel and the first scanning signal line Gate1 located in the first conductive layer, and is called the parasitic capacitance of the sub-pixel.

[0188] In an exemplary embodiment, the parasitic capacitances of different sub-pixels are different. For example, the parasitic capacitances of a red sub-pixel and a green sub-pixel can be the same, but different from the parasitic capacitance of a blue sub-pixel. The present disclosure can achieve a balanced data range between sub-pixels, adjust the black state voltage, and thereby improve the display quality of the display substrate by differentially designing the parasitic capacitances of different sub-pixels.

[0189] In an exemplary embodiment, the different parasitic capacitances of different sub-pixels can be achieved by making the active layers of the oxide transistors located in the second semiconductor layer (exemplarily, the active layer of the first transistor and the active layer of the second transistor) of the pixel circuits of different sub-pixels located in the first scanning signal line of the first conductive layer have different overlapping areas.

[0190] In an exemplary embodiment, the display substrate may further include a light emitting structure layer located on a side of the driving structure layer away from the substrate. The light emitting structure layer may include a light emitting device.

[0191] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0192] Figures 10 to 26 are schematic diagrams of a display substrate manufacturing process provided by an exemplary embodiment. Figures 10 to 26 are illustrated using two rows and four columns of sub-pixels as an example. As shown in Figures 10 to 26, a display substrate manufacturing process provided by an exemplary embodiment may include:

[0193] (1) forming a light-shielding layer pattern, including: depositing a first insulating film and a light-shielding film on a substrate in sequence, patterning the light-shielding film through a patterning process, and forming a first insulating layer covering the substrate and a light-shielding layer pattern located on the first insulating layer, as shown in FIG10 , which is a schematic diagram after the light-shielding layer pattern is formed.

[0194] In an exemplary embodiment, as shown in FIG. 10 , the light shielding layer may include at least a light shielding structure located in at least one sub-pixel.

[0195] In an exemplary embodiment, as shown in Figure 10, all the light shielding structures are interconnected as an integrated structure. The light shielding structures of adjacent sub-pixels in the same row are symmetrically arranged with respect to a virtual line extending along the second direction D2, and the light shielding structures of all sub-pixels in the same column are identical.

[0196] In an exemplary embodiment, as shown in Figure 10, the light shielding structure may include a light shielding portion 10, a first light shielding connection portion 11, a second light shielding connection portion 12, a third light shielding connection portion 13, and a fourth light shielding connection portion 14. The light shielding portion 10, the first light shielding connection portion 11, the second light shielding connection portion 12, the third light shielding connection portion 13, and the fourth light shielding connection portion 14 are an integrated structure connected to each other.

[0197] In an exemplary embodiment, as shown in FIG10 , the first light-shielding connection portion 11 and the second light-shielding connection portion 12 are arranged along the second direction D2. In the second direction D2, the first light-shielding connection portion 11 of a subpixel can be located on the side of the light-shielding portion 10 closer to the previous row of subpixels, and the second light-shielding connection portion 12 of the subpixel can be located on the side of the light-shielding portion 10 closer to the next row of subpixels. In the first direction D1, the third light-shielding connection portion 13 and the fourth light-shielding connection portion 14 of the subpixel are located on different sides of the light-shielding portion 10. When the third light-shielding connection portion 13 of a subpixel can be located on the side of the light-shielding portion 10 closer to the previous column of subpixels, the fourth light-shielding connection portion 14 of the subpixel can be located on the side of the light-shielding portion 10 closer to the next column of subpixels. When the third light-shielding connection portion 13 of a subpixel can be located on the side of the light-shielding portion 10 closer to the next column of subpixels, the fourth light-shielding connection portion 14 of the subpixel can be located on the side of the light-shielding portion 10 closer to the previous column of subpixels.

[0198] In an exemplary embodiment, as shown in FIG. 10 , the light shielding portion 10 may be in a rectangular shape, and corners of the rectangular shape may be chamfered.

[0199] 10 , the first light-shielding connection portion 11 and the second light-shielding connection portion 12 may be strip-shaped extending along the second direction D2 , and the third light-shielding connection portion 13 and the fourth light-shielding connection portion 14 may be strip-shaped extending along the first direction D1 .

[0200] In an exemplary embodiment, as shown in FIG10 , the first light-shielding connection portion of a sub-pixel is connected to the second light-shielding connection portion of a sub-pixel located in the same column and the previous row, the second light-shielding connection portion of the sub-pixel is connected to the first light-shielding connection portion of a sub-pixel located in the same column and the next row, the third light-shielding connection portion of the sub-pixel is connected to the third light-shielding connection portion of one adjacent sub-pixel located in the same row, and the fourth light-shielding connection portion of the sub-pixel is connected to the fourth light-shielding connection portion of another adjacent sub-pixel located in the same row.

[0201] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a second insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a second insulating layer covering the light-shielding layer and a first semiconductor layer pattern located on the second insulating layer, as shown in Figures 11 and 12, where Figure 11 is a schematic diagram of the first semiconductor layer pattern, and Figure 12 is a schematic diagram after the first semiconductor layer pattern is formed.

[0202] In an exemplary embodiment, as shown in Figures 11 and 12, the first semiconductor layer pattern may include at least: an active layer T31 of a third transistor located in at least one sub-pixel, an active layer T41 of a fourth transistor, an active layer T51 of a fifth transistor, an active layer T61 of a sixth transistor, and an active layer T71 of a seventh transistor.

[0203] In an exemplary embodiment, as shown in FIG. 11 and FIG. 12 , the active layer T31 of the third transistor to the active layer T71 of the seventh transistor are an integral structure connected to each other.

[0204] In an exemplary embodiment, as shown in FIG. 11 and FIG. 12 , the active layers T31 of the third transistor to T71 of the seventh transistor of adjacent sub-pixels are symmetrically arranged with respect to a virtual straight line extending in the second direction D2 .

[0205] In an exemplary embodiment, as shown in Figures 11 and 12, in the first direction D1, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be located on the same side of the active layer T31 of the third transistor in the subpixel, and the active layer T61 of the sixth transistor may be located on the same side of the active layer T31 of the third transistor in the subpixel. The active layer T61 of the sixth transistor and the active layer T41 of the fourth transistor may be located on different sides of the active layer T31 of the third transistor in the subpixel. In the second direction D2, the active layer T51 of the fifth transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor in the i-th row of subpixels may be located on a side of the active layer T31 of the third transistor in the subpixel away from the subpixel in the (i+1)th row of subpixels, and the active layer T41 of the fourth transistor in the i-th row of subpixels may be located on a side of the active layer T31 of the third transistor in the subpixel closer to the subpixel in the (i+1)th row of subpixels.

[0206] In an exemplary embodiment, as shown in FIG11 and FIG12 , the active layer T31 of the third transistor may have an inverted Ω shape. The active layer T41 of the fourth transistor, the active layer T51 of the fifth transistor, and the active layer T61 of the sixth transistor may have an I shape. The active layer T71 of the seventh transistor may have an L shape.

[0207] In an exemplary embodiment, as shown in FIG12 , an orthographic projection of the light-shielding portion on the substrate at least partially overlaps with an orthographic projection of the active layer T31 of the third transistor on the substrate. The orthographic projections of the first light-shielding connection portion, the second light-shielding connection portion, the third light-shielding connection portion, and the fourth light-shielding connection portion on the substrate do not overlap with an orthographic projection of any of the active layer T21 of the second transistor, the active layer T31 of the third transistor, and the active layer T71 of the seventh transistor on the substrate.

[0208] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region T31_1 of the active layer 13 of the third transistor may simultaneously serve as the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor. The second region T31_2 of the active layer T31 of the third transistor may simultaneously serve as the first region T61_1 of the active layer T61 of the sixth transistor. The second region T61_2 of the active layer T61 of the sixth transistor may serve as the second region T71_2 of the active layer T71 of the seventh transistor. The first region T41_1 of the active layer T41 of the fourth transistor, the first region T51_1 of the active layer T51 of the fifth transistor, and the first region T71_1 of the active layer T71 of the seventh transistor may be provided separately.

[0209] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a third insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a third insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the third insulating layer, as shown in FIG13 and FIG14 , FIG13 is a schematic diagram of the first conductive layer pattern, and FIG14 is a schematic diagram after forming the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0210] In an exemplary embodiment, as shown in FIG. 13 and FIG. 14 , the first conductive layer pattern may include at least a first scan signal line Gate1 , a light emitting signal line EM, and a first plate C1 of a capacitor located in at least one sub-pixel.

[0211] In an exemplary embodiment, the first plates C1 of the pixel circuits of adjacent sub-pixels are symmetrically arranged with respect to a virtual straight line extending along the second direction D2.

[0212] In an exemplary embodiment, the first electrode plate C1 may be rectangular, with chamfered corners. The orthographic projection of the first electrode plate C1 on the substrate at least partially overlaps the orthographic projection of the active layer of the third transistor on the substrate. In an exemplary embodiment, the first electrode plate C1 may serve as both a plate of the capacitor and the gate electrode T32 of the third transistor T3.

[0213] In an exemplary embodiment, the first scan signal line Gate1 may be in the shape of a line with a main portion extending along a first direction D1. The first scan signal line Gate1 connected to the i-th row of sub-pixels may be located on a side of the first plate C1 of the capacitor of this sub-pixel that is closer to the sub-pixels in the (i+1)th row. The area where the first scan signal line Gate1 overlaps with the active layer of the fourth transistor of this sub-pixel may serve as the gate electrode T42 of the fourth transistor, and the area where the first scan signal line Gate1 overlaps with the active layer of the seventh transistor of this sub-pixel may serve as the gate electrode T72 of the seventh transistor.

[0214] In an exemplary embodiment, the shape of the light-emitting signal line EM can be a line shape with a main portion extending along the first direction D1. The light-emitting signal line EM can be located on the side of the first electrode C1 of the sub-pixel away from the sub-pixel in the i+1th row. The area where the light-emitting signal line EM overlaps with the active layer of the fifth transistor of the sub-pixel serves as the gate electrode T52 of the fifth transistor, and the area where the light-emitting signal line EM overlaps with the active layer of the sixth transistor of the sub-pixel serves as the gate electrode T62 of the sixth transistor.

[0215] In an exemplary embodiment, the first scanning signal line Gate1 and the light-emitting signal line EM can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0216] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform a conductorization process on the first semiconductor layer. The first semiconductor layer in the areas shielded by the first conductive layer forms the channel regions of the third through seventh transistors T3 through T7, while the first semiconductor layer in the areas not shielded by the first conductive layer is conductorized. That is, the first and second regions of the active layers of the third through seventh transistors are all conductorized. After conductorization, the first region T31_1 of the active layer 13 of the third transistor (also the second region T41_2 of the active layer T41 of the fourth transistor and the second region T51_2 of the active layer T51 of the fifth transistor) can be reused as the first electrode T33 of the third transistor (also the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor).

[0217] In an exemplary embodiment, the gate electrode T32 of the third transistor is arranged across the active layer of the third transistor, the gate electrode T42 of the fourth transistor is arranged across the active layer of the fourth transistor, the gate electrode T52 of the fifth transistor is arranged across the active layer of the fifth transistor, the gate electrode T62 of the sixth transistor is arranged across the active layer of the sixth transistor, and the gate electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor. That is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0218] (4) Forming a second conductive layer pattern, including: sequentially depositing a fourth insulating film and a second conductive film on the substrate having the aforementioned pattern, and patterning the fourth insulating film and the second conductive film through a patterning process to form a fourth insulating layer and a second conductive layer pattern located on the fourth insulating layer, as shown in FIG15 and FIG16 , FIG15 is a schematic diagram of the second conductive layer pattern, and FIG16 is a schematic diagram after forming the second conductive layer pattern. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0219] In an exemplary embodiment, as shown in Figures 15 and 16, the second conductive layer pattern may include at least: a first initial signal line INIT1, a first sub-reset signal line ResetA of the reset signal line, a first sub-scanning signal line Gate2A of the second scan signal line, and a second plate C2 of the capacitor located at at least one sub-pixel.

[0220] In an exemplary embodiment, as shown in FIG. 15 and FIG. 16 , the second plates C2 of the pixel circuits of adjacent sub-pixels located in the same row are symmetrically arranged with respect to a virtual straight line extending along the second direction D2 .

[0221] In an exemplary embodiment, as shown in FIG15 , the second electrode C2 may include a main portion C21 and a connecting portion C22 connected to each other, wherein the connecting portion C22 of the sub-pixel is located on a side of the main portion C22 of the sub-pixel close to the previous or next column of sub-pixels.

[0222] In an exemplary embodiment, as shown in FIG15 , the outline of the main body portion C21 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the main body portion C21 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate. The second electrode plate can serve as another electrode plate of the capacitor, and the first electrode plate C1 and the second electrode plate C2 constitute the capacitor of the pixel circuit. The main body portion C21 is provided with an opening. The shape of the opening can be rectangular and can be located in the middle as shown in FIG20 , so as to form a ring structure as shown in FIG20 . The opening exposes the fourth insulating layer covering the first electrode plate, and the orthographic projection of the first electrode plate on the substrate includes the orthographic projection of the opening on the substrate. In an exemplary embodiment, the opening exposes the first electrode plate, so that the second electrode of the first transistor (also the second electrode of the second transistor) formed subsequently is connected to the first electrode plate.

[0223] In an exemplary embodiment, as shown in FIG. 15 , the connection portion C22 may have a rectangular outline.

[0224] In an exemplary embodiment, the length of the body portion C21 along the second direction may be equal to the length of the connection portion C22 along the second direction.

[0225] In an exemplary embodiment, for any sub-pixel, the second electrode plate C2 is spaced apart from the second electrode plate C2 of one adjacent sub-pixel in the same row, and is interconnected with the second electrode plate of another adjacent sub-pixel in the same row, forming an integral structure. For example, the second electrode plate of the sub-pixel in the i-th row, j-th column is spaced apart from the second electrode plate of the sub-pixel in the i-th row, j+1-th column, the second electrode plate of the sub-pixel in the i-th row, j+2-th column is spaced apart from the second electrode plate of the sub-pixel in the i-th row, j+3-th column, and the connecting portion of the second electrode plate of the sub-pixel in the i-th row, j+1-th column is connected to the connecting portion of the second electrode plate of the sub-pixel in the i-th row, j+2-th column. In the present disclosure, interconnecting the second electrodes of some adjacent sub-pixels in the same row can ensure display uniformity of the display substrate to a certain extent.

[0226] In an exemplary embodiment, the first initial signal line INIT1 may be in the shape of a line having a main portion extending along the first direction D1. The first initial signal line INIT1 connected to the sub-pixel in the i-th row may be located on a side of the second electrode plate C2 of the sub-pixel closer to the sub-pixel in the (i+1)-th row. For the same sub-pixel, the orthogonal projection of the first initial signal line INIT1 connected to the sub-pixel on the substrate is located on a side of the substrate away from the orthogonal projection of the first sub-reset signal line ResetA connected to the reset signal line.

[0227] In an exemplary embodiment, the shape of the first sub-reset signal line ResetA of the reset signal line may be a line having a main portion extending along the first direction D1. The first sub-reset signal line ResetA may be located between the second electrode C2 of the connected sub-pixel and the first initial signal line INIT1, and an area overlapping with the active layer of the first transistor of the subsequently formed sub-pixel serves as the first gate electrode T12A of the first transistor. For the same sub-pixel, the orthographic projection of the first sub-reset signal line ResetA connected to the sub-pixel on the substrate is located between the orthographic projection of the first scanning signal line connected to the sub-pixel and the orthographic projection of the first initial signal line INIT1 connected to the sub-pixel on the substrate.

[0228] In an exemplary embodiment, the first sub-scanning signal line Gate2A of the second scan signal line may be in the shape of a line with a main portion extending along the first direction D1. The first sub-scanning signal line Gate2A of the second scan signal line may be located between the second electrode C2 of the connected sub-pixel and the first sub-reset signal line ResetA of the reset signal line. The area overlapping with the active layer of a second transistor of the sub-pixel to be formed later serves as the first gate electrode T22A of the second transistor. For the same sub-pixel, the orthogonal projection of the first sub-scanning signal line Gate2A connected to the sub-pixel on the substrate is located between the orthogonal projection of the first electrode of the sub-pixel on the substrate and the orthogonal projection of the first scan signal line connected to the sub-pixel on the substrate.

[0229] In an exemplary embodiment, the first initial signal line INIT1, the first sub-reset signal line ResetA of the reset signal line, and the first sub-scanning signal line Gate2A of the second scan signal line can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0230] (5) forming a second semiconductor layer pattern, comprising: on a substrate on which the aforementioned pattern is formed, sequentially depositing a fifth insulating film and a second semiconductor film on the substrate, patterning the third insulating film and the second semiconductor film through a patterning process to form a fifth insulating layer and a second semiconductor layer pattern located on the fifth insulating layer, as shown in FIG17 and FIG18 , FIG17 is a schematic diagram of the second semiconductor layer pattern, and FIG18 is a schematic diagram after the second semiconductor layer pattern is formed.

[0231] In exemplary embodiments, as shown in FIG. 17 and FIG. 18 , the second semiconductor layer pattern may include at least an active layer T11 of a first transistor and an active layer T21 of a second transistor located in at least one sub-pixel.

[0232] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the active layer T11 of the first transistor and the active layer T21 of the second transistor are an integral structure connected to each other.

[0233] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the active layers T11 of the first transistor and the active layers T21 of the second transistor of adjacent sub-pixels are symmetrically disposed with respect to a virtual straight line extending in the second direction D2 .

[0234] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , in the second direction D2 , the active layer T21 of the second transistor in the current row of sub-pixels may be located on a side of the active layer T11 of the first transistor in the current row of sub-pixels close to the previous row of sub-pixels.

[0235] In exemplary embodiments, as shown in FIG. 17 and FIG. 18 , the active layer T11 of the first transistor and the active layer T21 of the second transistor may have an “I” shape or an “L” shape.

[0236] In an exemplary embodiment, as shown in Figures 17 and 18, for the same sub-pixel, the positive projection of the active layer T11 of the first transistor of the sub-pixel on the substrate at least partially overlaps with the positive projection of the first sub-reset signal line of the reset signal line connected to the sub-pixel and the first initial signal line connected to the sub-pixel on the substrate.

[0237] In an exemplary embodiment, as shown in FIG17 and FIG18 , for the same sub-pixel, the orthographic projection of the active layer T21 of the second transistor of the sub-pixel on the substrate overlaps with the orthographic projection of the first sub-scanning signal line of the second scan signal line connected to the sub-pixel on the substrate.

[0238] 17 , the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions. In an exemplary embodiment, the second region T11_2 of the active layer T11 of the first transistor may also serve as the first region T21_1 of the active layer T21 of the second transistor, and the first region T11_1 of the active layer T11 of the first transistor and the second region T21_2 of the active layer T21 of the second transistor may be separately provided.

[0239] In an exemplary embodiment, for the same sub-pixel, the orthographic projection of the second region T11_2 of the active layer T11 of the first transistor of the sub-pixel (also the first region T21_1 of the active layer T21 of the second transistor) on the substrate at least partially overlaps with the orthographic projection of the first scan signal line connected to the sub-pixel on the substrate.

[0240] In an exemplary embodiment, the active layer T11 of the first transistor is disposed across the first gate electrode of the first transistor, and the active layer T21 of the second transistor is disposed across the first gate electrode of the second transistor.

[0241] (6) Forming a third conductive layer pattern, including: sequentially depositing a sixth insulating film and a third conductive film on the substrate having the aforementioned pattern, and patterning the sixth insulating film and the third conductive film through a patterning process to form a sixth insulating layer pattern and a third conductive layer pattern located on the sixth insulating layer, as shown in FIG19 and FIG20 , FIG19 is a schematic diagram of the third conductive layer pattern, and FIG20 is a schematic diagram after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0242] In an exemplary embodiment, as shown in FIG. 19 and FIG. 20 , the third conductive layer pattern may include at least a second sub reset signal line ResetB of the reset signal line, a second sub scan signal line Gate2B of the second scan signal line, and a second initial signal line INIT2 .

[0243] In an exemplary embodiment, as shown in Figures 19 and 20, the shape of the second sub-reset signal line RLB of the reset signal line can be a line shape whose main portion extends along the first direction D1, and the orthographic projection of the second sub-reset signal line RLB of the reset signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-reset signal line of the reset signal line on the substrate, and is electrically connected to the first sub-reset signal line of the reset signal line.

[0244] In an exemplary embodiment, as shown in Figures 19 and 20, for the same sub-pixel, the orthographic projection of the second sub-reset signal line ResetB on the substrate is located between the orthographic projection of the first scan signal line and the orthographic projection of the first initial signal line INIT1 on the substrate. The area where the second sub-reset signal line ResetB overlaps with the active layer of the first transistor of this sub-pixel serves as the second gate electrode T12B of the first transistor. The first gate electrode and the second gate electrode of the first transistor constitute the gate electrode of the first transistor.

[0245] In an exemplary embodiment, as shown in Figures 19 and 20, the shape of the second sub-scanning signal line Gate2B of the second scan signal line can be a line shape in which the main portion extends along the first direction D1, and the positive projection of the second sub-scanning signal line Gate2B of the second scan signal line on the substrate at least partially overlaps with the positive projection of the first sub-scanning signal line of the second scan signal line on the substrate, and is electrically connected to the first sub-scanning signal line of the second scan signal line.

[0246] In an exemplary embodiment, as shown in Figures 19 and 20, the orthographic projection of the second sub-scanning signal line Gate2B on the substrate is located between the orthographic projection of the light-emitting signal line and the orthographic projection of the first scanning signal line on the substrate. The region where the second sub-scanning signal line Gate2B of the second scanning signal line overlaps with the active layer of the second transistor of the sub-pixel serves as the second gate electrode T22B of the second transistor. The first gate electrode and the second gate electrode of the second transistor constitute the gate electrode of the second transistor.

[0247] In an exemplary embodiment, as shown in Figures 19 and 20, the second initial signal line INIT2 may be in the shape of a line whose main portion extends along the first direction D1. The orthographic projection of the second initial signal line INIT2 on the substrate is located between the orthographic projection of the first initial signal line and the orthographic projection of the light-emitting signal line on the substrate.

[0248] In an exemplary embodiment, the second sub-reset signal line ResetB of the reset signal line, the second sub-scanning signal line Gate2B of the second scan signal line, and the second initial signal line INIT2 can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0249] In an exemplary embodiment, after forming the third conductive layer pattern, the third conductive pattern can be used as a shield to perform conductorization on the second semiconductor layer. The second semiconductor layer in the area shielded by the third conductive layer forms a channel region from the first transistor to the second transistor, and the second semiconductor layer in the area not shielded by the third conductive layer is conductorized, that is, the first region and the second region from the first transistor to the second active layer are both conductorized.

[0250] (7) forming a seventh insulating layer pattern, comprising: depositing a seventh insulating film on the substrate having the aforementioned pattern formed thereon, patterning the seventh insulating film through a patterning process to form a seventh insulating layer pattern covering the aforementioned pattern, wherein the seventh insulating layer is provided with a plurality of via patterns, as shown in FIG. 21 , which is a schematic diagram after the seventh insulating layer pattern is formed.

[0251] In an exemplary embodiment, as shown in FIG21 , the plurality of via holes of the seventh insulating layer include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9, a tenth via hole V10, an eleventh via hole V11, and a twelfth via hole V12 located in at least one sub-pixel.

[0252] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the fourth transistor on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the first via V1 are etched away to expose the surface of the first region of the active layer of the fourth transistor, and the first via V1 is configured to connect the first electrode of the subsequently formed fourth transistor to the first region of the active layer of the fourth transistor through the via.

[0253] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fifth transistor on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the second via V2 are etched away to expose the surface of the first area of ​​the active layer of the fifth transistor, and the second via V2 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active layer of the fifth transistor through the via.

[0254] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the third transistor (also the first area of ​​the active layer of the sixth transistor) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the third via V3 are etched away to expose the surface of the second area of ​​the active layer of the third transistor (also the first area of ​​the active layer of the sixth transistor), and the third via V3 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor and the first electrode of the sixth transistor) to the second area of ​​the active layer of the third transistor (also the first area of ​​the active layer of the sixth transistor) through the via.

[0255] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the sixth transistor (also the second area of ​​the active layer of the seventh transistor) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the fourth via V4 are etched away to expose the surface of the second area of ​​the active layer of the sixth transistor (also the second area of ​​the active layer of the seventh transistor), and the fourth via V4 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second area of ​​the active layer of the sixth transistor (also the second area of ​​the active layer of the seventh transistor) through the via.

[0256] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the seventh transistor on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the active layer of the seventh transistor, and the fifth via V5 is configured to connect the subsequently formed first initial connection portion (which is also the first electrode of the seventh transistor) to the first area of ​​the active layer of the seventh transistor through the via.

[0257] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first plate of the capacitor on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer within the sixth via V6 are etched away to expose the surface of the first plate of the capacitor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor) to the first plate of the capacitor through the via.

[0258] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the second plate of the capacitor on the substrate, the sixth insulating layer and the fifth insulating layer in the seventh via V7 are etched away to expose the surface of the second plate of the capacitor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fifth transistor to the second plate of the capacitor through the via.

[0259] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first initial signal line on the substrate, the sixth insulating layer and the fifth insulating layer in the eighth via V8 are etched away to expose the surface of the first initial signal line, and the eighth via V8 is configured to connect the first electrode of the subsequently formed first transistor to the first initial signal line through the via.

[0260] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the sixth insulating layer in the ninth via V9 is etched away to expose the surface of the first region of the active layer of the first transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed first transistor to the first region of the active layer of the first transistor through the via.

[0261] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) on the substrate, the sixth insulating layer in the tenth via V10 is etched away, exposing the surface of the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor), and the tenth via V10 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) through the via.

[0262] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second transistor on the substrate, the sixth insulating layer in the eleventh via V11 is etched away to expose the surface of the second region of the active layer of the second transistor, and the eleventh via V11 is configured to connect the second electrode of the subsequently formed second transistor (which is also the first electrode of the sixth transistor) to the second region of the active layer of the second transistor through the via.

[0263] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second initial signal line on the substrate, exposing the surface of the second initial signal line. The twelfth via V12 is configured to connect a subsequently formed second initial connection line to the second initial signal line through the via.

[0264] In an exemplary embodiment, as shown in Figure 21, the eighth via holes V8 of two adjacent sub-pixels are the same via hole. The eighth via holes V8 of two adjacent sub-pixels are the same via hole, which can reduce the number of via holes in the display substrate and simplify the manufacturing process of the display substrate.

[0265] (8) Forming a fourth conductive layer pattern, including: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern, as shown in FIG22 and FIG23 , where FIG22 is a schematic diagram of the fourth conductive layer pattern, and FIG23 is a schematic diagram after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0266] In an exemplary embodiment, as shown in Figures 22 and 23, the fourth conductive layer pattern may include at least: a first initial connection line CL1, a second initial connection line CL2, and a first electrode T13 of a first transistor, a second electrode T14 of a first transistor, a first electrode T23 of a second transistor, a second electrode T24 of a second transistor, a second electrode T34 of a third transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a first electrode T63 of a sixth transistor, a second electrode T64 of a sixth transistor, a first electrode T73 of a seventh transistor, and a second electrode T74 of a seventh transistor located at at least one sub-pixel.

[0267] In an exemplary embodiment, the first electrodes and the second electrodes of the plurality of transistors of adjacent sub-pixels are symmetrically arranged along a virtual straight line extending in the second direction D2.

[0268] In an exemplary embodiment, as shown in Figures 22 and 23, adjacent subpixels located in the same row as a subpixel include: a first adjacent subpixel and a second adjacent subpixel, wherein the subpixel and the first electrode of the first transistor are integrally structured with the first electrode of the first transistor of the first adjacent subpixel, and are spaced apart from the first electrode of the first transistor of the second adjacent subpixel. The first adjacent subpixel is the subpixel in the column preceding the subpixel, and the second adjacent subpixel is the subpixel in the column following the subpixel. For example, the first electrode of the first transistor of the subpixel in the i-th row and j-th column is integrally structured with the first electrode of the first transistor of the subpixel in the i-th row and j-th column, the first electrode of the first transistor of the subpixel in the i-th row and j-th column is integrally structured with the first electrode of the first transistor of the subpixel in the i-th row and j-th column, and the first electrode of the first transistor of the subpixel in the i-th row and j-th column is spaced apart from the first electrode of the first transistor of the subpixel in the i-th row and j-th column.

[0269] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode T13 of the first transistor is shaped like a strip extending along the first direction D1. The first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through a ninth via hole and is electrically connected to the first initial signal line through an eighth via hole.

[0270] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are integrally formed, and at least partially have a linear shape extending along the second direction D2. The second electrode T14 of the first transistor (also the first electrode T23 of the second transistor) is connected to the first plate of the capacitor via a sixth via and is connected to the second region of the active layer of the first transistor (also the first region of the active layer of the second transistor) via a tenth via.

[0271] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode T24 of the second transistor, the second electrode T34 of the third transistor, and the first electrode T63 of the sixth transistor are integrated into a block-shaped structure. The second electrode T24 of the second transistor (also the second electrode T34 of the third transistor and the first electrode T63 of the sixth transistor) is connected to the second region of the active layer of the third transistor (also the first region of the active layer of the sixth transistor) through a third via hole, and is connected to the second region of the active layer of the second transistor through an eleventh via hole.

[0272] 22 and 23 , the first electrode T43 of the fourth transistor is in a block shape and is connected to the first region of the active layer of the fourth transistor through a first via hole.

[0273] In an exemplary embodiment, as shown in Figures 22 and 23, the shape of the first electrode T53 of the fifth transistor can be a broken line shape, and the first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the second via hole, and is electrically connected to the second plate of the capacitor through the seventh via hole.

[0274] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) is block-shaped, and the second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) is connected to the second region of the active layer of the sixth transistor (also the second region of the active layer of the seventh transistor) through a fourth via.

[0275] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode T73 of the seventh transistor is shaped like a zigzag line that extends at least partially along the second direction D2. The first electrode T73 of the seventh transistor is connected to the first region of the active layer of the seventh transistor via a fifth via. The orthographic projection of the first electrode T73 of the seventh transistor on the substrate partially overlaps with the orthographic projections of the first initial signal line, the reset signal line, and the first scan signal line on the substrate.

[0276] 22 and 23 , the first preliminary connection line CL1 has a line shape extending in the second direction D2 . The first preliminary connection line CL1 is connected to the first preliminary signal line through the eighth via hole.

[0277] In an exemplary embodiment, as shown in FIG. 22 and FIG. 23 , the orthographic projection of the first initial connection line CL1 on the substrate at least partially overlaps with the orthographic projection of the second plate of the capacitor on the substrate, and does not overlap with the orthographic projection of the reset signal line on the substrate.

[0278] In an exemplary embodiment, as shown in Figures 22 and 23, the second initial connection line CL2 includes a main signal line CL2A, a first signal connection portion CL2B, and a second signal connection portion CL2C. The main signal line CL2A is shaped like a line extending along the second direction D2. The first signal connection portion CL2B and the second signal connection portion CL2C are located on either side of the main signal line CL2A and are connected to the main signal line CL2A. The first signal connection portion CL2B and the second signal connection portion CL2C extend along the first direction D1. The main signal line CL2A is connected to the second initial signal line through a twelfth via.

[0279] In an exemplary embodiment, the first signal connection portion CL2B is an integrally formed structure with the first pole of the seventh transistor of two sub-pixels located in the same row between the signal main line and one of the adjacent first initial connection lines, and the second signal connection portion CL2C is an integrally formed structure with the first pole of the seventh transistor of two sub-pixels located in the same row between the signal main line and another adjacent first initial connection line.

[0280] In an exemplary embodiment, the orthographic projections of the first signal connection portion CL2B and the second signal connection portion CL2C on the substrate at least partially overlap with the orthographic projection of the second initial signal line on the substrate. Exemplarily, the orthographic projection of the second initial signal line on the substrate covers the orthographic projections of the first signal connection portion CL2B and the second signal connection portion CL2C on the substrate.

[0281] In an exemplary embodiment, the first preliminary connection lines CL1 and the second preliminary connection lines CL2 are alternately arranged along the first direction D1, that is, the second preliminary connection lines CL2 are located between the two first preliminary connection lines CL1. The center lines of the two first preliminary connection lines CL1 along the second direction D2 pass through the signal main lines of the second preliminary connection lines CL2.

[0282] (9) forming a first flat layer pattern, comprising: depositing an eighth insulating film on a substrate having the aforementioned pattern formed thereon, patterning the eighth insulating film through a patterning process to form an eighth insulating layer, coating a first flat film on the eighth insulating layer, patterning the first flat film through a patterning process to form a first flat layer pattern covering the aforementioned pattern, wherein the first flat layer is provided with a plurality of via patterns, as shown in FIG. 24 , which is a schematic diagram after the first flat layer pattern is formed.

[0283] In an exemplary embodiment, as shown in FIG. 24 , the plurality of via holes include at least thirteenth to fifteenth via holes V13 to V15 located in at least one sub-pixel.

[0284] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the eighth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the first electrode of the fourth transistor, and the thirteenth via hole V13 is configured to connect a subsequently formed data signal line to the first electrode of the fourth transistor through the via hole.

[0285] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the eighth insulating layer in the fourteenth via V14 is etched away to expose the surface of the first electrode of the fifth transistor, and the fourteenth via V14 is configured to connect a subsequently formed first power line to the first electrode of the fifth transistor through the via.

[0286] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the sixth insulating layer in the fifteenth via hole V15 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the fifteenth via hole V15 is configured to connect a subsequently formed connecting electrode to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the via hole.

[0287] (10) Forming a fifth conductive layer pattern includes: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film through a patterning process to form a fifth conductive layer pattern, as shown in FIG. 25 and FIG. 26 . FIG. 25 is a schematic diagram of the fifth conductive layer pattern, and FIG. 26 is a schematic diagram after the fifth conductive layer pattern is formed. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0288] In exemplary embodiments, as shown in FIG. 25 and FIG. 26 , the fifth conductive layer pattern may include at least a data signal line Data, a first power line VDD, a flat portion BL, and a connection electrode VL located at at least one sub-pixel.

[0289] In an exemplary embodiment, a plurality of data signal lines Data are arranged along a first direction D1 , and a plurality of first power lines VDD are arranged along the first direction D1 .

[0290] In an exemplary embodiment, the first power line VDD connected to the subpixel is located on a side of the data signal line Data connected to the subpixel that is closer to the subpixel in the next column. The first power lines VDD connected to adjacent subpixels are symmetrically arranged with respect to a virtual line along the second direction D2. The data signal lines Data connected to adjacent subpixels are symmetrically arranged with respect to the virtual line along the second direction D2.

[0291] In an exemplary embodiment, the data signal line Data and the first power line VDD connected to the subpixel are located on the same side of the connection electrode of the subpixel, and the data signal line Data is located on a side of the first power line VDD away from the connection electrode.

[0292] In exemplary embodiments, as shown in FIG. 25 and FIG. 26 , the shape of the data signal line Data may be a line shape extending at least partially along the second direction D2 .

[0293] 25 and 26 , the first power line VDD may be in the shape of a line extending at least partially along the second direction D2. For example, the first power line VDD may be in the shape of a zigzag line.

[0294] In an exemplary embodiment, as shown in Figures 25 and 26, the first power line VDD is connected to one of the adjacent power lines and is spaced apart from the other adjacent power line. Two data signal lines Data are disposed between the two spaced-apart first power lines. Alternatively, the first power lines connected to adjacent sub-pixels can be spaced apart.

[0295] In an exemplary embodiment, the orthographic projection of the signal main line of the second initial connection line on the substrate is located between the orthographic projections of two adjacent data signal lines on the substrate. The orthographic projection of the first initial connection line on the substrate is located between the orthographic projections of two adjacent data signal lines on the substrate.

[0296] In an exemplary embodiment, as shown in FIG. 25 and FIG. 26 , the flat portion BL is disposed between two adjacent first power lines VDD and is connected to the adjacent two first power lines VDD.

[0297] In an exemplary embodiment, as shown in FIG. 25 and FIG. 26 , the shape of the flat portion BL may be a polygon, and the polygon may be a square or other shapes.

[0298] In example embodiments, as shown in FIG. 25 and FIG. 26 , an orthographic projection of the flat portion BL on the substrate may at least partially overlap with an orthographic projection of the active layer of the first transistor and the active layer of the second transistor on the substrate.

[0299] In an exemplary embodiment, as shown in FIG. 25 and FIG. 26 , an orthographic projection of the flat portion BL on the substrate at least partially overlaps with orthographic projections of the reset signal line, the first scan signal line, and the second scan signal line on the substrate.

[0300] In an exemplary embodiment, as shown in Figures 25 and 26, a structure formed by first power lines connecting two adjacent columns of sub-pixels and two flat portions of adjacent rows of sub-pixels includes multiple annular regions, at least two of which have different shapes.

[0301] In an exemplary embodiment, the structure of the annular region may be a symmetrical structure or an asymmetrical structure. FIG. 25 and FIG. 26 illustrate the case where the structure of the annular region is a symmetrical structure.

[0302] In an exemplary embodiment, adjacent flat portions in the same row may be arranged symmetrically or asymmetrically, which may be determined according to the shape of the first electrode of the connected light emitting device. Figures 25 and 26 illustrate the example of adjacent flat portions in the same row being arranged symmetrically.

[0303] In an exemplary embodiment, as shown in FIG. 26 , the orthographic projection of the connection electrode on the substrate is located within an annular region formed by the first power lines of two adjacent columns of sub-pixels and two flat portions of adjacent rows of sub-pixels.

[0304] In an exemplary embodiment, as shown in Figures 25 and 26, the connection electrode VL may be in a block shape. The connection electrode is configured to be connected to the first electrode of a subsequently formed light emitting device. The shape of the connection electrode connected to the first electrode of different light emitting devices may be different.

[0305] In an exemplary embodiment, as shown in Figures 25 and 26, the data signal line Data is electrically connected to the first electrode of the fourth transistor through a thirteenth via hole. The first power line VDD is connected to the first electrode of the fifth transistor through a fourteenth via hole, and the connection electrode VL is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through a fifteenth via hole.

[0306] (10) forming a second planar layer pattern, comprising: coating a first planar film as shown in the figure on the substrate having the aforementioned pattern formed thereon, and patterning the second planar film through a patterning process to form a second planar layer pattern covering the aforementioned pattern.

[0307] At this point, the drive structure layer is prepared on the substrate. In a plane parallel to the display substrate, the drive structure layer may include a plurality of pixel circuits, and the pixel circuits are connected to the first scan signal line, the second scan signal line, the light emitting signal line, the first initial signal line, the second initial signal line, the reset signal line, the data signal line and the first power line. The drive structure layer may be arranged on the substrate. The drive structure layer may include a first insulating layer, a light shielding layer, a second insulating layer, a first semiconductor layer, a third insulating layer, a first conductive layer, a fourth insulating layer, a second conductive layer, a fifth insulating layer, a second semiconductor layer, a sixth insulating layer, a third conductive layer, a seventh insulating layer, a fourth conductive layer, an eighth insulating layer, a first planar layer, a fifth conductive layer and a second planar layer, which are sequentially arranged on the substrate.

[0308] In example embodiments, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0309] In one exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0310] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0311] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, the seventh insulating layer and the eighth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer.

[0312] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of an organic material such as resin.

[0313] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0314] (11) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer pattern may include: depositing a sixth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the sixth conductive film using a patterning process to form a sixth conductive layer disposed on the second planar layer, wherein the sixth conductive layer includes at least a plurality of first electrode patterns.

[0315] In an exemplary embodiment, the sixth conductive layer pattern may include: a plurality of first electrode patterns. The plurality of first electrode patterns may include a first electrode of a first light-emitting device, a first electrode of a second light-emitting device, a first electrode of a third light-emitting device, and a first electrode of a fourth light-emitting device, wherein the first electrode of the first light-emitting device is located in a red sub-pixel emitting red light, the first electrode of the second light-emitting device may be located in a blue sub-pixel emitting blue light, the first electrode of the third light-emitting device may be located in a first green sub-pixel emitting green light, and the first electrode of the fourth light-emitting device may be located in a second green sub-pixel emitting green light.

[0316] In an exemplary embodiment, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along the second direction, and the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the second direction. Alternatively, the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along the first direction, and the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the first direction.

[0317] In an exemplary embodiment, the first electrode of the first light emitting device, the first electrode of the second light emitting device, the first electrode of the third light emitting device, and the first electrode of the fourth light emitting device may be connected to the connection electrode of the sub-pixel through a via hole exposing the connection electrode of the sub-pixel.

[0318] In an exemplary embodiment, the shapes and areas of the first electrodes of the four sub-pixels in one pixel unit may be the same, or may be different.

[0319] In an exemplary embodiment, at least one of the first electrodes of the first, second, third, and fourth light emitting devices may include an anode body portion and an anode connection portion connected to each other, the anode connection portion being connected to the connection electrode.

[0320] In an exemplary embodiment, the first electrode of a first light-emitting device may include a first anode body portion and a first anode connecting portion connected to each other. The first anode body portion may be rectangular, with arc-shaped chamfers at the corners of the rectangle, and the first anode connecting portion may be in the shape of a strip. In an exemplary embodiment, the first electrode of a second light-emitting device may include a second anode body portion and a second anode connecting portion connected to each other. The second anode body portion may be rectangular, with arc-shaped chamfers at the corners of the rectangle, and the second anode connecting portion may be in the shape of a strip. In an exemplary embodiment, the first electrode of a third light-emitting device may include a third anode body portion and a third anode connecting portion connected to each other. The third anode body portion may be rectangular, with arc-shaped chamfers at the corners of the rectangle, and the third anode connecting portion may be in the shape of a strip. In an exemplary embodiment, the first electrode of a fourth light-emitting device may include a fourth anode body portion and a fourth anode connecting portion connected to each other. The fourth anode body portion may be rectangular, with arc-shaped chamfers at the corners of the rectangle, and the fourth anode connecting portion may be in the shape of a strip.

[0321] In an exemplary embodiment, the sixth conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0322] (12) Forming a cathode conductive layer pattern. In an exemplary embodiment, forming the cathode conductive layer may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, depositing the pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film through a patterning process to form a pixel definition layer pattern exposing the sixth conductive layer pattern, coating an organic light-emitting material on the substrate on which the pixel definition layer pattern is formed, patterning the organic light-emitting material through a patterning process to form an organic structure layer pattern, depositing a cathode conductive film on the substrate on which the organic material layer pattern is formed, and patterning the cathode conductive film through a patterning process to form the cathode conductive layer.

[0323] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0324] In an exemplary embodiment, the organic structure layer may include at least an organic light emitting layer of a light emitting device.

[0325] In an exemplary embodiment, the cathode conductive layer may include at least cathodes of a plurality of light emitting devices.

[0326] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy thereof, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0327] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0328] An embodiment of the present disclosure further provides a display device, including: a display substrate.

[0329] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0330] In an exemplary embodiment, the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0331] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0332] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0333] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, include: A substrate and a plurality of sub-pixels, a plurality of first signal lines and a plurality of second signal lines arranged on the substrate, wherein the sub-pixels include: a pixel circuit, the pixel circuit is electrically connected to the first signal line, the first signal line includes at least one initial signal line, and the second signal line includes at least one initial connection line; the initial signal line extends along a first direction, the initial connection line extends along a second direction, and the first direction intersects with the second direction; The at least one initial signal line corresponds to the at least one initial connection line in a one-to-one manner, and the initial signal line is electrically connected to the corresponding initial connection line.

2. The display substrate according to claim 1, in, The at least one initial signal line includes: a first initial signal line and a second initial signal line, wherein the second initial signal line is located at a side of the first initial signal line away from the substrate.

3. The display substrate according to claim 2, further comprising: include: a plurality of reset signal lines, wherein at least a portion of the reset signal lines extend along a first direction; The orthographic projection of the first initial signal line on the substrate is located between the orthographic projection of the second initial signal line on the substrate and the orthographic projection of the reset signal line on the substrate, and does not overlap with the orthographic projection of the second initial signal line on the substrate and the orthographic projection of the reset signal line on the substrate.

4. The display substrate according to claim 2 or 3, further comprising: include: a plurality of light-emitting signal lines, wherein at least a portion of the light-emitting signal lines extend along a first direction; The orthographic projection of the second initial signal line on the substrate is between and does not overlap with the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the luminescent signal line on the substrate.

5. The display substrate according to claim 4, in, The at least one initial connection line comprises: a first initial connection line and a second initial connection line, the first initial connection line and the second initial connection line are arranged in the same layer, a plurality of first initial connection lines are arranged along a first direction, and a plurality of second initial connection lines are arranged along the first direction; The first initial connection lines and the second initial connection lines are alternately arranged along the first direction, and the midlines of the two first initial connection lines along the second direction pass through the signal main line of the second initial connection line located between the two first initial connection lines; The first initial connection line is electrically connected to the first initial signal line through a via hole, and the second initial connection line is electrically connected to the second initial signal line through a via hole.

6. The display substrate according to claim 5, in, The pixel circuit comprises: a capacitor, the capacitor comprises: a first plate and a second plate, the second plate of the capacitor is located on a side of the first plate of the capacitor away from the substrate; The orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the second plate of the capacitor on the substrate.

7. The display substrate according to claim 6, in, The second initial connection line includes: a signal main line, a plurality of first signal connection parts and a plurality of second signal connection parts; the signal main line extends along the second direction, the first signal connection part and the second signal connection part extend along the first direction, the first signal connection part and the second signal connection part are respectively connected to the signal main line, and the signal main line is connected to the second initial signal line; The first signal connection portion and the second signal connection portion are respectively located on both sides of the signal main line and are symmetrically arranged relative to the signal main line.

8. The display substrate according to claim 7, in, The orthographic projection of the signal main line on the substrate at least partially overlaps with the orthographic projection of the second plate of the capacitor on the substrate.

9. The display substrate according to claim 7, in, The orthographic projections of the first signal connection portion and the second signal connection portion on the substrate at least partially overlap with the orthographic projection of the second initial signal line on the substrate, and do not overlap with the orthographic projection of the reset signal line on the substrate.

10. The display substrate according to claim 1, in, The pixel structures of the pixel circuits of adjacent sub-pixels in the same row are symmetrically arranged along a virtual straight line extending along the second direction.

11. The display substrate according to claim 7, further comprising: include: a plurality of data signal lines, wherein the data signal lines extend along the second direction, and the data signal lines connecting adjacent sub-pixels are symmetrically arranged with respect to a virtual straight line extending along the second direction; The orthographic projection of the first signal connection line on the substrate or the orthographic projection of the signal main body line of the second signal connection line on the substrate is located between the orthographic projections of two adjacent data signal lines on the substrate.

12. The display substrate according to claim 7, further comprising: include: a plurality of first scanning signal lines, wherein at least a portion of the first scanning signal lines extends along a first direction, The orthographic projection of the reset signal line on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the first initial signal line on the substrate; The reset signal line comprises: a first sub-reset signal line and a second sub-reset signal line electrically connected to each other; The first sub-reset signal line is arranged on the same layer as the first initial signal line, the second sub-reset signal line is arranged on the same layer as the second initial signal line, and the orthographic projection of the first sub-reset signal line on the substrate at least partially overlaps with the orthographic projection of the second sub-reset signal line on the substrate.

13. The display substrate according to claim 12, further comprising: include: a plurality of second scanning signal lines, wherein at least a portion of the second scanning signal lines extend along the first direction; The orthographic projection of the second scanning signal line on the substrate is located between the orthographic projections of the first scanning signal line and the light emitting signal line on the substrate; The second scanning signal line comprises: a first sub-scanning signal line and a second sub-scanning signal line electrically connected to each other; The first sub-scanning signal line is arranged on the same layer as the first initial signal line, the second sub-scanning signal line is arranged on the same layer as the second initial signal line, and the orthographic projection of the first sub-scanning signal line on the substrate at least partially overlaps with the orthographic projection of the second sub-scanning signal line on the substrate.

14. The display substrate according to claim 1 or 13, in, Also includes: A plurality of first power supply lines and a plurality of flat portions, the sub-pixel further comprises: a light emitting device, the light emitting device comprises a first electrode, the pixel circuit comprises: an oxide transistor; The flat portion is disposed between adjacent first power lines and connected to the adjacent first power lines; The orthographic projection of the flat portion on the substrate at least partially overlaps with the orthographic projections of the reset signal line, the first scan signal line, the second scan signal line, the active layer of the oxide transistor and the first electrode of the light emitting device on the substrate; An orthographic projection of the at least one flat portion on the substrate also at least partially overlaps with an orthographic projection of the first initial signal line on the substrate.

15. The display substrate according to claim 14, in, A plurality of annular areas are formed between the plurality of first power lines and the plurality of flat portions; At least two of the annular regions have different shapes.

16. The display substrate according to claim 14, include: The display area and the non-display area further include: a third signal line located in the non-display area, the sub-pixel, the first signal line and the second signal line are located in the display area, the third signal line includes: at least one initial power supply line, the initial power supply line at least partially extends along the second direction; At least one initial power supply line corresponds to at least one initial signal line one by one, and the initial power supply line is electrically connected to the corresponding initial signal line.

17. The display substrate according to claim 16, in, The display area comprises: a first side and a second side arranged opposite to each other, and the third signal line is located on at least one of the first side and the second side of the display area.

18. The display substrate according to claim 15, further comprising: include: A driving structure layer stacked sequentially on the substrate; The driving structure layer comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked in sequence; The first conductive layer at least includes: a first scanning signal line, a light emitting signal line, and a first plate of a capacitor located in at least one sub-pixel; The second conductive layer at least includes: a first initial signal line, a first sub-reset signal line of the reset signal line, a first sub-scanning signal line of the second scan signal line, and a second plate of a capacitor located at at least one sub-pixel; The third conductive layer at least includes: a second sub-reset signal line of the reset signal line, a second sub-scanning signal line of the second scan signal line, and a second initial signal line; The fourth conductive layer at least includes: a first initial connection line and a second initial connection line; The fifth conductive layer at least includes: a data signal line, a first power line and a flat portion.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

Images