Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a driving back plate (BP), first electrodes (ANO), a pixel definition layer (PDL), a light-emitting layer (OL) and a second electrode (CAT), wherein the first electrodes (ANO) and the pixel definition layer (PDL) are arranged on one side surface of the driving back plate (BP); the pixel definition layer (PDL) is provided with pixel openings (PH) for exposing the first electrodes and separation grooves (SES) located between two adjacent pixel openings (PH), and the boundaries of the pixel openings (PH) are located within the boundaries of the exposed first electrodes (ANO); a first cut-off groove (CU1) is formed in the side wall of the pixel opening (PH), and a second cut-off groove (CU2) is formed in the side wall of the separation groove (SES); the first cut-off groove (CU1) is at least partially positioned on one side of the second cut-off groove (CU2) far away from the driving back plate (BP); the light-emitting layer (OL) covers the pixel definition layer (PDL) and the first electrode (ANO); the second electrode (CAT) covers the light emitting layer (OL).

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to PCT international application No. PCT / CN2021 / 133886, filed on November 29, 2021, entitled “Display Substrate.” The entire contents of this PCT international application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] With the development of display technology, display panels have been widely used in various electronic devices such as mobile phones to realize image display and touch operation. Among them, OLED (Organic Light-Emitting Diode) display panels are relatively common. However, existing display panels have the problem of color cross-talk.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] The present disclosure provides a display panel and a display device.

[0008] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0009] Driver backplane;

[0010] A plurality of first electrodes are arrayed and distributed on one side of the driving back plate;

[0011] a pixel definition layer disposed on the same side of the driving backplane as the first electrode and having pixel openings for exposing each of the first electrodes and a separation groove between two adjacent pixel openings, wherein the boundaries of the pixel openings are located within the boundaries of the exposed first electrodes; a first truncation groove is disposed on a sidewall of the pixel opening, and a second truncation groove is disposed on a sidewall of the separation groove; the first truncation groove is at least partially located on a side of the second truncation groove away from the driving backplane;

[0012] a light-emitting layer covering the pixel definition layer and the first electrode;

[0013] The second electrode covers the light-emitting layer.

[0014] In an exemplary embodiment of the present disclosure, the pixel definition layer includes an etch stop layer, a first definition layer, and a second definition layer sequentially stacked in a direction away from the driving backplane;

[0015] The pixel opening passes through the etch stop layer, the first definition layer, and the second definition layer; the separation groove passes through the first definition layer and the second definition layer, and exposes the etch stop layer;

[0016] The first truncation groove and the second truncation groove are located in the first definition layer.

[0017] In an exemplary embodiment of the present disclosure, the etch stop layer includes:

[0018] a buffer layer, at least partially disposed on a surface of the first electrode away from the driving backplane;

[0019] The barrier layer is stacked on the surface of the buffer layer away from the driving back plate; and the first definition layer is stacked on the surface of the barrier layer away from the driving back plate.

[0020] In an exemplary embodiment of the present disclosure, the pixel opening includes a first segment located in the etch stop layer and a second segment located in the second definition layer, and the boundary of the positive projection of the second segment on the driving backplane is surrounded by the boundary of the positive projection of the first segment on the driving backplane.

[0021] In an exemplary embodiment of the present disclosure, a distance between a boundary of an orthographic projection of the second segment on the driving backplane and a boundary of an orthographic projection of the first segment on the driving backplane is not greater than 0.2 μm and not less than 0.06 μm.

[0022] In an exemplary embodiment of the present disclosure, the distance between the portions of the two adjacent pixel openings located in the first segment is not greater than 1.9 μm and not less than 1.1 μm;

[0023] The distance between the two adjacent pixel openings located in the second segment is not greater than 1.6 μm and not less than 0.9 μm.

[0024] In an exemplary embodiment of the present disclosure, the length of the sidewalls of the first truncation groove away from the driving back plate is not less than 0.03 μm and not more than 0.05 μm.

[0025] In an exemplary embodiment of the present disclosure, the length of the sidewalls of the second truncation groove away from the driving back plate is not less than 0.07 μm and not more than 0.1 μm.

[0026] In an exemplary embodiment of the present disclosure, the pixel definition layer further includes:

[0027] The filling layer is provided on the same side of the driving back plate as the first electrodes and separates the first electrodes; a portion of the etching stop layer is stacked on a surface of the filling layer away from the driving back plate.

[0028] In an exemplary embodiment of the present disclosure, the surface of the filling layer away from the driving back plate is located on a side of the first electrode away from the driving back plate that is close to the driving back plate;

[0029] The pixel definition layer includes an edge portion, a middle portion and a connecting portion. The edge portion is located on the surface of the first electrode away from the driving backplane; the middle portion is located between two adjacent first electrodes; and the connecting portion connects the edge portion and the middle portion.

[0030] In an exemplary embodiment of the present disclosure, the sidewall of the separation groove is a slope that expands in a direction away from the driving back plate.

[0031] In an exemplary embodiment of the present disclosure, a bottom surface of the first truncation groove is a slope surface whose depth decreases in a direction away from the driving back plate.

[0032] The bottom surface of the second truncation groove is a sloped surface whose depth decreases in a direction away from the driving back plate.

[0033] In an exemplary embodiment of the present disclosure, a slope of the connecting portion is smaller than slopes of bottom surfaces of the first and second truncation grooves.

[0034] In an exemplary embodiment of the present disclosure, the orthographic projection of the first truncation groove on the driving backplate is located within the orthographic projection of the first electrode on the driving backplate.

[0035] In an exemplary embodiment of the present disclosure, the width of at least a portion of the second truncation groove is greater than the width of the first truncation groove.

[0036] In an exemplary embodiment of the present disclosure, a depth of the second truncation groove is smaller than a depth of the first truncation groove.

[0037] In an exemplary embodiment of the present disclosure, an angle between a side wall of the second truncation groove away from the driving back plate and a surface of the driving back plate on which the first electrode is provided is greater than an angle between a side wall of the first truncation groove away from the driving back plate and a surface of the driving back plate on which the first electrode is provided.

[0038] In an exemplary embodiment of the present disclosure, a distance between the first truncation groove and the second truncation groove perpendicular to the driving backplate is greater than 0 and smaller than a width of one of the first truncation groove and the second truncation groove.

[0039] In an exemplary embodiment of the present disclosure, half of the difference between the distance between two adjacent pixel openings and the width of the separation groove is greater than the width of the separation groove.

[0040] In an exemplary embodiment of the present disclosure, the first electrode includes:

[0041] A first conductive layer is provided on a side surface of the driving back plate;

[0042] a second conductive layer, stacked on a surface of the first conductive layer away from the driving backplane;

[0043] The first conductive protection layer covers the surface of the second conductive layer away from the driving back plate, and the side walls of the second conductive layer and the first conductive layer.

[0044] In an exemplary embodiment of the present disclosure, the first electrode further includes a second conductive protection layer covering the first conductive protection layer.

[0045] In an exemplary embodiment of the present disclosure, a first groove is provided on the surface of the driving back plate where the first electrode is provided, and a second groove is provided at the bottom of the first groove;

[0046] The first conductive protection layer and the second conductive protection layer cover the sidewalls and the bottom surface of the first groove in an area outside the second groove.

[0047] In an exemplary embodiment of the present disclosure, a width of the separation groove is equal to a width of the second groove.

[0048] In an exemplary embodiment of the present disclosure, the width of the first groove is not less than 0.5 μm and not more than 1.2 μm; the width of the second groove is not less than 0.2 μm and not more than 0.9 μm.

[0049] In an exemplary embodiment of the present disclosure, the light-emitting layer includes a hole injection layer and multiple light-emitting sublayers, each of the light-emitting sublayers is arranged on a side of the hole injection layer away from the driving backplane in a direction away from the driving backplane; two adjacent light-emitting sublayers are connected in series via a charge generation layer; the light-emitting sublayer includes a hole transport layer, at least one light-emitting material layer, and an electron transport layer arranged in a direction away from the driving backplane;

[0050] The hole injection layer is disconnected at the first truncation groove;

[0051] At least one of the charge generation layers is disconnected at the second cutoff groove.

[0052] In an exemplary embodiment of the present disclosure, a sidewall of at least one of the pixel openings is provided with a plurality of first truncation grooves distributed along the circumferential direction; and at least two of the first truncation grooves of the same pixel opening have different widths.

[0053] In an exemplary embodiment of the present disclosure, the number of the light-emitting sublayers is three, and the number of the charge generation layers is two;

[0054] In the two first truncation grooves of different widths in the same pixel opening, a width difference between the two first truncation grooves is 0.8 to 1.2 times a width difference between the first truncation groove and the second truncation groove.

[0055] In an exemplary embodiment of the present disclosure, the number of the light-emitting sublayers is two, and the number of the charge generation layer is one; the light-emitting sublayer farther from the driving backplane includes a light-emitting material layer that emits blue light;

[0056] The distance between the blue light emitting material layer and the charge generation layer in the pixel opening is greater than the distance between them in the pixel definition layer.

[0057] In an exemplary embodiment of the present disclosure, the second electrode forms a flat portion in a region corresponding to the first electrode, and forms a recessed portion in a region corresponding to the separation groove, and the recessed portion smoothly transitions to the flat portion.

[0058] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0059] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0061] FIG1 is a partial cross-sectional view of an embodiment of a display panel according to the present disclosure.

[0062] FIG2 is a partial cross-sectional view of a driving backplane, a first electrode, and a pixel definition layer in one embodiment of a display panel of the present disclosure.

[0063] FIG3 is a partial cross-sectional view of a driving backplane and a first electrode in one embodiment of a display panel disclosed herein.

[0064] FIG4 is a partial cross-sectional view of a driving backplane in one embodiment of a display panel disclosed herein.

[0065] FIG5 is a partial cross-sectional view of a driving backplane, a first electrode, and a pixel definition layer in another embodiment of a display panel disclosed herein.

[0066] FIG6 is a partial cross-sectional view of a first embodiment of the display panel disclosed herein.

[0067] FIG. 7 is a partial cross-sectional view of a second embodiment of the display panel disclosed herein.

[0068] FIG8 is a partial cross-sectional view of a driving backplane, a first electrode, and a pixel definition layer in one embodiment of a display panel of the present disclosure.

[0069] FIG9 is a partial cross-sectional view of a driving backplane, a first electrode, and a pixel definition layer in another embodiment of a display panel of the present disclosure.

[0070] FIG10 is a partial cross-sectional view of a driving backplane, a first electrode, and a pixel definition layer in yet another embodiment of a display panel of the present disclosure.

[0071] FIG11 is a schematic diagram showing a light-emitting unit having two light-emitting sub-layers in an embodiment of a display panel disclosed herein.

[0072] FIG12 is a schematic diagram showing a light-emitting unit having three light-emitting sub-layers in an embodiment of a display panel disclosed herein.

[0073] FIG13 is a partial top view of an embodiment of a display panel disclosed herein. DETAILED DESCRIPTION

[0074] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0075] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0076] Any "slope" in this application is a straight line in a cross section perpendicular to the driver backplane. The slope of the "slope" (for example, α and β in Figure 5) can be defined as the angle between the straight line or its extension and the surface on which the slope is located, which is the angle close to the first electrode surrounded by the slope. It should be noted that, considering the influence of process errors, the above-mentioned straight line may not be an absolute straight line, but may be a curve extending roughly along the straight line. The curve may have multiple tangents, each of which has an angle with the surface on which the slope is located. The slope of the curve may be the maximum angle among the angles, or the average of the angles.

[0077] In the related art, the silicon-based OLED display panel includes a driving backplane and a light-emitting functional layer, wherein: the light-emitting layer is arranged on one side of the driving backplane and includes a plurality of light-emitting units. The light-emitting unit may include a first electrode (anode), a light-emitting layer, and a second electrode (cathode) stacked in sequence in a direction away from the driving backplane. By applying an electrical signal to the first electrode and the second electrode, the light-emitting layer can be driven to emit light. The specific light-emitting principle of the light-emitting device will not be described in detail here.

[0078] In addition, the light-emitting layer of each light-emitting unit can be directly evaporated using a fine mask (FMM), and the light-emitting layer of each light-emitting unit is spaced apart and emits light independently, achieving color display. However, due to the limitations of the fine mask manufacturing process, it is difficult to achieve a high PPI (pixel density). Therefore, color display can also be achieved by combining monochromatic light or white light with a color filter. That is, each light-emitting unit shares the same continuous light-emitting layer, which can emit white light or other monochromatic light. The color filter layer has multiple filters that correspond one to one with the light-emitting units. A filter and the corresponding light-emitting unit can constitute a sub-pixel, and multiple sub-pixels constitute a pixel. Different filters can transmit different colors of light, so that different sub-pixels can emit different colors. The same pixel can include multiple sub-pixels of different colors. For example, a pixel can include three sub-pixels that emit red, green, and blue colors. In this way, color display can be achieved through multiple pixels.

[0079] However, if the light-emitting layer is a continuous, monolithic structure, leakage current can easily occur between one light-emitting unit and its surrounding light-emitting units, leading to color crosstalk. Each light-emitting unit may include multiple light-emitting devices connected in series. The light-emitting devices in the same light-emitting unit share a first electrode and a second electrode. Multiple light-emitting sublayers are located between the first and second electrodes, and at least two adjacent light-emitting sublayers can be connected in series via a charge generation layer. For example, when a light-emitting unit in the red filter portion of the color filter layer emits light, leakage current can also cause the light-emitting unit in the green filter portion of the color filter layer to emit light, reducing the purity of the light emitted by a single pixel and the color gamut of the entire display panel.

[0080] The present disclosure provides a display panel, as shown in FIG1 , which may include a driving backplane BP, a first electrode ANO, a pixel definition layer PDL, a light-emitting layer OL, and a second electrode CAT, wherein:

[0081] The first electrode ANO is provided on a side of the driving backplane BP. There are multiple first electrodes ANO, which are spaced apart. The pixel definition layer PDL and the first electrode ANO are provided on the same side of the driving backplane BP. The pixel definition layer PDL is provided with a pixel opening PH that exposes each first electrode ANO, and the boundary of the pixel opening PH is located within the boundary of the exposed first electrode ANO. At the same time, the pixel definition layer PDL is also provided with a separation groove SES that separates each pixel opening PH. The sidewalls of the pixel opening PH are provided with a first truncation groove CU1, and the sidewalls of the separation groove SES are provided with a second truncation groove CU2; the first truncation groove CU1 is at least partially located on the side of the second truncation groove CU2 away from the driving backplane BP. The light-emitting layer OL covers the pixel definition layer PDL and the first electrode ANO. The second electrode CAT covers the light-emitting layer OL.

[0082] In the display panel of the present embodiment, any first electrode ANO and its corresponding light-emitting layer OL and second electrode CAT can form a light-emitting unit LD. The pixel definition layer PDL can separate and define the range of each light-emitting unit LD. At the same time, due to the presence of the first truncation groove CU1 and the second truncation groove CU2, at least part of the film layer of the light-emitting layer OL can be disconnected at the first truncation groove CU1 and the second truncation groove CU2, thereby reducing the risk of leakage between adjacent light-emitting units LD and improving color crosstalk.

[0083] Since the first truncation groove CU1 is at least partially located on the side of the second truncation groove CU2 away from the driving backplane BP, the first truncation groove CU1 is at least partially higher than the second truncation groove CU2, wherein the second truncation groove CU2 can cut off the film layer in the light-emitting layer OL that is closer to the driving backplane BP. In addition to cutting off the film layer in the light-emitting layer OL that is closer to the driving backplane BP, the first truncation groove CU1 can also cut off the film layer farther away. Therefore, the risk of mutual leakage between adjacent light-emitting units LD can be further reduced by the first truncation groove CU1 and the second truncation groove CU2, thereby improving cross-color.

[0084] In addition, since the film layer in the light-emitting layer OL that is farther away from the driving backplane BP can be cut off through the second truncation groove CU2 that is closer to the driving backplane BP, there is no need to increase the thickness of the pixel definition layer PDL and the widths of the first truncation groove CU1 and the second truncation groove CU2, the puncture phenomenon caused by the second electrode CAT at the side walls of the pixel opening PH and the separation groove SES due to the increase in the thickness and width can be avoided, thereby avoiding the problem of excessive voltage drop in the second electrode CAT caused by the second puncture phenomenon.

[0085] The structure of the display panel of the present disclosure to realize the display function is described in detail below:

[0086] The display panel may include a display area and a peripheral area. The peripheral area is located outside the display area and may be arranged around the display area. The driving backplane BP is used to form a driving circuit that drives the light-emitting unit LD to emit light. The driving circuit may include a pixel circuit and a peripheral circuit, wherein:

[0087] The number of pixel circuits and light-emitting units LD can be multiple, and at least a part of the pixel circuits is located in the display area. The pixel circuit can be a 2T1C, 4T1C or other pixel circuits. As long as it can drive the light-emitting unit LD to emit light, its structure is not particularly limited here. The number of pixel circuits is the same as the number of first electrodes ANO, and is connected to the first electrode ANO in a one-to-one correspondence so as to control each light-emitting unit LD to emit light. Among them, nTmC means that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). Of course, the same pixel circuit can also drive multiple light-emitting units LD.

[0088] The peripheral circuit is located in the peripheral region and is connected to the pixel circuit. The peripheral circuit may include a light-emitting control circuit, a gate drive circuit, a source drive circuit, and the like. Furthermore, the peripheral circuit may include a power supply circuit connected to the second electrode CAT for inputting a power supply signal to the second electrode CAT. The peripheral circuit may input a signal to the first electrode ANO and the second electrode CAT through the pixel circuit, thereby causing the light-emitting unit LD to emit light.

[0089] In some embodiments of the present disclosure, as shown in FIG1 , the driving backplane BP may include a substrate SU, which may be a silicon substrate. The aforementioned driving circuit may be formed on the silicon substrate through a semiconductor process. For example, both the pixel circuit and the peripheral circuit may include multiple transistors. A well region WL may be formed in the silicon substrate through a doping process. The well region WL may have two doped regions DR spaced apart. Taking one well region WL as an example: a gate GATE is provided on one side of the driving backplane BP, and the orthographic projection of the gate GATE on the driving backplane BP is located between the two doped regions DR. The well region WL and the gate GATE may form a transistor. The doped regions DR of the well region WL are respectively the first and second poles of the transistor, and the well region WL between the two doped regions DR is the channel region of the transistor.

[0090] The driving backplane BP may further include at least one routing layer TL and a planar layer PLN. The routing layer TL is provided on one side of the substrate SU. The planar layer PLN covers the routing layer TL. At least one routing layer TL is connected to each doping region DR.

[0091] For example, as shown in FIG1 , there are two trace layers TL, which are located within the planar layer PLN. For example, the trace layer TL includes a first trace layer TL1 and a second trace layer TL2. The first trace layer TL1 is located on one side of the substrate SU, with a portion of the planar layer PLN disposed between the first trace layer TL1 and the substrate SU. The second trace layer TL2 is located on a side of the first trace layer TL1 away from the substrate SU, separated from the first trace layer TL1 by a portion of the planar layer PLN, and at least a portion of the second trace layer TL2 is connected to the first trace layer TL1.

[0092] Each trace layer TL can be formed by a sputtering process. The material of the planar layer PLN can be silicon oxide, silicon oxynitride or silicon nitride, and formed layer by layer through multiple deposition and polishing processes. In other words, the planar layer PLN can be formed by stacking multiple insulating film layers.

[0093] As shown in Figure 1 , the array of light-emitting units LD is distributed on one side of the driver backplane BP. For example, each light-emitting unit LD is located on the surface of the planar layer PLN away from the substrate SU. Each light-emitting unit LD may include a first electrode ANO, a second electrode CAT, and a light-emitting layer OL located between the first electrode ANO and the second electrode CAT. Both the first electrode ANO and the second electrode CAT can be connected to the trace layer TL. The driver backplane BP applies a drive signal to the first electrode ANO and a power signal to the second electrode CAT, thereby driving the light-emitting layer OL to emit light.

[0094] In order to achieve color display, each light-emitting unit LD can emit light of the same color, and cooperate with the color filter layer located on the side of the second electrode CAT away from the driving backplane BP to achieve color display. The embodiment of the present disclosure is explained using this color display solution as an example.

[0095] In some embodiments of the present disclosure, as shown in FIG1 , a plurality of light emitting units LD may be formed by a first electrode ANO, a pixel definition layer PDL, a light emitting layer OL, and a second electrode CAT, wherein:

[0096] The first electrode ANO is disposed on a side of the driving backplane BP, for example, on a surface of the planar layer PLN away from the substrate SU. Each first electrode ANO is located in the display area and connected to a pixel circuit, one first electrode ANO connected to one pixel circuit.

[0097] The first electrode ANO may be a single-layer or multi-layer structure, and its material is not particularly limited. As shown in Figures 1 and 3, in some embodiments of the present disclosure, the first electrode ANO may include a first conductive layer AL1, a second conductive layer AL2, and a first conductive protection layer AL3, wherein:

[0098] A first conductive layer AL1 is provided on the backplate BP. For example, the first conductive layer AL1 is provided on the surface of the planar layer PLN away from the substrate SU. The first conductive layer AL1 is made of a conductive material such as a metal or metal oxide, for example, titanium or titanium nitride. A second conductive layer AL2 is provided on the surface of the first conductive layer AL1 away from the driving backplate BP. Its material has a lower resistivity than the first conductive layer AL1. The second conductive layer AL2 can be made of a metal such as aluminum or silver, or a conductive material such as a metal oxide.

[0099] As shown in Figures 1 and 3, the first conductive protection layer AL3 covers the surface of the second conductive layer AL2 away from the driving backplate BP. It also covers the sidewalls of the second conductive layer AL2 and the first conductive layer AL1. In other words, the first conductive protection layer AL3 extends from the surface of the second conductive layer AL2 away from the driving backplate BP to the driving backplate BP, thereby covering the entire structure of the first conductive layer AL1 and the second conductive layer AL2, preventing corrosion or other damage to the second conductive layer AL2 during subsequent processing. The first conductive protection layer AL3 can be made of a metal or metal oxide, such as titanium or titanium nitride, and can be the same material as or different from the first conductive layer AL1.

[0100] Furthermore, as shown in Figures 1 and 3, the first electrode ANO may also include a second conductive protective layer AL4, which may cover the first conductive protective layer AL3, and the second conductive protective layer AL4 may be made of transparent conductive materials such as ITO (indium tin oxide) to further prevent subsequent processes from corroding or otherwise damaging the second conductive layer AL2.

[0101] As shown in Figures 1, 3, and 4, when forming the first conductive layer AL1 to the second conductive protection layer AL4 of the first electrode ANO, the first conductive layer AL1 and the second conductive layer AL2 can be sequentially formed on the driving backplate BP through a photolithography process. During this process, due to the etching of the first conductive layer AL1 and the second conductive layer AL2, a first groove FL1 can be formed on the driving backplate BP. For example, the first groove FL1 can be formed on the planar layer PLN. After the second conductive layer AL2 is formed, the first conductive protection layer AL3 and the second conductive protection layer AL4 can be sequentially formed through a photolithography process. During this process, due to the etching of the first conductive protection layer AL3 and the second conductive protection layer AL4, the bottom of the first groove FL1 can be further etched to form a second groove FL2, thereby patterning the first conductive protection layer AL3 and the second conductive protection layer AL4 to form the spaced first electrode ANO. The second groove FL2 is smaller than the bottom surface of the first groove FL1, and the first conductive protection layer AL3 and the second conductive protection layer AL4 both extend to the area of ​​the bottom surface of the first groove FL1 where the second groove FL2 is not set, mainly to ensure that the first conductive protection layer AL3 and the second conductive protection layer AL4 can cover the side walls of the second conductive layer AL2.

[0102] In some embodiments of the present disclosure, as shown in FIG. 2 and FIG. 4 , the width d1 of the first groove FL1 is not less than 0.5 μm and not more than 1.2 μm. For example, the width d1 of the first groove FL1 may be 0.5 μm, 0.8 μm, 1.1 μm, 1.2 μm, etc.

[0103] As shown in FIG. 2 and FIG. 4 , the width d2 of the second groove FL2 is not less than 0.2 μm and not more than 0.9 μm. For example, the width d2 of the second groove FL2 may be 0.2 μm, 0.5 μm, 0.8 μm, 0.9 μm, etc.

[0104] The width d4 of the separation groove SES may be equal to the width d2 of the second groove FL2. Accordingly, the width d4 of the separation groove SES may also be not less than 0.2 μm and not more than 0.9 μm.

[0105] In some embodiments of the present disclosure, the first electrode ANO may include only a first conductive layer AL1, a second conductive layer AL2 and a first conductive protective layer AL3, and the corrosion resistance of the first conductive protective layer AL3 is higher than that of the conductive material of the second conductive layer AL2. For example, the material of the second conductive layer AL2 is aluminum, and the material of the first conductive protective layer AL3 is indium tin oxide.

[0106] In some embodiments of the present disclosure, the first electrode ANO may include a first conductive layer AL1 to a second conductive protective layer AL4, but the second conductive protective layer AL4 may be stacked on the surface of the second conductive layer AL2 away from the driving backplane BP without covering the side walls of the second conductive layer AL2 and the first conductive layer AL1, and the second conductive protective layer AL4 covers the side walls of the first conductive layer AL1 to the first conductive protective layer AL3.

[0107] As shown in Figures 1 and 2 , the pixel definition layer PDL and the first electrodes ANO are disposed on the same surface of the driving backplane BP. For example, the pixel definition layer PDL is located on a surface of the planar layer PLN away from the substrate SU, and the pixel definition layer PDL exposes each first electrode ANO. Specifically, the pixel definition layer PDL may have a plurality of pixel openings PH that expose each first electrode ANO.

[0108] The positive projection of any pixel opening PH on the driving backplane BP can be located within the exposed first electrode ANO, that is, the pixel opening PH is not larger than the exposed first electrode ANO. For example, the boundary of the pixel opening PH is located on the inner side of the boundary of the exposed first electrode ANO, that is, the area of ​​the pixel opening PH is smaller than the area of ​​the exposed first electrode ANO, so that the pixel definition layer PDL covers the edge of the first electrode ANO.

[0109] As shown in FIG13 , the shape of the pixel opening PH can be a polygon such as a rectangle, a pentagon, or a hexagon, but is not necessarily a regular polygon. The shape of the pixel opening PH can also be other shapes such as an ellipse, which is not particularly limited here.

[0110] As shown in Figure 1 , the light-emitting layer OL covers the pixel definition layer PDL and the first electrode ANO. The area where the light-emitting layer OL overlaps the first electrode ANO forms a light-emitting unit LD. In other words, each light-emitting unit LD can share the same light-emitting layer OL, while the portions of the light-emitting layer OL overlapping different first electrodes ANO belong to different light-emitting units LD. Furthermore, because each light-emitting unit LD shares the light-emitting layer OL, the different light-emitting units LD emit the same color.

[0111] In some embodiments of the present disclosure, as shown in Figures 1, 11 and 12, the light-emitting unit LD may include a plurality of light-emitting devices connected in series, each light-emitting unit includes a first electrode ANO, a second electrode CAT and a plurality of light-emitting sublayers OLP between the first electrode ANO and the second electrode CAT, and the light-emitting devices of the same light-emitting unit LD may share the same first electrode ANO and the same second electrode CAT, that is, the same light-emitting unit LD may have only one first electrode ANO and one second electrode CAT.

[0112] For example, as shown in Figures 1, 11, and 12, the light-emitting layer OL may include a hole-injection layer HIL1, multiple light-emitting sublayers OLP, and an electron-injection layer EIL. The light-emitting sublayers OLP are disposed between the hole-injection layer HIL1 and the electron-injection layer EIL and are connected in series away from the driving backplane BP. Two adjacent light-emitting sublayers OLP can be connected in series via a charge generation layer CGL located therebetween. When an electrical signal is applied to the first electrode ANO and the second electrode CAT, each light-emitting sublayer OLP can emit light, and different light-emitting sublayers OLP can be used to emit light of different colors.

[0113] Furthermore, as shown in FIG11 and FIG12 , any light-emitting sublayer OLP may include at least a hole transport layer HTL, a light-emitting material layer EML, and an electron transport layer ETL distributed in a direction away from the driving backplane BP. The specific light-emitting principle is not described in detail here, wherein:

[0114] The number of hole injection layers HIL, hole transport layers HTL, electron transport layers ETL, and electron injection layers EIL is not particularly limited herein, and adjacent light-emitting sublayers OLP may share one or more of the hole injection layer HIL, hole transport layer HTL, electron transport layer ETL, and electron injection layer EIL. Furthermore, a charge generation layer CGL may be provided between at least two adjacent light-emitting sublayers OLP, thereby connecting the two light-emitting sublayers OLP in series.

[0115] In some embodiments of the present disclosure, as shown in FIG11 , the light-emitting layer OL may include two light-emitting sublayers OLP of different colors, namely, a first light-emitting sublayer that emits red and green light simultaneously, and a second light-emitting sublayer that emits blue light. The first and second light-emitting sublayers may emit light simultaneously, causing the light-emitting layer OL to emit white light. The first light-emitting sublayer includes two light-emitting material layers EML, namely, a red-emitting material layer R-EML and a green-emitting material layer G-EML. Specifically, the first light-emitting sublayer may include a hole transport layer HTL1, a light-emitting material layer R-EML, a light-emitting material layer G-EML, and an electron transport layer ETL2, stacked sequentially on the hole injection layer HIL1 in a direction away from the driving backplane BP.

[0116] The surface of the first light-emitting sublayer away from the driving backplane BP may be provided with a charge generation layer CGL. The second light-emitting sublayer is provided on the surface of the charge generation layer CGL away from the driving backplane BP, thereby connecting the first light-emitting sublayer and the second light-emitting sublayer in series. The second light-emitting sublayer includes a hole injection layer HIL2, a hole transport layer HTL2, a hole transport layer HTL3, a blue light-emitting material layer B-EML, a hole blocking layer HBL, and an electron transport layer ETL2, which are stacked in sequence along the direction away from the driving backplane BP on the side of the charge generation layer CGL away from the driving backplane BP. The electron injection layer EIL is provided on the surface of the electron transport layer ETL2 away from the driving backplane BP. The second electrode CAT is provided on the surface of the electron injection layer EIL away from the driving backplane BP.

[0117] In other embodiments of the present disclosure, as shown in Figure 12, the number of light-emitting sublayers OLP may be three, and they may be stacked between the hole injection layer HIL1 and the electron injection layer EIL in a direction away from the driving backplane BP, and each light-emitting sublayer OLP may only include a hole transport layer HTL, a light-emitting material layer EML and an electron transport layer ETL stacked in a direction away from the driving backplane BP.

[0118] The luminescent material layer EML of the three luminescent sublayers OPL can include two blue-emitting luminescent material layers B-EML and one yellow-emitting Y-EML. By selecting the color and material of the filter part of the color filter layer, color display can also be achieved. For example:

[0119] The three light-emitting sublayers OLP are respectively the first light-emitting sublayer, the second light-emitting sublayer and the third light-emitting sublayer, and the first light-emitting sublayer, the second light-emitting sublayer and the third light-emitting sublayer are sequentially distributed in a direction away from the driving backplane BP, wherein:

[0120] The first light-emitting sublayer includes a hole transport layer HTL1, a light-emitting material layer B-EML and an electron transport layer ETL1; the second light-emitting sublayer includes a hole transport layer HTL2, a light-emitting material layer Y-EML and an electron transport layer ETL2; the third light-emitting sublayer includes a hole transport layer HTL3, a light-emitting material layer B-EML and an electron transport layer ETL3.

[0121] There are two charge generation layers CGL, one of which is disposed between two adjacent light-emitting sublayers OLP, that is, one charge generation layer CGL is disposed between the first and second light-emitting sublayers, and another charge generation layer CGL is disposed between the second and third light-emitting sublayers.

[0122] Of course, in other embodiments of the present disclosure, the light-emitting material layers EML of the three light-emitting sublayers OPL may emit red light, blue light and green light respectively, and the colors are not particularly limited here.

[0123] In some embodiments of the present disclosure, for the case of three light-emitting sublayers OLP, in two first truncation grooves CU1 of different widths in the same pixel opening PH, the width difference between the two first truncation grooves CU1 is 0.8 to 1.2 times the width difference between the first truncation groove CU1 and the second truncation groove CU2. For example, as shown in FIG6 , the width difference between the first truncation groove CU11 and the second truncation groove CU2 is the first width difference, and the width difference between the first truncation groove CU12 and the first truncation groove CU2 is the second width difference, and the second width difference is 0.8 to 1.2 times the first width difference.

[0124] In addition, in some embodiments of the present disclosure, the widths of the second truncation grooves CU2 on the two side walls of the separation groove SES may also be different. The second truncation grooves CU2 of different widths may be located on the same side wall and distributed around the first electrode ANO. They may be connected or staggered, so that the second truncation grooves CU2 of different widths may be set on the same side wall; or, the second truncation grooves CU2 of different widths may also be located on the two side walls of the separation groove SES, so that the widths of the second truncation grooves CU2 on the same side wall are the same.

[0125] By providing a second truncation groove CU2 with a larger width, the two charge generation layers CGL and the hole injection layer HIL1 in the three-layer light-emitting sublayer solution can be truncated, thereby improving the anti-crosstalk effect.

[0126] It should be noted that, in the same display panel, there may be multiple first truncation grooves CU1 with different widths, and there may also be multiple second truncation grooves CU2 with different widths. As long as the hole injection layer HIL1 and the charge generation layer CGL can be cut off to prevent crosstalk, the combination of the first truncation grooves CU1 and the second truncation grooves CU2 with different widths can also reduce the risk of overlap between the charge generation layer CGL and the first electrode ANO, which is beneficial to ensure the normal light emission of the light-emitting unit LD.

[0127] The above-mentioned light-emitting layer OL structure is only an example and does not constitute a limitation on its film layer. The number of its light-emitting sublayers OLP can also be greater, or it can include only one light-emitting sublayer OLP, as long as it can cooperate with the color filter layer to achieve color display.

[0128] As shown in FIG1 , the second electrode CAT covers the light-emitting layer OL, and its orthographic projection on the driving backplane BP covers the display area and extends into the peripheral area. Each light-emitting unit LD can share the same second electrode CAT. The light-emitting layer OL can be controlled to emit light by controlling the voltage of the power signal input to the second electrode CAT and the voltage of the driving signal input to the first electrode ANO.

[0129] As shown in FIG1 , the display panel may further include a color filter layer, which may be disposed on a side of the second electrode CAT away from the driving backplane BP and includes a plurality of filter sections. Each first electrode ANO is disposed opposite each filter section in a direction perpendicular to the driving backplane BP, such that the orthographic projection of a filter section on the driving backplane BP at least partially overlaps with a first electrode ANO. Each filter section includes at least three color filters, for example, a filter section that transmits red light, a filter section that transmits green light, and a filter section that transmits blue light. Light emitted by each light-emitting unit LD is filtered by the filter section to produce monochromatic light of different colors, thereby achieving color display. A filter section and its corresponding light-emitting unit LD may constitute a sub-pixel. The color emitted by any sub-pixel is the color of the light transmitted by its filter section. Multiple sub-pixels may constitute a pixel, and each sub-pixel within the same pixel may emit light of different colors.

[0130] The color filter layer may further include a light-shielding portion separating the filter portion. The light-shielding portion is opaque and blocks the area between the two light-emitting units LD. The filter portion may be directly formed of a light-shielding material and spaced apart from the filter portion. Alternatively, in some embodiments of the present disclosure, adjacent filter portions may be stacked in the area corresponding to the area between two adjacent light-emitting units LD, with the two filter portions transmitting different colors of light, thereby rendering the stacked area opaque.

[0131] In addition, in some embodiments of the present disclosure, on the basis of the light-emitting layer OL emitting white light, in order to improve the brightness of the picture, the color filter layer may further include a transparent portion. In a direction perpendicular to the substrate, a transparent portion may be arranged opposite to a light-emitting unit LD, so that the color filter layer can also directly transmit the light emitted by the light-emitting layer OL, such as white light, and the brightness can be increased by the white light.

[0132] In order to improve light extraction efficiency, a light extraction layer may be covered on the side of the second electrode CAT away from the driving backplane BP to improve brightness. Furthermore, the light extraction layer may directly cover the surface of the second electrode CAT away from the driving backplane BP.

[0133] To facilitate connection of the second electrode CAT to the drive circuit, in some embodiments of the present disclosure, the first electrode layer FE further includes an adapter ring, the orthographic projection of which on the drive backplane BP is located in the peripheral area. The adapter ring can be connected to the peripheral circuit and surrounds the outside of the display area. The second electrode CAT can be connected to the adapter ring, thereby connecting the second electrode CAT to the peripheral circuit via the adapter ring so that the peripheral circuit can apply a drive signal to the second electrode CAT. The pattern of the adapter ring can be the same as the pattern of the first electrode ANO in the display area to improve the uniformity of the pattern of the first electrode layer FE.

[0134] In some embodiments of the present disclosure, as shown in FIG1 , the display panel of the present disclosure may further include an encapsulation layer, which may be provided on the side of the second electrode CAT away from the driving backplane BP, and between the color filter layer and the second electrode CAT, for blocking corrosion from external water and oxygen. The encapsulation layer may be a single-layer or multi-layer structure. For example, the encapsulation layer may include a first encapsulation sublayer, a second encapsulation sublayer, and a third encapsulation sublayer stacked in sequence in a direction away from the driving backplane BP, wherein the materials of the first encapsulation sublayer and the second encapsulation sublayer may be inorganic insulating materials such as silicon nitride and silicon oxide, and the second encapsulation sublayer may be formed by an ALD (Atomic layer deposition) process; the material of the third encapsulation sublayer may be an organic material, which may be formed by an MLD (Molecular Layer Deposition) process. Of course, the encapsulation layer may also adopt other structures, and the structure of the encapsulation layer is not particularly limited here.

[0135] In addition, the display panel may further include a transparent cover plate, which may cover the side of the encapsulation layer away from the driving backplane BP. The transparent cover plate may be a single-layer or multi-layer structure, and its material is not particularly limited here.

[0136] Based on the above analysis of related technologies, since each light-emitting unit LD shares the light-emitting layer OL, carriers (e.g., holes) from one light-emitting unit LD may migrate through layers such as the charge generation layer CGL and the hole injection layer near the driver backplane BP to other light-emitting units LD, particularly to adjacent light-emitting units LD, resulting in leakage, which affects the purity of the emitted light and causes cross-color. To this end, as shown in Figures 1 and 2, a separation groove SES can be provided in the pixel definition layer PDL, a first truncation groove CU1 is provided on the sidewall of the pixel opening PH, and a second truncation groove CU2 is provided on the sidewall of the separation groove SES. The light-emitting layer OL is confined by the first truncation groove CU1 and the second truncation groove CU2, making it difficult for at least a portion of the film layer of the light-emitting layer OL to be continuous within the first truncation groove CU1 and the second truncation groove CU2, thereby being disconnected. This prevents carriers from migrating between the light-emitting units LD and thereby avoids cross-color caused by leakage.

[0137] The sidewall of the separation groove SES is a sloped surface that expands in a direction away from the driving back plate BP.

[0138] As shown in Figures 1 and 2, since the light-emitting layer OL contains multiple layers that could potentially leak electricity, to ensure that the first and second truncation trenches CU1 and CU2 prevent leakage, the first and second truncation trenches CU1 and CU2 are staggered in a direction perpendicular to the driving backplate BP, so that the second truncation trench CU2 is at least partially located on the side of the first truncation trench CU1 that is closest to the driving backplate BP. The first truncation trench CU1 is positioned higher relative to the driving backplate BP. Even though the light-emitting layer OL comprises multiple layers, it can at least truncate the hole injection layer HIL1 closest to the driving backplate BP. At the same time, the second truncation trench CU2 is positioned lower, requiring a greater depth for the light-emitting layer OL to be recessed, which facilitates truncation of the charge generation layer CGL, which is further from the driving backplate BP than the hole injection layer HIL1. Of course, in this case, the hole injection layer HIL1 can also be truncation. Thus, the first and second truncation trenches CU1 and CU2 can achieve truncation of multiple layers, reducing the risk of leakage and improving color crosstalk.

[0139] The following is a detailed description of the solution to the color crosstalk problem of the display panel disclosed in the present invention:

[0140] As shown in FIG1 and FIG2 , to achieve the above-mentioned purpose, the pixel definition layer PDL may include at least an etch stop layer PL1, a first definition layer PL2, and a second definition layer PL3 stacked in sequence in a direction away from the driving backplane BP, and a separation groove SES penetrates the second definition layer PL2 and the first definition layer PL2 and exposes the etch stop layer PL1, wherein:

[0141] The etch stop layer PL1 is partially stacked on the surface of the first electrode ANO away from the driving back plate BP, and is partially located outside the first electrode ANO. When the separation groove SES is formed by the etching process, the etch stop layer PL1 can limit the depth of the separation groove SES and improve the uniformity of the depth of the separation groove SES.

[0142] In some embodiments of the present disclosure, as shown in FIG. 1 and FIG. 2 , the etch stop layer PL1 may include a buffer layer PL11 and a stop layer PL12 , wherein:

[0143] The buffer layer PL11 is partially stacked on the surface of the first electrode ANO away from the driving back plate BP and partially located outside the first electrode ANO. The buffer layer PL11 can be made of inorganic insulating materials such as silicon oxide and silicon nitride, or other insulating materials.

[0144] The barrier layer PL12 may be disposed on a surface of the buffer layer PL11 away from the driving backplate BP. The material of the barrier layer PL12 is different from that of the first definition layer PL2 and the second definition layer PL3. In at least one etching process, the first definition layer PL2 and the second definition layer PL3 are etched to a greater extent than the barrier layer PL12. The barrier layer PL12 may be made of aluminum oxide, although other materials may also be used.

[0145] In other embodiments of the present disclosure, the etch stop layer PL1 may have a single-layer structure, which may be a conductive material such as metal or metal oxide, but is spaced apart from the first electrode ANO. Alternatively, the etch stop layer PL1 may have three or more layers, as long as it can block etching when forming the separation groove SES.

[0146] The first definition layer PL2 is disposed on the surface of the etch stop layer PL1 away from the driving backplate BP, and the second definition layer PL3 is disposed on the surface of the first definition layer PL2 away from the driving backplate BP. The first definition layer PL2 and the second definition layer PL3 are made of different materials. For example, the first definition layer PL2 is made of silicon nitride, and the second definition layer PL3 can be made of silicon oxide. The same etching process can be used to etch these two materials to different degrees, causing the second definition layer PL3 to extend beyond the edge of the first definition layer PL2, thereby forming the first truncation trench CU1 and the second truncation trench CU2 in the first definition layer PL2.

[0147] As shown in FIG2 , both the first truncation groove CU1 and the second truncation groove CU2 have two sidewalls distributed in a direction perpendicular to the driving backplate BP. The width W1 of the first truncation groove CU1 is the distance between its two sidewalls, and the width W2 of the second truncation groove CU2 is the distance between its two sidewalls. For any one of the first truncation groove CU1 and the second truncation groove CU2, one sidewall is the surface of the second definition layer PL3 close to the driving backplate BP, and the other sidewall is the surface of the etch stop layer PL1 away from the driving backplate. The widths of the first truncation groove CU1 and the second truncation groove CU2 can be limited by the etch stop layer PL1, which is more difficult to etch than the first definition layer PL2. That is, the distance between the two sidewalls is limited, thereby improving the uniformity of the widths of the first truncation groove CU1 and the second truncation groove CU2, and avoiding the situation where the widths of different first truncation grooves CU1 have large deviations and the widths of different second truncation grooves CU2 have large deviations. Accordingly, this is conducive to improving the uniformity of the surface of the driving backplate BP. Because the pixel definition layer (PDL) already includes the etch stop layer PL1, there's no need to reserve space between adjacent first electrodes ANO for the etch stop layer PL1. This shortens the distance between adjacent first electrodes ANO, and therefore the spacing between light-emitting units LD. This allows for more light-emitting units LD while maintaining the same display panel size, thereby improving resolution. Experiments have shown that this distance can be reduced to less than 1μm, compared to the typical spacing of over 1μm in existing display panels.

[0148] In some embodiments of the present disclosure, due to the presence of the separation groove SES, the pixel definition layer PDL has a large step difference at the separation groove SES, and the light-emitting layer OL is highly concentrated in the separation groove SES, causing the second truncation groove CU2 to be subjected to greater pressure than the first truncation groove CU1, thereby increasing the risk of collapse. If collapse occurs, it will be difficult to perform the truncation function. To this end, the present disclosure provides a variety of means to solve this problem, for example:

[0149] In one embodiment, as shown in Figure 8, the width of at least part of the second truncation groove CU2 is greater than the width of the first truncation groove CU1. Of course, the width of any area of ​​the second truncation groove CU2 can be made greater than the first truncation groove CU1 to leave a margin for potential collapse. Even if the second truncation groove CU2 collapses to a certain extent, it can still play a truncation role.

[0150] In one embodiment, as shown in Figures 2 and 9 , the sidewalls of the first and second truncation grooves CU1 and CU2, distal to the driver backplate BP, can be considered cantilevers relative to their respective bottom surfaces. The longer the cantilevers, the longer the lever arm, and the greater the risk of collapse. To address the collapse issue, the depth d5 ​​of the second truncation groove CU2 can be made smaller than the depth d7 of the first truncation groove CU1. This depth can be the maximum distance between the end of the sidewall of the truncation groove CU2 distal to its bottom surface, parallel to the driver backplate BP, and its bottom surface. This shortens the cantilever of the second truncation groove CU2 and reduces the risk of collapse.

[0151] In one embodiment, as shown in FIG10 , the angle between the sidewall of the second truncation trench CU2 away from the driving back plate BP and the surface of the driving back plate BP on which the first electrode ANO is disposed can be greater than the angle between the sidewall of the first truncation trench CU1 away from the driving back plate BP and the surface of the driving back plate BP on which the first electrode ANO is disposed. In other words, the sidewall of the second truncation trench CU2 away from the driving back plate BP is tilted away from the driving back plate BP relative to the sidewall of the first truncation trench CU2 away from the driving back plate BP, thereby preventing the second truncation trench CU2 from collapsing. Even if the second truncation trench CU2 collapses, the sidewalls will not contact each other, thereby ensuring the truncation effect.

[0152] It should be noted that the above-mentioned implementation methods for solving the collapse problem can be applied individually or one or more of them can be applied simultaneously. For example, they will not be described in detail here.

[0153] In some embodiments of the present disclosure, as shown in FIG2 , a length d7 of the sidewalls of the first truncation trench CU1 away from the driving backplate BP is not less than 0.03 μm and not greater than 0.05 μm, such as 0.03 μm, 0.04 μm, or 0.05 μm. This length d7 can be regarded as the depth of the first truncation trench CU1 .

[0154] In some embodiments of the present disclosure, as shown in FIG2 , the length d5 ​​of the sidewalls of the second truncation trench CU2 away from the driving backplate BP is not less than 0.07 μm and not greater than 0.1 μm, for example, 0.07 μm, 0.08 μm, 0.09 μm, or 0.1 μm. This length d5 ​​can be regarded as the depth of the second truncation trench CU2.

[0155] In some embodiments of the present disclosure, the second truncating groove CU2 may be located on a side of the first truncating groove CU1 close to the driving back plate BP. The width difference between the first truncating groove CU1 and the second truncating groove CU2 is smaller than the width of one of the first truncating groove CU1 and the second truncating groove CU2.

[0156] It should be noted that the width difference between A and B in this article is: the absolute value of the difference between the width of A and the width of B. For example, the width difference between the first truncation groove CU1 and the second truncation groove CU2 is the absolute value of the difference between the two widths, so the width difference must be greater than or equal to 0.

[0157] In some embodiments of the present disclosure, as shown in Figure 5, the bottom surface of the first truncation groove CU1 is a slope whose depth decreases in the direction away from the driving backplane BP, and the slope of the slope is α, which can refer to the angle between the slope and the surface on which it is located.

[0158] The bottom surface of the second truncation groove CU2 is a slope whose depth decreases as it moves away from the driving back plate BP. The slope β of the slope can be smaller than the slope α, which can refer to the angle between the slope and the surface on which it is located. The slope β can be smaller than the slope α.

[0159] In some embodiments of the present disclosure, as shown in Figures 1 and 2, the pixel definition layer PDL may further include a filling layer PL4, which may be provided on the same side of the driving backplane BP as the first electrode, for example, both are provided on the flat layer PLN. The filling layer PL4 may separate the first electrodes ANO and contact the sidewalls of the first electrodes ANO. The filling layer PL4 may be regarded as a film layer having a plurality of through holes, and the first electrodes ANO may be provided in each through hole in a one-to-one correspondence. At the same time, part of the etch stop layer PL1 is stacked on the surface of the filling layer PL4 away from the driving backplane BP, and part is located on the surface of the first electrode ANO away from the driving backplane BP. The filling layer PL4 may also fill the first groove FL1 and the second groove FL2. The material of the filling layer PL4 may be silicon oxide, and of course, other insulating materials such as silicon nitride may also be used.

[0160] In some embodiments of the present disclosure, as shown in Figure 1, for the first electrode ANO including the first conductive layer AL1 to the second conductive protection layer AL4, the thickness of the etch barrier layer PL1 may be greater than the thickness of any layer from the first conductive layer AL1 to the second conductive protection layer AL4, but less than the sum of the thicknesses of the first conductive layer AL1 to the second conductive protection layer AL4.

[0161] In some embodiments of the present disclosure, as shown in Figures 1 and 2, the surface of the filling layer PL4 away from the driving backplate BP is located on the side of the surface of the first electrode ANO away from the driving backplate BP close to the driving backplate BP, so that the etching blocking layer PL1 and the first definition layer PL2 and the second definition layer PL3 thereon can be recessed at the filling layer PL4.

[0162] As shown in FIG2 , the pixel definition layer PDL may include an edge portion PE, a middle portion PM, and a connection portion PS. The edge portion PE is located on the surface of the first electrode ANO away from the driving backplane BP. The edge portion PE includes an etch stop layer PL1, a first definition layer PL2, and a second definition layer PL3. The pixel opening PH is located in the edge portion PE.

[0163] The middle portion PM is located between two adjacent first electrodes ANO, and includes a filling layer PL4 to a second definition layer PL3. The orthographic projection of the middle portion PM on the driving backplane BP does not overlap with the first electrodes ANO.

[0164] The connecting portion PS connects the edge portion PE and the middle portion PM. Because the etch stop layer PL1 and the first and second definition layers PL2 and PL3 thereon are recessed in the filler layer PL4, the middle portion PM requires the connecting portion PS to extend to the surface of the first electrode ANO away from the driving backplate BP to obtain the edge portion PE. Separation trenches SES can be formed in the middle portion PM.

[0165] The slope of the connecting portion PS is smaller than the slope of the bottom surface of the first truncation groove CU1 and the slope of the bottom surface of the second truncation groove CU2.

[0166] Of course, in other embodiments of the present disclosure, the surface of the filling layer PL4 away from the driving backplane BP can also be located in the same plane as the surface of the first electrode ANO away from the driving backplane BP, filling the space between adjacent first electrodes ANO, and the etching blocking layer PL1 extends along this plane.

[0167] In some embodiments of the present disclosure, the sidewalls of at least one pixel opening PH are provided with a plurality of first truncation grooves CU1 distributed along the circumferential direction. Adjacent first truncation grooves CU1 may be connected or staggered, without particular limitation herein. At least two first truncation grooves CU1 of the same pixel opening PH may have different widths. The first truncation groove CU1 with a larger width may truncate a film layer of the light-emitting layer OL that is further from the driving backplane BP.

[0168] As shown in FIG6 , in the first embodiment of the present disclosure, at least one pixel opening PH has a first truncation groove CU11 and a first truncation groove CU12, the width W12 of the first truncation groove CU12 is greater than the width W11 of the first truncation groove CU11, and the width W11 of the first truncation groove CU11 is greater than the width W2 of the second truncation groove CU2.

[0169] As shown in FIG7 , in the second embodiment of the present disclosure, at least one pixel opening PH includes a first truncation groove CU11 and a first truncation groove CU12. The width W12 of the first truncation groove CU12 is greater than the width W11 of the first truncation groove CU11, and the width W11 of the first truncation groove CU11 is equal to the width W2 of the second truncation groove CU2. Furthermore, at least one pixel opening PH includes a first truncation groove CU11 and a first truncation groove CU13. The width W13 of the first truncation groove CU13 is greater than the width W11 of the first truncation groove CU11.

[0170] In some embodiments of the present disclosure, there are three light-emitting sublayers OLP and two charge generation layers CGL. In combination with the first and second embodiments described above, the hole injection layer HIL1 can be interrupted by the first truncation trench CU11, while the charge generation layer CGL can extend continuously. The first truncation trench CU12 can interrupt the hole injection layer HIL1 and two charge generation layers CGL, while the other charge generation layer CGL can extend continuously. The second truncation trench CU2 can interrupt the hole injection layer HIL1 and the charge generation layer CGL closer to the driving backplate BP.

[0171] Therefore, on the basis of preventing the crosstalk problem by cutting off the hole injection layer HIL1 and one of the two charge generation layers CGL, the position where the hole injection layer HIL1 and the two charge generation layers CGL are cut off at the same time can be reduced, and the cut-off charge generation layer CGL can be prevented from extending to the driving backplane BP and contacting the first electrode ANO, thereby reducing the risk of internal short circuit in the light-emitting unit LD.

[0172] Furthermore, in two first truncation grooves CU1 of different widths in the same pixel opening PH, the width of one first truncation groove CU1 is 0.8 to 1.2 times the width of the other first truncation groove CU1. For example, as shown in Figures 6 and 7, the width of the first truncation groove CU12 is 0.8 to 1.2 times the width W11 of the first truncation groove CU13, and the width W13 of the first truncation groove CU13 is 0.8 to 1.2 times the width W11 of the first truncation groove CU11.

[0173] In some embodiments of the present disclosure, there are two light-emitting sublayers OLP and one charge generation layer CGL. The structure is similar to that described above for the embodiment with two light-emitting sublayers OLP. The light-emitting sublayer OLP farther from the driving backplane BP includes a blue-emitting material layer B-EML.

[0174] The distance between the blue light-emitting material layer B-EML and the charge generation layer CGL within the pixel opening PH is greater than the distance within the pixel definition layer PDL, so that the light-emitting layer OL within the pixel opening PH can emit light normally, while the area within the pixel definition layer PDL does not need to emit light.

[0175] The inventors have discovered that after the hole injection layer HIL1 of the light-emitting layer OL is truncated by the first truncation groove CU1, if the charge generation layer CGL is not truncated, it may bend toward the first electrode ANO and ultimately directly overlap the first electrode ANO, causing a short circuit. To this end, as shown in Figure 2, in some embodiments of the present disclosure, the pixel opening PH includes a first segment PH1 and a second segment PH2 arranged in a direction perpendicular to the driving backplane BP. The first segment PH1 is located in the etch stop layer PL1, the second segment PH2 is located in the second definition layer PL3, and the first truncation groove CU1 is located between the first segment PH1 and the second segment PH2. The boundary of the orthographic projection of the second segment PH2 on the driving backplane BP surrounds the boundary of the orthographic projection of the first segment PH1 on the driving backplane BH, that is, the range of the etch barrier layer PL1 extending to the first electrode ANO is larger than the range of the second definition layer PL3 extending to the first electrode ANO. Even if the charge generation layer CGL bends toward the first electrode ANO, it overlaps with the etch barrier layer PL1, and the etch barrier layer PL1 is insulated from the first electrode ANO, so it will not cause a short circuit between the charge generation layer CGL and the first electrode ANO.

[0176] Furthermore, in some embodiments of the present disclosure, the distance d8 between the boundary of the orthographic projection of the second segment PH2 on the driving backplane BH and the boundary of the orthographic projection of the first segment PH1 on the driving backplane BP is not greater than 0.2 μm and not less than 0.06 μm, for example, 0.06 μm, 0.08 μm, 0.1 μm, 0.2 μm, etc.

[0177] In some embodiments of the present disclosure, as shown in FIG. 2 , a distance d3 between two adjacent pixel openings PH located in the first segment PH1 is not greater than 1.9 μm and not less than 1.1 μm, for example, 1.1 μm, 1.4 μm, 1.7 μm, 1.9 μm, etc.

[0178] In some embodiments of the present disclosure, as shown in FIG. 2 , a distance d6 between two adjacent pixel openings PH located in the second segment PH2 is not greater than 1.6 μm and not less than 0.9 μm, for example, 0.9 μm, 1.1 μm, 1.3 μm, 1.5 μm, or 1.6 μm.

[0179] In some embodiments of the present disclosure, the interval d6 between two adjacent pixel openings PH and the width d4 of the separation groove SES satisfy the following relationship:

[0180] (d6-d4) / 2>d4;

[0181] Half of the difference between the distance d6 between two adjacent pixel openings PH and the width d4 of the separation groove SES is greater than the width d4 of the separation groove SES.

[0182] As shown in FIG1 , based on the topography of the pixel definition layer PDL and the light-emitting layer OL, the second electrode CAT can form a flat portion CATp in the region corresponding to the first electrode ANO and a recessed portion CATg in the region corresponding to the separation slot SES. The recessed portion CATg and the flat portion CATp can be smoothly connected by a transition portion CATi, thus avoiding sharp corners in the second electrode CAT. Because the light-emitting layer OL fills the separation slot SES, the depth of the recessed portion CATg of the second electrode CAT is less than the depth of the separation slot SES.

[0183] The present disclosure also provides a display device, which may include the display panel of any of the above-described embodiments. The specific structure and beneficial effects of the display panel have been described in detail in the above embodiments of the display panel and will not be further described here. The display device of the present disclosure can be used in electronic devices with image display functions, such as watches, bracelets, mobile phones, and tablet computers, which are not listed here one by one.

[0184] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, comprising: Driver backplane; A plurality of first electrodes are arrayed and distributed on one side of the driving back plate; a pixel definition layer disposed on the same side of the driving backplane as the first electrode and having pixel openings for exposing each of the first electrodes and a separation groove between two adjacent pixel openings, wherein the boundaries of the pixel openings are located within the boundaries of the exposed first electrodes; a first truncation groove is disposed on a sidewall of the pixel opening, and a second truncation groove is disposed on a sidewall of the separation groove; the first truncation groove is at least partially located on a side of the second truncation groove away from the driving backplane; a light-emitting layer covering the pixel definition layer and the first electrode; The second electrode covers the light-emitting layer.

2. The display panel according to claim 1, wherein The pixel definition layer includes an etching stop layer, a first definition layer and a second definition layer stacked in sequence in a direction away from the driving backplane; The pixel opening passes through the etch stop layer, the first definition layer, and the second definition layer; the separation groove passes through the first definition layer and the second definition layer, and exposes the etch stop layer; The first truncation groove and the second truncation groove are located in the first definition layer.

3. The display panel according to claim 2, wherein: The etch stop layer comprises: a buffer layer, at least partially disposed on a surface of the first electrode away from the driving backplane; The barrier layer is stacked on the surface of the buffer layer away from the driving back plate; and the first definition layer is stacked on the surface of the barrier layer away from the driving back plate.

4. The display panel according to claim 2, wherein: The pixel opening includes a first segment located on the etch stop layer and a second segment located on the second definition layer, wherein a boundary of an orthographic projection of the second segment on the driving backplane surrounds a boundary of an orthographic projection of the first segment on the driving backplane.

5. The display panel according to claim 4, wherein: A distance between a boundary of an orthographic projection of the second segment on the driving backplane and a boundary of an orthographic projection of the first segment on the driving backplane is not greater than 0.2 μm and not less than 0.06 μm. The display panel according to claim 4 , wherein: The distance between the two adjacent pixel openings located in the first section is not greater than 1.9 μm and not less than 1.1 μm; The distance between the two adjacent pixel openings located in the second segment is not greater than 1.6 μm and not less than 0.9 μm.

7. The display panel according to claim 1, wherein: The length of the sidewalls of the first truncation groove away from the driving back plate is not less than 0.03 μm and not more than 0.05 μm.

8. The display panel according to claim 1, wherein: The length of the side walls of the second truncation groove away from the driving back plate is not less than 0.07 μm and not more than 0.1 μm.

9. The display panel according to claim 2, wherein: The pixel definition layer further includes: The filling layer is provided on the same side of the driving back plate as the first electrodes and separates the first electrodes; a portion of the etching stop layer is stacked on a surface of the filling layer away from the driving back plate.

10. The display panel according to claim 9, wherein: The surface of the filling layer away from the driving back plate is located on a side of the first electrode away from the driving back plate that is close to the driving back plate; The pixel definition layer includes an edge portion, a middle portion and a connecting portion. The edge portion is located on the surface of the first electrode away from the driving backplane; the middle portion is located between two adjacent first electrodes; and the connecting portion connects the edge portion and the middle portion.

11. The display panel according to claim 10, wherein: The sidewall of the separation groove is a slope surface that expands in a direction away from the driving back plate.

12. The display panel according to claim 10, wherein: The bottom surface of the first truncation groove is a sloped surface whose depth decreases in a direction away from the driving back plate; The bottom surface of the second truncation groove is a sloped surface whose depth decreases in a direction away from the driving back plate.

13. The display panel according to claim 12, wherein: The slope of the connecting portion is smaller than the slopes of the bottom surfaces of the first truncation groove and the second truncation groove.

14. The display panel according to claim 1, wherein: The orthographic projection of the first truncation groove on the driving backplate is located within the orthographic projection of the first electrode on the driving backplate.

15. The display panel according to claim 1, wherein The width of at least a portion of the second truncation groove is greater than the width of the first truncation groove.

16. The display panel according to claim 1, wherein The depth of the second truncation groove is smaller than the depth of the first truncation groove.

17. The display panel according to claim 1, wherein: The angle between the side wall of the second truncation groove away from the driving back plate and the surface of the driving back plate where the first electrode is provided is greater than the angle between the side wall of the first truncation groove away from the driving back plate and the surface of the driving back plate where the first electrode is provided.

18. The display panel according to claim 1, wherein: The difference in width between the first truncation groove and the second truncation groove is smaller than the width of one of the first truncation groove and the second truncation groove.

19. The display panel according to claim 1, wherein: Half of the difference between the distance between two adjacent pixel openings and the width of the separation groove is greater than the width of the separation groove.

20. The display panel according to any one of claims 1 to 19, wherein: The first electrode comprises: A first conductive layer is provided on a side surface of the driving back plate; a second conductive layer, stacked on a surface of the first conductive layer away from the driving backplane; The first conductive protection layer covers the surface of the second conductive layer away from the driving back plate, and the side walls of the second conductive layer and the first conductive layer.

21. The display panel according to claim 20, wherein: The first electrode further includes a second conductive protection layer covering the first conductive protection layer.

22. The display panel according to claim 21, wherein: A first groove is provided on the surface of the driving back plate where the first electrode is provided, and a second groove is provided at the bottom of the first groove; The first conductive protection layer and the second conductive protection layer cover the sidewalls and the bottom surface of the first groove in an area outside the second groove.

23. The display panel according to claim 22, wherein: The width of the separation groove is equal to the width of the second groove.

24. The display panel according to claim 22, wherein: The width of the first groove is not less than 0.5 μm and not more than 1.2 μm; the width of the second groove is not less than 0.2 μm and not more than 0.9 μm.

25. The display panel according to any one of claims 1 to 24, wherein: The light-emitting layer includes a hole injection layer and multiple light-emitting sublayers, each of which is arranged on a side of the hole injection layer away from the driving backplane in a direction away from the driving backplane; two adjacent light-emitting sublayers are connected in series via a charge generation layer; the light-emitting sublayer includes a hole transport layer, at least one light-emitting material layer, and an electron transport layer arranged in a direction away from the driving backplane; The hole injection layer is disconnected at the first truncation groove; At least one of the charge generation layers is disconnected at the second cutoff groove.

26. The display panel according to claim 25, wherein: A plurality of first truncation grooves distributed along the circumferential direction are provided on the sidewall of at least one of the pixel openings; and at least two of the first truncation grooves of the same pixel opening have different widths.

27. The display panel according to claim 26, wherein: The number of the light-emitting sublayers is three, and the number of the charge generation layers is two; In the two first truncation grooves of different widths in the same pixel opening, a width difference between the two first truncation grooves is 0.8 to 1.2 times a width difference between the first truncation groove and the second truncation groove.

28. The display panel according to claim 25, wherein: There are two light-emitting sublayers and one charge generation layer; the light-emitting sublayer farther from the driving backplane includes a light-emitting material layer that emits blue light; The distance between the blue light emitting material layer and the charge generation layer in the pixel opening is greater than the distance between them in the pixel definition layer.

29. The display panel according to any one of claims 1 to 28, wherein: The second electrode forms a flat portion in a region corresponding to the first electrode and forms a recessed portion in a region corresponding to the separation groove, and the recessed portion smoothly transitions to the flat portion.

30. A display device comprising the display panel according to any one of claims 1 to 29.

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