Implementation method of multi-path parallel afterglow display technology based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the field of signal spectrum analysis, and discloses a method for realizing a multi-path parallel afterglow display technology based on an FPGA (Field Programmable Gate Array), the technology is applied to the field of signal spectrum analysis, and the digital afterglow display of a frequency spectrum is realized by utilizing the high parallelism of the FPGA and carrying out preprocessing, compression, vector interpolation and afterglow processing on the signal frequency spectrum. And the observation capability of sudden instantaneous signals is enhanced. The invention provides an implementation method of a multi-path parallel afterglow display technology based on an FPGA (Field Programmable Gate Array), which has the characteristics of high efficiency, real-time performance, flexibility and configurability, and has practical value for spectrum analysis, processing and research of signals.

Description

Technical Field

[0001] The present invention relates to the field of signal spectrum analysis, and more specifically, to a method for realizing a multi-channel parallel persistence display technology based on FPGA. Background Art

[0002] With the continuous development of electronic communication technology and the complex signal environment, in order to better obtain the characteristic information of the signal, higher requirements are placed on the accuracy, real-time performance, accuracy, versatility and other indicators of real-time spectrum analysis equipment.

[0003] In signal spectrum analysis, it is crucial to capture and analyze signals quickly and accurately.

[0004] Traditional technology has limitations when processing complex signals or instantaneous signals, resulting in loss of signal information; the serial processing digital persistence system has slow processing, small bandwidth for analyzing signals, and cannot accurately display the signal's spectrum information.

[0005] Therefore, it is becoming increasingly important to analyze signals more accurately, flexibly and in real time in multiple fields and complex electromagnetic environments.

[0006] In view of this, the present invention proposes a method for realizing multi-channel parallel persistence display technology based on FPGA To solve the above problems. Summary of the invention

[0007] In view of the above shortcomings of the prior art, the present invention aims to provide a multi-channel parallel persistence display system and method based on FPGA.

[0008] Based on the powerful parallel computing capability of FPGA, the spectrum data is analyzed and processed through multi-channel parallel processing to improve the computing speed and ensure the integrity of the signal. At the same time, a variety of afterglow display methods can accurately detect the instantaneous signal covered by the large signal and present it on the host computer through images, which is convenient for observing the signal information, thereby meeting the current requirements for real-time and high accuracy of signal processing.

[0009] A method for implementing a multi-channel parallel persistence display technology based on FPGA, comprising the following steps: The calculated linear and logarithmic spectrum data are selected and output according to the needs. The spectrum data is preprocessed. The matrix used for spectrum persistence display is 1024×768, which means that the power value is discretized into 768 units and the frequency range is discretized into 1024 units. The power value of each frequency point is divided by the step value of the power value to obtain the position of the power value of the frequency point in the display unit. The Divider IP is used for implementation. The calculation formula is as follows:

[0010] Where: L is the power value of the frequency point in the display unit, Indicates the power value of the frequency point. Indicates the step size of the power value of the host computer display unit; Furthermore, a true dual-port RAM is used to store the frequency probability value of each channel. Every 768 addresses correspond to a frequency point. Each RAM processes 64 frequency points, so the number of addresses of a RAM is 49152. The corresponding address of the frequency point probability value is calculated according to the formula. The calculation formula is as follows:

[0011] Where: Addr indicates the address of the RAM, N indicates the count value of each frequency point, ranging from 0 to 63, and L indicates the position of the power value of the frequency point in the display unit; Furthermore, both read and write ports of the true dual-port RAM are used, one port is used for read operation, and the other port is used for write operation, and both ports are performed simultaneously; after obtaining the address, the value of the RAM is read through the address, and the read value is added by one, that is, the frequency probability value is added by one, and then written to the address; the number of superimposed frames of the spectrum probability is controlled by the host computer configuration, and the spectrum probability is output when the set number of frames is reached; in order to prevent data loss, two true dual-port RAMs are designed, and probability statistics and output are performed using a data ping-pong method; Furthermore, after completing the point probability statistics, in order to make the persistence display of adjacent frequency points continuous, the vector interpolation method can be used to connect the discrete probability points, so that the image display is smoother. Here, the vector comparison method is used for interpolation; Furthermore, when performing vector interpolation, adjacent frequency points are compared, and when they are discontinuous, interpolation processing is performed; the vector comparison method takes frequency point i, and obtains the maximum address addr_max(i) and the minimum address addr_min(i) of the probability statistical value of the frequency point by comparison, takes frequency point i+1, and uses the same method to obtain the maximum address addr_max(i+1) and the minimum address addr_min(i+1) of the probability statistical value of the frequency point; when the value of addr_max(i) is less than the value of addr_min(i+1), and the difference is greater than 1, it is necessary to interpolate the frequency point i+1, and the interpolation address range calculation formula is:

[0012]

[0013] When the value of addr_max(i+1) is less than the value of addr_min(i) and the difference is greater than 1, it is necessary to interpolate the frequency point i. The calculation formula for the interpolation address range is:

[0014]

[0015] Among them: add_addr_max represents the maximum address of interpolation, add_addr_min represents the maximum address of interpolation, The size of the interpolation data can be configured by the host computer according to the display effect of the image. The sixteenth data of the first frame needs to be compared with the first data of the second frame. At this time, it is necessary to perform storage processing. When all lines are interpolated, multiple data will be generated. At this time, the data of the same number of lines needs to be merged. Here, the comparison method is used, that is, the data of the same line are compared, the same ones are retained, and the maximum value of the two sets of data is retained for the different ones. The retained data is the output of the vector interpolation of this line; Furthermore, the persistence mode can only output one of the point probability statistics and vector interpolation statistics. Therefore, the host computer selects one of the two data for output, and the output data enters the persistence module for persistence processing. The persistence module is mainly divided into three modes: infinite persistence, no persistence, and variable persistence. Infinite persistence means data superposition display, and the output data is accumulated in units of each frame. The infinite persistence calculation formula is as follows:

[0016] Where: data_out(i) is the output data of the i-th frame after afterglow processing, data(i) is the i-th frame input data of the previous module, i represents the number of output frames, no afterglow means no processing of the data, and the infinite afterglow calculation formula is as follows:

[0017] Variable persistence is the output of the first frame data. When the second frame data arrives, the output of the second frame data is the value of the first frame data multiplied by the variable coefficient and the sum of the second frame data. The output of the third frame data is the value of the second frame output multiplied by the variable coefficient and the sum of the second frame data. And so on. The calculation formula of variable persistence is as follows:

[0018]

[0019]

[0020] Recursively, the calculation formula for outputting data starting from the second frame is as follows:

[0021] Among them: data_out(i) is the output data of the i-th frame afterglow processing, data(i) is the i-th frame input data of the previous module, i represents the number of output frames, p represents the variable coefficient, there are four main variable coefficients, namely 0.75, 0.5, 0.25 and 0.125, and different digital afterglow modes are mainly realized through the state machine.

[0022] Furthermore, the digital persistence processing design is mainly implemented through a true dual-port RAM. After the host computer configures the persistence output mode, when the first frame of data arrives, the first frame is output and the first frame of data is stored in the RAM. When the second frame of data arrives, the data stored in the RAM is taken out and processed according to the configured persistence mode. The processed result is output and stored in the RAM at the same time. In this way, data processing is performed and the output data is transmitted to the host computer through PCIE for display.

[0023] Furthermore, the output data is transmitted to the upper computer display module through PCIE, and the data needs to be rearranged for display. The transmitted data is sixteen-way parallel data, and each clock transmits data of 16 frequency points at the same time. The method for displaying each frame of image data is to first layout the probability statistical values ​​of the first 16 frequency points, and then layout the probability statistical values ​​of the next 16 frequency points, and so on, until the layout of the probability statistical values ​​of 1024 frequency points is completed, that is, the layout of one frame of image is completed and displayed.

[0024] Technical effects and advantages of the present invention: 1. The present invention utilizes heterogeneous software and hardware combined design to give full play to the performance and advantages of software and hardware and achieve more efficient computing and data processing capabilities.

[0025] 2. The present invention designs a parallel digital persistence processing architecture based on FPGA, which can improve the speed of signal processing, enhance the real-time performance of signal processing, and facilitate the observation of instantaneous small signals.

[0026] 3. The present invention adds a hardware-based vector interpolation method, which can complete the data processing of vector persistence more quickly. Through the configuration of the host computer, different modes of digital persistence display can be performed. The interpolation configuration method can further optimize the image display effect and facilitate the observation of signal information characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is an overall implementation process architecture diagram of a method for implementing a multi-channel parallel persistence display technology based on FPGA of the present invention; Figure 2 It is a point-like probability statistics implementation architecture diagram of an implementation method of a multi-channel parallel persistence display technology based on FPGA of the present invention; Figure 3It is a vector interpolation implementation framework diagram of a method for implementing a multi-channel parallel persistence display technology based on FPGA of the present invention; Figure 4 It is a multi-channel parallel vector interpolation effect diagram of a method for realizing a multi-channel parallel persistence display technology based on FPGA of the present invention; Figure 5 It is a persistence processing flow chart of a method for realizing a multi-channel parallel persistence display technology based on FPGA of the present invention; Figure 6 The present invention is a host computer afterglow display data arrangement diagram of a method for realizing a multi-channel parallel afterglow display technology based on FPGA. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] See also Figure 1 As shown in FIG. 1 , an overall implementation process architecture diagram of an implementation method of a multi-channel parallel persistence display technology based on FPGA is shown, and the implementation steps are as follows: Step 1: Spectral data preprocessing The calculated linear and logarithmic spectrum data are selected and output according to the needs. The spectrum data is preprocessed. The matrix used for spectrum persistence display is 1024×768, which means that the power value is discretized into 768 units and the frequency range is discretized into 1024 units. The power value of each frequency point is divided by the step value of the power value to obtain the position of the power value of the frequency point in the display unit, which is implemented using Divider IP. The calculation formula is as follows:

[0030] Where: L is the power value of the frequency point in the display unit, Indicates the power value of the frequency point. Indicates the step size of the power value of the host computer display unit.

[0031] Use true dual-port RAM to store the frequency probability value of each channel. Every 768 addresses correspond to a frequency point. Each RAM processes 64 frequency points, so the number of addresses of a RAM is 49152. The corresponding address of the frequency point probability value is calculated according to the formula. The calculation formula is as follows:

[0032] Where: Addr represents the address of the RAM, N represents the count value of each frequency point in the range of 0 to 63, and L represents the position of the power value of the frequency point in the display unit.

[0033] Step 2: Pointwise Probability Statistics See also Figure 2 As shown in the figure, the point probability statistics implementation architecture diagram is implemented by a true dual-port RAM. Both read and write ports of the RAM are used, one port is used for read operation, and the other port is used for write operation. The two ports are performed simultaneously. After obtaining the address, the value of the RAM is read through the address, and the read value is added by one, that is, the frequency probability value is added by one, and then written to the address. The number of superimposed frames of the spectrum probability is controlled by the host computer configuration. When the set number of frames is reached, the spectrum probability is output. In order to prevent data loss, two true dual-port RAMs are designed, and probability statistics and output are performed using data ping-pong.

[0034] Step 3: Vector interpolation processing See also Figure 3 As shown, when performing vector interpolation, adjacent frequency points are compared. When they are discontinuous, interpolation processing is performed. The vector comparison method is used to take frequency point i, and the maximum address addr_max(i) and the minimum address addr_min(i) of the probability statistical value of the frequency point are obtained by comparison. The frequency point i+1 is taken, and the maximum address addr_max(i+1) and the minimum address addr_min(i+1) of the probability statistical value of the frequency point are obtained by the same method. When the value of addr_max(i) is less than the value of addr_min(i+1), and the difference is greater than 1, the frequency point i+1 needs to be interpolated. The calculation formula for the interpolation address range is:

[0035]

[0036] When the value of addr_max(i+1) is less than the value of addr_min(i) and the difference is greater than 1, it is necessary to interpolate the frequency point i. The calculation formula for the interpolation address range is:

[0037]

[0038] Among them: add_addr_max represents the maximum address of interpolation, add_addr_min represents the maximum address of interpolation, The size of the interpolation data can be configured by the host computer according to the display effect of the image. The sixteenth data of the first frame needs to be compared with the first data of the second frame. At this time, it is necessary to perform storage processing. When all lines are interpolated, multiple data will be generated. At this time, the data of the same number of lines needs to be merged. Here, the comparison method is used, that is, the data of the same line is compared, the same ones are retained, and the maximum value of the two sets of data is retained if they are different. The retained data is the output of the vector interpolation of this line. For the effect of vector interpolation, please refer to Figure 4 shown.

[0039] Step 4: Afterglow Processing See also Figure 5 and Figure 6 As shown, the persistence mode can only output one of the point probability statistics and vector interpolation statistics. Therefore, the host computer selects one of the two data for output, and the output data enters the persistence module for persistence processing. The persistence module is mainly divided into three modes: infinite persistence, no persistence and variable persistence. Infinite persistence means data superposition display, and the output data is accumulated in units of each frame. The infinite persistence calculation formula is as follows:

[0040] Where: data_out(i) is the output data of the i-th frame after afterglow processing, data(i) is the i-th frame input data of the previous module, i represents the number of output frames, no afterglow means no processing of the data, and the infinite afterglow calculation formula is as follows:

[0041] Variable persistence is the output of the first frame data. When the second frame data arrives, the output of the second frame data is the value of the first frame data multiplied by the variable coefficient and the sum of the second frame data. The output of the third frame data is the value of the second frame output multiplied by the variable coefficient and the sum of the second frame data. And so on. The calculation formula of variable persistence is as follows:

[0042]

[0043]

[0044] Recursively, the calculation formula for outputting data starting from the second frame is as follows:

[0045] Among them: data_out(i) is the output data of the i-th frame afterglow processing, data(i) is the i-th frame input data of the previous module, i represents the number of output frames, p represents the variable coefficient, there are four main variable coefficients, namely 0.75, 0.5, 0.25 and 0.125, and different digital afterglow modes are mainly realized through the state machine.

[0046] The digital persistence processing design is mainly implemented through true dual-port RAM. After the host computer configures the persistence output mode, when the first frame of data arrives, the first frame is output and the first frame of data is stored in RAM. When the second frame of data arrives, the data stored in RAM is taken out and processed according to the configured persistence mode. The processed result is output and stored in RAM at the same time. In this way, data processing is performed and the output data is transmitted to the host computer through PCIE for display.

[0047] Step 5: PC display The output data is transmitted to the upper computer display module through PCIE. The data needs to be rearranged for display. The transmitted data is 16 parallel data. Each clock transmits 16 frequency points of data at the same time. The method of displaying each frame of image data is to first layout the probability statistics of the first 16 frequency points, and then layout the probability statistics of the next 16 frequency points, and so on, until the probability statistics of 1024 frequency points are laid out, that is, the layout of one frame of image is completed and displayed. See Figure 6 , which is the data arrangement diagram of the host computer afterglow display.

[0048] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technical users in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for implementing multi-channel parallel persistence display technology based on FPGA, It is characterized in that The spectrum data is preprocessed, and point probability statistics and vector interpolation statistics are performed in parallel in multiple channels, as well as different persistence modes are implemented.

2. The method for implementing the multi-channel parallel persistence display technology based on FPGA according to claim 1, It is characterized in that Preprocess the spectrum data. The matrix used for spectrum persistence display is 1024×768, which means that the power value is discretized into 768 units and the frequency range is discretized into 1024 units. The power value of each frequency point is divided by the step value of the power value to obtain the position of the power value of the frequency point in the display unit. This is implemented using the Divider IP. The calculation formula is as follows: Where: L is the power value of the frequency point in the display unit, Indicates the power value of the frequency point. Indicates the step size of the power value of the host computer display unit.

3. The method for realizing the multi-channel parallel persistence display technology based on FPGA according to claim 1, It is characterized in that Use true dual-port RAM to store the frequency probability value of each channel. Every 768 addresses correspond to a frequency point. Each RAM processes 64 frequency points, so the number of addresses of a RAM is 49152. The corresponding address of the frequency point probability value is calculated according to the formula. The calculation formula is as follows: Where: Addr represents the address of the RAM, N represents the count value of each frequency point in the range of 0 to 63, and L represents the position of the power value of the frequency point in the display unit.

4. The method for implementing a multi-channel parallel persistence display technology based on FPGA according to claim 1, It is characterized in that Both read and write ports of the true dual-port RAM are used, one port is used for read operation and the other port is used for write operation. Both ports are performed simultaneously. After obtaining the address, the value of the RAM is read through the address, and the read value is added by one, that is, the frequency probability value is added by one, and then written to the address. The number of superimposed frames of the spectrum probability is controlled by the host computer configuration. When the set number of frames is reached, the spectrum probability is output. In order to prevent data loss, two true dual-port RAMs are designed, and probability statistics and output are performed using data ping-pong.

5. The method for realizing the multi-channel parallel persistence display technology based on FPGA according to claim 1, It is characterized in that After completing the point probability statistics, in order to make the afterglow display of adjacent frequency points continuous, the vector interpolation method can be used to connect the discrete probability points so that the image display is smoother. Here, the frequency point comparison method is used for interpolation.

6. The method for realizing the multi-channel parallel persistence display technology based on FPGA according to claim 5, It is characterized in that When performing vector interpolation, adjacent frequency points are compared. When they are discontinuous, interpolation is performed. In the vector comparison method, frequency point i is taken, and the maximum address addr_max(i) and the minimum address addr_min(i) of the probability statistics value of the frequency point are obtained by comparison. Frequency point i+1 is taken, and the maximum address addr_max(i+1) and the minimum address addr_min(i+1) of the probability statistics value of the frequency point are obtained by the same method. When the value of addr_max(i) is less than the value of addr_min(i+1), and the difference is greater than 1, the frequency point i+1 needs to be interpolated. The calculation formula for the interpolation address range is: When the value of addr_max(i+1) is less than the value of addr_min(i) and the difference is greater than 1, it is necessary to interpolate the frequency point i. The calculation formula for the interpolation address range is: Wherein: add_addr_max indicates the maximum address of interpolation, add_addr_min indicates the minimum address of interpolation, and the size of interpolation data can be configured by the host computer according to the display effect of the image. The sixteenth data of the first frame needs to be compared with the first data of the second frame. At this time, storage processing is required. When all lines are interpolated, multiple data will be generated. At this time, the data of the same number of lines needs to be merged. Here, the comparison method is used, that is, the data of the same line are compared, the same ones are retained, and the different ones are retained by taking the maximum value of the two sets of data. The retained data is the output of the vector interpolation of this line.

7. The method for realizing the multi-channel parallel persistence display technology based on FPGA according to claim 1, It is characterized in that The persistence mode can only output one of the point probability statistics and vector interpolation statistics. Therefore, the host computer selects one of the two data for output, and the output data enters the persistence module for persistence processing. The persistence module is mainly divided into three modes: infinite persistence, no persistence and variable persistence. Infinite persistence means data superposition display, and the output data is accumulated in units of each frame. The infinite persistence calculation formula is as follows: Where: data_out(i) is the output data of the i-th frame after afterglow processing, data(i) is the i-th frame input data of the previous module, i represents the number of output frames, no afterglow means no processing of the data, and the infinite afterglow calculation formula is as follows: Variable persistence is the output of the first frame data. When the second frame data arrives, the output of the second frame data is the value of the first frame data multiplied by the variable coefficient and the sum of the second frame data. The output of the third frame data is the value of the second frame output multiplied by the variable coefficient and the sum of the second frame data. And so on. The calculation formula of variable persistence is as follows: Recursively, the calculation formula for outputting data starting from the second frame is as follows: Among them: data_out(i) is the output data of the i-th frame afterglow processing, data(i) is the i-th frame input data of the previous module, i represents the number of output frames, p represents the variable coefficient, there are four main variable coefficients, namely 0.75, 0.5, 0.25 and 0.125, and different digital afterglow modes are mainly realized through the state machine.

8. The method for realizing the multi-channel parallel persistence display technology based on FPGA according to claim 1, It is characterized in that The host computer configures the digital persistence mode to process and output data, which is mainly achieved through the true dual-port RAM. After the host computer configures the persistence output mode, when the first frame of data arrives, the first frame is output and the first frame of data is stored in the RAM. When the second frame of data arrives, the data stored in the RAM is taken out and processed according to the configured persistence mode. The processed results are output and stored in the RAM at the same time. In this way, data processing is performed and the output data is transmitted to the host computer through PCIE for display.

9. The method for realizing the multi-channel parallel persistence display technology based on FPGA according to claim 8, It is characterized in that The output data is transmitted to the upper computer display module through PCIE. The data needs to be rearranged for display. The transmitted data is 16 parallel data. Each clock transmits data of 16 frequency points at the same time. The method of displaying each frame of image data is to first layout the probability statistical values ​​of the first 16 frequency points, and then layout the probability statistical values ​​of the next 16 frequency points, and so on, until the layout of the probability statistical values ​​of 1024 frequency points is completed, that is, the layout of one frame of image is completed and displayed.

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