Chip testing system, method, device, terminal equipment and readable storage medium

Abstract

The application is suitable for the chip testing technical field, and provides a chip testing system, method, device, terminal equipment and readable storage medium, which are characterized in that: a probe station and a tester are included; the tester obtains level information corresponding to each bit of a to-be-tested signal of a to-be-tested chip in N signal periods, wherein the level information includes high level and low level, and N is greater than or equal to 1; the tester performs quantity statistics on the level information corresponding to each bit of the to-be-tested signal in the N signal periods to determine a maximum continuous high level quantity and a maximum continuous low level quantity; the tester performs calculation according to the maximum continuous high level quantity and the maximum continuous low level quantity to obtain a duty cycle of the to-be-tested chip; and the tester sends the duty cycle of the to-be-tested chip to the probe station. The application has high practicability, is simple to use, and can quickly and accurately test the duty cycle of a chip.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of chip testing, and particularly relates to a chip testing system, method, device, terminal equipment and readable storage medium. BACKGROUND

[0002] In the field of chip testing, since the duty cycle has an important influence on the function and performance of a chip, it is particularly important to test whether the duty cycle of the chip meets the design rules.

[0003] The duty cycle of a chip refers to the proportion of the time in a high (or low) state to the entire time period in a time period. The duty cycle of a chip has an important influence on the function and performance of the chip. The duty cycle of a chip directly affects its power consumption and heat generation. Generally, the higher the duty cycle, the greater the power consumption of the chip and the more heat it generates. Therefore, for applications requiring low power consumption and low heat, it is necessary to reduce the duty cycle of the chip as much as possible. The duty cycle of a chip affects its stability and reliability. Especially when running at high frequency, an inappropriate duty cycle can cause signal distortion and circuit instability. Therefore, for applications requiring high stability and reliability, the duty cycle of the chip needs to be precisely controlled. In a communication system, the duty cycle of a chip directly affects the communication rate. The higher the duty cycle, the higher the frequency of the signal, and the faster the communication rate. Therefore, when designing a communication chip, the duty cycle needs to be reasonably selected according to the communication requirements to achieve the required communication rate. In some applications, the timing requirements of a chip have strict restrictions on the duty cycle. For example, for some timing-sensitive applications such as high-speed bus communication or synchronous data transmission, the duty cycle must be within a certain range to meet the timing requirements, otherwise it may cause communication errors or data loss. The duty cycle of a chip also affects its circuit design. When designing, the influence of the duty cycle on the circuit, such as clock division, power management and signal processing, needs to be considered to ensure the normal operation of the circuit and the performance indicators meet the standards.

[0004] However, when the existing hardware environment does not support the use of Time Management Unit (TMU) hardware resources, the chip duty cycle cannot be measured. SUMMARY

[0005] The embodiments of the present application provide a chip testing system, method, device, terminal equipment and readable storage medium, which can solve the problem that the chip duty cycle cannot be measured when the existing hardware environment does not support the use of Time Management Unit (TMU) hardware resources.

[0006] In a first aspect, the embodiments of the present application provide a chip testing system, comprising: a probe station and a tester, wherein the probe station is electrically connected to the tester.

[0007] The test instrument obtains level information corresponding to each bit of a to-be-tested signal of a to-be-tested chip in N signal periods, wherein the level information includes high level and low level, and N≥1.

[0008] The test instrument counts the level information corresponding to each bit of the to-be-tested signal in the N signal periods to determine a maximum number of continuous high levels and a maximum number of continuous low levels.

[0009] The test instrument calculates a duty cycle of the to-be-tested chip according to the maximum number of continuous high levels and the maximum number of continuous low levels.

[0010] The test instrument sends the duty cycle of the to-be-tested chip to the probe station.

[0011] In a possible implementation of the first aspect, the obtaining of the level information corresponding to each bit of the to-be-tested signal of the to-be-tested chip in the N signal periods includes:

[0012] The level information corresponding to each bit of the to-be-tested signal of the to-be-tested chip in the N signal periods is obtained by capturing and storing the level information of the chip pin signal.

[0013] In a possible implementation of the first aspect, the chip testing system further includes a probe card arranged on the probe station, and the test instrument obtains the to-be-tested signal of the to-be-tested chip through the probe card.

[0014] In a possible implementation of the first aspect, N≤2.

[0015] In a possible implementation of the first aspect, the counting of the level information corresponding to each bit of the to-be-tested signal in the N signal periods to determine the maximum number of continuous high levels and the maximum number of continuous low levels includes:

[0016] It is determined whether the level information corresponding to each bit of the to-be-tested signal in the N signal periods is a high level or a low level.

[0017] For a case where the current bit is a high level, it is continuously determined whether each bit appearing subsequently is a high level, and when a bit appearing subsequently is a high level, the number of continuous high levels is increased by 1, until the bit appearing subsequently is a low level, or the process is ended when no bit appears subsequently.

[0018] When the subsequent bit is low, it is determined whether the current continuous high level number after one or more times of increasing 1 is greater than the first number threshold, and if yes, the first number threshold is updated as the current continuous high level number, the current continuous low level number is set as 1, and the step of the current bit being low is performed, where the first number threshold is initially 1;

[0019] For the case that the current bit is low, it is continuously determined whether each subsequent bit is low, and when a subsequent bit is low, the continuous low level number is increased by 1 until the subsequent bit is high, or the process ends if there is no subsequent bit;

[0020] When the subsequent bit is high, it is determined whether the current continuous low level number after one or more times of increasing 1 is greater than the second number threshold, and if yes, the second number threshold is updated as the current continuous low level number, the current continuous high level number is set as 1, and the step of the current bit being high is performed, where the second number threshold is initially 1;

[0021] When the level information corresponding to the last bit is determined, the current first number threshold is determined as the maximum continuous high level number, and the current second number threshold is determined as the maximum continuous low level number.

[0022] In a possible implementation of the first aspect, the calculating according to the maximum continuous high level number and the maximum continuous low level number to obtain the duty cycle of the chip to be tested comprises:

[0023] determining a total number of levels according to the maximum continuous high level number and the maximum continuous low level number;

[0024] determining the duty cycle of the chip to be tested according to the total number of levels and any one of the maximum continuous high level number and the maximum continuous low level number.

[0025] In a second aspect, an embodiment of the present application provides a chip testing method, comprising:

[0026] obtaining level information corresponding to each bit of a signal to be tested of a chip to be tested in N signal periods, where the level information comprises high level and low level, and N≥1;

[0027] performing number statistics on the level information corresponding to each bit of the signal to be tested of the chip to be tested in the N signal periods to determine a maximum continuous high level number and a maximum continuous low level number;

[0028] calculating according to the maximum continuous high level number and the maximum continuous low level number to obtain a duty cycle of the chip to be tested.

[0029] In a third aspect, an embodiment of the present application provides a chip testing device, comprising:

[0030] an information obtaining module, configured to obtain level information corresponding to each bit of a to-be-tested signal of a to-be-tested chip in N signal periods, wherein the level information comprises a high level and a low level, and N is greater than or equal to 1;

[0031] a quantity counting module, configured to count the level information corresponding to each bit of the to-be-tested signal in the N signal periods, to determine a maximum number of continuous high levels and a maximum number of continuous low levels;

[0032] a result calculating module, configured to calculate the maximum number of continuous high levels and the maximum number of continuous low levels, to obtain a duty cycle of the to-be-tested chip.

[0033] In a fourth aspect, an embodiment of the present application provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor implements the chip testing method in the second aspect when executing the computer program.

[0034] In a fifth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the chip testing method in the second aspect.

[0035] Compared with the prior art, the embodiment of the present application has the beneficial effects that the embodiment of the present application achieves the technical effect of chip duty cycle testing without using time measurement module hardware resources and without changing hardware design, and the embodiment of the present application does not need manual manual welding circuit and does not need to change existing test resources. The probe table and the tester electrically connected to each other cooperate with each other, the tester obtains level information corresponding to each bit of a to-be-tested signal of a to-be-tested chip in N signal periods, the tester counts the level information corresponding to each bit of the to-be-tested signal in the N signal periods, to determine a maximum number of continuous high levels and a maximum number of continuous low levels, the tester calculates the maximum number of continuous high levels and the maximum number of continuous low levels, to obtain a duty cycle of the to-be-tested chip, and the tester sends the duty cycle of the to-be-tested chip to the probe table. Through actual verification, the present application has high practicability, is simple to use, and can quickly and accurately test the chip duty cycle.

[0036] Through the practice and application in actual production, the chip test system can simply and quickly meet the requirements of customers on chip duty cycle test, debugging is simple and easy to understand, the debugging period is short, a large amount of time is saved, and the debugging work is more efficient, fast and high quality. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0038] Figure 1 is a schematic diagram of a chip test system provided by an embodiment of the present application;

[0039] Figure 2 is a schematic diagram of resource allocation of a square card public board of a Chroma tester provided by an embodiment of the present application;

[0040] Figure 3 is a schematic diagram of a flow provided by the present application on the basis of the chip test system embodiment; Figure 1

[0041] Figure 4 is another schematic diagram of a flow provided by the present application on the basis of the chip test system embodiment; Figure 1

[0042] Figure 5 is a schematic diagram of a flow of program running provided by an application embodiment of the present application;

[0043] Figure 6 is a schematic diagram of a flow of a chip test method provided by another embodiment of the present application;

[0044] Figure 7 is a schematic diagram of a structure of a chip test device provided by another embodiment of the present application;

[0045] Figure 8 is a structure example diagram of a terminal device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0046] In the following description, specific details such as specific system structures, techniques, etc. are presented in order to thoroughly understand the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits and methods are omitted to avoid unnecessary details that hinder the description of the present application. ​​

[0047] It should be understood that the word "comprise" or variations such as "comprises" or "comprising", when used in this specification and in the accompanying claims, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] It should also be understood that the term "and / or" when used in this specification and in the following claims is to be interpreted as open language, not as limiting, such that at least one of the items can be present, and the maximum number of items is not limited to only one.

[0049] As used in this specification and in the claims, the terms "if" and "when" can be interpreted to mean "upon" or "in response to a determination" or "in response to a detection" depending on the context.

[0050] In addition, the terms "first", "second", "third", etc. are used herein only to distinguish one element from another and do not imply a relative importance of the elements.

[0051] Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, although it can. The terms "including," "comprising," "having" and variations thereof are meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

[0052] Since the duty cycle of a chip has an important influence on the function and performance of the chip, it is particularly important to test whether the chip duty cycle meets the design rules, and then how to test the chip duty cycle without using the hardware resources of the time measurement module. The present application is a chip test scheme for testing whether the chip duty cycle can meet the expected design of the chip.

[0053] Figure 1 is a schematic diagram of a chip test system provided by an embodiment of the present application. As shown in the figure, the chip test system comprises a chip test device 1 and a chip 2. Figure 1As shown, the system comprises a probe station 10 and a tester 11, and the probe station 10 is electrically connected to the tester 11.

[0054] The probe station 10 can be a UF300 probe station, for example. The UF300 probe station is a fully automated general-purpose probe station suitable for a variety of applications with a modular concept, six-stage Z-axis, SR-3300 vision system, and laser pattern recognition function. The UF300 probe station can achieve high-precision wafer and mold testing with maximum throughput and accuracy while requiring minimal manual intervention.

[0055] The tester 11 can be a Chroma tester, for example. The Chroma tester belongs to a chip tester that has been widely used.

[0056] Here, the probe station 10 can control the movement of the wafer so that each chip at different positions on the wafer is tested. After the tester 11 tests the duty cycles of different chips on the wafer, the tester 11 sends the duty cycles of different chips to the probe station 10. The probe station 10 can determine whether the chips meet the design expectations based on the duty cycles of the chips, such as whether the duty cycles are within the 49%-51% range. The probe station 10 and the tester 11 jointly complete the testing of the chips.

[0057] In one embodiment, the chip testing system can further comprise a signal source. The signal source transmits an input signal (the input signal frequency is 10 khz, for example) to the tester 11 through a signal line. The tester 11 transmits the input signal to the chip to be tested so that the chip to be tested can work normally. Here, the chip to be tested needs to be continuously supplied with the input signal and VDD voltage to work normally.

[0058] In one embodiment, the chip testing system further comprises a probe card arranged on the probe station 10, and the tester 11 obtains the test signal of the chip to be tested through the probe card.

[0059] Here, the probe card can be a square card public board of the Chroma tester, for example, and there are 16 sites in total. The corresponding resource allocation can be seen from Figure 2 The SDA and SCL pins used in the embodiments of the present application.

[0060] Here, the probe station 10 can control the movement of the wafer so that each chip at different positions on the wafer is in contact with the probe card for chip testing.

[0061] The embodiments of the present application use the probe card to transmit the test signal of the chip to be tested to the tester, and only need to slightly modify the test vector of the measured pin to perform testing, without the need to change the hardware environment, which can improve the convenience and ease of data transmission and improve the convenience of debugging.

[0062] Figure 3 is Figure 1 A flowchart is provided based on the chip testing system embodiment.

[0063] As Figure 3 shown, in S11, the tester 11 obtains the level information corresponding to each bit of the to-be-tested signal of the to-be-tested chip in N signal periods, wherein the level information includes high level and low level, and N≥1.

[0064] Here, the signal period of the to-be-tested signal can be determined based on the frequency of the to-be-tested signal. The distribution of the high level and low level information of the to-be-tested signal in each signal period is the same. For example, one signal period of the to-be-tested signal is 6 ms, which includes the level information of 6 bits, the first 3 bits are high level, and the last 3 bits are low level. It can be understood that the to-be-tested signal will continue to repeat accordingly. Since the specific time point at which each signal period of the to-be-tested signal starts cannot be determined, the tester 11 can obtain the level information corresponding to each bit of the to-be-tested signal of the to-be-tested chip in more than one signal period to obtain at least one complete signal period of the to-be-tested signal.

[0065] In one embodiment, 1≤N≤2. For example, N can be 1.5, 1.6, 1.7, 1.8, etc.

[0066] In the embodiment of the present application, by setting the to-be-tested signal of 1 to 2 signal periods, on the one hand, the chip testing can be quickly performed, and on the other hand, the reliability of the chip testing result is ensured, and the effectiveness of the overall chip testing scheme is improved.

[0067] In one embodiment, the tester 11 obtains the level information corresponding to each bit of the to-be-tested signal of the to-be-tested chip in N signal periods, including:

[0068] The tester 11 obtains the level information corresponding to each bit of the to-be-tested signal of the to-be-tested chip in N signal periods based on the level information capture of the chip pin signal by the capture memory (Capture Memory) function. Here, the tester 11 is, for example, a Chroma tester, and the Capture Memory function of the Chroma tester can realize the digitization of the waveform. The Chroma tester performs K capture by the Capture Memory function, and the program statement is “SET_CAPTURE_MEM_MODE (Pin_name, PEL_K, ON, 16K)”.

[0069] Here, the Capture Memory function of the Chroma tester can record and capture the three states of the output of the chip under test as high level (H), low level (L) and high impedance state (Z):

[0070] - Read the readings in some registers of the chip under test, such as ADC convert data and trimming data.

[0071] - When the customer needs to more intuitively reflect some data information (such as Unique ID) in the chip register to the test data (datalog), the Capture Memory needs to be used to read back the data for processing, and then printed to the data (log) through JUDGE_VARIABLE.

[0072] - Signals that cannot be processed by the general IMATCH function need to use Capture Memory to read back all signals in a period of time, and then processed through an algorithm.

[0073] The overall function overview of the Capture Memory function of the Chroma tester includes:

[0074] - MXLPC / SNPEC default function, supported by 3360 / 3380 series.

[0075] - 8 pins per group, with a maximum of single pin 64K data and a minimum of per pin 8K data.

[0076] - Support for three capture modes (PEL, PEH, PFAIL).

[0077] - Support for two trigger methods (H / L / Z fail trigger in pattern, K symbol trigger in pattern).

[0078] - Any pin can be assigned to any site (supporting use in APAS mode).

[0079] - Maximum test vector (pattern) frequency of 100Mhz.

[0080] Here, the embodiments of the present application use the Capture Memory function of the Chroma tester to capture the level information of the chip pin signals, so that the test chip duty cycle can be realized without using the hardware resources of the time measurement module, greatly saving the hardware cost and improving the use efficiency.

[0081] In S12, the tester 11 counts the number of the level information corresponding to each bit in the N signal periods of the to-be-tested signal, to determine the maximum number of continuous high levels and the maximum number of continuous low levels.

[0082] Here, the maximum number of continuous high levels refers to the number of the maximum number of high levels in the case of continuous high levels of multiple bits in the N signal periods. The maximum number of continuous low levels refers to the number of the maximum number of low levels in the case of continuous low levels of multiple bits in the N signal periods. For example, 2 continuous high levels and then 2 continuous low levels occur in 1 signal period (4 bits). The tester 11 obtains 1.5 signal periods (6 bits) of the to-be-tested signal, and the level information corresponding to each bit is: 1 high level, 2 low levels, 2 high levels, and 1 low level. The tester 11 counts the number of the level information corresponding to each bit in the 1.5 signal periods, to determine that the maximum number of continuous high levels is 2 and the maximum number of continuous low levels is 2.

[0083] Those skilled in the art should understand that steps S11 and S12 have no strict sequence. In an embodiment, the tester 11 can obtain the level information corresponding to each bit in the N signal periods of the to-be-tested signal of the to-be-tested chip, and then count the number of the level information corresponding to each bit in the N signal periods. In another embodiment, the tester 11 can count the number of the level information corresponding to the first bit in the N signal periods after obtaining the level information corresponding to the first bit, and then count the number of the level information corresponding to the second bit after obtaining the level information corresponding to the second bit, and so on, until counting the number of the level information corresponding to the last bit after obtaining the level information corresponding to the last bit. Those skilled in the art should understand that the tester 11 can set other sequences of S11 and S12 according to actual needs. The technical solutions of the tester 11 in other sequences of S11 and S12 should also belong to the protection scope of the present application.

[0084] In an embodiment, as shown in FIG. 1, the counting of the number of the level information corresponding to each bit in the N signal periods of the to-be-tested signal, to determine the maximum number of continuous high levels and the maximum number of continuous low levels, includes: Figure 4

[0085] ​S51: judge whether the level information corresponding to the first bit to the last bit of the signal to be tested in N signal periods is high or low; if the first bit is high, go to S521, and if the first bit is low, go to S531;

[0086] S521: for the case that the current bit is high, continuously determine whether each bit appearing subsequently is high; when a bit appearing subsequently is high, the number of continuous high levels is increased by 1, until a bit appearing subsequently is low, go to S522, and if there is no subsequent bit, end;

[0087] S522: when a bit appearing subsequently is low, determine whether the current number of continuous high levels after increasing 1 for one or more times is greater than a first number threshold; if yes, update the first number threshold to the current number of continuous high levels, set the current number of continuous low levels to 1, and go to the step S531 that the current bit is low, wherein the first number threshold is initially 1;

[0088] S531: for the case that the current bit is low, continuously determine whether each bit appearing subsequently is low; when a bit appearing subsequently is low, the number of continuous low levels is increased by 1, until a bit appearing subsequently is high, go to S532, and if there is no subsequent bit, end;

[0089] S532: when a bit appearing subsequently is high, determine whether the current number of continuous low levels after increasing 1 for one or more times is greater than a second number threshold; if yes, update the second number threshold to the current number of continuous low levels, set the current number of continuous high levels to 1, and go to the step S521 that the current bit is high, wherein the second number threshold is initially 1;

[0090] S54: when the level information corresponding to the last bit is determined, determine the current first number threshold as the maximum number of continuous high levels, and determine the current second number threshold as the maximum number of continuous low levels.

[0091] In the previous example, two high levels appear in succession in one signal period (4 bits), followed by two successive low levels. The tester 11 obtains 1.5 signal periods (6 bits), and the levels corresponding to the bits appear in the following order: one high level, two low levels, two high levels, and one low level. The tester 11 continuously determines the level information corresponding to the first bit to the sixth bit in the 1.5 signal periods in S51. Since the first bit is a high level, go to S521. In S521, the tester 11 determines whether the second bit is a high level. Since the second bit is a low level, the number of successive high levels does not increase by one, and go to S522. In S522, the current number of successive high levels is one, which is not greater than the first number threshold (1), and go to S531. In S531, the tester 11 determines that the second bit is a low level and the third bit is a low level, and the number of successive low levels increases by one. Until the tester 11 determines that the fourth bit is a high level, go to S532. In S532, the current number of successive low levels (2) after increasing by one is greater than the second number threshold (1), and the second number threshold is updated to 2. Since the fourth bit is a high level, the current number of successive high levels is one, and go to S521 for the second time. In the second time of going to S521, the tester 11 determines that the fourth bit is a high level and the fifth bit is a high level, and the number of successive high levels increases by one. Until the tester 11 determines that the sixth bit is a low level, go to S522 for the second time. In the second time of going to S522, the current number of successive high levels (2) after increasing by one is greater than the first number threshold (1), and the first number threshold is updated to 2. Since the sixth bit is a low level, the current number of successive low levels is one, and go to S531 for the second time. In the second time of going to S531, since there is no subsequent bit, the tester 11 ends this step. In S54, when the level information corresponding to the last (sixth) bit is determined, the current first number threshold (2) is determined as the maximum number of successive high levels, and the current second number threshold (2) is determined as the maximum number of successive low levels.

[0092] The embodiment of the present application obtains the maximum number of successive high levels and the maximum number of successive low levels through loop calculation, which can simply and quickly meet the requirements of customers on chip duty cycle testing, shorten the debugging period, and make the debugging work more efficient, fast, and high quality.

[0093] In S13, the tester 11 calculates the duty cycle of the chip to be tested according to the maximum number of successive high levels and the maximum number of successive low levels.

[0094] As in the previous example, the tester 11 calculates the duty cycle of the chip under test according to the maximum number of consecutive high levels (2) and the maximum number of consecutive low levels (2), and obtains the duty cycle of the chip under test = 2 / (2+2) = 50%.

[0095] In one embodiment, the calculation of the duty cycle of the chip under test according to the maximum number of consecutive high levels and the maximum number of consecutive low levels comprises:

[0096] determining the total number of levels according to the maximum number of consecutive high levels and the maximum number of consecutive low levels;

[0097] determining the duty cycle of the chip under test according to the total number of levels and either the maximum number of consecutive high levels or the maximum number of consecutive low levels.

[0098] Here, the total number of levels is the sum of the maximum number of consecutive high levels and the maximum number of consecutive low levels. The tester 11 can determine the duty cycle as the proportion of the maximum number of consecutive high levels to the total number of levels. The tester 11 can also determine the duty cycle as the proportion of the maximum number of consecutive low levels to the total number of levels.

[0099] The embodiments of the present application simplify the duty cycle test algorithm and scheme by calculating the duty cycle of the chip under test using the maximum number of consecutive high levels and the maximum number of consecutive low levels, and can simply and quickly meet the needs of customers for chip duty cycle testing.

[0100] In S14, the tester 11 sends the duty cycle of the chip under test to the probe station 10.

[0101] Here, the tester 11 sends the calculated duty cycle of the chip under test to the probe station 10. The probe station 10 can determine whether the chip under test is qualified based on whether the determined duty cycle (e.g., 50%) meets a predetermined interval range (e.g., 49%-51%).

[0102] In one embodiment, the tester 11 and the probe station 10 can also print the duty cycle result to the test record.

[0103] In order to solve the technical problem of duty cycle test of the chip without hardware resources of the time module, the embodiment of the application realizes the technical effect of chip duty cycle test without changing the hardware design, and only needs to modify the test vector (pattern) of the measured pin and the program code of the tester, without manual manual area welding circuit and without changing the existing test resources. The probe station and the tester cooperate with each other, the tester obtains the level information corresponding to each bit in N signal periods of the to-be-tested signal of the to-be-tested chip, the tester counts the level information corresponding to each bit in N signal periods of the to-be-tested signal to determine the maximum number of continuous high levels and the maximum number of continuous low levels, the tester calculates the duty cycle of the to-be-tested chip according to the maximum number of continuous high levels and the maximum number of continuous low levels, and the tester sends the duty cycle of the to-be-tested chip to the probe station. Through actual verification, the application has high practicability, is simple to use, can quickly and accurately test the chip duty cycle.

[0104] Through practice and application in actual production, the embodiment of the application can simply and quickly meet the requirements of customers on chip duty cycle test, is simple and easy to understand, has a short debugging period, saves a large amount of time, and makes the debugging work more efficient, fast and high-quality.

[0105] In one application embodiment, the application scheme can be realized through a program. When the program starts running, K capture is first performed through the Capture Memory function of the Chroma tester, and the program statement is "SET_CAPTURE_MEM_MODE (Pin_name, PEL_K, ON, 16K)". Before testing, the size of the test frequency needs to be known, and 1.5 signal periods are optimal. Then the maximum number of continuous high levels (H) and the maximum number of continuous low levels (L) are screened out through for loop and if statement. Finally, the result of the chip duty cycle is obtained through calculation (H / H+L)*100%. The program statement is as follows:

[0106]

[0107]

[0108] Figure 5 The flowchart of the above program is shown in the figure. Figure 5As shown in FIG. 5, in S501, the Capture Memory function of the Chroma tester performs capturing. In S502, the Chroma tester calculates the maximum number of consecutive high levels, i.e., the maximum number of occurrences of high levels (H). In S503, the Chroma tester calculates the maximum number of consecutive low levels, i.e., the maximum number of occurrences of low levels (L). In S504, the Chroma tester calculates the duty cycle of the chip, i.e., Cuty = H / (H+L)*100%. In S505, the Chroma tester calculates the end. In S506, the Chroma tester prints the result to the test log.

[0109] Figure 6 FIG. 6 is a flowchart of a chip testing method according to another embodiment of the present application.

[0110] As shown in FIG. 6, the chip testing method includes the following steps. Figure 6

[0111] S61, obtaining level information corresponding to each bit of a to-be-tested signal of a to-be-tested chip in N signal periods, wherein the level information includes high levels and low levels, and N≥1.

[0112] S62, performing number statistics on the level information corresponding to each bit of the to-be-tested signal in the N signal periods to determine a maximum number of consecutive high levels and a maximum number of consecutive low levels.

[0113] S63, calculating a duty cycle of the to-be-tested chip according to the maximum number of consecutive high levels and the maximum number of consecutive low levels.

[0114] Another embodiment of the present application discloses another chip testing method. This embodiment is based on the above-mentioned corresponding embodiment, and step S61 specifically includes the following steps. Figure 6

[0115] The level information corresponding to each bit of the to-be-tested signal of the to-be-tested chip in the N signal periods is obtained by means of level information capturing of a tester.

[0116] Another embodiment of the present application discloses another chip testing method. This embodiment is based on the above-mentioned corresponding embodiment, and the to-be-tested signal of the to-be-tested chip is obtained by means of a probe card. Figure 6

[0117] Another embodiment of the present application discloses another chip testing method. This embodiment is based on the above-mentioned corresponding embodiment, and 1≤N≤2. Figure 6 Another embodiment of the present application discloses another chip testing method. This embodiment is based on the above-mentioned corresponding embodiment, and 1≤N≤2. ​​

[0118] Another embodiment of the present application discloses another chip testing method. This embodiment is based on the above-mentioned Figure 6 According to the corresponding embodiment, step S62 specifically comprises:

[0119] S621: continuously determine whether the level information corresponding to each bit from the first bit to the last bit of the to-be-tested signal in N signal periods is high or low; if the first bit is high, go to S6221, and if the first bit is low, go to S6231;

[0120] S6221: for the case that the current bit is high, continuously determine whether each subsequent bit is high; when a subsequent bit is high, the number of continuous high levels is increased by 1, and when a subsequent bit is low, go to S6222; if there is no subsequent bit, end;

[0121] S6222: determine whether the current number of continuous high levels after one or more times of increasing by 1 is greater than a first number threshold; if yes, update the first number threshold to the current number of continuous high levels, set the current number of continuous low levels to 1, and go to S6231, where the first number threshold is initially 1;

[0122] S6231: for the case that the current bit is low, continuously determine whether each subsequent bit is low; when a subsequent bit is low, the number of continuous low levels is increased by 1, and when a subsequent bit is high, go to S6232; if there is no subsequent bit, end;

[0123] S6232: determine whether the current number of continuous low levels after one or more times of increasing by 1 is greater than a second number threshold; if yes, update the second number threshold to the current number of continuous low levels, set the current number of continuous high levels to 1, and go to S6221, where the second number threshold is initially 1;

[0124] S624: when the level information corresponding to the last bit is determined, determine the current first number threshold as the maximum number of continuous high levels, and determine the current second number threshold as the maximum number of continuous low levels.

[0125] Another embodiment of the present application discloses another chip testing method. This embodiment is based on the above-mentioned Figure 6 According to the corresponding embodiment, step S63 comprises:

[0126] determine the total number of levels according to the maximum number of continuous high levels and the maximum number of continuous low levels;

[0127] The duty cycle of the chip to be tested is determined according to the total number of levels, and any one of the maximum number of continuous high levels and the maximum number of continuous low levels.

[0128] Figure 7 is a structural block diagram of a chip testing device provided by another embodiment of the present application.

[0129] As shown in Figure 7 , the chip testing device comprises:

[0130] An information obtaining module 71 is configured to obtain level information corresponding to each bit of a to-be-tested signal of a to-be-tested chip in N signal periods, wherein the level information comprises high levels and low levels, and N≥1.

[0131] A number counting module 72 is configured to count the level information corresponding to each bit of the to-be-tested signal in the N signal periods to determine the maximum number of continuous high levels and the maximum number of continuous low levels.

[0132] A result calculating module 73 is configured to calculate the maximum number of continuous high levels and the maximum number of continuous low levels to obtain the duty cycle of the to-be-tested chip.

[0133] Another embodiment of the present application discloses another chip testing device. Figure 7 Based on the above-mentioned corresponding embodiment, the information obtaining module 71 comprises:

[0134] A first obtaining unit is configured to obtain the level information corresponding to each bit of the to-be-tested signal of the to-be-tested chip in the N signal periods by capturing the level information of the chip pin signal based on the capture memory function of the tester.

[0135] Figure 7 Another embodiment of the present application discloses another chip testing device. Based on the above-mentioned

[0136] corresponding embodiment, the information obtaining module 71 is configured to obtain the to-be-tested signal of the to-be-tested chip through a probe card, and the probe card is arranged on a probe table. Figure 7 Another embodiment of the present application discloses another chip testing device.

[0137] Based on the above-mentioned Figure 7 corresponding embodiment, N≤2.

[0138] The first statistical unit continuously determines whether the level information corresponding to each bit from the first bit to the last bit in N signal periods is high or low, and if the first bit is high, the operation is transferred to the second statistical unit, and if the first bit is low, the operation is transferred to the fourth statistical unit.

[0139] The second statistical unit continuously determines whether each subsequent bit is high or low when the current bit is high, and when a subsequent bit is high, the number of continuous high levels is increased by 1, and the operation is transferred to the third statistical unit when a subsequent bit is low, and the operation is ended when there is no subsequent bit.

[0140] The third statistical unit determines whether the current number of continuous high levels after one or more times of increasing by 1 is greater than the first number threshold, and if yes, the first number threshold is updated to the current number of continuous high levels, the current number of continuous low levels is set to 1, and the operation is transferred to the fourth statistical unit, wherein the first number threshold is initially 1.

[0141] The fourth statistical unit continuously determines whether each subsequent bit is low or high when the current bit is low, and when a subsequent bit is low, the number of continuous low levels is increased by 1, and the operation is transferred to the fifth statistical unit when a subsequent bit is high, and the operation is ended when there is no subsequent bit.

[0142] The fifth statistical unit determines whether the current number of continuous low levels after one or more times of increasing by 1 is greater than the second number threshold, and if yes, the second number threshold is updated to the current number of continuous low levels, the current number of continuous high levels is set to 1, and the operation is transferred to the second statistical unit, wherein the second number threshold is initially 1.

[0143] The sixth statistical unit determines the maximum number of continuous high levels as the current first number threshold and the maximum number of continuous low levels as the current second number threshold when the level information corresponding to the last bit is determined.

[0144] Another embodiment of the application discloses another chip testing device. The embodiment is based on the above-mentioned Figure 7 Based on the corresponding embodiment, the result calculation module 73 comprises:

[0145] The first calculation unit determines the total number of levels according to the maximum number of continuous high levels and the maximum number of continuous low levels.

[0146] The second calculation unit determines the duty cycle of the chip to be tested according to the total number of levels and any one of the maximum number of continuous high levels and the maximum number of continuous low levels.

[0147] It should be noted that the information interaction, execution process and the like between the above method, device, unit are based on the same concept as the method embodiments of the present application, and the specific functions and technical effects brought by them can be referred to the system embodiment part. Therefore, details are not described here.

[0148] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The above integrated unit can be realized in the form of hardware or software. In addition, the specific name of each functional unit and module is only for convenient distinction, and does not limit the protection scope of the present application. The specific working process of the unit and module in the above system can refer to the corresponding process in the foregoing method embodiment, and details are not described here.

[0149] The embodiments of the present application also provide a terminal device, as shown in the figure. Figure 8 The terminal device 80 includes at least one processor 801, a memory 802, and a computer program 803 stored in the memory and executable on the at least one processor, and the processor executes the computer program to implement the steps in any of the above method embodiments.

[0150] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps in each of the above method embodiments.

[0151] The embodiments of the present application provide a computer program product, when the computer program product is run on a mobile terminal, so that the mobile terminal executes to implement the steps in each of the above method embodiments.

[0152] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the present application can implement all or part of the processes in the above-mentioned embodiment methods through a computer program to instruct relevant hardware to complete, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by a processor, the steps of each method embodiment described above can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable files or some intermediate forms. The computer readable medium at least includes any entity or device capable of carrying the computer program code to the photographing device / terminal equipment, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium. For example, U disk, mobile hard disk, magnetic disk or optical disk, etc. In some jurisdictions, according to legislation and patent practice, the computer readable medium can not be an electrical carrier signal and a telecommunication signal.

[0153] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0154] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0155] In the embodiments provided in the present application, it should be understood that the disclosed apparatus / network device and method can be implemented in other ways. For example, the apparatus / network device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection between each other can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0156] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may also be distributed to multiple network units. Part or all of the units can be selected to achieve the purpose of the embodiment scheme according to actual needs.

[0157] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A chip testing system, characterized by, The chip testing system comprises: a probe station and a tester, wherein the probe station is electrically connected with the tester; the tester obtains level information corresponding to each bit of a to-be-tested signal of a to-be-tested chip in N signal periods, wherein the level information comprises high level and low level, and N>1, and the level information corresponding to each bit of the to-be-tested signal of the to-be-tested chip in the N signal periods is obtained by capturing and storing the level information of the pin signal of the chip; the tester counts the level information corresponding to each bit of the to-be-tested signal in the N signal periods to determine a maximum continuous high level quantity and a maximum continuous low level quantity, wherein the maximum continuous high level quantity refers to a quantity corresponding to a maximum number of high levels in a case where multiple bits continuously appear as high levels in the N signal periods, and the maximum continuous low level quantity refers to a quantity corresponding to a maximum number of low levels in a case where multiple bits continuously appear as low levels in the N signal periods; the tester calculates the duty cycle of the to-be-tested chip according to the maximum continuous high level quantity and the maximum continuous low level quantity; the tester sends the duty cycle of the to-be-tested chip to the probe station.

2. The chip testing system according to claim 1, wherein: The chip testing system further comprises a probe card arranged on the probe station, and the tester obtains the to-be-tested signal of the to-be-tested chip through the probe card.

3. The chip testing system of claim 1, wherein, N≤2.

4. The chip testing system of claim 1, wherein, The counting of the level information corresponding to each bit of the to-be-tested signal in the N signal periods to determine the maximum continuous high level quantity and the maximum continuous low level quantity comprises: determining whether the level information corresponding to each bit of the to-be-tested signal in the N signal periods is high level or low level; for a case where the current bit is high level, continuously determining whether each subsequent bit is high level, and when a subsequent bit is high level, the continuous high level quantity is increased by 1, until the subsequent bit is low level, and if there is no subsequent bit, the process is ended; when the subsequent bit is low level, determining whether the current continuous high level quantity after one or more times of increase by 1 is greater than a first quantity threshold, and if yes, the first quantity threshold is updated to the current continuous high level quantity, the current continuous low level quantity is set to 1, and the process is transferred to a step of a case where the current bit is low level, wherein the first quantity threshold is initially 1; for a case where the current bit is low level, continuously determining whether each subsequent bit is low level, and when a subsequent bit is low level, the continuous low level quantity is increased by 1, until the subsequent bit is high level, and if there is no subsequent bit, the process is ended. When the subsequent bit is high, it is determined whether the current number of consecutive low levels after one or more increases of 1 is greater than a second number threshold, and if so, the second number threshold is updated to the current number of consecutive low levels, the current number of consecutive high levels is set to 1, and the process returns to the step of the current bit being high, wherein the second number threshold is initially 1; When the level information corresponding to the last bit is determined, the current first number threshold is determined as the maximum number of consecutive high levels, and the current second number threshold is determined as the maximum number of consecutive low levels.

5. The chip testing system of claim 1, wherein, The calculation according to the maximum number of consecutive high levels and the maximum number of consecutive low levels obtains the duty cycle of the chip to be tested. The total number of levels is determined according to the maximum number of consecutive high levels and the maximum number of consecutive low levels. The duty cycle of the chip to be tested is determined according to the total number of levels and either the maximum number of consecutive high levels or the maximum number of consecutive low levels.

6. A method of testing a chip, characterized by, It includes: The level information corresponding to each bit of the test signal of the chip to be tested in N signal periods is obtained, wherein the level information includes high and low, and N>1, wherein the level information corresponding to each bit of the test signal of the chip to be tested in N signal periods is obtained by capturing and storing the chip pin signal level information; The maximum number of consecutive high levels and the maximum number of consecutive low levels are determined by counting the level information corresponding to each bit of the test signal in N signal periods, wherein the maximum number of consecutive high levels refers to the number of the most high levels appearing when multiple bits in N signal periods appear high, and the maximum number of consecutive low levels refers to the number of the most low levels appearing when multiple bits in N signal periods appear low; The duty cycle of the chip to be tested is obtained by calculating according to the maximum number of consecutive high levels and the maximum number of consecutive low levels.

7. A chip testing apparatus characterized by comprising: It includes: The information obtaining module is used to obtain the level information corresponding to each bit of the test signal of the chip to be tested in N signal periods, wherein the level information includes high and low, and N>1, wherein the information obtaining module includes a first obtaining unit that captures and stores the chip pin signal level information to obtain the level information corresponding to each bit of the test signal of the chip to be tested in N signal periods; The maximum number of consecutive high levels and the maximum number of consecutive low levels are determined by counting the level information corresponding to each bit of the test signal in N signal periods, wherein the maximum number of consecutive high levels refers to the number of the most high levels appearing when multiple bits in N signal periods appear high, and the maximum number of consecutive low levels refers to the number of the most low levels appearing when multiple bits in N signal periods appear low; The duty cycle of the chip to be tested is obtained by calculating according to the maximum number of consecutive high levels and the maximum number of consecutive low levels. A quantity counting module is configured to count the quantity of the level information corresponding to each bit in the N signal periods of the to-be-tested signal, to determine a maximum continuous high level quantity and a maximum continuous low level quantity, wherein the maximum continuous high level quantity refers to the quantity corresponding to the maximum number of high levels in the case that multiple bits continuously appear as high levels in the N signal periods, and the maximum continuous low level quantity refers to the quantity corresponding to the maximum number of low levels in the case that multiple bits continuously appear as low levels in the N signal periods. A result calculation module is configured to calculate according to the maximum continuous high level quantity and the maximum continuous low level quantity, to obtain the duty cycle of the to-be-tested chip.

8. A terminal device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method in claim 6.

9. A computer-readable storage medium storing a computer program, characterized in that: The computer program is executed by the processor to implement the method in claim 6.

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