Display device

Abstract

The purpose of the present embodiment is to provide a display device capable of suppressing a reduction in display quality. A display device according to an embodiment includes a first substrate including a first pixel and a second pixel, a liquid crystal layer including a polymer and a liquid crystal molecule located between the first substrate and the second substrate, and a light-emitting element disposed between the first pixel and the second substrate, the second pixel being adjacent to the first pixel, and the liquid crystal layer including a polymer and a liquid crystal molecule located between the first pixel and the second pixel. And a first substrate disposed between the light emitting element and the first pixel, the first substrate including a switching element including a semiconductor layer disposed in the first pixel, a pixel electrode electrically connected to the switching element, and a first light shielding portion disposed between the switching element and the first pixel. The first light-shielding portion is disposed in the second pixel and adjacent to the semiconductor layer, and the first light-shielding portion is located between the semiconductor layer and the light-emitting element in a plan view, and is located closer to the first pixel than the center of the second pixel.

Description

[0001] This application is a divisional application of the Chinese national phase application with an international application date of January 28, 2020, an international application number of PCT / JP2020 / 003032, and an invention name of “Display Device”, and a national phase entry date of the PCT application on August 13, 2021, and an application number of 202080014301.3. All contents of this application are incorporated herein for reference. Technical Field

[0002] An embodiment of the present invention relates to a display device. Background Art

[0003] In recent years, a display device using a polymer dispersed liquid crystal that can switch between a scattering state for scattering incident light and a transmissive state for transmitting incident light has been proposed. In one example, a display device is disclosed in which a reflective layer formed of aluminum, silver, etc. covers a pixel switch circuit portion.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2017-167214 Summary of the invention

[0007] Technical problem to be solved by the invention

[0008] An object of this embodiment is to provide a display device capable of suppressing a decrease in display quality.

[0009] Solutions for solving technical problems

[0010] According to this embodiment, a display device is provided, comprising a first substrate, a second substrate, a liquid crystal layer and a light-emitting element, wherein the first substrate comprises a first pixel and a second pixel, the liquid crystal layer is located between the first substrate and the second substrate and comprises a polymer and a liquid crystal molecule, the second pixel is adjacent to the first pixel and is located between the light-emitting element and the first pixel, the first substrate comprises a switching element, a pixel electrode and a first shading portion, the switching element comprises a semiconductor layer arranged in the first pixel, the pixel electrode is electrically connected to the switching element, the first shading portion is arranged in the second pixel and is adjacent to the semiconductor layer, and the first shading portion is located between the semiconductor layer and the light-emitting element when viewed from above, and is located on a side closer to the first pixel than to the center of the second pixel.

[0011] According to this embodiment, a display device is provided, comprising a first substrate, a second substrate, a liquid crystal layer and a light-emitting element, wherein the liquid crystal layer is located between the first substrate and the second substrate and comprises a polymer and liquid crystal molecules, the first substrate comprises a switching element, a pixel electrode and a first shading portion, the switching element comprises a semiconductor layer, the pixel electrode is electrically connected to the switching element, the first shading portion is adjacent to the semiconductor layer, the first shading portion is located between the semiconductor layer and the light-emitting element when viewed from above, the first substrate comprises a transparent substrate, a first insulating film and a second insulating film stacked in sequence, the semiconductor layer is located between the first insulating film and the second insulating film when viewed in cross section, and the first shading portion is provided in a through hole penetrating the first insulating film and the second insulating film.

[0012] Effects of the Invention

[0013] According to this embodiment, a display device capable of suppressing a decrease in display quality can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 1 is a plan view showing the display device DSP according to the present embodiment.

[0015] Figure 2 It is shown Figure 1 FIG. 1 is a top view of a main portion of a pixel PX in a first substrate SUB1 .

[0016] Figure 3 Yes Figure 2 FIG. 1 is an enlarged top view of the periphery of the semiconductor layer SC.

[0017] Figure 4A It shows that Figure 3 FIG. 1 is a cross-sectional view of the display panel PNL along line AB of the first to fourth light shielding portions LS1 to LS4 .

[0018] Figure 4B Yes Figure 4A An enlarged cross-sectional view of a main portion of the first substrate is shown.

[0019] Figure 5 It shows that Figure 3 FIG. 1 is a cross-sectional view of the display panel PNL along line CD of the scanning line G2 and the connecting portion DEA.

[0020] Figure 6 It shows that Figure 3 FIG. 1 is a cross-sectional view of the display panel PNL along line EF of the signal line S1.

[0021] Figure 7 It is a cross-sectional view showing a configuration example of the display device DSP according to the present embodiment.

[0022] Figure 8 It is a figure which shows the simulation result.

[0023] Fig. 9 2 is a cross-sectional view showing the display panel PNL in the second configuration example of the present embodiment.

[0024] Fig.10 : is a cross-sectional view showing the display panel PNL in the third configuration example of the present embodiment.

[0025] Fig.11 It is a cross-sectional view showing the first substrate SUB1 in the fourth configuration example of the present embodiment.

[0026] Fig.12 It is a cross-sectional view showing the first substrate SUB1 in the fifth configuration example of the present embodiment.

[0027] Fig.13 It is a plan view showing the first substrate SUB1 in the sixth configuration example of the present embodiment.

[0028] Fig.14 It is a plan view showing the first substrate SUB1 in the seventh configuration example of the present embodiment.

[0029] Fig.15 1 is a plan view showing the display device DSP of the eighth configuration example.

[0030] Fig.16 1 is a plan view showing an example of the layout of the switching element SW2 and its peripheral portion in the second pixel PX2.

[0031] Fig.17 1 is a plan view showing another example of the layout of the switching element SW2 and its peripheral portion in the second pixel PX2.

[0032] Fig.18 1 is a plan view showing an example of the layout of the switching element SW3 and its surrounding area in the third pixel PX3.

[0033] Fig.19 is shown along Fig.18 FIG. 4 is a cross-sectional view of the first substrate SUB1 taken along line GH.

[0034] Fig. 20 1 is a plan view showing a display device DSP according to a ninth configuration example. DETAILED DESCRIPTION

[0035] Below, the present embodiment is described with reference to the accompanying drawings. It should be noted that the disclosure is only an example, and appropriate changes that can be thought of by those skilled in the art without departing from the main purpose of the invention are of course also included in the scope of the present invention. In addition, in order to further clarify the description, the drawings sometimes schematically show the width, thickness, shape, etc. of each part compared to the actual scheme, but this is only an example and is not used to limit the interpretation of the present invention. In addition, in this specification and each figure, the same figure mark is marked for the constituent elements that perform the same or similar functions as the components described in the above-mentioned figures, and sometimes repeated detailed descriptions are appropriately omitted.

[0036] [First Configuration Example]

[0037] Figure 1 : is a top view showing the display device DSP of the present embodiment. In one example, the first direction X, the second direction Y and the third direction Z are orthogonal to each other, but they may also intersect at angles other than 90 degrees. The first direction X and the second direction Y correspond to directions parallel to the main surfaces of the substrates constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP. In this specification, the direction from the first substrate SUB1 toward the second substrate SUB2 is referred to as the "upper side" (or simply "up"), and the direction from the second substrate SUB2 toward the first substrate SUB1 is referred to as the "lower side" (or simply "lower"). In the case of "the second component above the first component" and "the second component below the first component", the second component may be connected to the first component or may be separated from the first component. In addition, assuming that the front end side of the arrow representing the third direction Z has an observation position for observing the display device DSP, viewing from the observation position toward the XY plane defined by the first direction X and the second direction Y is referred to as top view.

[0038] In this embodiment, a liquid crystal display device to which polymer-dispersed liquid crystal is applied is described as an example of a display device DSP. The display device DSP includes a display panel PNL, a wiring substrate 1, an IC chip 2, and a light-emitting element LD.

[0039] The display panel PNL includes a first substrate SUB1, a second substrate SUB2, a liquid crystal layer LC, and a sealant SL. The first substrate SUB1 and the second substrate SUB2 are formed into a flat plate shape parallel to the XY plane. The first substrate SUB1 and the second substrate SUB2 overlap when viewed from above. The first substrate SUB1 and the second substrate SUB2 are bonded by the sealant SL. The liquid crystal layer LC is held between the first substrate SUB1 and the second substrate SUB2 and is encapsulated by the sealant SL. Figure 1 In the figure, the liquid crystal layer LC and the seal SL are represented by different oblique lines.

[0040] like Figure 1As shown in the figure enlarged and schematically, the liquid crystal layer LC has a polymer dispersed liquid crystal including a polymer 31 and liquid crystal molecules 32. In one example, the polymer 31 is a liquid crystal polymer. The polymer 31 is formed into a stripe shape extending in one direction. For example, the extension direction D1 of the polymer 31 refers to the direction along the first direction X. The liquid crystal molecules 32 are dispersed in the gaps of the polymer 31 and are oriented in such a way that their long axes are along the first direction X. The polymer 31 and the liquid crystal molecules 32 have optical anisotropy or refractive index anisotropy, respectively. The responsiveness of the polymer 31 to the electric field is lower than the responsiveness of the liquid crystal molecules 32 to the electric field.

[0041] In one example, the orientation direction of the polymer 31 hardly changes regardless of the presence or absence of an electric field. On the other hand, the orientation direction of the liquid crystal molecules 32 changes according to the electric field when a high voltage above the threshold is applied to the liquid crystal layer LC. When no voltage is applied to the liquid crystal layer LC, the optical axes of the polymer 31 and the liquid crystal molecules 32 are parallel to each other, and the light incident on the liquid crystal layer LC is transmitted and hardly scattered in the liquid crystal layer LC (transparent state). When a voltage is applied to the liquid crystal layer LC, the optical axes of the polymer 31 and the liquid crystal molecules 32 cross each other, and the light incident on the liquid crystal layer LC is scattered in the liquid crystal layer LC (scattering state).

[0042] The display panel PNL includes a display portion DA for displaying an image and a frame-shaped non-display portion NDA surrounding the display portion DA. The seal SL is located in the non-display portion NDA. The display portion DA includes pixels PX arranged in a matrix along the first direction X and the second direction Y.

[0043] like Figure 1 As shown in the enlarged figure, each pixel PX has a switching element SW, a pixel electrode PE, a common electrode CE, and a liquid crystal layer LC. The switching element SW is composed of, for example, a thin film transistor (TFT), and is electrically connected to the scanning line G and the signal line S. The scanning line G is electrically connected to the switching element SW of each pixel PX arranged in the first direction X. The signal line S is electrically connected to the switching element SW of each pixel PX arranged in the second direction Y. The pixel electrode PE is electrically connected to the switching element SW. The pixel electrode PE is opposite to the common electrode CE in the third direction Z, and the liquid crystal layer LC (especially the liquid crystal molecules 32) is driven by the electric field generated between the pixel electrode PE and the common electrode CE. The capacitor CS is formed, for example, between the common electrode CE and an electrode of the same potential, and between the pixel electrode PE and an electrode of the same potential.

[0044] The wiring substrate 1 is electrically connected to the extension Ex of the first substrate SUB1. The wiring substrate 1 is a bendable flexible printed circuit board. The IC chip 2 is electrically connected to the wiring substrate 1. The IC chip 2 has a built-in display driver for outputting signals necessary for image display, etc. It should be noted that the IC chip 2 can also be electrically connected to the extension Ex. The wiring substrate 1 and the IC chip 2 sometimes also read signals from the display panel PNL, but are mainly used as a signal source for providing signals to the display panel PNL.

[0045] The light emitting element LD overlaps the extension portion Ex. The plurality of light emitting elements LD are arranged at intervals along the first direction X. The light emitting elements LD are arranged along the end portion E21 of the second substrate SUB2 and emit light toward the end portion E21.

[0046] Figure 2 It is shown Figure 1 A top view of the main part of the pixel PX on the first substrate SUB1 shown. The first substrate SUB1 includes a first pixel PX1 and a second pixel PX2 as the pixels PX. The second pixel PX2 is adjacent to the first pixel PX1 in the second direction Y and is located between the light emitting element LD and the first pixel PX1. The first substrate SUB1 includes scanning lines G1 and G2, a semiconductor layer SC, signal lines S1 and S2, an organic insulating film O, a metal wiring M, a first light shielding portion LS1, a second light shielding portion LS2, and pixel electrodes PE1 and PE2. The organic insulating film O is represented by a single-dot chain line, and the pixel electrodes PE1 and PE2 are represented by a double-dot chain line. The pixel electrode PE1 is arranged in the first pixel PX1, and the pixel electrode PE2 is arranged in the second pixel PX2.

[0047] The scanning lines G1 and G2 extend in the first direction X, and the signal lines S1 and S2 extend in the second direction Y. The pixel electrode PE1 disposed in the pixel PX is surrounded by two signal lines S1 and S2 arranged in the first direction X and two scanning lines G1 and G2 arranged in the second direction Y.

[0048] The semiconductor layer SC of the switching element SW disposed in the first pixel PX1 is disposed near the intersection of the scanning line G2 and the signal line S1. Figure 2 In the example shown, the semiconductor layer SC extends along the first direction X. The semiconductor layer SC has a first end E1 close to the signal line S1 and a second end E2 on the opposite side of the first end E1. The semiconductor layer SC has a width W1. The width W1 corresponds to the distance from the first end E1 to the second end E2 in the first direction X (or a direction orthogonal to the arrangement direction of the first pixel and the second pixel (second direction Y)). Although the semiconductor layer is formed of amorphous silicon, for example, it can also be formed of polycrystalline silicon or an oxide semiconductor.

[0049] The organic insulating film O is patterned and formed into a grid shape when viewed from above. The organic insulating film O overlaps the scanning lines G1 and G2, the semiconductor layer SC, and the signal lines S1 and S2, respectively. That is, the organic insulating film O includes a first portion OX and a second portion OY. The first portion OX overlaps the scanning lines G1 and G2. The second portion OY overlaps the signal lines S1 and S2. The first portion OX has a side surface E11 close to the light emitting element LD, and a side surface E12 on the opposite side of the side surface E11. The side surfaces E11 and E12 extend along the extension direction D1 (or the first direction X) of the polymer 31.

[0050] The metal wiring M is arranged on the organic insulating film O and is formed in a grid shape when viewed from above. The metal wiring M overlaps with the scanning lines G1 and G2, the semiconductor layer SC, and the signal lines S1 and S2, respectively. That is, the metal wiring M includes a first wiring portion MX and a second wiring portion MY. The first wiring portion MX overlaps with the scanning lines G1 and G2 and the first portion OX. The second wiring portion MY overlaps with the signal lines S1 and S2 and the second portion OY.

[0051] The first light shielding portion LS1 is located between the semiconductor layer SC and the light emitting element LD along the second direction Y, and is adjacent to the semiconductor layer SC. The first light shielding portion LS1 is separated from the signal lines S1 and S2, the metal wiring M, and the organic insulating film O when viewed from above, and is formed in an island shape. In addition, the first light shielding portion LS1 is arranged in the second pixel PX2, and overlaps with the pixel electrode PE2 when viewed from above. The first light shielding portion LS1 is located on the side closer to the first pixel PX1 (or the pixel electrode PE1) than the center O of the second pixel PX2 (or the center O of the pixel electrode PE2) in the second direction Y. Alternatively, the first light shielding portion LS1 is located on the side closer to the semiconductor layer SC between the center O of the second pixel PX2 and the semiconductor layer SC of the first pixel PX1.

[0052] The first light shielding portion LS1 extends along the first direction X. The first light shielding portion LS1 has a third end E3 close to the signal line S1, and a fourth end E4 on the opposite side of the third end E3. The first light shielding portion LS1 has a width W2. The width W2 is equivalent to the distance from the third end E3 to the fourth end E4 in the first direction X (or a direction orthogonal to the arrangement direction of the first pixel and the second pixel (the second direction Y)). The width W2 is greater than the width W1 of the semiconductor layer SC. In addition, in the first direction X, the first end E1 is farther away from the signal line S1 than the third end E3, and the second end E2 is closer to the signal line S1 than the fourth end E4. That is, the semiconductor layer SC is set so that its first end E1 and the second end E2 are located between the third end E3 and the fourth end E4 in the first direction X.

[0053] The first light shielding portion LS1 is disposed on the same layer as the metal wiring M. In this specification, the first member and the second member disposed on “the same layer” refer to members formed by the same material and the same process.

[0054] The second light shielding portion LS2 is located between the semiconductor layer SC and the first light shielding portion LS1 along the second direction Y, and overlaps the side surface E11 of the first portion OX. Figure 2 In the example shown, the second light shielding portion LS2 is formed integrally with the first wiring portion MX of the metal wiring M. In other words, a portion of the first wiring portion MX extends to a side away from the semiconductor layer SC (or toward the light emitting element LD), thereby forming the second light shielding portion LS2 overlapping the side surface E11.

[0055] The spacer SP is disposed at a position overlapping with the semiconductor layer SC. Figure 1 A predetermined cell gap is formed between the first substrate SUB1 and the second substrate SUB2.

[0056] The pixel electrodes PE1 and PE2 are arranged in the second direction Y. Figure 2 In the illustrated example, in the vicinity of the scanning line G2 , the pixel electrode PE1 overlaps the semiconductor layer SC, and the pixel electrode PE2 overlaps the first light shielding portion LS1 .

[0057] Figure 3 Yes Figure 2 An enlarged top view of the periphery of the semiconductor layer SC shown. The third light shielding portion LS3 and the gate electrode GE of the switching element SW are formed integrally with the scanning line G2. The semiconductor layer SC overlaps the gate electrode GE. The third light shielding portion LS3 extends toward the first light shielding portion LS1 on the opposite side of the gate electrode GE. The first light shielding portion LS1 and the second light shielding portion LS2 overlap with the third light shielding portion LS3, respectively. The third light shielding portion LS3 is formed continuously without interruption between the first light shielding portion LS1 and the second light shielding portion LS2. The fourth light shielding portion LS4 overlaps with the first to third light shielding portions LS1 to LS3. The cross-sectional structure of the above first to fourth light shielding portions LS1 to LS4 will be described in detail later.

[0058] The light shielding layers GS1 and GS2 extend respectively along the second direction Y. The scanning line G2 is located between the light shielding layers GS1 and GS2 and is separated from the light shielding layers GS1 and GS2. The light shielding layers GS1 and GS2 are respectively formed in an island shape.

[0059] The signal line S1 intersects with the scanning line G2 and overlaps with the light shielding layers GS1 and GS2. The source electrode SE and the connecting portion SJ of the switching element SW are formed integrally with the signal line S1. The connecting portion SJ connects the source electrode SE with the signal line S1 and overlaps with the light shielding layer GS1. The source electrode SE branches into two from the connection position with the connecting portion SJ, each extending along the first direction X and overlapping with the semiconductor layer SC respectively.

[0060] The drain electrode DE of the switch element SW is located between the two source electrodes SE and overlaps the semiconductor layer SC. Figure 2 The pixel electrode PE1 is shown to be electrically connected to a connection portion DEA. The connection portion DEA overlaps the light shielding layer GI.

[0061] The metal wiring M overlaps with the source electrode SE, and overlaps with the drain electrode DE except for the connection portion DEA.

[0062] Figure 4A It is shown that Figure 3 The cross-sectional view of the display panel PNL along the AB line of the first to fourth light shielding parts LS1 to LS4 shown in FIG. The first substrate SUB1 further includes a transparent substrate 10, insulating films 11 to 13, a capacitor electrode C, and an alignment film AL1. In this embodiment, the insulating film 11 is equivalent to a first insulating film located on the transparent substrate 10, the insulating film 12 is equivalent to a second insulating film located on the insulating film 11, and the organic insulating film O is equivalent to a third insulating film located on the insulating film 12.

[0063] The gate electrode GE and the third light shielding portion LS3 integrated with the scanning line G2 are located between the transparent substrate 10 and the insulating film 11. Figure 4A In the illustrated example, the gate electrode GE and the third light shielding portion LS3 are in contact with the transparent substrate 10 , but another insulating film may be interposed between the gate electrode GE and the third light shielding portion LS3 and the transparent substrate 10 .

[0064] The semiconductor layer SC is located between the insulating film 11 and the insulating film 12 just above the gate electrode GE. The lower surface SCA of the semiconductor layer SC is in contact with the insulating film 11. The two source electrodes SE integral with the signal line S1 are in contact with the upper surface SCB of the semiconductor layer SC, and a part of them is located above the insulating film 11. The drain electrode DE is in contact with the upper surface SCB of the semiconductor layer SC. The insulating film 12 covers the source electrode SE and the drain electrode DE and is in contact with the upper surface SCB of the semiconductor layer SC.

[0065] The fourth light shielding portion LS4 is provided in the through hole CH1 penetrating the insulating film 11 to the third light shielding portion LS3 and is connected to the third light shielding portion LS3. The fourth light shielding portion LS4 is separated from the signal line S1, the source electrode SE and the drain electrode DE.

[0066] The first light shielding portion LS1 is provided in the through hole CH2 penetrating the insulating film 12 to the fourth light shielding portion LS4, and is connected to the fourth light shielding portion LS4. The through hole CH2 is arranged to overlap with the through hole CH1. Therefore, the first light shielding portion LS1 is arranged to overlap with the through holes CH1 and CH2. In addition, in the area where the through holes CH1 and CH2 overlap, the third light shielding portion LS3, the fourth light shielding portion LS4 and the first light shielding portion LS1 overlap in sequence along the third direction Z. That is, the first light shielding portion LS1 is electrically connected to the third light shielding portion LS3 integrated with the scanning line G2 via the fourth light shielding portion LS4. Therefore, the potential of the first light shielding portion LS1 is the same potential as that of the scanning line G2.

[0067] The fourth light shielding portion LS4 is arranged on the same layer as the signal line S1 , the source electrode SE, and the drain electrode DE.

[0068] The first portion OX of the organic insulating film O overlaps the switching element SW. The side surface E11 of the first portion OX is located between the through hole CH1 and the semiconductor layer SC along the second direction Y. The first wiring portion MX of the metal wiring M overlaps the first portion OX. The second light shielding portion LS2 covers the side surface E11 and is in contact with the insulating film 12.

[0069] The capacitor electrode C directly covers the first wiring portion MX and is electrically connected to the first wiring portion MX. In addition, the capacitor electrode C directly covers the second light shielding portion LS2 and is electrically connected to the second light shielding portion LS2. Therefore, the potential of the second light shielding portion LS2 is the same potential as that of the capacitor electrode. In addition, the capacitor electrode C covers the side E12 of the first portion OX. In addition, the capacitor electrode C is connected to the insulating film 12 in the area not overlapping the organic insulating film O. The first light shielding portion LS1 is arranged at the opening CB of the capacitor electrode C. Therefore, the first light shielding portion LS1 is electrically insulated from the capacitor electrode C. In addition, the first light shielding portion LS1 and the second light shielding portion LS2 are electrically insulated from each other.

[0070] The insulating film 13 covers the capacitor electrode C and the first light shielding portion LS1. The insulating film 13 is connected to the insulating film 12 between the capacitor electrode C and the first light shielding portion LS1 in the opening CB. The pixel electrodes PE1 and PE2 are located on the insulating film 13. The pixel electrodes PE1 and PE2 are respectively opposite to the capacitor electrode C through the insulating film 13 in the third direction Z, and form a storage capacitor required for displaying the pixel on the pixel PX. The alignment film AL1 covers the insulating film 13, the pixel electrodes PE1 and PE2. The alignment film AL1 is connected to the insulating film 13 between the pixel electrode PE1 and the pixel electrode PE2.

[0071] The second substrate SUB2 includes a transparent substrate 20, a light shielding layer BM, a common electrode CE, and an alignment film AL2. The light shielding layer BM is located directly above the scanning line G2, the switching element SW, the first light shielding portion LS1, and the second light shielding portion LS2. The common electrode CE is located between the light shielding layer BM and the alignment film AL2. The potential of the common electrode CE is the same as that of the capacitor electrode C.

[0072] The liquid crystal layer LC is located between the first substrate SUB1 and the second substrate SUB2, and is in contact with the alignment films AL1 and AL2 respectively.

[0073] The transparent substrates 10 and 20 are insulating substrates such as glass substrates and plastic substrates. The insulating films 11 to 13 are formed of transparent inorganic insulating materials such as silicon nitride and silicon oxide. The organic insulating film O is formed of transparent organic insulating materials such as acrylic resin.

[0074] The scanning line G, the signal line S and the metal wiring M are formed of an opaque metal material such as molybdenum, aluminum, tungsten, titanium, silver, etc. The first light shielding portion LS1 and the second light shielding portion LS2 are formed of the same material as the metal wiring M. The third light shielding portion LS3 is formed of the same material as the scanning line G. The fourth light shielding portion LS4 is formed of the same material as the signal line S.

[0075] The capacitor electrode C, the pixel electrode PE and the common electrode CE are transparent electrodes formed of transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO). The light shielding layer BM can be an insulating layer or a conductive layer having a lower resistance than the common electrode CE. When the light shielding layer BM is a conductive layer, the resistance of the common electrode CE is reduced by electrically connecting the common electrode CE to the light shielding layer BM.

[0076] The alignment films AL1 and AL2 are horizontal alignment films having an alignment regulating force substantially parallel to the XY plane. In one example, the alignment films AL1 and AL2 are aligned along the first direction X. It should be noted that the alignment may be a rubbing treatment or a photo-alignment treatment.

[0077] Here, reference Figure 7 A cross-sectional view showing a configuration example of the display device DSP according to the present embodiment will be described. It should be noted that only a main portion of the display panel PNL is shown in the figure.

[0078] The light emitting element LD is opposite to the side surface 20C of the transparent substrate 20 in the second direction Y. The side surface 20C corresponds to Figure 1The end E21 of the second substrate SUB2 is shown. The light emitting element LD is electrically connected to the wiring substrate F. The light emitting element LD is, for example, a light emitting diode, and has a red light emitting portion, a green light emitting portion, and a blue light emitting portion, which will not be described in detail. It should be noted that a transparent light guide can also be arranged between the light emitting element LD and the side surface 20C.

[0079] Next, refer to Figure 7 Light L1 emitted from the light emitting element LD will be described.

[0080] The light emitting element LD emits light L1 toward the side surface 20C. The light L1 emitted from the light emitting element LD travels in the direction of the arrow indicating the second direction Y and enters the transparent substrate 20 from the side surface 20C. The light L1 entering the transparent substrate 20 travels inside the display panel PNL while being repeatedly reflected.

[0081] The light L1 incident on the liquid crystal layer LC to which no voltage is applied is transmitted through the liquid crystal layer LC and is hardly scattered. In addition, the light L1 incident on the liquid crystal layer LC to which voltage is applied is scattered by the liquid crystal layer LC. The display device DSP can be observed from the first substrate SUB1 side and also from the second substrate SUB2 side. In addition, whether the display device DSP is observed from the first substrate SUB1 side or from the second substrate SUB2 side, the background of the display device DSP can be observed through the display device DSP.

[0082] Here, the light L2 emitted from the light emitting element LD and directed toward the switch element SW is discussed. If the light L2 directed toward the switch element SW among the light traveling inside the display panel PNL is incident on the semiconductor layer SC, carriers are generated in the semiconductor layer SC due to light excitation, and the leakage current of the switch element SW increases. If the leakage current increases, the potential maintained in the pixel PX changes significantly, which may lead to a decrease in display quality.

[0083] According to this embodiment, Figure 4B As shown, among the light toward the switching element SW, the light L21 propagating in the transparent substrate 10 is blocked by the third light shielding portion LS3, the scanning line G2, and the gate electrode GE. The light L22 propagating in the insulating film 11 is blocked by the third light shielding portion LS3 and the fourth light shielding portion LS4. The light L23 propagating in the insulating film 12 is blocked by the first light shielding portion LS1 and the fourth light shielding portion LS4. The light L24 toward the first portion OX of the organic insulating film O is blocked by the second light shielding portion LS2. Therefore, it is difficult for the light L2 to reach the lower surface SCA and the upper surface SCB of the semiconductor layer SC.

[0084] In addition, if Figure 2As shown, since the semiconductor layer SC is set to be located between the third end E3 and the fourth end E4 of the first shading portion LS1, not only the light L25 traveling straight along the second direction Y, but also the light L26 and L27 traveling in a direction inclined relative to the second direction Y when viewed from above are blocked.

[0085] This can suppress leakage current from occurring in the semiconductor layer SC, and can also suppress degradation in display quality such as reduction in luminance due to a change in the potential of the pixel PX.

[0086] In addition, compared with the light shielding layer formed of black resin, the first to fourth light shielding parts LS1 to LS4 can be formed of a material with high reflectivity. According to the first to fourth light shielding parts LS1 to LS4 formed of such a material with high reflectivity, it is possible to suppress the absorption of light advancing in the display panel, thereby suppressing the reduction in the utilization efficiency of light from the light emitting element LD.

[0087] In addition, even if undesired scattering occurs on the first to fourth light shielding portions LS1 to LS4, the scattered light is shielded by the light shielding layer BM of the second substrate SUB2, thereby suppressing degradation of display quality.

[0088] Figure 5 Yes Figure 3 FIG. 1 is a cross-sectional view of the display panel PNL along line CD of the scanning line G2 and the connecting portion DEA.

[0089] On the first substrate SUB1, the light shielding layer GI is arranged on the same layer as the scanning line G2, and is located on the transparent substrate 10, and is formed of the same material as the scanning line G2. The scanning line G2 and the light shielding layer GI are covered by the insulating film 11. The connecting portion DEA is located on the insulating film 11 just above the light shielding layer GI, and is covered by the insulating film 12. The first portion OX of the organic insulating film O is located on the insulating film 12 just above the scanning line G2. The first wiring portion MX of the metal wiring M is located on the first portion OX just above the scanning line G2. The capacitor electrode C covers the side surfaces E11 and E12 of the first portion OX. The pixel electrode PE1 is provided in the through hole CH3 penetrating the insulating films 12 and 13 and the opening CA of the capacitor electrode C, and is connected to the connecting portion DEA.

[0090] On the second substrate SUB2, the light shielding layer BM is located directly above each of the first portion OX and the connecting portion DEA.

[0091] Figure 6 It is shown that Figure 3 FIG. 1 is a cross-sectional view of the display panel PNL along line EF of the signal line S1.

[0092] On the first substrate SUB1, the light shielding layer GS1 is located on the transparent substrate 10 and is covered by the insulating film 11. The signal line S1 is located on the insulating film 11 directly above the light shielding layer GS1 and is covered by the insulating film 12. The second part OY of the organic insulating film O is located on the insulating film 12 directly above the signal line S1. The second wiring part MY of the metal wiring M is located on the second part OY directly above the signal line S1. The capacitor electrode C is connected to the second wiring part MY and covers the side surfaces E13 and E14 of the second part OY.

[0093] On the second substrate SUB2, the light shielding layer BM is located directly above the second portion OY.

[0094] Here, a simulation for verifying the effect of this embodiment is described. In this simulation, a voltage different from the potential Vcom of the common electrode CE is applied to the pixel electrode PE, and the brightness of the pixel PX formed in a scattered state is calculated. For the calculated brightness, when the brightness just after rising is defined as La and the brightness just before falling is defined as Lb, the brightness reduction rate is defined as {1-(La / Lb)}.

[0095] Figure 8 It is a figure which shows the simulation result. Figure 8 (A) shows the simulation results in the configuration of the comparative example, Figure 8 (B) shows the simulation results in the configuration of this embodiment. The display panel of the comparative example does not have Figure 4A The display panel of this embodiment includes the first to fourth light shielding parts shown. Figure 4A The first to fourth light shielding parts shown.

[0096] During the period T1 when the potential Vcom is positive relative to the reference potential Vr, the brightness reduction rate is 1.34% in the comparative example, while the brightness reduction rate is 0.69% in the present embodiment. During the period T2 when the potential Vcom is negative relative to the reference potential Vr, the brightness reduction rate is 10.7% in the comparative example, while the brightness reduction rate is 3.8% in the present embodiment. Thus, according to the present embodiment, it is confirmed that the brightness reduction can be suppressed.

[0097] Next, other configuration examples will be described.

[0098] [Second Configuration Example]

[0099] Fig. 9 2 is a cross-sectional view showing the display panel PNL in the second configuration example of the present embodiment. Fig. 9 The second configuration example shown is the same as Figure 4ACompared with the first configuration example shown in FIG. 1 , the first light shielding portion LS1 and the second light shielding portion LS2 are formed integrally and the third light shielding portion LS3 is separated from the scanning line G2. In addition, the first light shielding portion LS1 and the second light shielding portion LS2 are formed integrally with the metal wiring M. In such a second configuration example, the first to fourth light shielding portions LS1 to LS4 are electrically connected to the metal wiring M and the capacitor electrode C. Therefore, the potentials of the first to fourth light shielding portions LS1 to LS4 are respectively equal, and are the same potential as the metal wiring M and the capacitor electrode C.

[0100] Even in such a second configuration example, the same effects as those of the above-described first configuration example can be obtained. In addition, between the first light shielding portion LS1 and the second light shielding portion LS2, it is possible to shield the light L28 from the liquid crystal layer LC toward the insulating film 12.

[0101] [Third Configuration Example]

[0102] Fig.10 : is a cross-sectional view showing the display panel PNL in the third configuration example of the present embodiment. Fig.10 The third configuration example shown is the same as Figure 4A Compared with the first configuration example shown in FIG. 1 , the first light shielding portion LS1 and the second light shielding portion LS2 are formed integrally and the second light shielding portion LS2 is separated from the metal wiring M. The capacitor electrode C is in contact with the second light shielding portion LS2 and the metal wiring M. In such a third configuration example, the first to fourth light shielding portions LS1 to LS4 are electrically connected to the scanning line G2. Therefore, the potentials of the first to fourth light shielding portions LS1 to LS4 are respectively equal, which is the same potential as the scanning line G2.

[0103] Even in such a third configuration example, the same effects as those of the above-mentioned second configuration example can be obtained.

[0104] [Fourth Configuration Example]

[0105] Fig.11 It is a cross-sectional view showing the first substrate SUB1 in the fourth configuration example of the present embodiment. Fig.11 The fourth configuration example shown is the same as Figure 4A The first configuration example shown is different in that the fourth light shielding portion LS4 is omitted. The first light shielding portion LS1 is provided in the through hole CH12 penetrating the insulating films 11 and 12 to the third light shielding portion LS3 and is in contact with the third light shielding portion LS3.

[0106] Even in the fourth configuration example, the light L21 propagating in the transparent substrate 10, the light L22 propagating in the insulating film 11, and the light L23 propagating in the insulating film 12 are shielded by the first light shielding portion LS1 and the third light shielding portion LS3. Therefore, the same effect as the first configuration example described above can be obtained.

[0107] It should be noted that even in Fig. 9 The second configuration example shown, and Fig.10 In the third configuration example shown, the fourth configuration example in which the fourth light shielding portion LS4 is omitted can also be applied.

[0108] [Fifth Configuration Example]

[0109] Fig.12 It is a cross-sectional view showing the first substrate SUB1 in the fifth configuration example of the present embodiment. Fig.12 The fifth configuration example shown is the same as Figure 4A The third light shielding portion LS3 and the fourth light shielding portion LS4 are omitted from the first configuration example shown. The first light shielding portion LS1 is provided in the through hole CH12 penetrating the insulating films 11 and 12 to the transparent substrate 10 .

[0110] Even in the fifth configuration example, the light L21 propagating through the transparent substrate 10, the light L22 propagating through the insulating film 11, and the light L23 propagating through the insulating film 12 are blocked by the first light shielding portion LS1. Therefore, the same effect as in the first configuration example can be obtained.

[0111] It should be noted that even in Fig. 9 The second configuration example shown and Fig.10 In the third configuration example shown, the fifth configuration example in which the third light shielding portion LS3 and the fourth light shielding portion LS4 are omitted can also be applied.

[0112] [Sixth Configuration Example]

[0113] Fig.13 It is a plan view showing the first substrate SUB1 in the sixth configuration example of the present embodiment. Fig.13 The sixth configuration example shown is the same as Figure 3 Compared with the first structural example shown, the semiconductor layer SC extends in the second direction Y in a different point. Fig.13 , the scanning line G2, the signal line S2, the switching element SW and the first light shielding portion LS1 are shown, while the illustration of other structures is omitted. The first light shielding portion LS1 is separated from the signal line S1, the source electrode SE and the drain electrode DE. The width W2 of the first light shielding portion LS1 is greater than the width W1 of the semiconductor layer SC. In addition, the semiconductor layer SC is configured such that its first end E1 and the second end E2 are located between the third end E3 and the fourth end E4 in the first direction X. The signal line S1 is bent in a manner separated from the third end E3 of the first light shielding portion LS1. It should be noted that, with respect to the portion overlapping the first light shielding portion LS1, as shown in the above-mentioned configuration example, at least one of the third light shielding portion LS3 and the fourth light shielding portion LS4 may also be configured. In addition, the second light shielding portion LS2 may also be configured between the first light shielding portion LS1 and the semiconductor layer SC.

[0114] Even in such a sixth configuration example, it is possible to block the light L21 to L27 in the same manner as in the above-mentioned configuration examples.

[0115] [Seventh Configuration Example]

[0116] Fig.14 It is a plan view showing the first substrate SUB1 in the seventh configuration example of the present embodiment. Fig.14 The seventh configuration example shown is the same as Figure 2 Compared with the first configuration example shown in FIG. 1 , the capacitor electrode C is different in that it has an electrode portion EL and an opening portion OP. That is, as shown by the oblique lines, the electrode portion EL overlaps the peripheral portion of the pixel electrode PE1. In addition, the opening portion OP overlaps the central portion of the pixel electrode PE1. That is, the capacitor electrode C is formed into a grid shape when viewed from above. In addition, in the area overlapping with the pixel electrode PE1, the first light shielding portion LS1 is located at the opening portion OP. The capacitor electrode C overlaps the metal wiring M and is electrically connected to the metal wiring M.

[0117] Even in such a seventh configuration example, the same effect as in the first configuration example can be obtained. In addition, the arrangement area (or volume) of the capacitor electrode C is smaller than when the capacitor electrode C does not have the opening OP. Therefore, light absorption by the capacitor electrode C of light propagating in the first substrate SUB1 can be suppressed.

[0118] Furthermore, by adjusting the area of ​​the electrode portion EL (or the area of ​​the opening OP), an optimal capacitance can be formed between the pixel electrode PE1 and the capacitor electrode C. For example, in response to the requirement to reduce the size of the switching element SW, an optimal capacitance can be formed by reducing the area of ​​the electrode portion EL overlapping the pixel electrode PE1.

[0119] [Eighth Configuration Example]

[0120] Fig.15 1 is a plan view showing the display device DSP of the eighth configuration example.

[0121] The display device DSP includes a display panel PNL, a first light source unit LU1, and a second light source unit LU2. The display unit DA is provided between the first light source unit LU1 and the second light source unit LU2. Fig.15In the example shown, the display portion DA is formed in a rectangular shape extending along the first direction X. The display portion DA includes a first area DA1, a second area DA2, and a third area DA3. The first area DA1 is an area located near the end E21 of the second substrate SUB2, and includes a first pixel PX1. The second area DA2 is an area located near the end E22 of the second substrate SUB2, and includes a second pixel PX2. The third area DA3 is an area located between the first area DA1 and the second area DA2, and includes a third pixel PX3.

[0122] The first light source unit LU1 includes a plurality of light emitting elements LD1 arranged in the first direction X. These light emitting elements LD1 are arranged along the end E21 and emit light toward the end E21. The second light source unit LU2 includes a plurality of light emitting elements LD2 arranged in the first direction X. These light emitting elements LD2 are arranged along the end E22 and emit light toward the end E22. That is, the light emitting elements LD1 and LD2 are respectively provided along the long sides of the display unit DA.

[0123] The switching element SW in the first pixel PX1 has Figure 3 The semiconductor layer SC is shown. Figure 3 The first light shielding portion LS1 , the second light shielding portion LS2 , the third light shielding portion LS3 and the fourth light shielding portion LS4 are provided between the light emitting element LD1 and the semiconductor layer SC of the first pixel PX1 .

[0124] Next, the switching elements of the second pixel PX2 and the third pixel PX3 are described.

[0125] Fig.16 1 is a plan view showing an example of the layout of the switch element SW2 of the second pixel PX2 and its peripheral portion. Fig.16 In the case where the front end of the arrow indicating the second direction Y is regarded as the top and the opposite end thereof is regarded as the bottom, Fig.16 The layout shown is equivalent to Figure 3 The layout shown is flipped upside down.

[0126] Fig.17 A plan view showing another example of the layout of the switch element SW2 of the second pixel PX2 and its peripheral portion. Fig.17 In the case where the tip of the arrow indicating the second direction Y is taken as the top and the opposite end thereof is taken as the bottom, and the tip of the arrow indicating the first direction X is taken as the right and the opposite end thereof is taken as the left, Fig.17 The layout shown is equivalent to Figure 3 The layout shown is flipped upside down and left to right.

[0127] Fig.16 and Fig.17The cross section of the display panel PNL along the AB line is shown in FIG4 , and the cross section of the display panel PNL along the CD line is shown in FIG5 . Figure 5 As shown, the cross section of the display panel PNL along line EF is as follows Figure 6 shown.

[0128] The first light shielding portion LS1 , the second light shielding portion LS2 , the third light shielding portion LS3 , and the fourth light shielding portion LS4 are provided between the light emitting element LD2 and the semiconductor layer SC of the switching element SW2 .

[0129] Thus, the light from the light emitting element LD2 toward the switch element SW2 is shielded by the first light shielding portion LS1, the second light shielding portion LS2, the third light shielding portion LS3, and the fourth light shielding portion LS4. Therefore, even in the switch element SW2, it is possible to suppress the leakage current generated on the semiconductor layer SC, thereby suppressing the reduction in display quality such as the reduction in brightness due to the change in the potential of the second pixel PX2.

[0130] Fig.18 1 is a plan view showing an example of the layout of the switch element SW3 of the third pixel PX3 and its peripheral portion. Fig.18 The switch element SW3 shown is connected to Figure 3 The switching element SW of the first pixel PX1 shown in FIG. 1 is different in that the first light shielding portion LS1 , the second light shielding portion LS2 , the third light shielding portion LS3 , and the fourth light shielding portion LS4 are not provided. Fig.18 The cross section of the display panel PNL along the CD line is shown as follows: Figure 5 As shown, the cross section of the display panel PNL along line EF is as follows Figure 6 shown.

[0131] Fig.19 It is shown Fig.18 1 is a cross-sectional view of the first substrate SUB1 along line GH. Fig.19 The first substrate SUB1 shown in FIG. Figure 4B Compared with the first substrate SUB1 shown, it is different in that neither the through hole CH1 penetrating the insulating film 11 nor the through hole CH2 penetrating the insulating film 12 is provided.

[0132] like Fig.18 and Fig.19 As shown, the first light shielding portion LS1, the second light shielding portion LS2, the third light shielding portion LS3 and the fourth light shielding portion LS4 are not provided on the third pixel PX3. Therefore, compared with the first pixel PX1 and the second pixel PX2, the opening area of ​​each pixel (the area that contributes to display) can be enlarged.

[0133] [Ninth Configuration Example]

[0134] Fig. 201 is a top view showing a display device DSP according to a ninth configuration example.

[0135] Fig. 20 The display device DSP of the ninth configuration example shown in FIG. Fig.15 Compared with the display device DSP of the eighth configuration example shown, the display unit DA is different in that the display unit DA does not include a third display unit. That is, the display unit DA includes a first area DA1 located near the end E21 and a second area DA2 located near the end E22, and the first area DA1 and the second area DA2 are adjacent to each other in the second direction Y.

[0136] The switching element SW of the first pixel PX1 of the first area DA1 is as follows: Figure 3 shown. Figure 3 The first light shielding portion LS1 , the second light shielding portion LS2 , the third light shielding portion LS3 and the fourth light shielding portion LS4 are disposed between the light emitting element LD1 and the semiconductor layer SC of the first pixel PX1 .

[0137] The switching element SW2 of the second pixel PX2 of the second area DA2 is as follows: Fig.16 or Fig.17 The first light shielding portion LS1, the second light shielding portion LS2, the third light shielding portion LS3 and the fourth light shielding portion LS4 are disposed between the light emitting element LD2 and the semiconductor layer SC of the switch element SW2.

[0138] Also in the ninth configuration example, similar to the eighth configuration example, the switch element SW of the first pixel PX1 and the switch element SW2 of the second pixel PX2 can suppress the leakage current from occurring in the semiconductor layer SC.

[0139] As described above, according to the present embodiment, a display device capable of suppressing a decrease in display quality can be provided.

[0140] It should be noted that, although several embodiments of the present invention have been described, these embodiments are shown only as examples and are not intended to limit the scope of the invention. These new embodiments may also be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are also included in the invention described in the claims and the scope of their equivalents.

[0141] Description of Reference Numerals

[0142] DSP…display device; PNL…display panel; LD…light emitting element; SUB1…first substrate; SUB2…second substrate; LC…liquid crystal layer; LS1…first light shielding portion; LS2…second light shielding portion; LS3…third light shielding portion; LS4…fourth light shielding portion; G…scanning line; S…signal line; SW…switching element; SC…semiconductor layer; PE…pixel electrode.

Claims

1. A display device comprising a first substrate, a second substrate, a liquid crystal layer, and a light-emitting element, The liquid crystal layer is located between the first substrate and the second substrate and includes polymers and liquid crystal molecules. The first substrate includes a transparent substrate, a first insulating film, a switching element, a pixel electrode, a scanning line, and a fourth light shielding portion, the switching element includes a semiconductor layer located on the first insulating film, the pixel electrode is electrically connected to the switching element, and the scanning line is electrically connected to the switching element. The scanning line has a protrusion that protrudes from a position overlapping with the switching element toward a side where the light emitting element is located. The first insulating film has a first through hole that is located between the semiconductor layer and the light emitting element in a plan view and overlaps the protruding portion. The fourth light shielding portion is located between the semiconductor layer and the light emitting element in a plan view, overlaps with the protruding portion, and covers a side wall of the first insulating film at the first through hole.

2. The display device according to claim 1, wherein: The first substrate has a signal line connected to the switching element. The semiconductor layer has a first end portion close to the signal line and a second end portion on the opposite side of the first end portion. The fourth light shielding portion has a third end portion close to the signal line and a fourth end portion on the opposite side of the third end portion, The first end is farther away from the signal line than the third end, The second end is closer to the signal line than the fourth end.

3. The display device according to claim 1 or 2, wherein: The first substrate includes a second insulating film. The semiconductor layer is located between the first insulating film and the second insulating film in cross-sectional view, The fourth light shielding portion is provided between the first insulating film and the second insulating film.

4. A display device comprising a first substrate, a second substrate, a liquid crystal layer and a light emitting element, The liquid crystal layer is located between the first substrate and the second substrate and includes polymers and liquid crystal molecules. The first substrate includes a transparent substrate, a first insulating film, a second insulating film, a switching element, a third insulating film, a pixel electrode, a scanning line, a second light shielding portion, and a fourth light shielding portion, the switching element includes a semiconductor layer located between the first insulating film and the second insulating film, the third insulating film overlaps the switching element, the pixel electrode is electrically connected to the switching element, and the scanning line is electrically connected to the switching element. The first insulating film has a first through hole located between the semiconductor layer and the light emitting element in a plan view. The third insulating film includes a side surface between the semiconductor layer and the first through hole. The second light shielding portion covers the side surface, The fourth light shielding portion is located between the semiconductor layer and the light emitting element in a plan view, covers a side wall of the first insulating film at the first through hole, and is provided between the first insulating film and the second insulating film.

5. The display device according to claim 3, wherein: The first substrate includes a third insulating film and a second light shielding portion overlapping the switching element. The third insulating film includes a side surface between the semiconductor layer and the first through hole. The second light shielding portion covers the side surface.

6. The display device according to any one of claims 3 to 5, wherein: The scanning line is located between the transparent substrate and the first insulating film.

7. The display device according to claim 6, wherein: The first substrate includes a first light shielding portion. The first light shielding portion is provided in a second through hole penetrating the first insulating film and the second insulating film.

8. The display device according to claim 5, wherein: The first substrate includes a metal wiring overlapping the third insulating film. The second light shielding portion is formed integrally with the metal wiring.

9. The display device according to claim 8, wherein: The first substrate includes a capacitor electrode electrically connected to the metal wiring. The capacitor electrode includes an electrode portion overlapping a peripheral portion of the pixel electrode and an opening portion overlapping a central portion of the pixel electrode. The fourth light shielding portion is located at the opening.

10. A display device comprising a first substrate, a second substrate, a liquid crystal layer, and a light emitting element, The liquid crystal layer is located between the first substrate and the second substrate and includes polymers and liquid crystal molecules. The light emitting element is opposite to an end portion of the second substrate, The first substrate includes a plurality of scanning lines, a plurality of signal lines, a plurality of switching elements, a first insulating layer, and a plurality of first light shielding layers. The plurality of scan lines extend along a first direction and are arranged along a second direction intersecting the first direction. The plurality of signal lines extend along the second direction and are arranged along the first direction. The plurality of switch elements are respectively connected to the plurality of scan lines, the plurality of signal lines and the plurality of pixel electrodes and each has a semiconductor layer. The first insulating layer overlaps each of the plurality of switch elements in a plan view and has a first side surface on the light emitting element side. The plurality of first light shielding layers are disposed on the first side surface of the first insulating layer.

11. The display device according to claim 10, wherein: The second substrate has a plurality of openings at positions corresponding to the plurality of pixel electrodes in a plan view, and has a second light shielding layer overlapping the plurality of switching elements, the plurality of scanning lines, and the plurality of signal lines. The first insulating layer overlaps with the second light shielding layer in a plan view. The first side surface of the first insulating layer is located inside an end portion of the second light shielding layer.

12. The display device according to claim 11, wherein: The first insulating layer has a second side surface opposite to the first side surface, The second side surface is located inside an end portion of the second light shielding layer.

13. The display device according to claim 10, wherein: The first insulating layer is an organic insulating film.

14. The display device according to claim 11, wherein: The light emitting element is arranged to face the end of the second substrate in the second direction. Each of the semiconductor layers has a long side extending along the second direction and a short side extending along the first direction, The first side surface on which the first light shielding layer is disposed is a side surface along the short side.

15. The display device according to any one of claims 10 to 14, wherein: The first substrate includes a transparent substrate, a first inorganic insulating film and a second inorganic insulating film. The first inorganic insulating film is disposed on the liquid crystal layer side of the transparent substrate. The second inorganic insulating film is arranged on the liquid crystal layer side of the first inorganic insulating film, The switching element is disposed between the first inorganic insulating film and the second inorganic insulating film.

16. The display device according to claim 15, wherein: The first insulating layer is arranged on the liquid crystal layer side of the second inorganic insulating film.

17. The display device according to claim 11, wherein: The first insulating layer overlaps the plurality of scanning lines and the plurality of signal lines in a plan view. The first side surface of the first insulating layer is located inside an end portion of the second light shielding layer.

18. The display device according to claim 12, wherein: The first insulating layer overlaps the plurality of scanning lines and the plurality of signal lines in a plan view. The first side surface and the second side surface of the first insulating layer are located inside an end portion of the second light shielding layer.

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