Overlay error mark pattern and forming method and measuring method

Abstract

The present invention discloses an overlay error mark pattern and a forming method and a measuring method, belonging to the field of semiconductor photolithography technology. The overlay error mark pattern forming method comprises the overlay error mark pattern including a main mark pattern and at least one auxiliary mark pattern, the main mark pattern including a previous layer mark pattern and a current layer mark pattern, the current layer mark pattern is arranged within the contour of the previous layer mark pattern, and the previous layer mark pattern is arranged within the auxiliary mark pattern. By adding a group of auxiliary mark patterns to the current layer photoresist layer outside the corresponding position of the previous layer mark pattern, the mark pattern in the current layer photoresist is isolated or blocked, thereby preventing the mark pattern in the current layer photoresist from being affected by the surrounding patterns outside the overlay error, and improving the accuracy of the overall measurement data of the overlay error.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor lithography, and in particular to an overlay error mark pattern and a forming method and a measuring method. Background Art

[0002] The photolithography process is a process of transferring the mask pattern to the wafer through a series of steps such as alignment and exposure. In the process of semiconductor device manufacturing, the photolithography process needs to be used multiple times for overlay operations. Usually, special equipment is used to measure the relative position between the current layer pattern and the previous layer pattern on the wafer, and then the overlay error (OVL) is determined through image and algorithm processing. The overlay error quantitatively describes the deviation of the current layer pattern relative to the previous layer (pre-layer) pattern in the X and Y directions and the distribution of this deviation on the wafer surface. It is a key indicator in the production process and affects the yield of the product. At present, the marking patterns commonly used in the industry to obtain overlay errors are mainly divided into two categories: image recognition technology (IBO) and diffraction-based (DBO).

[0003] Common IBO engraving marks include Bar In Bar, Box in Bar, Box in Box, such as Figure 1-Figure 3 The front layer mark pattern 200 and the current layer mark pattern 100 are shown. When measuring the overlay error through the above IBO overlay mark pattern, the photoresist layer morphology (PR profile) of the current layer may be poor or deformed, such as Figure 6-Figure 9 , which will lead to inaccurate reading of the mark signal and thus make it impossible to obtain the actual overlay error measurement data.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide an overlay error mark pattern and a forming method and a measuring method to solve the problem of large deviation of overlay error measurement data when the photoresist layer is thick.

[0006] In order to solve the above technical problems, the present invention provides a method for forming an overlay error mark pattern, wherein the overlay error mark pattern includes a main mark pattern and at least one auxiliary mark pattern, wherein the main mark pattern includes a front layer mark pattern and a current layer mark pattern, wherein the current layer mark pattern is arranged within the contour of the front layer mark pattern, and the front layer mark pattern is arranged within the auxiliary mark pattern, wherein the forming method includes:

[0007] coating a photoresist layer on the substrate on which the front layer mark pattern is formed;

[0008] The photoresist layer is exposed and developed to form the current layer mark pattern and the auxiliary mark pattern, and the photoresist at the auxiliary mark pattern is removed to isolate the photoresist at the current layer mark pattern.

[0009] Preferably, the overlay error mark pattern is an IBO overlay error mark pattern.

[0010] Preferably, the preset distance between the auxiliary marking pattern and the front layer marking pattern is 2-5µm.

[0011] Preferably, the auxiliary marking pattern is a rectangular frame sleeved outside the front layer marking pattern.

[0012] Preferably, it comprises a plurality of auxiliary marking patterns, wherein the auxiliary marking patterns are strip-shaped structures, and the plurality of strip-shaped structures are arranged around the outer side of the front-layer marking pattern.

[0013] Preferably, the thickness of the photoresist layer is greater than 1 µm.

[0014] Preferably, the length of the auxiliary mark pattern is 10-40 μm.

[0015] Based on the same technical concept, the present disclosure further provides an overlay error mark pattern, which is formed by the above-mentioned overlay error mark pattern forming method, including:

[0016] A front layer mark pattern is arranged on the front layer dielectric layer of the substrate, and the front layer mark pattern has an inner side and an outer side opposite to each other;

[0017] The current layer mark pattern is formed in the current layer dielectric layer and is located inside the position of the previous layer mark pattern;

[0018] At least one auxiliary mark pattern is formed on the current medium layer corresponding to the outer position of the front mark pattern, and there is a preset distance between the auxiliary mark pattern and the front mark pattern.

[0019] Preferably, the material of the current dielectric layer is photoresist, and the thickness of the photoresist is greater than 1µm.

[0020] Based on the same technical concept, the present disclosure also provides a method for measuring overlay error, which uses the overlay error mark pattern as described above for measurement.

[0021] In the method for forming an overlay error mark pattern provided by the present invention, a new overlay error mark pattern is proposed, and a group of auxiliary mark patterns are added to the current photoresist layer outside the corresponding position of the previous mark pattern to isolate or block the mark pattern in the current photoresist layer, thereby avoiding the mark pattern in the current photoresist layer from being affected by the surrounding patterns outside the overlay error, thereby improving the problem that the overlay error mark pattern of the current layer is easy to deform when the photoresist is too thick, similar to the IBO overlay pattern mark, and improving the accuracy of the overall measurement data of the overlay error, so that the overall measurement data of the overlay error mark pattern can truly reflect the overlay deviation of the actual photolithography process.

[0022] The overlay error mark pattern provided by the present invention and the method for forming the overlay error mark pattern provided by the present invention belong to the same inventive concept. Therefore, the overlay error mark pattern provided by the present invention at least has all the advantages of the method for forming the overlay error mark pattern provided by the present invention, which will not be repeated here.

[0023] The overlay error measurement method provided by the present invention and the method for forming an overlay error mark pattern provided by the present invention belong to the same inventive concept. Therefore, the overlay error measurement method provided by the present invention has at least all the advantages of the method for forming an overlay error mark pattern provided by the present invention, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0025] Figure 1 It is a schematic diagram of the existing Bar in Bar marking graphic structure;

[0026] Figure 2 It is a schematic diagram of the existing Box in Bar markup graphic structure;

[0027] Figure 3 It is a schematic diagram of the existing Box in Box marking graphic structure;

[0028] Figure 4 It is the Raw data diagram of the overlay error diagram of the existing marking pattern in different surrounding environments;

[0029] Figure 5 It is the Qmerit diagram of the overlay error diagram of the existing marking pattern in different surrounding environments;

[0030] Figure 6 It is an electron microscope image of the existing marking pattern;

[0031] Figure 7 It is another electron microscope image of the existing marking pattern;

[0032] Figure 8 It is another electron microscope image of the existing marking pattern;

[0033] Fig. 9 is along Figure 1 Schematic diagram of the cross section along the AB direction;

[0034] Fig.10 It is a schematic diagram of the structure of an embodiment of the present invention on a Bar in Bar marking graphic;

[0035] Fig.11 It is a schematic diagram of the structure of an embodiment of the present invention on a Box in Bar mark graphic;

[0036] Fig.12 It is a schematic diagram of the structure of an embodiment of the present invention on a Box in Box mark graphic;

[0037] Fig.13 is a schematic diagram of the structure of another embodiment of the present invention on a Bar in Bar marking graphic;

[0038] Fig.14 is a schematic diagram of the structure of another embodiment of the present invention on a Box in Bar mark graphic;

[0039] Fig.15 is a schematic diagram of the structure of another embodiment of the present invention on a Box in Box mark graphic;

[0040] Fig.16 is along Fig.10 Schematic diagram of the cross section along the CD direction.

[0041] In the attached figure:

[0042] 100, current layer mark graphic; 200, previous layer mark graphic; 300, auxiliary mark graphic. DETAILED DESCRIPTION

[0043] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0044] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. The term "proximal end" is usually the end close to the operator, and the term "distal end" is usually the end close to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" usually refer to two corresponding parts, which include not only the endpoints. The terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of the two elements or the interaction relationship between the two elements. In addition, as used in the present invention, an element is arranged on another element, which usually only means that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0045] The inventors have found that the marking pattern of the overlay error is often Figure 1-Figure 3 The Bar in Bar, Box in Bar and Box in Box marking graphs shown in the figure are analyzed as follows: Figure 4-Figure 5 They are the Raw data and Qmerit data of the overlay error mark graphics in different surrounding environments. The Raw data diverges in two directions, and the Qmerit center and upper right corner are obviously different from the others. It can be seen that this is caused by the asymmetry of the photoresist (PR) around the overlay error mark graphics. The different sizes of PR during PAB make their curing and shrinkage rates different, resulting in asymmetric overlay error mark graphics and poor Qmerit.

[0046] The inventors further discovered that the asymmetric mark pattern of the above-mentioned overlay error, the damage of the overlay error mark pattern (OVL Mark damage) or the morphology problem of the photoresist layer generally occurs in a thicker photoresist layer. An overly thick photoresist layer will cause asymmetric pattern after exposure, resulting in measurement errors, which directly affects the scanner's compensation and correction of the layer. Thick photoresist layers are usually used as barrier layers for high-dose ion implantation layers. The size of the above-mentioned mark pattern is usually 24μm×24μm, which is relatively large and occupies a larger area on the mask. It is easier to form an asymmetric pattern on the wafer. Please refer to Figure 6-Figure 8 Electron micrographs of Fig. 9 The example diagram of the layout cross-section results in inaccurate measurement of the overlay error, which makes the exposure machine unable to compensate and correct in time, resulting in a decrease in product yield.

[0047] Based on this, the core idea of ​​the present invention is to propose a new marking pattern of overlay error, add an auxiliary marking pattern (Assist pattern) in the current photoresist layer outside the corresponding position of the previous layer marking pattern, isolate or block the marking pattern in the current photoresist layer, thereby avoiding the mark pattern in the current photoresist layer from being affected by the surrounding patterns outside the overlay error, and improve the problem that the overlay error mark of the current layer is easy to deform when the photoresist is too thick, similar to the IBO overlay pattern mark, and improve the accuracy of the overall measurement data of the overlay error, so that the overall measurement data of the overlay error mark pattern can truly reflect the overlay deviation of the actual lithography process.

[0048] For details, please refer to Figure 10-Figure 16 , which is a schematic diagram of an embodiment of the present invention. Based on the same technical concept, the present disclosure provides a method for forming an overlay error mark pattern, wherein the overlay error mark pattern includes a main mark pattern and at least one auxiliary mark pattern 300, wherein the main mark pattern includes a front layer mark pattern 200 and a current layer mark pattern 100, wherein the current layer mark pattern 100 is arranged within the contour of the front layer mark pattern 200, and the front layer mark pattern 200 is arranged within the auxiliary mark pattern 300, wherein the forming method includes:

[0049] Applying a photoresist layer on the substrate on which the front layer mark pattern 200 is formed;

[0050] The photoresist layer is exposed and developed to form the current layer mark pattern 100 and the auxiliary mark pattern 300 , and the photoresist at the auxiliary mark pattern 300 is removed to isolate the photoresist at the current layer mark pattern 100 .

[0051] like Figure 10-Figure 15As shown, in the measurement process of the overlay error of a thicker photoresist layer, especially when the photoresist thickness is greater than 1µm, a group of auxiliary mark patterns 300 are added to the current photoresist layer outside the corresponding positions of the different types of front-layer mark patterns 200 to isolate or block the mark patterns in the current photoresist layer, thereby preventing the mark patterns in the current photoresist layer from being affected by the surrounding patterns outside the overlay error, improving the problem that the overlay error mark pattern of the current layer is easy to deform when the photoresist is too thick, and further improving the accuracy of the overall measurement data of the overlay error, so that the overall measurement data of the overlay error mark pattern can truly reflect the overlay deviation of the actual photolithography process. For example Fig.16 The morphology of the photoresist after adopting the auxiliary mark pattern 300 provided by the present disclosure is shown.

[0052] Obviously, the front-layer marking pattern 200 can be directly formed on the substrate surface by etching, or formed by a front-layer dielectric layer existing on the substrate surface, and no specific limitation is made here. The front-layer dielectric layer can also be a HM (Hard Mask) or a photoresist. The auxiliary marking pattern 300 is used to perform optical compensation or optical balance, thereby reducing the presence of large blocks of photoresist near the marking pattern, making the shrinkage and curing process of the photoresist relatively balanced, and improving the morphology of the marking pattern with overlay error.

[0053] The material of the photoresist layer is, for example, a sticky photoresist film or photoresist used in semiconductor chip packaging or printed circuit board manufacturing, usually a photosensitive polymer material, which may be polyimide (PI: polyimide), benzocyclobutene (BCB: bis-BenzoCycloButene), polyparaphenylenebenzobisoxazole (PBO: P-phenylene-2,6-BenzobisOxazole).

[0054] Exemplarily, the overlay error mark pattern is an IBO overlay error mark pattern.

[0055] In one embodiment, a plurality of auxiliary marking patterns 300 are included, and the auxiliary marking patterns 300 are strip structures, and the plurality of strip structures are arranged around the outside of the front layer marking pattern 200. For example, four strip structures are arranged to match the shape of the front layer marking pattern 200.

[0056] like Fig.10 As shown, the front layer marking pattern 200 and the current layer marking pattern 100 are both four strip structures enclosed in a rectangle, and a strip structure parallel to each strip structure of the front layer marking pattern 200 is arranged outside as an auxiliary marking pattern 300. Fig.11As shown, the front layer marking pattern 200 is a strip structure enclosing four rectangles, and the current layer marking pattern 100 is a rectangular structure. Similarly, a strip structure is arranged in parallel on the outer side of the front layer marking pattern 200 as an auxiliary marking pattern 300.

[0057] Obviously, the number and distribution of the stripe structures can also be set according to the distribution of the photoresist outside the front-layer mark pattern 200. For example, at least two stripe structures parallel to each stripe structure of the front-layer mark pattern 200 are set outside as the auxiliary mark pattern 300; or a stripe structure is set outside a stripe structure of the front-layer mark pattern 200, and at least two stripe structures parallel to each stripe structure of the front-layer mark pattern 200 are set outside as the auxiliary mark pattern 300.

[0058] like Fig.12 The front layer mark pattern 200 and the current layer mark pattern 100 are both rectangular structures, and each side of the front layer mark pattern 200 is provided with a strip structure parallel thereto.

[0059] The distance between the auxiliary marking pattern 300 and the front layer marking pattern 200 is 2-5µm. When the auxiliary marking pattern 300 is a strip structure, the length of the strip structure is 10-40µm and the width is 1-5µm.

[0060] In one embodiment, the auxiliary marking pattern 300 is a rectangular frame that is sleeved outside the front marking pattern 200. Figure 13-Figure 15 For the front layer mark pattern 200 and the current layer mark pattern 100 of different structures, an auxiliary mark pattern 300 with a rectangular frame structure is formed outside the front layer mark pattern 200. The distance between the auxiliary mark pattern 300 and the front layer mark pattern 200 is 2-5µm. When the auxiliary mark pattern 300 is a rectangular frame, the length of each side is 10-40µm, and the line width of the rectangular frame is 1-5µm.

[0061] Based on the same technical concept, the present invention also discloses an overlay error mark pattern, including:

[0062] A front layer mark pattern 200 is disposed on the front dielectric layer of the substrate, and the front layer mark pattern 200 has an inner side and an outer side opposite to each other;

[0063] The current layer mark pattern 100 is formed in the current layer dielectric layer and is located inside the position of the previous layer mark pattern 200;

[0064] At least one auxiliary mark pattern 300 is formed on the current dielectric layer corresponding to the outer position of the front mark pattern 200 , and there is a preset distance between the auxiliary mark pattern 300 and the front mark pattern 200 .

[0065] like Figure 10-Figure 15 As shown, in the measurement process of the overlay error containing a thicker photoresist layer, especially when the material of the current dielectric layer is photoresist and the thickness of the photoresist is greater than 1µm, a group of auxiliary mark patterns 300 are added to the current photoresist layer outside the corresponding position of the previous mark pattern 200 to isolate or block the mark pattern in the current photoresist layer, thereby preventing the mark pattern in the current photoresist layer from being affected by the surrounding patterns outside the overlay error, improving the problem of the overlay error mark pattern of the current layer being easily deformed when the photoresist is too thick, and improving the accuracy of the overall measurement data of the overlay error, so that the overall measurement data of the overlay error mark pattern can truly reflect the overlay deviation of the actual photolithography process. For example Fig.16 The morphology of the photoresist after adopting the auxiliary mark pattern 300 provided by the present disclosure is shown.

[0066] In one embodiment, a plurality of auxiliary marking patterns 300 are included, and the auxiliary marking patterns 300 are strip structures, and the plurality of strip structures are arranged around the outside of the front layer marking pattern 200. For example, four strip structures are arranged to match the shape of the front layer marking pattern 200.

[0067] like Fig.10 As shown, the front layer marking pattern 200 and the current layer marking pattern 100 are both four strip structures enclosed in a rectangle, and a strip structure parallel to each strip structure of the front layer marking pattern 200 is arranged outside as an auxiliary marking pattern 300. Fig.11 As shown, the front layer marking pattern 200 is a strip structure enclosing four rectangles, and the current layer marking pattern 100 is a rectangular structure. Similarly, a strip structure is arranged in parallel on the outer side of the front layer marking pattern 200 as an auxiliary marking pattern 300.

[0068] Obviously, the number and distribution of the stripe structures can also be set according to the distribution of the light resistance outside the front-layer mark pattern 200. For example, at least two stripe structures parallel to each stripe structure of the front-layer mark pattern 200 are set outside as the auxiliary mark pattern 300; or a stripe structure is set outside one stripe structure of the front-layer mark pattern 200, and at least two stripe structures parallel to each stripe structure of the front-layer mark pattern 200 are set outside another stripe structure of the front-layer mark pattern 200 as the auxiliary mark pattern 300.

[0069] like Fig.12 The front layer mark pattern 200 and the current layer mark pattern 100 are both rectangular structures, and each side of the front layer mark pattern 200 is provided with a strip structure parallel thereto.

[0070] The distance between the auxiliary marking pattern 300 and the front layer marking pattern 200 is 2-5µm. When the auxiliary marking pattern 300 is a strip structure, the length of the strip structure is 10-40µm and the width is 1-5µm.

[0071] In one embodiment, the auxiliary marking pattern 300 is a rectangular frame that is sleeved outside the front marking pattern 200. Figure 13-Figure 15 For the front layer mark pattern 200 and the current layer mark pattern 100 of different structures, an auxiliary mark pattern 300 with a rectangular frame structure is formed outside the front layer mark pattern 200. The distance between the auxiliary mark pattern 300 and the front layer mark pattern 200 is 2-5µm. When the auxiliary mark pattern 300 is a rectangular frame, the length of each side is 10-40µm, and the line width of the rectangular frame is 1-5µm.

[0072] Based on the same technical concept, the present disclosure also provides a method for measuring overlay error, which uses the above-mentioned overlay error mark pattern for measurement, and includes the following steps:

[0073] Providing a substrate, and coating a photoresist layer on the substrate on which the front layer mark pattern 200 is formed;

[0074] Exposing and developing on the photoresist layer to form the current layer mark pattern 100 and the auxiliary mark pattern 300, and removing the photoresist at the auxiliary mark pattern 300 and the photoresist at the current layer mark pattern 100;

[0075] The offset value between the previous layer mark pattern 200 and the current layer mark pattern 100 is measured.

[0076] In the overlay error mark pattern, formation method, and measurement method provided by the present invention, a group of auxiliary mark patterns are added to the current photoresist layer outside the corresponding position of the previous mark pattern to isolate or block the mark pattern in the current photoresist layer, thereby avoiding the mark pattern in the current photoresist layer from being affected by the surrounding patterns outside the overlay error, improving the problem that the overlay error mark pattern of the current layer is easy to deform when the photoresist is too thick, and improving the accuracy of the overall measurement data of the overlay error, so that the overall measurement data of the overlay error mark pattern can truly reflect the overlay deviation of the actual photolithography process. The above description is only a description of the preferred embodiment of the present invention, and is not any limitation to the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming an overlay error mark pattern, characterized in that: The overlay error mark pattern includes a main mark pattern and at least one auxiliary mark pattern, the main mark pattern includes a front layer mark pattern and a current layer mark pattern, the current layer mark pattern is arranged within the outline of the front layer mark pattern, and the front layer mark pattern is arranged within the auxiliary mark pattern, and the forming method includes: coating a photoresist layer on the substrate on which the front layer mark pattern is formed; The photoresist layer is exposed and developed to form the current layer mark pattern and the auxiliary mark pattern, and the photoresist at the auxiliary mark pattern is removed to isolate the photoresist at the current layer mark pattern.

2. The method according to claim 1, characterized in that The overlay error mark pattern is an IBO overlay error mark pattern.

3. The method according to claim 1, characterized in that The preset distance between the auxiliary marking pattern and the front layer marking pattern is 2-5µm.

4. The method according to claim 1, characterized in that: The auxiliary marking pattern is a rectangular frame sleeved outside the front layer marking pattern.

5. The method according to claim 1, characterized in that It comprises a plurality of auxiliary marking patterns, wherein the auxiliary marking patterns are strip-shaped structures, and the plurality of strip-shaped structures are arranged around the outer side of the front-layer marking pattern.

6. The method according to claim 1, characterized in that The thickness of the photoresist layer is greater than 1 μm.

7. The method according to claim 1, characterized in that The length of the auxiliary marking pattern is 10-40 μm.

8. An overlay error mark pattern, formed by the overlay error mark pattern forming method according to any one of claims 1 to 7, characterized in that: include: A front layer mark pattern is arranged on the front layer dielectric layer of the substrate, and the front layer mark pattern has an inner side and an outer side opposite to each other; The current layer mark pattern is formed in the current layer dielectric layer and is located inside the position of the previous layer mark pattern; At least one auxiliary mark pattern is formed on the current medium layer corresponding to the outer position of the front mark pattern, and there is a preset distance between the auxiliary mark pattern and the front mark pattern.

9. The overlay error mark pattern according to claim 8, characterized in that: The material of the current dielectric layer is photoresist, and the thickness of the photoresist is greater than 1µm.

10. A method for measuring overlay error, characterized in that: The measurement is performed using the overlay error mark pattern as described in claim 8.

Images