Hardware reset circuit, daisy chain communication system, electronic circuit and electronic device

Abstract

The invention provides a hardware reset circuit, a daisy chain communication system, an electronic circuit and electronic equipment. The hardware reset circuit comprises an independent voltage stabilization source module, a reset detection module and a power supply reset module. The independent voltage-stabilizing source module is used for supplying power to the other two modules, the reset detection module is used for judging whether a reset signal is input by a chip serial communication pin, if the reset signal is input, the reset signal is transmitted to the power supply reset module, and if the reset signal is input, the power supply reset module is reset. And the power supply reset module is used for cutting off the power supply voltage input to the linear voltage stabilization module according to the reset signal and pulling down the module power supply voltage output by the linear voltage stabilization module so as to reset the chip. According to the hardware reset circuit, reset is completed by detecting the signal input by the serial communication pin and then disconnecting the power supply voltage and the power supply voltage of the pull-down module, so that the reset circuit can complete reset without additionally arranging pins, and the conditions of mistaken touch and incomplete reset are well avoided.

Description

Technical Field

[0001] The invention relates to the field of reset circuits, and in particular to a hardware reset circuit, a daisy chain communication system, an electronic circuit and an electronic device. Background Art

[0002] Hardware reset circuit, also known as initialization circuit, is an important component in electronic systems. Its main function is to restore the circuit's operating state to the initial state under certain circumstances. This is an important measure to ensure the normal operation of the circuit and avoid abnormal conditions.

[0003] In electronic systems, due to various factors, such as power fluctuations, electromagnetic interference, hardware failures, etc., the operating state of the circuit may deviate from the normal state, causing the system to fail to work properly. At this time, the hardware reset circuit can play a role, restoring the circuit to the initial state through a certain mechanism, thereby ensuring the normal operation of the system.

[0004] Traditional hardware reset systems usually reset the target circuit through key combinations or communication interface signals. This not only requires the system to provide specific pins and their combination logic to complete the reset, but also increases system resources and may even cause false triggering.

[0005] Therefore, providing a reset circuit that does not require additional pins and can avoid false triggering has become a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a hardware reset circuit, which solves the problem that the existing reset circuit needs to add an extra port and has the risk of false triggering.

[0007] According to a first aspect of the present invention, there is provided a hardware reset circuit, characterized in that it is used to pull down and power off a linear voltage regulator module in a chip to reset, and the linear voltage regulator module is used to power other functional modules in the chip that have no reset function, including:

[0008] An independent voltage-stabilizing source module, the independent voltage-stabilizing source module is used to supply power to the reset detection module and the power reset module;

[0009] A reset detection module is used to detect a communication signal connected to a serial communication pin of a chip. If the communication signal is determined to be a reset signal, the reset detection module outputs the reset signal.

[0010] A power reset module is used to pull down the power supply voltage input to the linear voltage regulator module and the module power supply voltage output by the linear voltage regulator module for a first time according to the input reset signal.

[0011] The independent voltage stabilizing source module, the reset detection module and the power reset module are all integrated in the same chip.

[0012] Optionally, the power reset module includes:

[0013] A reset capacitor charging switch, wherein the reset capacitor charging switch is configured to be turned on by being controlled by the reset signal;

[0014] A pull-down power-off control unit, the pull-down power-off control unit being used to output a first control signal lasting for a first time according to the power supply of the independent voltage-stabilizing source module when the reset capacitor charging switch is turned on;

[0015] A pull-down power-off unit is used to pull down the power supply voltage input to the linear voltage regulator module and the module power supply voltage output by the linear voltage regulator module according to the first control signal.

[0016] Optionally, a first end of the reset capacitor charging switch is connected to a first end of the pull-down power-off control unit, and a second end of the reset capacitor charging switch is connected to a first end of the independent voltage stabilizing source module.

[0017] Optionally, the pull-down power-off unit includes a first NMOS tube and a second NMOS tube, the gate ends of the first NMOS tube and the second NMOS tube are the first end of the pull-down power-off unit, the source ends of the first NMOS tube and the second NMOS tube are the second end of the pull-down power-off unit, the drain end of the first NMOS tube is connected to the first end of the linear voltage regulator module, and the drain end of the second NMOS tube is connected to the second end of the linear voltage regulator module.

[0018] Optionally, the pull-down power-off control unit includes a first resistor and a reset capacitor, the first end of the reset capacitor is respectively connected to the first end of the first resistor, the first end of the reset capacitor charging switch and the first end of the pull-down power-off unit, and the second end of the reset capacitor is respectively connected to the second end of the first resistor, the second end of the pull-down power-off unit and ground.

[0019] Optionally, the independent voltage-stabilizing source module includes a second resistor, a first diode and a third NMOS tube, the first end of the second resistor is connected to the power supply voltage and connected to the drain end of the third NMOS tube, the second end of the second resistor is connected to the cathode of the first diode and the gate end of the third NMOS tube, the source end of the third NMOS tube is connected to the second end of the reset capacitor charging switch, and the source end of the third NMOS tube is the first end of the independent voltage-stabilizing source module.

[0020] Optionally, the reset detection module includes a first filtering unit, a second filtering unit, a first operational amplifier, a second operational amplifier and a first counter; the first end of the first filtering unit is connected to the first voltage divider of the differential voltage of the communication signal, the first end of the second filtering unit is connected to the second voltage divider of the differential voltage of the communication signal, the second end of the first filtering unit is connected to the inverting input of the first operational amplifier, the second end of the second filtering unit is connected to the non-inverting input of the second operational amplifier, the non-inverting input of the first operational amplifier is connected to a first reference voltage, the inverting input of the second operational amplifier is connected to a second reference voltage, the output of the first operational amplifier is connected to the output of the second operational amplifier, and the output of the first operational amplifier and the output of the second operational amplifier jointly output a reset pulse; the first counter is used to record the number of reset pulses.

[0021] Optionally, the first filtering unit and the second filtering unit have the same structure, and the first operational amplifier and the second operational amplifier have the same parameters.

[0022] Optionally, the power reset module also includes a second diode, the anode of the second diode is connected to the first end of the reset capacitor charging switch, and the cathode of the second diode is connected to the first end of the pull-down power-off unit and the first end of the pull-down power-off control unit.

[0023] According to a second aspect of the present invention, there is provided a daisy chain communication system, characterized in that it comprises a plurality of chips and micro control units connected in series;

[0024] The serial input pin of the first chip is connected to the serial output pin of the micro control unit, the serial output pin of each chip is connected to the serial input pin of the next chip, and each chip is integrated with the hardware reset circuit;

[0025] The serial output pin of the microcontroller unit outputs a reset signal to the serial input pin of the first chip. After receiving the reset signal, the hardware reset circuit on the chip starts to pull down and power off the linear voltage regulator module in the chip to reset. After the linear voltage regulator module completes the reset, the reset signal is transmitted from the serial output pin of the chip to the serial input pin of the next-level chip. The next-level chip starts to pull down and power off the linear voltage regulator module in the chip to reset, and so on. The reset signal starts from the first chip and is transmitted to the next-level chip after the hardware reset circuit in the chip completes the reset, completing the reset of the linear voltage regulator units corresponding to all the chips connected in series in turn.

[0026] According to a third aspect of the present invention, there is provided an electronic circuit, characterized in that it comprises the hardware reset circuit.

[0027] According to a fourth aspect of the present invention, there is provided an electronic device, characterized in that it comprises the electronic circuit.

[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0029] The hardware reset circuit provided by the embodiment of the present invention includes a reset detection module and a power reset module. The reset detection module is used to detect whether the communication signal input from the serial communication pin is a reset signal. If it is detected as a reset signal, the reset detection module will send a reset signal to the power reset module to start the power reset module. This avoids the use of additional input pins to complete the reset, which is conducive to integration, and completes the reset through a specific reset signal, avoiding the hardware reset function from being triggered by mistake in a complex application environment.

[0030] Furthermore, the power reset module in the embodiment of the present invention completes the reset by disconnecting the power supply voltage and the pull-down module power supply voltage at the same time, so that the reset can be more complete and the occurrence of incomplete reset can be reduced.

[0031] The daisy chain communication system provided by the embodiment of the present invention includes a plurality of chips and micro control units connected in series, and each chip is integrated with the hardware reset circuit. The micro control unit outputs a reset signal to the hardware reset circuit in the first chip, and the hardware reset circuit in the chip starts to work. After the reset is completed, the reset signal is transmitted to the next level chip, and so on until the last level chip completes the reset. The daisy chain communication system can complete the reset of all chips in the system in an orderly manner through the level-by-level transmission of the reset signal, which greatly saves system resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The circuit block diagram of the hardware reset circuit provided by the embodiment of the present invention is Figure 1 ;

[0033] Figure 2 The circuit block diagram of the hardware reset circuit provided by the embodiment of the present invention is Figure 2 ;

[0034] Figure 3 FIG. 1 is a schematic diagram of the circuit structure of the hardware reset circuit provided by an embodiment of the present invention. Figure 1 ;

[0035] Figure 4 FIG. 1 is a schematic diagram of the circuit structure of the hardware reset circuit provided by an embodiment of the present invention. Figure 2 ;

[0036] Figure 5 FIG. 1 is a schematic diagram of the circuit structure of the hardware reset circuit provided by an embodiment of the present invention. Figure 3 ;

[0037] Figure 6 FIG. 1 is a schematic diagram of the circuit structure of the hardware reset circuit provided by an embodiment of the present invention. Figure 4 ;

[0038] Figure 7 FIG. 1 is a schematic diagram of the circuit structure of the hardware reset circuit provided by an embodiment of the present invention. Figure 5 ;

[0039] Figure 8 4 is a circuit block diagram of a daisy chain communication system provided by an embodiment of the present invention.

[0040] Reference numerals:

[0041] V1-reset signal;

[0042] V2-reset pulse;

[0043] VP-supply voltage;

[0044] Wake-communication signal;

[0045] VQ-module power supply voltage;

[0046] C1-reset capacitor;

[0047] K1-reset capacitor charging switch;

[0048] Q1-first NMOS tube;

[0049] Q2- the second NMOS tube;

[0050] Q3-the third NMOS tube;

[0051] Q4-the fourth NMOS tube;

[0052] R1-first resistor;

[0053] R2-second resistor;

[0054] R3-the third resistor;

[0055] D1-first diode;

[0056] D2-second diode;

[0057] ISOA-first partial pressure;

[0058] ISOB-second partial pressure;

[0059] VREFP-first reference voltage;

[0060] VREFN-second reference voltage;

[0061] A1 - first operational amplifier;

[0062] A2 - Second operational amplifier. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the embodiments in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The terms "first", "second", "third", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0064] As described in the background technology, in order to meet the needs of chip reset, the prior art usually adopts a traditional hardware reset system, that is, reset the target circuit through a key combination or a communication interface signal. This not only requires the system to provide specific pins and their combination logic to complete the reset, but also increases system resources, and even causes false triggering and incomplete reset.

[0065] In view of this, the present invention creatively proposes a new hardware reset circuit.

[0066] in, Figure 1 The circuit block diagram of the hardware reset circuit provided by the embodiment of the present invention is Figure 1 .

[0067] Please refer to Figure 1 An embodiment of the present invention provides a hardware reset circuit, characterized in that it includes:

[0068] An independent voltage-stabilizing source module 11, wherein the independent voltage-stabilizing source module 11 is used to supply power to the reset detection module 12 and the power reset module 13;

[0069] The reset detection module 12 is used to detect the communication signal Wake connected to the serial communication pin of the chip 1. If the communication signal Wake is detected to be the reset signal V1, the reset detection module 12 outputs the reset signal V1.

[0070] The power reset module 13 is used to pull down the power supply voltage VP input to the power reset module 14 and the module power supply voltage VQ output by the power reset module 14 for a first time according to the input reset signal V1.

[0071] The independent voltage stabilizing source module 11 , the reset detection module 12 and the power reset module 13 are all integrated in the same chip 1 .

[0072] Through the above technical means, the embodiment of the present invention can provide a reset circuit that does not require additional pins and can avoid false triggering. The specific principle is as follows:

[0073] In the hardware reset circuit of the embodiment of the present invention, a reset detection module 12 and a power reset module 13 are provided. The reset detection module 12 is used to determine whether the communication signal Wake connected to the serial communication pin of the chip 1 is a reset signal V1. If it is a reset signal, the reset detection module 12 outputs the reset signal V1 to the power reset module 13. The power reset module 13 disconnects and pulls down the power supply voltage VP input to the power reset module 14 and the module power supply voltage VQ output by the power reset module 14 for the first time according to the reset signal V1, thereby completing the reset of the chip 1.

[0074] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0075] Figure 2 The circuit block diagram of the hardware reset circuit provided by the embodiment of the present invention is Figure 2 .

[0076] Please refer to Figure 2 As a specific implementation, the power reset module 13 includes:

[0077] A reset capacitor charging switch K1, wherein the reset capacitor charging switch K1 is configured to be turned on by being controlled by the reset signal V1;

[0078] A pull-down power-off control unit 131, wherein the pull-down power-off control unit 131 is configured to output a first control signal lasting for a first time according to the power supply of the independent voltage-stabilizing source module 11 when the reset capacitor charging switch K1 is turned on;

[0079] The pull-down power-off unit 132 is used to disconnect and pull down the power supply voltage VP input to the power reset module 14 and the module power supply voltage VQ output by the power reset module 14 according to the first control signal.

[0080] A first end of the reset capacitor charging switch K1 is connected to a first end of the pull-down power-off control unit 131 , and a second end of the reset capacitor charging switch K1 is connected to the independent voltage stabilizing source module 11 .

[0081] Figure 3 FIG. 1 is a schematic diagram of the circuit structure of the hardware reset circuit provided by an embodiment of the present invention. Figure 1 .

[0082] Please refer to Figure 3 As a specific implementation, the pull-down power-off unit 132 includes a first NMOS tube Q1 and a second NMOS tube Q2, the gate terminals of the first NMOS tube Q1 and the second NMOS tube Q2 are the first terminals of the pull-down power-off unit 132, the source terminals of the first NMOS tube Q1 and the second NMOS tube Q2 are the second terminals of the pull-down power-off unit 132, the drain terminal of the first NMOS tube Q1 is connected to the first terminal of the linear voltage regulator module 14, and the drain terminal of the second NMOS tube Q2 is connected to the second terminal of the linear voltage regulator module 14.

[0083] The pull-down power-off control unit 131 includes a first resistor R1 and a reset capacitor C1, the first end of the reset capacitor C1 is respectively connected to the first end of the first resistor R1, the first end of the reset capacitor charging switch K1 and the first end of the pull-down power-off unit 132, and the second end of the reset capacitor C1 is respectively connected to the second end of the first resistor R1, the second end of the pull-down power-off unit 132 and the ground.

[0084] The following Figure 3 Taking the circuit structure diagram shown in FIG. 1 as an example, the working process of the pull-down power-off unit 132 and the pull-down power-off control unit 131 in the hardware reset circuit provided by the embodiment of the present invention is described:

[0085] Please refer to Figure 3, when the reset signal V1 controls the reset capacitor charging switch K1 to close, the pull-down power-off control unit 131 is connected to the independent voltage-stabilizing source module 11, and the independent voltage-stabilizing source module 11 supplies power to the reset capacitor C1 in the pull-down power-off control unit 131, and the reset capacitor C1 starts to charge. When the voltage across the reset capacitor C1 reaches the first control voltage, the first NMOS transistor Q1 and the second NMOS transistor Q2 of the pull-down power-off unit 132 start to conduct. At this time, the power supply voltage VP input to the power reset module 14 is disconnected, and the module power supply voltage VQ output by the power reset module 14 is pulled down to the ground, and the chip 1 starts to reset. Then the reset capacitor C1 is discharged through the first resistor R1, and the discharge time is the first time. Within the first time, the pull-down power-off module will disconnect the power supply voltage VP input to the linear voltage-stabilizing module 14 and pull down the module power supply voltage VQ output by the linear voltage-stabilizing module 14. When the charge on the reset capacitor C1 is completely released, the first NMOS transistor Q1 and the second NMOS transistor Q2 are closed, the power supply voltage VP input to the power reset module 14 and the module power supply voltage VQ output by the power reset module 14 are restored, and the chip 1 completes the reset.

[0086] Figure 4 FIG. 1 is a schematic diagram of a circuit structure of a hardware reset circuit provided by an embodiment of the present invention. Figure 2 .

[0087] Please refer to Figure 4 As a specific implementation, the independent voltage-stabilizing source module 11 includes a second resistor R2, a first diode D1 and a third NMOS tube Q3, the first end of the second resistor R2 is connected to the power supply voltage VP and connected to the drain end of the third NMOS tube Q3, the second end of the second resistor R2 is connected to the cathode of the first diode D1 and the gate end of the third NMOS tube Q3, the source end of the third NMOS tube Q3 is connected to the second end of the reset capacitor charging switch K1, and the source end of the third NMOS tube Q3 is the first end of the independent voltage-stabilizing source module 11.

[0088] Figure 5 FIG. 1 is a schematic diagram of a circuit structure of a hardware reset circuit provided by an embodiment of the present invention. Figure 3 .

[0089] Please refer to Figure 5As a specific implementation, the reset detection module 12 includes a first filtering unit 121, a second filtering unit 122, a first operational amplifier A1, a second operational amplifier A2 and a first counter 123; the first end of the first filtering unit 121 is connected to the first divided voltage ISOA of the differential voltage of the communication signal Wake, the first end of the second filtering unit 122 is connected to the second divided voltage ISOB of the differential voltage of the communication signal Wake, the second end of the first filtering unit 121 is connected to the inverting input end of the first operational amplifier A1, the second end of the second filtering unit 122 is connected to the non-inverting input end of the second operational amplifier A2, the non-inverting input end of the first operational amplifier A1 is connected to the first reference voltage VREFP, the inverting input end of the second operational amplifier A2 is connected to the second reference voltage VREFN, the output end of the first operational amplifier A1 is connected to the output end of the second operational amplifier A2, the output end of the first operational amplifier A1 and the output end of the second operational amplifier A2 jointly output a reset pulse V2; the first counter 123 is used to record the number of the reset pulses V2.

[0090] The first filtering unit 121 and the second filtering unit 122 have the same structure, and the first operational amplifier A1 and the second operational amplifier A2 have the same parameters.

[0091] The following Figure 5 Taking the circuit structure diagram shown as an example, the working process of the reset detection module 12 in the hardware reset circuit provided by the embodiment of the present invention is described:

[0092] Please refer to Figure 5 After the differential voltage of the communication signal Wake is connected to the reset detection module 12, it passes through the filtering unit. When the differential voltage value is greater than the difference between the first reference voltage VREFP and the second reference voltage VREFN, the output end of the first operational amplifier A1 and the output end of the second operational amplifier A2 jointly output a reset pulse V2, and at the same time, the output reset pulse V2 is recorded by the first counter 123. When the number of reset pulses V2 recorded by the counter 123 within the second time is greater than the first number, the reset detection module 12 determines that the communication signal Wake is a reset signal V1, and sends the reset signal V1 to the power reset module 13 to control the reset capacitor charging switch K1 to close.

[0093] Figure 6 FIG. 1 is a schematic diagram of a circuit structure of a hardware reset circuit provided by an embodiment of the present invention. Figure 4 .

[0094] Please refer to Figure 6As a preferred implementation, the power reset module 13 also includes a second diode D2, the anode of the second diode D2 is connected to the first end of the reset capacitor charging switch K1, and the cathode of the second diode D2 is connected to the first end of the pull-down power-off unit 132 and the first end of the pull-down power-off control unit 131.

[0095] The beneficial effect of providing the second diode D2 is that the second diode D2 utilizes the reverse breakdown characteristic of the diode so that the reset capacitor C1 can only be discharged through the first resistor R1.

[0096] Figure 7 FIG. 1 is a schematic diagram of a circuit structure of a hardware reset circuit provided by an embodiment of the present invention. Figure 5 .

[0097] Please refer to Figure 7 As a specific implementation, the power reset module 14 includes: a third resistor R3, a fourth NMOS tube Q4, a first linear regulator 141 and a first linear regulator 142; the first end of the third resistor R3 is connected to the power supply voltage VP, the second end of the third resistor R3 is respectively connected to the first end of the first linear regulator 141, the drain end of the first NMOS tube Q1 and the gate end of the fourth NMOS tube Q4, the source end of the fourth NMOS tube Q4 is respectively connected to the second end of the first linear regulator 141 and the first end of the first linear regulator 142, and the second end of the first linear regulator 142 outputs the module power supply voltage VQ.

[0098] The following Figure 7 Taking the circuit structure schematic diagram shown as an example, the working process of the hardware reset circuit provided by the embodiment of the present invention is described:

[0099] Please refer to Figure 7When the reset capacitor charging switch K1 is closed by the reset signal V1, the reset capacitor C1 starts to charge. When the voltage at the first end of the reset capacitor C1 is greater than the first control voltage, the first NMOS transistor Q1 and the second NMOS transistor Q2 start to conduct. The first NMOS transistor Q1 pulls the gate end of the fourth NMOS transistor Q4 down to the ground, and the second NMOS transistor Q2 pulls the second end of the first linear regulator 142 down to the ground. Therefore, the fourth NMOS transistor Q4 is turned off, that is, the power supply voltage VP no longer supplies power to the linear regulator module 14, and the module power supply voltage VQ output by the power reset module 14 is pulled down to the ground. , the reset capacitor C1 starts to discharge. Due to the reverse breakdown characteristic of the second diode D2, the reset capacitor C1 can only be discharged through the first resistor R1. When the reset capacitor C1 finishes discharging, the first NMOS tube Q1 and the second NMOS tube Q2 are turned off, and the power supply voltage VP is restored to supply power to the power reset module 14. The power reset module 14 starts to output the module power supply voltage VQ to the remaining functional modules of the non-reset function in the chip 1, and the chip 1 completes the reset.

[0100] In summary, the hardware reset circuit in the embodiment of the present invention is provided with three parts: an independent voltage-stabilizing source module, a reset detection module, and a power reset module, wherein the independent voltage-stabilizing source module supplies power to the reset detection module and the power reset module, and the reset detection module is used to detect whether the communication signal Wake connected to the serial communication pin of the chip is a reset signal. If the communication signal Wake is judged to be a reset signal, the reset signal is sent to the power reset module, so that the power supply voltage input to the power reset module and the power supply voltage output from the power reset module are pulled down to the ground, and the chip starts to reset. The hardware reset circuit determines the reset signal by detecting the communication signal Wake input from the serial communication pin of the chip, and then completes the chip reset by pulling down the power supply voltage VP and the module power supply voltage. This not only avoids the disadvantage of adding a reset port and the risk of false touch for manual hardware reset, but also simultaneously pulling down the power supply voltage and the module power supply voltage can make the chip reset more complete.

[0101] The technical solution of the present invention also provides a daisy chain communication system.

[0102] Figure 8 4 is a circuit block diagram of a daisy chain communication system provided by an embodiment of the present invention.

[0103] Please refer to Figure 8 As a specific implementation, a daisy chain communication system provided by an embodiment of the present invention includes: a plurality of chips 1 and micro control units 2 connected in series;

[0104] The serial input pin of the first chip 1 is connected to the serial output pin of the micro control unit 2, the serial output pin of each chip 1 is connected to the serial input pin of the next chip 1, and each chip 1 is integrated with the hardware reset circuit;

[0105] The serial output pin of the microcontroller unit 2 outputs a reset signal V1 to the serial input pin of the first chip 1. After receiving the reset signal V1, the hardware reset circuit on the chip 1 starts to pull down and power off the power reset module 14 in the chip 1 to reset it. After the power reset module 14 completes the reset, the reset signal V1 is transmitted from the serial output pin of the chip 1 to the serial input pin of the next-level chip 1. The next-level chip 1 starts to pull down and power off the power reset module 14 in the chip 1, and so on. The reset signal V1 starts from the first chip 1, and is transmitted to the next-level chip 1 after the hardware reset circuit in the chip 1 completes the reset, and the reset of the linear voltage regulator units corresponding to all the chips 1 connected in series is completed in sequence.

[0106] The beneficial effect of setting up a daisy chain communication system is that the daisy chain communication system can complete the reset of all chips in the system in an orderly manner through the level-by-level transmission of reset signals, which can improve the utilization rate of system resources and achieve resource conservation.

[0107] An embodiment of the present invention further provides an electronic circuit, which includes the hardware reset circuit and other parts of the electronic circuit.

[0108] An embodiment of the present invention further provides an electronic device, which includes the electronic circuit and other parts of the electronic device.

[0109] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A hardware reset circuit, characterized in that: Used to pull down and power off the linear voltage regulator module in the chip to reset it. The linear voltage regulator module is used to power the remaining functional modules in the chip without reset functions, including: An independent voltage-stabilizing source module, the independent voltage-stabilizing source module is used to supply power to the reset detection module and the power reset module; A reset detection module is used to detect a communication signal connected to a serial communication pin of a chip. If the communication signal is determined to be a reset signal, the reset detection module outputs the reset signal. A power reset module is used to pull down the power supply voltage input to the linear voltage regulator module and the module power supply voltage output by the linear voltage regulator module for a first time according to the input reset signal. The independent voltage stabilizing source module, the reset detection module and the power reset module are all integrated in the same chip.

2. The hardware reset circuit according to claim 1, characterized in that: The power reset module comprises: A reset capacitor charging switch, wherein the reset capacitor charging switch is configured to be turned on by being controlled by the reset signal; A pull-down power-off control unit, the pull-down power-off control unit being used to output a first control signal lasting for a first time according to the power supply of the independent voltage-stabilizing source module when the reset capacitor charging switch is turned on; A pull-down power-off unit is used to disconnect and pull down the power supply voltage input to the linear voltage regulator module and the module power supply voltage output by the linear voltage regulator module according to the first control signal.

3. The hardware reset circuit according to claim 2, characterized in that: The first end of the reset capacitor charging switch is connected to the first end of the pull-down power-off control unit, and the second end of the reset capacitor charging switch is connected to the first end of the independent voltage stabilizing source module.

4. The hardware reset circuit according to claim 2, characterized in that: The pull-down power-off unit includes a first NMOS tube and a second NMOS tube, the gate ends of the first NMOS tube and the second NMOS tube are the first end of the pull-down power-off unit, the source ends of the first NMOS tube and the second NMOS tube are the second end of the pull-down power-off unit, the drain end of the first NMOS tube is connected to the first end of the linear voltage regulator module, and the drain end of the second NMOS tube is connected to the second end of the linear voltage regulator module.

5. The hardware reset circuit according to claim 2, characterized in that: The pull-down power-off control unit includes a first resistor and a reset capacitor, wherein the first end of the reset capacitor is respectively connected to the first end of the first resistor, the first end of the reset capacitor charging switch and the first end of the pull-down power-off unit, and the second end of the reset capacitor is respectively connected to the second end of the first resistor, the second end of the pull-down power-off unit and the ground.

6. The hardware reset circuit according to claim 1, characterized in that: The independent voltage-stabilizing source module includes a second resistor, a first diode and a third NMOS tube, the first end of the second resistor is connected to the power supply voltage and connected to the drain end of the third NMOS tube, the second end of the second resistor is connected to the cathode of the first diode and the gate end of the third NMOS tube, the source end of the third NMOS tube is connected to the second end of the reset capacitor charging switch, and the source end of the third NMOS tube is the first end of the independent voltage-stabilizing source module.

7. The hardware reset circuit according to claim 1, characterized in that: The reset detection module includes a first filtering unit, a second filtering unit, a first operational amplifier, a second operational amplifier and a first counter; the first end of the first filtering unit is connected to the first voltage division of the differential voltage of the communication signal, the first end of the second filtering unit is connected to the second voltage division of the differential voltage of the communication signal, the second end of the first filtering unit is connected to the inverting input end of the first operational amplifier, the second end of the second filtering unit is connected to the non-inverting input end of the second operational amplifier, the non-inverting input end of the first operational amplifier is connected to the first reference voltage, the inverting input end of the second operational amplifier is connected to the second reference voltage, the output end of the first operational amplifier is connected to the output end of the second operational amplifier, and the output end of the first operational amplifier and the output end of the second operational amplifier jointly output a reset pulse; the first counter is used to record the number of the reset pulses.

8. The hardware reset circuit according to claim 8, characterized in that: The first filtering unit and the second filtering unit have the same structure, and the first operational amplifier and the second operational amplifier have the same parameters.

9. The hardware reset circuit according to claim 2, characterized in that: The power reset module also includes a second diode, the anode of the second diode is connected to the first end of the reset capacitor charging switch, and the cathode of the second diode is connected to the first end of the pull-down power-off unit and the first end of the pull-down power-off control unit.

10. A daisy chain communication system, characterized in that: It includes a plurality of chips and micro control units connected in series; The serial input pin of the first chip is connected to the serial output pin of the microcontroller unit, the serial output pin of each chip is connected to the serial input pin of the next chip, and each chip is integrated with the hardware reset circuit according to any one of claims 1 to 10; The serial output pin of the microcontroller unit outputs a reset signal to the serial input pin of the first chip. After receiving the reset signal, the hardware reset circuit on the chip starts to pull down and power off the linear voltage regulator module of claim 1 in the chip to reset. After the linear voltage regulator module completes the reset, the reset signal is transmitted from the serial output pin of the chip to the serial input pin of the next-level chip. The next-level chip starts to pull down and power off the linear voltage regulator module of claim 1 in the chip to reset, and so on. The reset signal starts from the first chip and is transmitted to the next-level chip after the hardware reset circuit in the chip completes the reset, thereby completing the reset of the linear voltage regulator units corresponding to all the chips connected in series in turn.

11. An electronic circuit, characterized in that: A hardware reset circuit comprising any one of claims 1 to 9.

12. An electronic device, characterized in that: Comprising the electronic circuit of claim 11.

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