Display system control method and display control system

Abstract

The invention provides a display system control method and a display control system, and the method is mainly applied to a control method that a display system enters an idle power-saving mode from a working mode when data is stopped from being transmitted to a screen. And when the display system starts to transmit data to the screen, returning from the idle mode to the working mode. The method mainly comprises the following steps: (a) establishing a software process for controlling access to an idle power-saving mode and an error processing mechanism; (b) establishing a proper idle switching mechanism according to different screen types and actual application scenes; (c) configuring an idle controller and other hardware control circuits related to display to realize the operation that the hardware automatically enters and exits from an idle mode; and (d) establishing an overflow protection mechanism of the memory write-in circuit.

Description

Technical Field

[0001] The present invention generally relates to a display system control method and a display control system, and mainly to a display system control method and a display control system for improving the switching speed between an idle mode and an operating mode. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

[0003] When a user does not issue any command to the electronic device for a short period of time, an electronic device with a screen may enter an idle mode. For example, if a user is using a laptop and then leaves his seat for a while, the laptop may enter an idle mode and its screen may remain unchanged until the laptop enters sleep mode or the user issues a command to the laptop again. Similarly, if a user is browsing a web page and temporarily stops scrolling the web page, a mobile phone may enter an idle mode and its screen may remain unchanged until the mobile phone enters sleep mode or the user uses the mobile phone again.

[0004] However, existing conventional idle control methods may bring "millisecond" or "second" level user experience (UX) delays to end users, and there is a possibility of causing screen flickering, especially when the electronic device frequently switches between idle mode and working mode.

[0005] Therefore, a new idle mode control mechanism is needed for the display system. Summary of the invention

[0006] A simplified summary of one or more aspects is presented below in order to provide a basic understanding of such aspects. The summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or important elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that is presented later.

[0007] An object of the present invention is to provide a display system control method that can select a suitable idle mode switching mechanism to minimize UX delay and maintain stable picture quality when frequently switching between idle mode and working mode.

[0008] The present invention provides a display system control method, which is applied to a display system including a screen, a host coupled to the screen, and an image generation module. The display system control method includes: (a) establishing a software process and an error handling mechanism for controlling entry and exit of an idle power saving mode; (b) establishing a suitable idle switching mechanism according to different screen types and actual application scenarios; (c) configuring an idle controller and other display-related hardware control circuits to realize the operation of automatically entering and exiting the idle mode of the hardware; and (d) establishing an overflow protection mechanism for a memory write circuit.

[0009] According to an embodiment of the present invention, step (a) of the display system control method includes: obtaining current scene information and screen information, determining the timing and method of entering and exiting the idle mode, triggering the hardware circuit of the display system to execute idle mode switching, and performing error checking on the idle mode switching result.

[0010] According to an embodiment of the present invention, step (b) of the display system control method includes: determining the timing and method of entering and exiting the idle mode according to different scenarios, and determining the idle switching method according to different screen types, wherein when the screen is a command type screen, all display-related hardware circuits of the host are powered off in the idle mode, and no time is required to be reserved to observe whether there is a new data update request, wherein the command type screen has an image buffer for storing idle images, and when the screen is a video type screen, the host generates an idle image using the memory write circuit or the image processing unit, and periodically updates the idle image to the screen in the idle mode, wherein the video type screen does not have an image buffer, and if the memory write circuit is used to output the idle image, a suitable idle switching mechanism is selected based on the number of layers, frame rate and application screen update cycle of the current scene.

[0011] According to an embodiment of the present invention, step (c) of the display system control method includes: providing registers through the idle controller to facilitate software triggering requests to enter and exit the idle mode, and automatically coordinating other display-related hardware modules to complete the operations of entering and exiting the idle mode; when the idle controller receives the idle switching request, it will automatically complete the power-off operation of the host-side display-related hardware circuit and the switching operation of the screen-side transmission mode for the command type screen, and automatically complete the operation of turning on the memory write circuit function to generate an idle image, switching the hardware circuit and reducing the frame rate for the video type screen; and notifying the software module of the hardware operation results through the idle controller to assist the software module in performing error checking and error handling, wherein the host is provided with a hardware circuit of a display control system, including an idle controller and multiple display-related hardware modules.

[0012] According to an embodiment of the present invention, the display-related hardware module in the display system control method includes: a bandwidth controller, coupled to the idle controller, for adjusting the data throughput capacity of the memory management system; a direct connection module group, which is only used in the direct connection hardware circuit, and when the hardware circuit is switched to the decoupling mode, the direct connection module can be powered off or stopped working, wherein the direct connection module serves the command type screen and the video type screen at the same time; a decoupling module group, which is turned on in the decoupling hardware circuit, and selectively turns on or off one or more decoupling modules after the hardware circuit is switched to the direct connection mode, and when the video type screen enters the idle mode , the decoupling hardware circuit is used for power saving; a power management module is coupled to the idle controller, and is used to control the power supply and register backup / recovery of the direct-connected module group, the decoupling module group and the related memory control bus and dependent modules; a screen control circuit is coupled to the idle controller, and is used to control the transmission mode and image refresh rate of the screen; a memory management system is used to control the memory buffer for caching images on the host side; and at least one memory control bus circuit is coupled to the direct-connected module group and the decoupling module group, and is used to support the read and write requests, bus arbitration, and priority management of the direct-connected module and the decoupling module to the memory.

[0013] According to an embodiment of the present invention, a display system control method includes: when the display system switches to the idle mode, the idle controller automatically switches the hardware circuit, notifies the power management module to perform register backup and power-off processing on the display-related hardware circuit that is no longer working on the host side, and notifies the bandwidth processor to reduce the display-related bandwidth request, and finally notifies the screen control circuit to change the transmission mode or refresh rate to reduce power consumption; when the display system exits the idle mode, the idle controller automatically notifies the bandwidth processor to restore the display-related bandwidth request, notifies the power management module to power on and restore the register setting of the hardware circuit that is powered off when idle, and automatically restores the hardware circuit configuration; and notifies the frequency control circuit to restore the transmission mode or refresh rate.

[0014] According to an embodiment of the present invention, the error handling mechanism in step (a) of the display system control method includes: checking whether the host's memory management system has sufficient resources to support the memory write circuit to output an idle image; if the memory management system has sufficient resources to support the memory write circuit, issuing an idle switching request to the hardware circuit of the idle controller; if the memory management system does not have sufficient resources to support the memory write circuit, requesting the image processing unit to draw an idle image; and after the display system uses the memory write circuit to output the idle image, using software to check whether the idle image generated by the memory write circuit is valid; if the check fails, ignoring the invalid idle image generated by the memory write circuit, and requesting the image processing unit to generate an idle image while turning off the output function of the memory write circuit.

[0015] According to an embodiment of the present invention, step (d) of the display system control method includes: in the process of the memory write circuit outputting the idle image to the memory buffer via the memory control bus, if the hardware circuit of the display system detects that the memory write circuit outputs slowly and blocks the data flow of transmitting the image to the screen, the overflow protection function of the memory write circuit is automatically turned on to ensure the normal display of the screen image; and a retry function is provided for the software through the idle controller to continue to try to use the memory write circuit to output the correct idle image when the number of errors specified by the software is not exceeded, until the number of failures of the memory write circuit output reaches the maximum number of errors allowed by the software, and the idle controller stops entering the idle mode and returns the operation result to the software.

[0016] Another object of the present invention is to provide a display system, comprising: a host, a screen coupled to the host, an image generation module, and display-related hardware circuits, for performing the following steps: (a) establishing a software process and error handling mechanism for controlling entry and exit of an idle power saving mode; (b) establishing a suitable idle switching mechanism according to different screen types and actual application scenarios; (c) configuring an idle controller and other display-related hardware control circuits to implement the operation of automatically entering and exiting the idle mode of the hardware; and (d) establishing an overflow protection mechanism for a memory write circuit.

[0017] To accomplish the foregoing and related ends, the one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and drawings set forth in detail certain illustrative features of the one or more aspects. However, these features are merely indicative of a few of the various ways in which the principles of the various aspects may be employed, and the description is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram showing that when the display system is in a working mode, at least one normal image is received from a host.

[0019] Figure 2 is a schematic diagram describing screens, and different types of screens receive at least one idle image from a host in an idle mode.

[0020] Figure 3 The software flow chart of the display system entering the idle mode according to the present invention is as follows.

[0021] Figure 4 It is a flowchart of switching to the idle mode using the memory write circuit (WDMA).

[0022] Figure 5 is a flow chart of switching to an idle mode using a graphics processing unit (GPU).

[0023] Figure 6 It is a hardware block diagram of a display control system described according to the present invention.

[0024] Figure 7 This is a block diagram of the hardware control flow for entering idle mode.

[0025] Figure 8 The software flow chart of the display system exiting the idle mode according to the present invention is as follows.

[0026] Fig. 9 This is a block diagram of the hardware control flow for exiting idle mode.

[0027] Fig.10 According to the invention described Figure 8 Schematic diagram of step 801 in FIG. DETAILED DESCRIPTION

[0028] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details that provide a thorough understanding of the various concepts. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid ambiguity.

[0029] In the following description, several are provided to explain the concepts of the present application. The terms "first", "second", and "third" in the following description are only used to distinguish different elements and do not indicate the order of the elements. For example, a first device and a second device only indicate that these devices may have the same structure but are different devices.

[0030] Figure 1 It is a schematic diagram of the screen being in working mode and receiving at least one normal image from a host (also called a master device). Figure 1As shown, the display system 100 includes a screen 101 and a host 103. In the working mode, it may mean that the user is using the display system 100, and the host 103 is a hardware circuit related to the host-side display, which is mainly used to receive a new image from an application (APP) or generate a new image in response to the instruction of the APP. The host 103 continuously provides normal images Img_1, Img_2... (new images) to the screen 101, and then the screen 101 displays normal images Img_1, Img_2... accordingly. In some scenarios, different normal images have different contents. However, in other scenarios, different normal images may have the same content, depending on the operation of the APP. The host 103 may be a device independent of the screen 101, for example, in a desktop computer, the host 103 and the screen 101 are independently configured and connected to each other. Alternatively, the host 103 may be integrated with the screen 101 in the same device, for example, in a mobile phone or tablet computer, the host 103 and the screen 101 are integrated into one. The details of the screen 101 and the host 103 will be described in detail in the following description.

[0031] If the display system 100 enters the idle mode, the screen 101 displays an idle image instead of Figure 1 However, for different types of screens, the host 103 or the screen 101 may have different operations. Figure 2 1 is a schematic diagram of different types of screens in idle mode and receiving at least one idle image from the host 103. Figure 2 In the above figure, screen 101 is a command type screen (hereinafter referred to as a CMD type screen). Figure 2 In the lower figure of , screen 101 is a video type screen (hereinafter referred to as VDO screen).

[0032] The CMD type screen is provided with a graphic buffer (GRAM) 201. Figure 2 In the above figure, the screen 101 receives the idle image Img_i and stores the idle image Img_i in the image buffer 201. The idle image Img_i may also be the last normal image received in the working mode. After entering the idle mode, the screen 101 displays the idle image Img_i. The host 103 may be turned off and does not transmit any image to the screen 101 until the display system 100 exits the idle mode.

[0033] In contrast, the VDO screen is not equipped with an image buffer 201. Figure 2 In the figure below, after entering the idle mode, the host 103 saves Img_i in the memory buffer 203 on the host side, and periodically transmits the idle image Img_i to the screen 101 at a frame rate lower than that in the working mode.

[0034] Figure 3 1 is a software flow chart of the display system control method described in the present invention. The steps shown in the figure can be completed by hardware circuits, and the hardware circuits can be set at any position according to different requirements. For example, in some cases, the hardware circuit is set in the host 103, but the present invention is not limited to this. In some cases, only steps 305 and 309 are completed by hardware circuits, while steps 301, 303, 307, 311, 313 and 315 are controlled by software. In addition, the steps 305 and 309 can be removed according to different requirements. Figure 3 Steps in .

[0035] Figure 3 The steps include:

[0036] Step 301: Control the display system 100 to start entering the idle mode. The way in which the display system switches from the working mode to the idle mode is determined according to the scene and screen information.

[0037] Please note that in step 301, the display system 100 has not entered the idle mode. Different examples of step 301 will be described later.

[0038] Step 303: Determine the idle switching mode according to the screen information.

[0039] If the screen 101 is a CMD type screen, go to step 305 .

[0040] If the screen 101 is a VDO screen, go to step 307 .

[0041] Step 305: Execute the idle switching mechanism of the CMD type screen. Figure 2 is shown in the upper figure of .

[0042] In this patent, step 305 is performed by the display control system. The display control system includes a hardware circuit of an idle controller and multiple display-related hardware circuits. After the hardware circuit of the idle controller receives the idle switching request, step 305 is automatically completed. The details of the display control system will be described later.

[0043] If the screen 101 is a VDO screen, an idle image can be selectively generated by a WDMA idle switching mechanism or a GPU idle switching mechanism. The WDMA idle switching mechanism is described in step 309, and the GPU idle switching mechanism is described in step 313. GPU and WDMA are more commonly used in mobile phones. However, some hosts 103 have neither WDMA nor GPU. In this case, the idle image can be generated by a CPU or a microprocessor.

[0044] Step 307: The host 103 may have a memory management system, which may include memory devices (e.g., DRAM) and a bus architecture. In this case, in step 307, it is checked whether the memory management system in the host has enough idle resources to support the display system to output idle images using WDMA. For example, it is checked whether the current bandwidth resources of the memory management system can be used to support the hard real-time requirements of WDMA output. If the answer is yes, the voltage of the memory device or the clock frequency of the memory control bus can be adjusted before WDMA output (see Figure 7 Otherwise, the software should abandon the hard real-time solution of WDMA output and select the soft real-time solution of GPU redrawing. That is, if the answer to step 307 is yes, step 309 is executed to implement the WDMA idle switching mechanism. On the contrary, if the answer to step 307 is no, step 313 is executed to implement the GPU idle switching mechanism.

[0045] Step 309: Execute the WDMA idle switching mechanism. That is, use WDMA to output the idle image to the memory device at the host 103 end via the memory control bus system. This patent will be in Figure 4 The details of the WDMA idle switching mechanism are described in . Among them, step 309 is completed by a display control system including an idle controller and multiple display-related hardware circuits. That is, when the idle controller receives the idle switching request, it automatically completes the relevant operations of entering the idle mode using WDMA in step 309.

[0046] Step 311: Before the host 103 periodically transmits the idle image to the VDO type screen 101, step 311 needs to first check the validity of the idle image, that is, check whether WDMA successfully outputs the idle image. If WDMA fails to output the idle image, the idle image generated by WDMA is abandoned and the idle image is redrawn using the GPU idle switching mechanism. If WDMA successfully outputs the idle image, the idle image is applied to the screen display in the idle mode. There are many ways to check whether WDMA successfully outputs the idle image. For example, the idle controller can notify the software of the result of WDMA outputting the idle image through an interrupt.

[0047] In order to reduce power consumption, no matter whether the idle image is successfully generated in step 311 , the WDMA output function should be turned off after step 309 .

[0048] Step 313: Execute the GPU idle switching mechanism. In other words, if the memory management system does not have enough resources to support WDMA or the idle image generated by WDMA is invalid, submit a GPU redraw request to generate an idle image. The details of the GPU idle switching mechanism will be described in Figure 5 Described in.

[0049] Step 315: End. At this point, the display system has entered the idle mode.

[0050] In addition, it can be removed according to different needs Figure 3 For example, step 309 or step 313 may be selected for execution through a different mechanism (rather than step 307 or step 311).

[0051] Figure 4 It is a hardware flow chart of the VDO screen switching to idle mode using WDMA.

[0052] The display-related hardware modules located in the host 103 include: a mobile display processor (MDP) 401, an image overlay circuit (IOV) 403, a memory read circuit (Read Direct Memory Access, RDMA) 405, an image quality improvement circuit (QIC) 407, a compressor (CPR) 409 and a transmission interface (TI) 411. Please note that Figure 4 and Figure 5 The electronic devices shown may be named in other different ways; other hardware modules, such as an image resizer, may be added according to different design requirements; at least one hardware module, such as the memory reading circuit 405, the image quality improvement circuit 407, and the compressor 409, may be selectively removed; a plurality of different electronic devices may be integrated into a few other hardware modules, or renamed as other hardware modules, for example, the image overlay circuit 403 and the transmission interface 411 may be replaced by other modules with similar functions.

[0053] In working mode, the image finally output to the screen is composed of layers generated by different drawing methods. Figure 4 In the example of , layer L2 is generated by MDP 401, and layers L1 and L3 are generated by the GPU or CPU in host 103. Figure 4 During the displayed WDMA idle switching process, both the normal image and the idle image are generated by the same hardware circuit, namely "MDP->IOV->RDMA->QIC->CPR". Therefore, the quality of the normal image and the idle image is the same or the difference is very small, which ensures that there will be no screen flickering when switching from working mode to idle mode.

[0054] In detail, the image superposition circuit 403 superimposes all layers L1, L2, and L3 to generate the image data stream to be displayed. The memory reading circuit 405 is used to read the superimposed data stream. The image quality improvement circuit 407 is used to improve the quality of the image to be displayed. The compressor 409 is used to compress the data stream to reduce the volume. The transmission interface 411 finally transmits the compressed data stream to the screen 101 to achieve image update. Among them, the transmission interface 411 is the transmission interface used in steps 305, 311, and 313.

[0055] Figure 4 When the N-1 frame is in the working mode, after receiving the idle switching request, the system 100 in the working mode triggers the output function of the memory writing circuit (WDMA) for the next frame at the end of the N-1 frame. At the Nth frame, the WDMA 413 outputs the idle image Img_i to the memory device on the host side. At this time, the screen 101 still displays the Nth frame, but the host 103 has completed the first stage of entering the idle mode.

[0056] Next, during the N+1th frame, the host 103 reads the idle image Img_i from the memory device and sends it to the screen 101. When the screen 101 displays the idle image Img_i, the image overlay circuit 403, the image quality improvement circuit 407, the compressor 409, etc. can stop working, while the memory reading circuit 405 and the transmission interface 411 still remain in working state. That is, the hardware circuit switches from the direct link mode to the decoupled mode. During the N-1th frame and the Nth frame, the host 103 uses the hardware circuit in the direct link mode. During the N+1th frame, the host 103 uses the hardware circuit in the decoupled mode.

[0057] Figure 5 It is a flowchart of the VDO screen using the GPU to enter the idle mode. At the N-1 frame, after the system 100 in the working mode receives the idle switching request, it applies to the GPU 501 through the software to draw the idle image Img_i. At the Nth frame, the GPU saves the drawn idle image in the memory device on the host side. Next, at the N+1 frame, the host 103 reads and displays Img_i from the memory device. At this time, the Img_i generated by the GPU is already the result of the superposition of layers L1, L2, and L3. After switching to the idle mode using the GPU, the hardware circuit of the host 103 has been working in the direct connection mode, which will be worse than the low power consumption effect of switching to the idle state using WDMA. At the same time, when the image drawer changes from MDP and IOV to GPU, the image flicker problem visible to the human eye may occur, especially when the display system frequently enters and exits the idle mode.

[0058] The above-mentioned image generation module includes but is not limited to at least one of the following: CPU, MDP, WDMA and GPU, and may also include other components, such as other microprocessors or any other hardware circuits.

[0059] Returning to step 301, an idle switching request is generated according to the actual situation to control the display system to start entering the idle mode. The common condition for entering the idle mode is that the APP does not generate a new image within a period of time, or the host 103 does not receive a screen update instruction, and the software can decide to switch to the idle mode. For example, the user is browsing the web, but stops scrolling the web. In this case, if the screen is of CMD type, the display system 100 can enter the idle mode immediately after the last screen update is completed, without observing whether there is a screen update request within a period of time. This is because when the present invention exits the idle state, the display-related modules of the host 103 are automatically powered on and restored to the settings through hardware circuits such as the idle controller and the power management module, which can greatly reduce the time required for the CMD type screen to switch between the idle mode and the working mode, especially when the frame rate is low, the delay in entering / exiting the idle state is transparent and imperceptible to the user experience.

[0060] If the VDO screen uses WDMA to switch to idle mode, the display system can decide the appropriate time to enter idle mode based on the number of layers, frame rate and APP screen update cycle of the current scene. For example, the scene of browsing news has multiple layers at a high frame rate, which has occupied a lot of bandwidth resources, resulting in limited idle bandwidth resources of the memory management system. In this case, it is more suitable to switch to idle mode only (refer to Figure 4 The WDMA output function is turned on in the Nth frame of Figure 4 The WDMA output function is stopped immediately after the Nth frame of Img_i is generated. On the contrary, the full-screen video playback scene has only one layer at a low refresh rate, which occupies very little bandwidth resources and has sufficient available idle bandwidth resources. And if the picture update cycle is short, it is recommended to always keep the WDMA output function to increase the idle mode switching speed of the VDO screen. In other words, the software can determine the best idle switching method in real time according to the actual situation of the current scene.

[0061] In general, when high frame rates and multiple layers have consumed most of the bandwidth resources, the memory management system must increase bandwidth capabilities to support the WDMA output of idle images. For example, increasing the clock frequency and voltage level of the memory control bus and memory devices, etc., constitutes the power consumption cost of entering idle mode. In order to avoid unnecessary power consumption, the software needs to observe for a period of time before starting the idle switching mechanism to confirm that there is no new image update requirement. Otherwise, frequent entry and exit of idle mode will not only fail to achieve the goal of low power consumption, but will waste more power.

[0062] On the contrary, in the case of low frame rate and a small number of layers, the host 103 has sufficient idle bandwidth resources to support the function of WDMA outputting idle images without adjusting the hardware settings of the memory management system. That is, the power consumption cost required for the VDO screen to enter the idle mode is considered to be controllable. Therefore, the display system 100 can enter the idle mode immediately when receiving the idle request, without observing whether there is a new drawing demand within a predetermined time period.

[0063] The APP screen update cycle is also one of the factors for determining the idle switching method in step 301. For example, in the scenario of browsing news or text chatting, the APP screen update cycle is long and the idle time is unpredictable. In order to reduce the power consumption of the display system, it is recommended to turn off the WDMA output function immediately after entering the idle mode. At the same time, in order to avoid the power consumption waste caused by frequent state switching due to too short an idle state, it is recommended to reserve a period of time to observe and confirm that there is no screen update request before using WDMA to enter the idle mode.

[0064] On the contrary, in the full-screen video playback scenario, the APP screen update has a stable periodic law and a short cycle. If we still reserve a period of time to observe the screen update request, it will be difficult for the display system 100 to enter the idle mode. At this time, it is recommended that the display system 100 enter the idle mode immediately after the previous frame of the screen is updated, and obtain low power consumption benefits by maximizing the length of the idle state. In other scenarios, such as camera preview, although the screen update cycle is shorter, the larger number of layers leads to a higher idle switching cost. It is recommended that the display system remain in working mode and ignore idle state switching. As mentioned above, different scenarios may have different timings or different idle switching methods, so it is necessary for us to establish a real-time determination mechanism for idle switching methods.

[0065] As described above, the present invention provides a display control system, including an idle controller, a power management module, a bandwidth controller, a screen control circuit and multiple other display-related hardware modules. When the hardware circuit of the idle controller receives an idle entry request sent by the software, the hardware automatically completes step 305 or 309. Figure 66 is a hardware circuit block diagram of a display control system 600 according to the present invention, wherein display-related hardware modules such as an idle controller 601 and a power management module 609 are located in the host 103 and can be implemented by various hardware such as circuits or logic gates. These components and their locations can be adjusted and changed according to different requirements. At the same time, the idle controller 601, the power management module 609 and other display-related hardware modules in the present invention can also support an exit idle request.

[0066] Figure 6 In the embodiment, the display-related hardware modules include: a bandwidth controller 603, a direct link (DL) module group 605, a decoupling (DC) module group 607, a power management module 609, a screen control circuit 602, at least one memory control bus interface (MB_1 and MB_2 are used as examples for relevant description), and some necessary dependent modules (DM_1 and DM_2 are used as examples for relevant description).

[0067] In the present invention, as the main control circuit of the display control system 600, the idle controller 601 is used to respond to the idle switching request triggered by the software in a timely manner, and coordinate other hardware modules in the management system to automatically complete the idle switching action.

[0068] The screen control circuit 602 coupled to the idle controller 601 is mainly used to control the power supply or transmission mode of the screen 101. However, since some screens 101 do not need or support the function of entering the low power consumption mode in the idle state, the screen control circuit 602 can be removed from the present invention.

[0069] The bandwidth controller 603 coupled to the idle controller 601 is used to send bandwidth requests or directly adjust hardware settings related to the bandwidth capabilities of the host-side memory management system. In some cases, the bandwidth controller 603 can be removed. For example, the bandwidth settings of the memory management system do not change between the working mode and the idle mode. Otherwise, the bandwidth controller 603 can back up the working bandwidth settings and update the idle bandwidth settings before entering the idle mode, and restore the working bandwidth settings when exiting the idle mode.

[0070] The direct connection module group 605 is a display-related hardware function module located in the host 103. When the system enters the idle mode, the direct connection module can be powered off and stop working in the hardware circuit of the decoupling mode. For example, the direct connection module group 605 includes Figure 4 The image superposition circuit 403, image quality improvement circuit 407 and compressor 409 are shown.

[0071] The decoupling module group 607 is a display-related hardware functional module located in the host 103. When the system enters the idle mode, the decoupling module must be in a working state in the hardware circuit of the decoupling mode. For example, Figure 4 The memory reading circuit 405 and the transmission interface 411 in.

[0072] The power management module 609 coupled to the idle controller 601 is used to perform power supply control and register setting backup and recovery for all display-related hardware function modules in the host 103. It includes a direct-connected module group 605, a decoupled module group 607, memory control bus interfaces MB_1 and MB_2 coupled to them, and display-related dependent modules DM_1 and DM_2. Among them, MB_1 and MB_2 are used to support data transmission between the memory management system and the direct-connected module group 605 or the decoupled module group 607. When entering the idle state, the power management module 609 will decide whether to back up and power off the register settings of the direct-connected module group, the decoupled module group, MB_1, MB_2, DM_1, and DM_2 according to the information transmitted by the idle controller; when exiting the idle state, it will decide whether to power on and restore the register settings of the direct-connected module group, the decoupled module group, MB_1, MB_2, DM_1, and DM_2 according to the information transmitted by the idle controller. In addition, the power management module 609 will also return the power supply control result to the idle controller 601.

[0073] Back to Figure 3 Step 311 in the figure. Before starting the WDMA output function, the idle controller 601 has adjusted the bandwidth capacity, but since there are many other memory users sharing the memory management system at the same time, the actual situation is more complicated, that is, the memory management system cannot guarantee the stability of bandwidth capacity and resources. Slow WDMA output behavior in an unstable bandwidth environment will block Figure 4 The data stream in the Nth frame from the compressor 409 to the transmission interface 411 is transmitted normally, and then the terminal user will see an abnormal picture on the screen 101. This is a catastrophic consequence that is difficult for the user to accept, even if the probability is very low.

[0074] The present invention provides a protection mechanism in the critical situation that WDMA output blocks screen transmission, that is, WDMA outputs an overflow idle image to the memory buffer, thereby ensuring that the image data stream transmitted to the screen 101 is normal. Furthermore, the software can set the maximum number of allowed WDMA output failures. That is, when the number of errors specified by the software is not exceeded, the idle controller can continue to try to use WDMA to output the correct idle image until the number of WDMA output failures reaches the maximum number of errors allowed by the software. The idle controller will terminate the action of entering the idle mode and return the operation result to the software in some way. This mechanism strengthens the security protection function of the solution of using WDMA to enter the idle mode, thereby reducing the side effects and risks brought by the WDMA output function to the greatest extent.

[0075] Figure 7 and Fig. 9 yes Figure 6 The detailed flow control block diagram of the display control system when entering / exiting idle is shown. Figure 7 In the case of a display system 100, the software requests that the display system 100 enter an idle mode. Fig. 9 In the example, the software requests the display system 100 to exit the idle mode.

[0076] Figure 7 The operation shown includes the following steps:

[0077] Step 1: After receiving the software-triggered request to enter the idle mode, the idle controller 601 triggers a series of hardware operations for switching to the idle mode. This step may correspond to Figure 3 For example, if the host 103 does not receive any request to update the image within a period of time, the software will generate an idle switching request.

[0078] Step 2: The idle controller 601 checks the hardware state machine. If the software triggers a request to exit the idle state, the current and subsequent steps are canceled. Otherwise, the idle controller 601 determines whether the display-related hardware circuit in the host 103 needs to be changed according to the type of the screen 101. In other words, the idle controller 601 determines and executes the switching of the hardware circuit according to the type of the screen 101, which is described in detail as follows:

[0079] If the VDO type screen generates an idle image using WDMA, the hardware circuit of the host 103 will switch from the direct connection mode to the decoupled mode. That is, in the idle mode, the decoupled mode is used to update the idle image to the screen at a lower frame rate, and the direct connection modules such as the image overlay module 403 and the image quality optimization module 407 are turned off to maximize the benefits of low power consumption. Figure 4 The host 103 uses the direct path in the N-1 frame and the N frame, and switches to the decoupled path in the N+1 frame. The hardware circuit of the idle controller automatically completes the path switching operation for the VDO screen in the N and N+1 frames.

[0080] If it is a CMD type screen, the screen 101 can use the last working image stored in the screen image buffer as an idle image, and does not need to generate any new idle images during the idle switching process, so that all display-related hardware circuits in the host 103 can be turned off and powered off. That is, both the direct connection module group 605 and the decoupling module group 607 will stop working, so the idle controller will ignore the hardware circuit switching operation in step 2 for the CMD type screen.

[0081] Step 3: The idle controller 601 checks the hardware state machine. If the software triggers a request to exit the idle state, the current and subsequent steps are canceled. Otherwise, the idle controller 601 determines whether the transmission mode or frame rate of the screen 101 should be changed according to the type of the screen 101. Specifically, if the screen 101 is of the CMD type, the idle controller 601 can switch the screen from the transmission mode to the power saving mode (such as the ULPS mode) through the screen interface control module 602; if the screen 101 is of the VDO type, the idle controller 601 can reduce the transmission frame rate of the screen through the screen interface control module 602.

[0082] Step 4: The idle controller 601 checks the hardware state machine. If the software triggers a request to exit the idle state, the current and subsequent steps are canceled. Otherwise, the idle controller 601 sends a bandwidth control request to the bandwidth controller 603. Correspondingly, when the bandwidth controller 603 receives the idle switching notification from the idle controller 601, it will back up the bandwidth settings in the working mode and clear the idle bandwidth of the CMD type screen to 0 after the host 103 stops working; or update the bandwidth setting of the VDO screen to a lower idle bandwidth setting.

[0083] Step 5: The idle controller 601 checks the hardware state machine. If the software triggers a request to exit the idle state, the current and subsequent steps are canceled. Otherwise, the idle controller 601 sends different power supply requests to the power management module 609 according to the screen type. For a CMD type screen, the idle controller 601 will request the power management module 609 to perform register backup and power off for both the direct-connected module group and the decoupled module group, the memory bus interfaces MB_1, MB_2, and the dependency modules DM_1, DM_2; for a VDO type screen, the idle controller 601 will request the power management module 609 to perform register backup and power off only for the direct-connected module group, the memory bus interface MB_1, and the dependency module DM_1.

[0084] When the screen 101 is in the image display state, no matter the display system is in the idle mode or the working mode, the hardware circuit of the idle controller 601 will keep the power supply state. In other words, the idle controller 601 will keep the working state unless the screen display function is turned off, so as to achieve a timely response to the idle switching request issued by the software.

[0085] Figure 8 Describes the software operation flow chart of the display system exiting idle mode, and the detailed description is as follows:

[0086] Step 801: Determine the timing and method of the display system 100 exiting the idle mode according to the actual situation. In other words, step 801 determines how to switch the display system from the idle mode to the working mode. Please note that the display system 100 is in the idle mode at this time, and different examples of step 801 will be described later.

[0087] Step 803 : Check the screen type of the screen 101 .

[0088] If the screen 101 is of the CMD type, step 805 is executed; if the screen 101 is of the VDO type, step 807 is executed.

[0089] Step 805: After the software sends an exit idle request to the idle controller 601, the idle controller 601 sends a power supply request to the power management module 609, so that the power management module 609 automatically powers on the direct-connected module group and the decoupling module group and restores register settings.

[0090] Step 807: The software confirms whether the idle image is generated by the GPU. If the answer is no (i.e., the idle image is generated by the WDMA), go to step 809; if the answer is yes (i.e., the idle image is generated by the GPU), go to step 811.

[0091] Step 809: After the software sends an exit idle request to the idle controller 601, the idle controller 601 will send a power request to the power management module 609, so that the power management module 609 automatically powers on the direct connection module group 605 and restores the register settings, and switches the display-related hardware circuits from the decoupling mode to the direct connection mode, and restores the frame rate of updating the screen in the working mode.

[0092] Step 811: When the software exits the idle mode entered by the GPU mode, it only needs to restore the frame rate of the picture update in the working mode.

[0093] Step 813: End. At this point, the display system has entered the working mode.

[0094] Fig. 9 Describes Figure 8 The hardware flow chart of steps 805 and 809 in FIG. Fig. 9 Also refer to Figure 8 , in order to clearly understand the content of the present invention. The detailed description is as follows:

[0095] Step 1': After receiving the exit idle request sent by the software, the idle controller 601 triggers a series of hardware operations to exit the idle mode. Figure 8 For example, when the host 103 receives a request to update the screen, or transmits other data to the screen 101, the software will immediately trigger a request to exit the idle state.

[0096] Step 2': The idle controller 601 will check the current hardware state machine. If the last idle action has not been executed Figure 7 If you have not completed step 5 in the previous step, skip this step.

[0097] Otherwise, the idle controller 601 will send a power supply request to the power management module 609 according to the screen type. For a VDO type screen, the power management module 609 will automatically restore the power supply and register settings of the direct connection module group 605, MB1 and DM1. For a CMD type screen, the power management module 609 will automatically restore the power supply and register settings of the direct connection module group 605, the decoupling module group 607, MB1, MB2, DM1 and DM2.

[0098] Step 3': The idle controller 601 will check the current hardware state machine. If the last idle action has not been executed Figure 7 If you have not completed step 4 in the previous step, skip this step.

[0099] Otherwise, the idle controller 601 will send a bandwidth request to the bandwidth controller 603 to restore the bandwidth settings in the working mode, including but not limited to the clock frequency and voltage of the display-related functional modules, the memory control bus and the memory device.

[0100] Step 4': The idle controller 601 will check the current hardware state machine. If the action of entering idle last time was not executed Figure 7 If you have not completed step 3 in the previous step, skip this step.

[0101] Otherwise, the idle controller 601 will determine the operation method of the screen interface control module 602 according to the screen type. For a CMD type screen, the idle controller 601 can switch from the low power mode to the working mode (such as exiting the ULPS mode) through the screen control circuit 602 as needed. For a VDO type screen, the image update frame rate in the working mode can be restored through the screen control circuit 602.

[0102] Step 5': Display related hardware circuit switching is an optional step that can be decided by the idle controller 601 according to the screen type. For CMD type screens, the idle controller 601 will skip this step. For VDO type screens, the idle controller 601 will check the current hardware state machine. If the last idle switching action has not been executed, Figure 7 If step 2 in FIG. 1 is not specified, this step is skipped. Otherwise, the idle controller 601 automatically switches the hardware circuit from the decoupling mode to the direct connection mode and turns off the WDMA output function.

[0103] Since the hardware circuit realizes the automatic power supply control and register setting of the display-related hardware modules, the memory control bus interface and the dependent modules, that is, when switching between the idle mode and the working mode, there is no need for the software to manually set the hardware configuration in the screen 101 or the host 103, thereby improving the Figure 7 and Fig. 9 The idle switching speed shown in the figure. Considering the multi-thread competition, it is usually recommended that the software add a mutex lock protection during the idle mode switching process. As we all know, the mutex lock is a synchronization technology. Figure 4 For example, before this patent, in order to avoid the possibility of multiple threads accessing the same hardware circuit at the same time, the software started holding the mutex lock when starting the WDMA output in the N-1 frame, and did not release the mutex lock until the WDMA output was turned off in the N+1 frame. If the request for screen update arrives before the N+1 frame, the software must wait for the operation of entering the idle mode to be completed and the mutex lock to be released before starting the related operations of exiting the idle mode. This means that there may be a 3-frame delay when exiting the idle mode through the existing software method, which brings instability to the user experience. In this patent, the actions of entering and exiting the idle mode are automatically completed by the hardware. That is, Figure 3 Entering idle operation in steps 305 and 309, and Figure 8 The exit idle operation in steps 805 and 809 is automatically completed by the idle controller 601 in coordination with other display-related hardware modules. In this process, the software only holds the mutex lock for a very short time (less than 1 frame), so that when competition occurs, it is ensured that the exit idle action will not be blocked by the entry idle action, and finally a stable and good user experience effect is achieved.

[0104] In general, before this innovation, the lock time for entering idle is more than 2 frames, including manual software operations such as turning on / off the WDMA output function, waiting for the WDMA output to be completed, and switching the hardware circuit. If an exit idle request occurs before the idle operation is completed, the longer lock time causes a UX delay problem in screen update. Based on this patented innovation, the software only needs to hold the lock protection for a very short time when triggering an idle switching request to the idle controller 601, and the user experience delay problem will no longer occur. The idle controller 601 automatically completes the operation of entering / exiting idle according to the hardware state machine, that is, the hardware circuit will automatically complete or cancel operations such as turning on / off WDMA output and switching the hardware circuit mode according to the hardware state machine, thereby ensuring that the operation of exiting idle will not be blocked by the operation of entering idle.

[0105] The display system control method of the present invention also provides a timing control method for exiting the idle mode (refer to Figure 8 801 in step 802). Fig.101 is a schematic diagram of step 801 described according to the present invention. NG is used to indicate the time when the APP starts to generate a new image. For example, when the user clicks on the screen 101, the APP is triggered to generate a new image, or when the host 103 receives new information from the web page, the APP is triggered to generate a new image. NI is used to indicate the time when the host 103 receives the request to update the image. NR is used to indicate the time when the screen 101 completes the screen update.

[0106] Usually, the exit idle operation is triggered from the time point NI. Since the exit idle operation requires some processing time, this may cause the user to feel a delay in screen update. Therefore, it is necessary for the software to adjust the timing of exiting idle according to different UX performance standards and low power requirements.

[0107] exist Fig.10 In Example 1, the software starts to exit the idle mode when the APP starts to generate a new image, that is, the display system 100 has already exited the idle mode long before the host 103 receives the screen update request, which may lead to a decrease in low power consumption benefits. In Example 2, the display system 100 triggers the operation of exiting the idle mode at a time T1 after the APP starts to generate a new image. When the screen update request (time point NI) arrives, the display system 100 has just completed the operation of exiting the idle mode and switched to the working mode. Then T1 can be called the golden time point for balancing UX performance and low power consumption benefits. In Example 3, the display system 100 triggers the exit of the idle mode at a time T2 after the APP starts to generate a new image, which is too late for the display system 100, resulting in the delayed satisfaction of the screen update request, and ultimately resulting in a delay in the display of the first frame of the screen after exiting the idle mode. In short, in the present invention, it is recommended that the software of the host 103 determine the appropriate time point to exit the idle mode based on the UX performance standard and low power consumption requirements of the display system.

[0108] In summary, the software can select the appropriate time and method for the idle mode switching mechanism according to the actual scenario. At the same time, the idle mode switching operation can be automatically completed by the hardware, thereby improving the delay problem of switching between the idle mode and the working mode. Among them, the WDMA output scheme has a higher priority than the GPU redrawing scheme, so that the idle image and the normal image are generated by the same hardware module or circuit as much as possible, thereby avoiding or minimizing the screen flickering problem caused by the difference in image quality.

[0109] It should be understood that the disclosed architecture design, operation sequence or module arrangement in the control flow chart is an exemplary description. Different products can rearrange, combine, add or delete some modules or operations based on their own design requirements and preferences. The order described in the attached method claims is only used to exemplify the description of each module and process element, and is not intended to be limited to the specific order or hierarchy presented.

[0110] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications of these aspects are obvious to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown in this article, but to meet the full scope consistent with the text claims, wherein, unless explicitly so provided, the reference to the element in the singular form does not mean "one and only one", but means "one or more". The word "exemplary" is used herein to mean "used as an example, instance or illustration". Any aspect described as "exemplary" herein is not necessarily interpreted as preferred or advantageous over other aspects. Unless otherwise specifically provided, the term "some" refers to one or more. Combinations such as "at least one of A, B or C", "one or more of A, B or C", "at least one of A, B and C", "one or more of A, B and C" and "A, B, C or any combination thereof" include any combination of A, B and / or C, and may include multiples of A, multiples of B or multiples of C. Specifically, combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more of A, B, or C. All structural and functional equivalents of the elements throughout the various aspects of the present description that are known or later learned by those of ordinary skill in the art are expressly incorporated herein by reference and are covered by the claims. In addition, regardless of whether such disclosure is explicitly stated in the claims, nothing disclosed herein is intended to be dedicated to the public. The words "module," "mechanism," "element," "device," and the like are not intended to be substitutes for the word "means." Thus, no claim element is to be interpreted as means plus function unless the phrase "means for" is used to expressly state a claim element.

[0111] Although the present invention has been described in conjunction with certain specific embodiments for guiding purposes, the present invention is not limited thereto. Therefore, various modifications, changes and combinations of the various features of the described embodiments may be practiced without departing from the scope of the present invention as set forth in the claims.

Claims

1. A display system control method, applied to a display system including a screen, a host and an image generation module, the display system control method comprising: (a) Establish software flow and error handling mechanism to control entry and exit of idle power saving mode; (b) Establish appropriate idle switching mechanisms according to different screen types and actual application scenarios; (c) configuring an idle controller and other display-related hardware control circuits to implement automatic hardware entry and exit from idle mode; and (d) Establish an overflow protection mechanism for the memory write circuit.

2. The display system control method according to claim 1, characterized in that: Step (a) comprises: Acquire current scene information and screen information, determine the timing and method of entering and exiting the idle mode, trigger the hardware circuit of the display system to execute idle mode switching, and perform error checking on the idle mode switching result.

3. The display system control method according to claim 1, characterized in that: Step (b) comprises: The timing and method of entering and exiting the idle mode are determined according to different scenarios, and the idle switching method is determined according to different screen types. When the screen is a command type screen, all display-related hardware circuits of the host are powered off in idle mode, and there is no need to reserve time to observe whether there are new data update requests. The command type screen has an image buffer for storing idle images. When the screen is a video type screen, the host generates an idle image using the memory write circuit or the image processing unit, and the idle image is periodically updated to the screen in the idle mode. The video type screen does not have an image buffer. If the memory write circuit is used to output the idle image, a suitable idle switching mechanism is selected according to the number of layers, frame rate and application screen update cycle of the current scene.

4. The display system control method according to claim 1, characterized in that: Step (c) comprises: Through the idle controller, registers are provided to facilitate software triggering requests to enter and exit the idle mode, and other display-related hardware modules are automatically coordinated to complete the operations of entering and exiting the idle mode. When the idle controller receives the idle switching request, it will automatically complete the power-off operation of the host-side display-related hardware circuit and the switching operation of the screen-side transmission mode for the command type screen, and automatically complete the operations of turning on the memory write circuit function to generate an idle image, switching the hardware circuit and reducing the frame rate for the video type screen; and the hardware operation results are notified to the software module through the idle controller to assist the software module in performing error checking and error handling. Among them, the host is provided with a hardware circuit of a display control system, including an idle controller and multiple display-related hardware modules.

5. The display system control method according to claim 4, characterized in that: The display-related hardware modules include: a bandwidth controller, coupled to the idle controller, for adjusting the data throughput capacity of the memory management system; The direct connection module group is only used in the direct connection hardware circuit. When the hardware circuit is switched to the decoupling mode, the direct connection module can be powered off or stopped working. The direct connection module serves both the command type screen and the video type screen. A decoupling module group is turned on in the decoupling hardware circuit, and one or more decoupling modules are selectively turned on or off after the hardware circuit switches to the direct connection mode. When the video type screen enters the idle mode, the decoupling hardware circuit is used to save power; A power management module, coupled to the idle controller, for performing power supply control and register backup / recovery for the direct-connect module group, the decoupled module group, and the related memory control bus and dependent modules; A screen control circuit, coupled to the idle controller, for controlling the transmission mode and image refresh rate of the screen; A memory management system that controls the memory buffers used to cache images on the host side; and At least one memory control bus circuit is coupled to the direct-connect module group and the decoupling module group, and is used to support the read and write requests, bus arbitration, and priority management of the direct-connect module and the decoupling module to the memory.

6. The display system control method according to claim 4, characterized in that: When the display system switches to the idle mode, the idle controller automatically switches the hardware circuit, notifies the power management module to perform register backup and power-off processing on the display-related hardware circuit that is no longer working on the host side, and notifies the bandwidth processor to reduce the display-related bandwidth request, and finally notifies the screen control circuit to change the transmission mode or refresh rate to reduce power consumption; when the display system exits the idle mode, the idle controller automatically notifies the bandwidth processor to restore the display-related bandwidth request, notifies the power management module to power on and restore the register setting of the hardware circuit that is powered off when idle, and automatically restores the hardware circuit configuration; and notifies the frequency control circuit to restore the transmission mode or refresh rate.

7. The display system control method according to claim 1, characterized in that: The error handling mechanism in step (a) includes: Check whether the host's memory management system has sufficient resources to support the memory write circuit to output the idle image; if the memory management system has sufficient resources to support the memory write circuit, issue an idle switch request to the hardware circuit of the idle controller; if the memory management system does not have sufficient resources to support the memory write circuit, request the image processing unit to draw the idle image; as well as After the display system outputs the idle image using the memory writing circuit, software is used to check whether the idle image generated by the memory writing circuit is valid; If the check fails, the invalid idle image generated by the memory write circuit is ignored, and the image processing unit is requested to generate an idle image while the output function of the memory write circuit is turned off.

8. The display system control method according to claim 1, characterized in that: Step (d) comprises: In the process of the memory writing circuit outputting the idle image to the memory buffer via the memory control bus, if the hardware circuit of the display system detects that the memory writing circuit outputs slowly and blocks the data flow of transmitting the image to the screen, the overflow protection function of the memory writing circuit is automatically turned on to ensure the normal display of the screen image; and The idle controller provides a retry function for the software so that when the number of errors specified by the software is not exceeded, the software continues to try to output the correct idle image using the memory write circuit until the number of failed outputs of the memory write circuit reaches the maximum number of errors allowed by the software. The idle controller stops entering the idle mode and returns the operation result to the software.

9. A display system comprising: Host; A screen coupled to the host; an idle image generation module; and A processing circuit is configured to perform the following steps: (a) Establish software flow and error handling mechanism to control entry and exit of idle power saving mode; (b) Establish appropriate idle switching mechanisms according to different screen types and actual application scenarios; (c) configuring an idle controller and other display-related hardware control circuits to implement automatic hardware entry and exit from idle mode; and (d) Establish an overflow protection mechanism for the memory write circuit.

10. The display system according to claim 9, characterized in that: Step (a) comprises: Acquire current scene information and screen information, determine the timing and method of entering and exiting the idle mode, trigger the hardware circuit of the display system to execute idle mode switching, and perform error checking on the idle mode switching result.

11. The display system according to claim 9, characterized in that: Step (b) comprises: The timing and method of entering and exiting the idle mode are determined according to different scenarios, and the idle switching method is determined according to different screen types. When the screen is a command type screen, all display-related hardware circuits of the host are powered off in idle mode, and there is no need to reserve time to observe whether there are new data update requests. The command type screen has an image buffer for storing idle images. When the screen is a video type screen, the host generates an idle image using the memory write circuit or the image processing unit, and the idle image is periodically updated to the screen in the idle mode. The video type screen does not have an image buffer. If the memory write circuit is used to output the idle image, a suitable idle switching mechanism is selected according to the number of layers, frame rate and application screen update cycle of the current scene.

12. The display system according to claim 9, characterized in that: Step (c) comprises: The idle controller provides registers to facilitate software triggering requests to enter and exit the idle mode, and automatically coordinates other display-related hardware modules to complete operations to enter and exit the idle mode. When the idle controller receives an idle switching request, it will automatically complete the power-off operation of the host-side display-related hardware circuit and the switching operation of the screen-side transmission mode for the command type screen, and automatically complete the operation of turning on the memory write circuit function to generate an idle image, switching the hardware circuit and reducing the frame rate for the video type screen; and notifying the software module of the hardware operation results through the idle controller to assist the software module in performing error checking and error handling.

13. The display system according to claim 12, characterized in that: The display-related hardware modules include: a bandwidth controller, coupled to the idle controller, for adjusting the data throughput capacity of the memory management system; The direct connection module group is only used in the direct connection hardware circuit. When the hardware circuit is switched to the decoupling mode, the direct connection module can be powered off or stopped working. The direct connection module serves both the command type screen and the video type screen. A decoupling module group is turned on in the decoupling hardware circuit, and one or more decoupling modules are selectively turned on or off after the hardware circuit switches to the direct connection mode. When the video type screen enters the idle mode, the decoupling hardware circuit is used to save power; A power management module, coupled to the idle controller, for performing power supply control and register backup / recovery for the direct-connect module group, the decoupled module group, and the related memory control bus and dependent modules; A screen control circuit, coupled to the idle controller, for controlling the transmission mode and image refresh rate of the screen; A memory management system that controls the memory buffers used to cache images on the host side; and At least one memory control bus circuit is coupled to the direct-connect module group and the decoupling module group, and is used to support the read and write requests, bus arbitration, and priority management of the direct-connect module and the decoupling module to the memory.

14. The display system according to claim 12, characterized in that: When the display system switches to the idle mode, the idle controller automatically switches the hardware circuit, notifies the power management module to perform register backup and power-off processing on the display-related hardware circuit that is no longer working on the host side, and notifies the bandwidth processor to reduce the display-related bandwidth request, and finally notifies the screen control circuit to change the transmission mode or refresh rate to reduce power consumption; when the display system exits the idle mode, the idle controller automatically notifies the bandwidth processor to restore the display-related bandwidth request, notifies the power management module to power on and restore the register setting of the hardware circuit that is powered off when idle, and automatically restores the hardware circuit configuration; and notifies the frequency control circuit to restore the transmission mode or refresh rate.

15. The display system according to claim 9, characterized in that: The error handling mechanism in step (a) includes: Check whether the host's memory management system has sufficient resources to support the memory write circuit to output the idle image; if the memory management system has sufficient resources to support the memory write circuit, issue an idle switch request to the hardware circuit of the idle controller; if the memory management system does not have sufficient resources to support the memory write circuit, request the image processing unit to draw the idle image; as well as After the display system outputs the idle image using the memory writing circuit, software is used to check whether the idle image generated by the memory writing circuit is valid; If the check fails, the invalid idle image generated by the memory write circuit is ignored, and the image processing unit is requested to generate an idle image while the output function of the memory write circuit is turned off.

16. The display system according to claim 9, characterized in that: Step (d) comprises: In the process of the memory writing circuit outputting the idle image to the memory buffer via the memory control bus, if the hardware circuit of the display system detects that the memory writing circuit outputs slowly and blocks the data flow of transmitting the image to the screen, the overflow protection function of the memory writing circuit is automatically turned on to ensure the normal display of the screen image; and The idle controller provides a retry function for the software so that when the number of errors specified by the software is not exceeded, the software continues to try to output the correct idle image using the memory write circuit until the number of failed outputs of the memory write circuit reaches the maximum number of errors allowed by the software. The idle controller stops entering the idle mode and returns the operation result to the software.

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