A reliability data management method and system for chip three-dimensional packaging process technology

Abstract

The present invention discloses a reliability data management method and system for a chip three-dimensional packaging process technology, and relates to the field of big data analysis technology. The method is to firstly model and obtain a corresponding yield prediction model for each type of bare chip with different chip models in all bare chip stacked three-dimensional packaging products based on multiple three-dimensional packaging process parameters of all corresponding bare chips and the yield of the corresponding packaging products, and then obtain a corresponding yield prediction model for each bare chip in the target product according to the corresponding chip model, and finally apply the yield prediction model corresponding to each bare chip, optimize multiple three-dimensional packaging process parameters of each bare chip based on an optimization algorithm, obtain a chip three-dimensional packaging process plan designed for the target product and output it, so that not only can the optimal chip three-dimensional packaging process plan for the new product be automatically managed and analyzed, but also the manpower and material costs can be greatly reduced, and the process design time can be shortened.

Description

Technical Field

[0001] The present invention belongs to the technical field of big data analysis, and specifically relates to a reliability data management method and system for a chip three-dimensional packaging process technology. Background Art

[0002] Chip 3D packaging technology, also known as stacked chip packaging technology, refers to the packaging technology of stacking two or more chips in the vertical direction in a package without changing the size of the package. There are three main types of chip 3D packaging: embedded 3D packaging, active substrate 3D packaging and stacked 3D packaging. The stacked 3D packaging is based on 2D packaging, and multiple bare chips, packaged chips, multi-chip modules and even silicon wafers are stacked and interconnected to form a 3D package.

[0003] At present, the most common type of stacked 3D packaging is bare chip stacked 3D packaging, that is, firstly, a qualified chip with growth bumps is turned upside down and welded on a film substrate (the material of this film substrate is ceramic or epoxy glass, with conductor wiring on it, internal interconnection solder joints, and external interconnection solder joints on both sides), and then multiple film substrates are stacked and interconnected; its typical structural principle is as follows Figure 1 The process of bare chip stacking 3D packaging is mainly divided into the following three steps:

[0004] (1) Growing bumps on the bare chip (if gold bumps are used, the bumps are formed by gold wire balling, and pressure is applied at 250-400°C to interconnect the chip and the substrate; if lead-tin bumps are used, lead-tin bumps with a weight ratio of Pb:Sn=95:5 are used, and such bumps have a higher melting point and will not melt in the next process) and performing flip-down soldering; the specific method is to first solder the chip and the substrate at a temperature lower than the melting point of the bumps (for example, 180-250°C) (i.e., soldering is performed by metal diffusion at this temperature), and then heating to 250-400°C so that the solder balls can be melted at this temperature, thereby completing the soldering of the chip and the substrate; the aforementioned diffusion soldering temperature and melting soldering temperature are obtained through yield tests: when it is lower than 150°C, the open circuit phenomenon increases, and when it is higher than 300°C, the short circuit phenomenon of adjacent solder joints increases;

[0005] (2) Filling the gap between the bare chip and the substrate with epoxy resin glue with a spacing of 0.05 mm, i.e., performing underfilling;

[0006] (3) Stacking the substrates with bumps together. The bumps on the substrates are solder bumps (whose composition is Pb-Sn or Sn-Ag, and the melting point is set at 200-240°C). This last step is to stack the substrates and then solder them at a temperature of 230-250°C.

[0007] Based on the above-mentioned process of bare chip stacking 3D packaging, it can be known that each bare chip stacking 3D packaging product will have corresponding reliability data (such as yield rate and chip 3D packaging process plan including but not limited to multiple 3D packaging process parameters of each bare chip), and the existing bare chip stacking 3D packaging process design method is mainly for production personnel to explore and obtain chip 3D packaging process plans suitable for new products through a large number of process experiments, which inevitably leads to high manpower and material costs, long design time and difficulty in obtaining optimal process parameters. Therefore, based on historical bare chip stacking 3D packaging products and including the reliability data of yield rate and chip 3D packaging process plan, how to manage and analyze to obtain new products and the optimal chip 3D packaging process plan, and save manpower and material costs and shorten process design time, is a topic that technical personnel in this field urgently need to study. Summary of the invention

[0008] The purpose of the present invention is to provide a reliability data management method, system, computer equipment, computer-readable storage medium and computer program product for a chip three-dimensional packaging process technology, so as to solve the problems of high manpower and material costs, long design time and difficulty in obtaining optimal process parameters in the existing bare chip stacking three-dimensional packaging process design method.

[0009] In order to achieve the above object, the present invention adopts the following technical solutions:

[0010] In a first aspect, a reliability data management method for a chip three-dimensional packaging process technology is provided, comprising:

[0011] Obtaining reliability data of all bare chip stacked 3D packaging products, wherein the bare chip stacked 3D packaging product includes at least two bare chips stacked from bottom to top, the reliability data includes a chip 3D packaging process scheme and a yield rate, and the chip 3D packaging process scheme includes a plurality of 3D packaging process parameters of each bare chip in the corresponding product;

[0012] For each type of bare chip with different chip models in all the bare chip stacked three-dimensional packaging products, the plurality of three-dimensional packaging process parameters of all the corresponding bare chips are used as first model input items, and the yield of the packaging products to which all the corresponding bare chips belong is used as a first model output item, and a first machine learning model based on a first artificial intelligence algorithm is calibrated and verified to obtain a corresponding yield prediction model;

[0013] Obtaining chip models of each bare chip in a target product to be packaged using a bare chip stacking stereo packaging process;

[0014] For each bare chip, a corresponding yield prediction model is matched according to the corresponding chip model;

[0015] A yield prediction model corresponding to each bare chip is applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on an optimization algorithm to obtain and output the chip three-dimensional packaging process solution designed for the target product.

[0016] Based on the above invention content, a new solution is provided for optimizing the design of chip three-dimensional packaging process solutions for new products based on the reliability data of historical bare chip stacked three-dimensional packaging products, that is, first, for each bare chip with different chip models in all bare chip stacked three-dimensional packaging products, based on the corresponding multiple three-dimensional packaging process parameters of all bare chips and the yield of the corresponding packaging products, a model is built to obtain a corresponding yield prediction model, and then for each bare chip in the target product, according to the corresponding chip model, a corresponding yield prediction model is matched to obtain a corresponding yield prediction model, and finally, the yield prediction model corresponding to each bare chip is applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on the optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the target product and output it, which can not only automatically manage and analyze to obtain the optimal chip three-dimensional packaging process solution for new products, but also greatly reduce manpower and material costs, shorten process design time, and facilitate practical application and promotion.

[0017] In one possible design, the multiple three-dimensional packaging process parameters include the size of the bumps grown on the chip, the diffusion welding temperature of the bumps grown on the chip and the substrate, the melting welding temperature of the bumps grown on the chip and the substrate, the spacing between the chip and the substrate, the size of the bumps grown on the substrate, the melting welding temperature of the bumps grown on the substrate and the substrate and / or the chip serial number from bottom to top.

[0018] In a possible design, for each bare chip, a corresponding yield prediction model is matched according to the corresponding chip model, including:

[0019] According to the chip model of a bare chip in the target product, searching among all the bare chip stacked three-dimensional packaging products whether there is a bare chip with the chip model;

[0020] If so, the yield prediction model of the bare chip is used as the yield prediction model of the bare chip;

[0021] If it does not exist, first obtain the integrated circuit layout of the certain bare chip and the integrated circuit layout of each type of bare chip respectively, and then calculate the similarity between the integrated circuit layout of the certain bare chip and the integrated circuit layout of each type of bare chip respectively, and finally use the yield prediction model of any bare chip corresponding to the maximum similarity in all the bare chip stacked three-dimensional packaging products as the yield prediction model of the certain bare chip.

[0022] In a possible design, the yield prediction model corresponding to each bare chip is applied, and the plurality of three-dimensional packaging process parameters of each bare chip are optimized based on an optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the target product, including:

[0023] The yield prediction model corresponding to each bare chip is applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on the particle swarm optimization algorithm or the gray wolf optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the target product.

[0024] In a possible design, the yield prediction model corresponding to each bare chip is applied, and the plurality of three-dimensional packaging process parameters of each bare chip are optimized based on a particle swarm optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the target product, including the following steps S501 to S512:

[0025] S501. Initialize the algorithm parameters of the particle swarm optimization algorithm including the population size N, the maximum number of iterations T', the self-learning factor C1 and the global learning factor C2, and randomly generate the initial position of each particle in the particle population, and then execute step S502, wherein the initial position of each particle is randomly generated based on the following formula:

[0026]

[0027] In the formula, i' represents a positive integer, j represents a positive integer less than or equal to J, J represents the total number of bare chips in the target product, d represents a positive integer less than or equal to D, D represents the number of dimensions of the parameter vector to be optimized, and the parameter vector to be optimized includes the multiple three-dimensional packaging process parameters to be optimized. represents the initial position of the i'th particle in the particle population on the jth bare chip in the target product and on the dth dimension in the parameter vector to be optimized, u c,j,d represents the upper limit of the parameter search space on the j-th bare chip and in the d-th dimension, l c,j,d represents the lower limit of the parameter search space on the j-th bare chip and in the d-th dimension, and rand(0,1) represents a pure decimal random generation function;

[0028] S502. For each particle, the corresponding initial position on each bare chip is used as the parameter search result and input into the yield prediction model corresponding to each bare chip one by one, and the yield prediction value and confidence level corresponding to each bare chip are outputted, and the yield comprehensive evaluation index prediction value of the target product is calculated according to the yield prediction value and confidence level corresponding to each bare chip as the corresponding fitness F, and then step S503 is executed;

[0029] S503. Determine whether the maximum value among the fitness of each particle is greater than or equal to a preset threshold value. If so, the initial positions corresponding to the maximum value and on each bare chip are used as the multiple three-dimensional packaging process parameters designed for each bare chip, thereby obtaining the chip three-dimensional packaging process solution designed for the target product. Otherwise, execute step S504;

[0030] S504. Take the initial position of a particle with the maximum fitness as the initial global optimal position G ini , the position of the i'th particle in the iteration process and corresponding to the maximum fitness is the local optimal position P reached by the i'th particle i’ , and the position of the particle population in the iteration process and corresponding to the maximum fitness is recorded as the global optimal position G reached by the particle population, and the moving speed of the i'th particle is recorded as V i’ , and finally initialize the local optimal position P i’ =G=G ini , and initialize the moving speed to V i’ is zero, and the particle movement inertia coefficient range is also set to [T min ,T max ], and initialize the period T of the periodic reduction of the inertia coefficient to a randomly selected value within the range of the particle movement inertia coefficient, and also initialize the particle movement inertia coefficient in the iteration process to a value greater than zero, and also initialize the current iteration number t' to 0, and then execute step S505;

[0031] S505. Update the particle movement inertia coefficient of each particle, and then execute step S506, wherein the update formula of the particle movement inertia coefficient is as follows:

[0032]

[0033] In the formula, represents the particle movement inertia coefficient of the i'th particle on the jth bare chip and in the dth dimension obtained after the t'+1th iteration, represents the particle movement inertia coefficient of the i'th particle on the j'th bare chip and in the dth dimension before the t'+1th iteration, t'%T represents the modulo operation result of the previous iteration number t' on the period T, and if If it is less than 0, a new value is randomly selected within the range of the particle's inertia coefficient as the new period t, and the calculation is recalculated. until Not less than 0;

[0034] S506. Update the moving speed of each particle, and then execute step S507, wherein the updating formula of the moving speed is as follows:

[0035]

[0036] In the formula, represents the moving speed of the i'th particle on the jth bare chip and in the dth dimension obtained after the t'+1th iteration, represents the moving speed of the i'th particle on the jth bare chip and in the dth dimension before the t'+1th iteration, γ1 represents the first random number uniformly distributed in (0,1), represents the local optimal position reached by the i'th particle on the j'th bare chip and in the dth dimension during the first t' iterations, represents the position of the i'th particle on the jth bare chip and in the dth dimension before the t'+1th iteration, γ2 represents a second random number uniformly distributed in (0,1), represents the global optimal position reached by the particle population on the j-th bare chip and in the d-th dimension during the first t' iterations;

[0037] S507. Update the position of each particle, and then execute step S508, wherein the update formula of the position is as follows:

[0038]

[0039] In the formula, represents the position of the i'th particle on the jth bare chip and in the dth dimension obtained after the t'+1th iteration;

[0040] S508. For each particle, the corresponding position on each bare chip is used as a parameter search new result, and is input into the yield prediction model corresponding to each bare chip one by one, and a new yield prediction value and a new confidence corresponding to each bare chip are output, and a new prediction value of the finished product comprehensive evaluation index of the target product is calculated according to the new yield prediction value and the new confidence corresponding to each bare chip as the corresponding fitness F, and then step S509 is executed;

[0041] S509. Determine whether the maximum value among the current fitness of each particle is greater than or equal to the preset threshold value. If so, the initial positions corresponding to the maximum value and on each bare chip are used as the multiple three-dimensional packaging process parameters designed for each bare chip, thereby obtaining the chip three-dimensional packaging process solution designed for the target product. Otherwise, execute step S510;

[0042] S510. Determine the local optimal position P i’ Is the corresponding fitness less than the current fitness of the i'th particle? If so, the local optimal position P i’ Update to the current position of the i'th particle, and then execute step S511, otherwise directly execute step S511;

[0043] S511. Determine whether the fitness corresponding to the global optimal position G is less than the maximum value among the current fitness of each particle. If so, update the global optimal position G to the current position of any particle with the maximum value, and then execute step S512. Otherwise, directly execute step S512;

[0044] S512. Increment the current number of iterations t' by 1, and determine whether the current number of iterations t' reaches the maximum number of iterations T'. If so, the initial positions corresponding to the global optimal fitness and on each bare chip are used one-to-one as the multiple three-dimensional packaging process parameters designed for each bare chip, and then the three-dimensional packaging process solution for the chip designed for the target product is obtained. Otherwise, return to step S505, wherein the global optimal fitness refers to the fitness corresponding to the global optimal position G.

[0045] In a possible design, the predicted value of the finished product comprehensive evaluation index of the target product is calculated based on the yield rate prediction value and confidence level corresponding to each bare chip, including:

[0046] According to the yield rate prediction value and confidence level corresponding to each bare chip, the finished product comprehensive evaluation index prediction value P of the target product is calculated according to the following formula:

[0047]

[0048] In the formula, p j represents the yield prediction value corresponding to the j-th bare chip, η j represents the confidence level corresponding to the j-th bare chip.

[0049] In one possible design, the method further includes:

[0050] For each product among all the bare chip stacked three-dimensional packaging products, the yield prediction model of each bare chip in the corresponding product is applied, and the multiple three-dimensional packaging process parameters of each bare chip in the corresponding product are optimized based on the optimization algorithm to obtain the newly designed chip three-dimensional packaging process solution for the corresponding product and output it as a chip three-dimensional packaging process optimization suggestion for the corresponding product.

[0051] In one possible design, the method further includes:

[0052] For any chip combination consisting of the various bare chips, a yield prediction model of each bare chip in the corresponding combination is applied, and the plurality of three-dimensional packaging process parameters of each bare chip in the corresponding combination are optimized based on an optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the corresponding combination;

[0053] If a chip combination is matched to the chip models of each bare chip in the target product to which the bare chip stacking 3D packaging process is to be adopted, the chip 3D packaging process scheme designed for the chip combination will be directly regarded as the chip 3D packaging process scheme designed for the target product and output.

[0054] In a possible design, when the three-dimensional chip packaging process solution further includes process costs of each bare chip in the corresponding product and corresponding to the multiple three-dimensional packaging process parameters, the method further includes:

[0055] For each of the bare chips, the plurality of three-dimensional packaging process parameters of all the corresponding bare chips are used as second model input items, and the process costs of all the corresponding bare chips and corresponding to the plurality of three-dimensional packaging process parameters are used as second model output items, and are introduced into a second machine learning model based on a second artificial intelligence algorithm for training to obtain a corresponding process cost prediction model;

[0056] For each bare chip, a corresponding process cost prediction model is matched according to the corresponding chip model;

[0057] Applying the yield prediction model corresponding to each bare chip, optimizing the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtaining the chip three-dimensional packaging process solution designed for the target product and outputting it, including:

[0058] The yield prediction model and process cost prediction model corresponding to each bare chip are applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on the optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the target product and output it.

[0059] In the second aspect, a reliability data management system for a chip three-dimensional packaging process technology is provided, including a data acquisition unit, a model building unit, a model acquisition unit, a model matching unit and a process optimization unit;

[0060] The data acquisition unit is used to acquire reliability data of all bare chip stacked three-dimensional packaging products, wherein the bare chip stacked three-dimensional packaging product includes at least two bare chips stacked from bottom to top, and the reliability data includes a chip three-dimensional packaging process scheme and a yield rate, and the chip three-dimensional packaging process scheme includes a plurality of three-dimensional packaging process parameters of each bare chip in the corresponding product;

[0061] The model building unit is communicatively connected to the data acquisition unit, and is used to perform calibration and verification modeling on a first machine learning model based on a first artificial intelligence algorithm for each type of bare chip with different chip models in all the bare chip stacked three-dimensional packaging products, using the multiple three-dimensional packaging process parameters of all the corresponding bare chips as first model input items, and using the yield of the packaging products to which all the corresponding bare chips belong as a first model output item, to obtain a corresponding yield prediction model;

[0062] The model acquisition unit is used to acquire the chip model of each bare chip in the target product to be packaged using the bare chip stacking three-dimensional packaging process;

[0063] The model matching unit is respectively connected to the model building unit and the model acquisition unit for matching and obtaining a corresponding yield prediction model for each bare chip according to the corresponding chip model;

[0064] The process optimization unit is communicatively connected to the model matching unit, and is used to apply the yield prediction model corresponding to each bare chip, optimize the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtain the chip three-dimensional packaging process solution designed for the target product and output it.

[0065] In a possible design, the process optimization unit is also communicatively connected to the model building unit, and is also used to apply the yield prediction model of each bare chip in the corresponding product to each product among all the bare chip stacked three-dimensional packaging products, optimize the multiple three-dimensional packaging process parameters of each bare chip in the corresponding product based on the optimization algorithm, obtain the chip three-dimensional packaging process plan newly designed for the corresponding product and output it as a chip three-dimensional packaging process optimization suggestion for the corresponding product.

[0066] In a possible design, the process optimization unit is further communicatively connected to the model building unit, and is further used to apply the yield prediction model of each bare chip in the corresponding combination to any chip combination composed of the various bare chips, and optimize the multiple three-dimensional packaging process parameters of each bare chip in the corresponding combination based on the optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the corresponding combination;

[0067] The model acquisition unit is also communicatively connected to the process optimization unit, and is also used to directly output the chip 3D packaging process plan designed for the certain chip combination as the chip 3D packaging process plan designed for the target product if the chip models of each bare chip in the target product to be equipped with the bare chip stacking 3D packaging process are matched to a certain chip combination.

[0068] In a possible design, when the chip three-dimensional packaging process solution further includes the process costs of the various bare chips in the corresponding product and corresponding to the multiple three-dimensional packaging process parameters, the model building unit is further used for taking the multiple three-dimensional packaging process parameters of all the corresponding bare chips as second model input items, and taking the process costs of all the corresponding bare chips and corresponding to the multiple three-dimensional packaging process parameters as second model output items, and importing them into a second machine learning model based on a second artificial intelligence algorithm for training, so as to obtain a corresponding process cost prediction model;

[0069] The model matching unit is also used to match each bare chip to obtain a corresponding process cost prediction model according to the corresponding chip model;

[0070] The process optimization unit is also used to apply the yield prediction model and process cost prediction model corresponding to each bare chip, optimize the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtain the chip three-dimensional packaging process plan designed for the target product and output it.

[0071] In a third aspect, the present invention provides a computer device comprising a memory, a processor and a transceiver which are communicatively connected in sequence, wherein the memory is used to store a computer program, the transceiver is used to send and receive messages, and the processor is used to read the computer program to execute the reliability data management method as described in the first aspect or any possible design of the first aspect.

[0072] In a fourth aspect, the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed on a computer, executes the reliability data management method as described in the first aspect or any possible design of the first aspect.

[0073] In a fifth aspect, the present invention provides a computer program product, comprising a computer program or instructions, which, when executed by a computer, implement the reliability data management method as described in the first aspect or any possible design of the first aspect.

[0074] Beneficial effects of the above scheme:

[0075] (1) The present invention provides a new solution for optimizing the design of a chip 3D packaging process solution for a new product based on the reliability data of historical bare chip stacked 3D packaging products, that is, first, for each bare chip with different chip models in all bare chip stacked 3D packaging products, based on multiple 3D packaging process parameters of all corresponding bare chips and the yield of the corresponding packaging products, a corresponding yield prediction model is modeled, then for each bare chip in the target product, according to the corresponding chip model, a corresponding yield prediction model is matched, and finally, the yield prediction model corresponding to each bare chip is applied, and multiple 3D packaging process parameters of each bare chip are optimized based on an optimization algorithm, so as to obtain and output the chip 3D packaging process solution designed for the target product. In this way, not only can the optimal chip 3D packaging process solution for the new product be automatically managed and analyzed, but also the manpower and material costs can be greatly reduced, the process design time can be shortened, and practical application and promotion are facilitated;

[0076] (2) Based on the yield rate of historical bare chip stacking 3D packaging products and the chip 3D packaging process plan, automatic management and analysis can be performed to obtain chip 3D packaging process optimization suggestions for old products, which is conducive to improving the yield rate of old products;

[0077] (3) By optimizing in advance, the chip 3D packaging process solutions designed for various chip combinations can be obtained, which can facilitate the direct matching of the packaging process design results of the new product after the internal bare chip model of the new product is determined, thereby improving the user experience;

[0078] (4) The packaging process can also be optimized from the dimensions of finished product and process cost to further improve the excellence of the packaging process design results. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0080] Figure 1 This is a typical structural schematic diagram of bare chip stacking three-dimensional packaging.

[0081] Figure 2 A flow chart of a reliability data management method for a chip three-dimensional packaging process technology provided in an embodiment of the present application.

[0082] Figure 3 A schematic diagram of the structure of a reliability data management system for the three-dimensional chip packaging process technology provided in an embodiment of the present application.

[0083] Figure 4 A schematic diagram of the structure of a computer device provided in an embodiment of the present application.

[0084] In the above drawings: 101 - bare chip; 102 - substrate; 103 - bumps grown on the chip; 104 - bumps grown on the substrate; 105 - epoxy resin layer. DETAILED DESCRIPTION

[0085] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structures of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these embodiments without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0086] It should be understood that although the terms first and second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another object. For example, a first object can be referred to as a second object, and similarly, a second object can be referred to as a first object without departing from the scope of the exemplary embodiments of the present invention.

[0087] It should be understood that the term "and / or" that may appear in this document is merely a description of the association relationship between associated objects, indicating that there may be three relationships. For example, A and / or B can indicate three situations: A exists alone, B exists alone, or A and B exist at the same time. For another example, A, B and / or C can indicate the existence of any one of A, B and C or any combination of them. The term " / and" that may appear in this document describes another type of association object relationship, indicating that there may be two relationships. For example, A / and B can indicate two situations: A exists alone or A and B exist at the same time. In addition, the character " / " that may appear in this document generally indicates that the previous and next associated objects are in an "or" relationship.

[0088] Example

[0089] like Figure 2 As shown, the reliability data management method of the chip three-dimensional packaging process technology provided in the first aspect of this embodiment can be, but is not limited to, executed by a computer device with certain computing resources, such as a cloud server, a personal computer (PC, which refers to a multi-purpose computer with a size, price and performance suitable for personal use; desktops, laptops, small laptops, tablets and ultrabooks are all personal computers), smart phones, personal digital assistants (PDA) or wearable devices. Figure 2 As shown, the reliability data management method may include but is not limited to the following steps S1 to S5.

[0090] S1. Obtain reliability data of all bare chip stacked three-dimensional packaging products, wherein the bare chip stacked three-dimensional packaging products include but are not limited to at least two bare chips stacked from bottom to top, etc., and the reliability data include but are not limited to chip three-dimensional packaging process solutions and yield rates, etc., and the chip three-dimensional packaging process solutions include but are not limited to multiple three-dimensional packaging process parameters of each bare chip in the corresponding product, etc.

[0091] In step S1, the bare chip stacked three-dimensional packaging product is a product obtained by using a bare chip stacked three-dimensional packaging process, so the reliability data of the corresponding product can be collected in the packaging production process through conventional production management technology. Specifically, the multiple three-dimensional packaging process parameters include but are not limited to the size of the growth bumps on the chip, the diffusion welding temperature of the growth bumps on the chip and the substrate, the melting welding temperature of the growth bumps on the chip and the substrate, the spacing between the chip and the substrate, the size of the growth bumps on the substrate, the melting welding temperature of the growth bumps on the substrate and the substrate, and / or the bottom-up sequence number of the chip.

[0092] S2. For each bare chip with different chip models in all the bare chip stacked three-dimensional packaging products, the multiple three-dimensional packaging process parameters of all the corresponding bare chips are used as the first model input items, and the yield of the corresponding packaging products of all the corresponding bare chips is used as the first model output item, and the first machine learning model based on the first artificial intelligence algorithm is calibrated and verified to obtain a corresponding yield prediction model.

[0093] In the step S2, for example, if there are type A bare chips, type B bare chips, type C bare chips, type D bare chips, type E bare chips and type F bare chips among all the bare chip stacked three-dimensional packaging products, it is necessary to use the multiple three-dimensional packaging process parameters of all type A bare chips as the first model input items, and the yield rates of the packaging products to which all type A bare chips belong as the first model output items, import the first machine learning model based on the first artificial intelligence algorithm for training, and obtain the yield prediction model of type A bare chips; it is necessary to use the multiple three-dimensional packaging process parameters of all type B bare chips as the first model input items, and the yield rates of the packaging products to which all type B bare chips belong as the first model output items, import the first machine learning model based on the first artificial intelligence algorithm for training, and obtain the yield prediction model of type B bare chips; it is necessary to use the multiple three-dimensional packaging process parameters of all type C bare chips as the first model input items, and the yield rates of the packaging products to which all type C bare chips belong as the first model output items, import the first machine learning model based on the first artificial intelligence algorithm for training, and obtain the yield prediction model of type B bare chips. It is necessary to train the first machine learning model of the artificial intelligence algorithm to obtain a yield prediction model for C-type bare chips; it is necessary to take the multiple three-dimensional packaging process parameters of all D-type bare chips as the first model input items, and the yield of the packaged products to which all D-type bare chips belong as the first model output item, import the first machine learning model based on the first artificial intelligence algorithm for training, and obtain the yield prediction model for D-type bare chips; it is necessary to take the multiple three-dimensional packaging process parameters of all E-type bare chips as the first model input items, and the yield of the packaged products to which all E-type bare chips belong as the first model output item, import the first machine learning model based on the first artificial intelligence algorithm for training, and obtain the yield prediction model for E-type bare chips; it is necessary to take the multiple three-dimensional packaging process parameters of all F-type bare chips as the first model input items, and the yield of the packaged products to which all F-type bare chips belong as the first model output item, import the first machine learning model based on the first artificial intelligence algorithm for training, and obtain the yield prediction model for F-type bare chips.

[0094] In the step S2, the artificial intelligence algorithm is a core artificial intelligence algorithm that specifically studies how computers simulate or implement human learning behavior to acquire new knowledge or skills, reorganize the existing knowledge structure to continuously improve its own performance, and is the fundamental way to make computers intelligent; specifically, the first artificial intelligence algorithm preferably uses a linear regression algorithm based on the Python sklearn library to quickly and accurately find the rules in the data. The specific process of the calibration verification modeling includes the calibration process and the verification process of the model, that is, first by comparing the model simulation results with the measured data, and then adjusting the model parameters according to the comparison results, so that the simulation results are consistent with the actual process, so the yield prediction model can be obtained through the conventional calibration verification modeling method. Preferably, in the calibration verification modeling process of the first machine learning model, the model parameters are tuned using a Bayesian optimization algorithm based on a tree structure. In addition, the first artificial intelligence algorithm can also be but not limited to a machine learning algorithm based on support vector machine, K nearest neighbor method, stochastic gradient descent method, multivariate linear regression, multilayer perceptron, decision tree, back propagation neural network or radial basis function network.

[0095] S3. Obtain the chip model of each bare chip in the target product to be packaged using the bare chip stacking three-dimensional packaging process.

[0096] In step S3, the target product is the object to be subjected to the bare chip stacking three-dimensional packaging process, and the chip model of each bare chip can be obtained by manual input or automatic import.

[0097] S4. For each bare chip, a corresponding yield prediction model is matched according to the corresponding chip model.

[0098] In step S4, the specific matching method is to search whether there is a certain bare chip with the chip model in all the bare chip stacked three-dimensional packaging products according to the chip model of a certain bare chip in the target product; if so, the yield prediction model of the certain bare chip is used as the yield prediction model of the certain bare chip. Considering the situation that there are new bare chips in the target product, in order to also match the yield prediction model of the new bare chip, preferably, for each bare chip, according to the corresponding chip model, the corresponding yield prediction model is matched, including but not limited to the following steps S41 to S43.

[0099] S41. According to the chip model of a bare chip in the target product, search among all the bare chip stacked three-dimensional packaging products whether there is a bare chip with the chip model.

[0100] S42. If it exists, the yield prediction model of the certain bare chip is used as the yield prediction model of the certain bare chip.

[0101] S43. If it does not exist, first obtain the integrated circuit layout of the certain bare chip and the integrated circuit layout of each type of bare chip respectively, and then calculate the similarity between the integrated circuit layout of the certain bare chip and the integrated circuit layout of each type of bare chip respectively, and finally use the yield prediction model of any bare chip corresponding to the maximum similarity in all the bare chip stacked three-dimensional packaging products as the yield prediction model of the certain bare chip.

[0102] In step S43, the specific algorithm of the similarity can be derived based on the conventional existing related algorithms, for example, firstly performing singular value decomposition processing on the integrated circuit layout of the bare chip (Singular Value Decomposition ValueDecomposition, which is a very important decomposition method in matrix analysis applications, especially the unitary diagonalization of normal matrices occupies an important position in signal processing, digital image processing, statistics and other fields, and is widely used; singular value decomposition has important properties such as transposition invariance, rotation invariance, displacement invariance and mirror transformation invariance, which makes the singular value features more stable when describing images) to obtain the first singular value eigenvector, and also perform singular value decomposition processing on the integrated circuit layout of each bare chip to obtain the second singular value eigenvector of each bare chip, and then for each bare chip, calculate the cosine distance between the corresponding second singular value eigenvector and the first singular value eigenvector (which is a method for measuring the similarity between two vectors, which is calculated based on the complement of cosine similarity; its value range is between 0 and 2, the closer to 0, the more similar the two vectors are, and the closer to 2, the less similar they are) as the corresponding similarity.

[0103] S5. Apply the yield prediction model corresponding to each bare chip, optimize the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtain the chip three-dimensional packaging process solution designed for the target product and output it.

[0104] In the step S5, the optimization algorithm may be, but is not limited to, a particle swarm optimization algorithm or a gray wolf optimization algorithm, that is, specifically, a yield prediction model corresponding to each bare chip is applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on the particle swarm optimization algorithm or the gray wolf optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the target product. The particle swarm optimization algorithm (PSO) is a heuristic optimization algorithm that simulates the information sharing and collaboration mechanism in the foraging behavior of a flock of birds, and finds the optimal solution to the problem through interaction between individuals. In order to balance the local optimum and global optimum capabilities in parameter optimization, improve the efficiency of optimizing parameter search while ensuring overall reliability, preferably, a yield prediction model corresponding to each bare chip is applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on the particle swarm algorithm to obtain the chip three-dimensional packaging process solution designed for the target product, including the following steps S501 to S512.

[0105] S501. Initialize the algorithm parameters of the particle swarm optimization algorithm including the population size N, the maximum number of iterations T', the self-learning factor C1 and the global learning factor C2, and randomly generate the initial position of each particle in the particle population, and then execute step S502, wherein the initial position of each particle is randomly generated based on the following formula:

[0106]

[0107] In the formula, i' represents a positive integer, j represents a positive integer less than or equal to J, J represents the total number of bare chips in the target product, d represents a positive integer less than or equal to D, D represents the number of dimensions of the parameter vector to be optimized, and the parameter vector to be optimized includes the multiple three-dimensional packaging process parameters to be optimized. represents the initial position of the i'th particle in the particle population on the jth bare chip in the target product and on the dth dimension in the parameter vector to be optimized, u c,j,d represents the upper limit of the parameter search space on the j-th bare chip and in the d-th dimension, l c,j,d represents the lower limit of the parameter search space on the j-th bare chip and in the d-th dimension, and rand(0,1) represents a pure decimal random generation function.

[0108] In the step S501, the initial position of each particle includes initial values ​​of the plurality of three-dimensional packaging process parameters of J bare chips in the target product.

[0109] S502. For each of the particles, the corresponding initial positions on each bare chip are respectively input into the yield prediction model corresponding to each bare chip as the parameter search results, and the yield prediction value and confidence level corresponding to each bare chip are output. According to the yield prediction value and confidence level corresponding to each bare chip, the prediction value of the finished product comprehensive evaluation index of the target product is calculated as the corresponding fitness F, and then step S503 is executed.

[0110] In step S502, for example, if the target product includes three bare chips, namely, a type B bare chip, a type C bare chip, and a type E bare chip, the initial position on the type B bare chip (i.e., the initial values ​​of the multiple three-dimensional packaging process parameters of the type B bare chip) needs to be input as a parameter search result into the yield prediction model corresponding to the type B bare chip, and the yield prediction value and confidence level corresponding to the type B bare chip are output; the initial position on the type C bare chip (i.e., the initial values ​​of the multiple three-dimensional packaging process parameters of the type C bare chip) needs to be input as a parameter search result into the yield prediction model corresponding to the type C bare chip, and the yield prediction value and confidence level corresponding to the type C bare chip are output; the initial position on the type E bare chip (i.e., the initial values ​​of the multiple three-dimensional packaging process parameters of the type E bare chip) needs to be input as a parameter search result into the yield prediction model corresponding to the type E bare chip, and the yield prediction value and confidence level corresponding to the type E bare chip are output. The predicted value of the comprehensive evaluation index of the finished product is used to comprehensively reflect the predicted results of the finished product conditions corresponding to the multiple three-dimensional packaging process parameters of the J bare chips, so as to promote the particle swarm optimization algorithm to continue as a fitness. Specifically, according to the predicted value of the yield rate and the confidence corresponding to each bare chip, the predicted value of the comprehensive evaluation index of the finished product of the target product is calculated, including but not limited to: according to the predicted value of the yield rate and the confidence corresponding to each bare chip, the predicted value P of the comprehensive evaluation index of the finished product of the target product is calculated according to the following formula:

[0111]

[0112] In the formula, p j represents the yield prediction value corresponding to the j-th bare chip, η j represents the confidence level corresponding to the j-th bare chip.

[0113] S503. Determine whether the maximum value among the fitness of each particle is greater than or equal to a preset threshold value. If so, the initial positions corresponding to the maximum value and on each bare chip are respectively used as the multiple three-dimensional packaging process parameters designed for each bare chip, thereby obtaining the chip three-dimensional packaging process solution designed for the target product. Otherwise, execute step S504.

[0114] In the step S503, when it is determined that the maximum value among the fitness of each particle is greater than or equal to the preset threshold, it indicates that the initial values ​​of the multiple three-dimensional packaging process parameters of the J bare chips have reached the process parameter optimization target, and therefore the subsequent steps S504 to S512 may no longer be executed.

[0115] S504. Take the initial position of a particle with the maximum fitness as the initial global optimal position G ini , the position of the i'th particle in the iteration process and corresponding to the maximum fitness is the local optimal position P reached by the i'th particle i’ , and the position of the particle population in the iteration process and corresponding to the maximum fitness is recorded as the global optimal position G reached by the particle population, and the moving speed of the i'th particle is recorded as V i’ , and finally initialize the local optimal position P i’ =G=G ini , and initialize the moving speed to V i’ is zero, and the particle movement inertia coefficient range is also set to [T min ,T max ], and initialize the period T of the periodic reduction of the inertia coefficient to a randomly selected value within the range of the particle movement inertia coefficient, and also initialize the particle movement inertia coefficient during the iteration process to a value greater than zero, and also initialize the current iteration number t' to 0, and then execute step S505.

[0116] S505. Update the particle movement inertia coefficient of each particle, and then execute step S506, wherein the update formula of the particle movement inertia coefficient is as follows:

[0117]

[0118] In the formula, represents the particle movement inertia coefficient of the i'th particle on the jth bare chip and in the dth dimension obtained after the t'+1th iteration, represents the particle movement inertia coefficient of the i'th particle on the j'th bare chip and in the dth dimension before the t'+1th iteration, t'%T represents the modulo operation result of the previous iteration number t' on the period T, and if If it is less than 0, a new value is randomly selected within the range of the particle's inertia coefficient as the new period T, and the calculation is recalculated. until Not less than 0.

[0119] S506. Update the moving speed of each particle, and then execute step S507, wherein the updating formula of the moving speed is as follows:

[0120]

[0121] In the formula, represents the moving speed of the i'th particle on the jth bare chip and in the dth dimension obtained after the t'+1th iteration, represents the moving speed of the i'th particle on the jth bare chip and in the dth dimension before the t'+1th iteration, γ1 represents the first random number uniformly distributed in (0,1), represents the local optimal position reached by the i'th particle on the j'th bare chip and in the dth dimension during the first t' iterations, represents the position of the i'th particle on the jth bare chip and in the dth dimension before the t'+1th iteration, γ2 represents a second random number uniformly distributed in (0,1), represents the global optimal position reached by the particle population on the j-th bare chip and in the d-th dimension during the first t' iterations.

[0122] S507. Update the position of each particle, and then execute step S508, wherein the update formula of the position is as follows:

[0123]

[0124] In the formula, represents the position of the i'th particle on the jth bare chip and in the dth dimension obtained after the t'+1th iteration.

[0125] S508. For each particle, the corresponding position on each bare chip is used as a parameter to search for new results, and the results are input one by one into the yield prediction model corresponding to each bare chip. The new yield prediction value and new confidence level corresponding to each bare chip are output, and based on the new yield prediction value and new confidence level corresponding to each bare chip, the new prediction value of the comprehensive evaluation index of the finished product of the target product is calculated as the corresponding fitness F, and then step S509 is executed.

[0126] In the step S508, the specific process can be conventionally derived by referring to the above-mentioned step S502, and will not be described in detail here.

[0127] S509. Determine whether the maximum value among the current fitness of each particle is greater than or equal to the preset threshold value. If so, the initial positions corresponding to the maximum value and on each bare chip are used one by one as the multiple three-dimensional packaging process parameters designed for each bare chip, thereby obtaining the chip three-dimensional packaging process solution designed for the target product. Otherwise, execute step S510.

[0128] S510. Determine the local optimal position P i’ Is the corresponding fitness less than the current fitness of the i'th particle? If so, the local optimal position P i’ Update to the current position of the i'th particle, and then execute step S511; otherwise, directly execute step S511.

[0129] S511. Determine whether the fitness corresponding to the global optimal position G is less than the maximum value among the current fitnesses of the particles. If so, update the global optimal position G to the current position of any particle with the maximum value, and then execute step S512; otherwise, directly execute step S512.

[0130] S512. Increment the current number of iterations t' by 1, and determine whether the current number of iterations t' reaches the maximum number of iterations T'. If so, the initial positions corresponding to the global optimal fitness and on each bare chip are used one-to-one as the multiple three-dimensional packaging process parameters designed for each bare chip, and then the three-dimensional packaging process solution for the chip designed for the target product is obtained. Otherwise, return to step S505, wherein the global optimal fitness refers to the fitness corresponding to the global optimal position G.

[0131] In the step S512, the initial positions corresponding to the global optimal fitness and on the bare chips are used as the multiple three-dimensional packaging process parameters designed for the bare chips, indicating that the current values ​​of the multiple three-dimensional packaging process parameters of the J bare chips have reached the optimal process parameters, and further optimization is stopped. In addition, based on the above steps S501 to S512, the multiple three-dimensional packaging process parameters of the bare chips can be optimized using an improved particle swarm optimization algorithm, and a dynamic adjustment item of the inertia coefficient is added to the particle swarm algorithm, which balances the local optimal and global optimal capabilities in parameter optimization, improves the optimization parameter search efficiency, and ensures overall reliability.

[0132] Therefore, based on the reliability data management method described in the aforementioned steps S1 to S5, a new solution is provided for optimizing the design of chip three-dimensional packaging process solutions for new products based on the reliability data of historical bare chip stacked three-dimensional packaging products, that is, first, for each bare chip with different chip models in all bare chip stacked three-dimensional packaging products, based on the corresponding multiple three-dimensional packaging process parameters of all bare chips and the yield of the corresponding packaging products, a model is built to obtain a corresponding yield prediction model, and then for each bare chip in the target product, according to the corresponding chip model, a corresponding yield prediction model is matched to obtain a corresponding yield prediction model, and finally, the yield prediction model corresponding to each bare chip is applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on the optimization algorithm, so as to obtain the chip three-dimensional packaging process solution designed for the target product and output it. In this way, not only can the optimal chip three-dimensional packaging process solution for new products be automatically managed and analyzed, but also the manpower and material costs can be greatly reduced, the process design time can be shortened, and practical application and promotion are facilitated.

[0133] Based on the technical solution of the first aspect, this embodiment also provides a possible design for providing packaging process optimization suggestions for historical bare chip stacked three-dimensional packaging products. That is, the method also includes but is not limited to the following steps: for each product in all the bare chip stacked three-dimensional packaging products, the yield prediction model of each bare chip in the corresponding product is applied, and the multiple three-dimensional packaging process parameters of each bare chip in the corresponding product are optimized based on the optimization algorithm to obtain the newly designed chip three-dimensional packaging process solution for the corresponding product and output it as the chip three-dimensional packaging process optimization suggestion for the corresponding product. The specific details of the above optimization can be obtained by referring to the above step S5, which will not be repeated here.

[0134] Therefore, based on the above-mentioned possible design one, it is also possible to automatically manage and analyze the yield of historical bare chip stacked 3D packaging products and the chip 3D packaging process plan to obtain chip 3D packaging process optimization suggestions for old products, which is conducive to improving the yield of old products.

[0135] Based on the technical solution of the first aspect, the present embodiment also provides a possible second design for how to quickly obtain the packaging process design result of a new product, that is, the method also includes but is not limited to the following steps: for any chip combination composed of the various bare chips, the yield prediction model of each bare chip in the corresponding combination is applied, and the multiple three-dimensional packaging process parameters of each bare chip in the corresponding combination are optimized based on the optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the corresponding combination; if the chip model of each bare chip in the target product to be equipped with the bare chip stacking three-dimensional packaging process is matched to a certain chip combination, the chip three-dimensional packaging process solution designed for the certain chip combination is directly regarded as the chip three-dimensional packaging process solution designed for the target product and output. The specific details of the aforementioned optimization can be derived from the aforementioned step S5 and will not be repeated here. For example, the chip combination including a type B bare chip, a type C bare chip and a type E bare chip can be optimized in advance to obtain the chip three-dimensional packaging process scheme designed for the combination. Then, when the chip model of each bare chip in the target product to be subjected to the bare chip stacking three-dimensional packaging process is obtained, if the target product contains three bare chips and they are a type B bare chip, a type C bare chip and a type E bare chip respectively, the chip three-dimensional packaging process scheme designed for the combination can be directly regarded as the chip three-dimensional packaging process scheme designed for the target product and output, thereby eliminating the need to execute step S5, which can help to quickly obtain the packaging process design results of the new product.

[0136] Therefore, based on the aforementioned possible design two, a chip three-dimensional packaging process solution designed for various chip combinations is obtained through advance optimization, which can facilitate direct matching of the packaging process design results of the new product after determining the internal bare chip model of the new product, thereby improving the user experience.

[0137] Based on the technical solution of the first aspect mentioned above, this embodiment also provides a possible design three for optimizing the packaging process from the dimensions of finished product and process cost, that is, when the chip three-dimensional packaging process solution also includes the process cost of each bare chip in the corresponding product and corresponding to the multiple three-dimensional packaging process parameters, the method also includes but is not limited to the following steps S200, S400 and S500.

[0138] S200. For each type of bare chip, the multiple three-dimensional packaging process parameters of all corresponding bare chips are used as the second model input items, and the process costs of all corresponding bare chips and corresponding to the multiple three-dimensional packaging process parameters are used as the second model output items, and the second machine learning model based on the second artificial intelligence algorithm is calibrated and verified to obtain a corresponding process cost prediction model.

[0139] In the step S200, the process cost can also be collected during the packaging production process through conventional production management technology. For example, if there are type A bare chips, type B bare chips, type C bare chips, type D bare chips, type E bare chips and type F bare chips among all the bare chip stacked three-dimensional packaging products, it is necessary to use the multiple three-dimensional packaging process parameters of all type A bare chips as the second model input items, and the process costs of all type A bare chips and corresponding to the multiple three-dimensional packaging process parameters as the second model output items, import the second machine learning model based on the second artificial intelligence algorithm for training, and obtain the process cost prediction model of type A bare chips; it is necessary to use the multiple three-dimensional packaging process parameters of all type B bare chips as the second model input items, and the process costs of all type B bare chips and corresponding to the multiple three-dimensional packaging process parameters as the second model output items, import the second machine learning model based on the second artificial intelligence algorithm for training, and obtain the process cost prediction model of type B bare chips; it is necessary to use the multiple three-dimensional packaging process parameters of all type C bare chips as the second model input items, and the process costs of all type C bare chips and corresponding to the multiple three-dimensional packaging process parameters as the second model output items, import the second machine learning model based on the second artificial intelligence algorithm for training, and obtain the process cost prediction model of type B bare chips; The second machine learning model is used for training to obtain a process cost prediction model for C-type bare chips; the multiple three-dimensional packaging process parameters of all D-type bare chips need to be taken as the second model input items, and the process costs of all D-type bare chips and corresponding to the multiple three-dimensional packaging process parameters are taken as the second model output items, and are imported into the second machine learning model based on the second artificial intelligence algorithm for training to obtain a process cost prediction model for D-type bare chips; the multiple three-dimensional packaging process parameters of all E-type bare chips need to be taken as the second model input items, and the process costs of all E-type bare chips and corresponding to the multiple three-dimensional packaging process parameters are taken as the second model output items, and are imported into the second machine learning model based on the second artificial intelligence algorithm for training to obtain a process cost prediction model for E-type bare chips; the multiple three-dimensional packaging process parameters of all F-type bare chips need to be taken as the second model input items, and the process costs of all F-type bare chips and corresponding to the multiple three-dimensional packaging process parameters are taken as the second model output items, and are imported into the second machine learning model based on the second artificial intelligence algorithm for training to obtain a process cost prediction model for F-type bare chips. In addition, the second artificial intelligence algorithm preferably adopts a linear regression algorithm based on the Python sklearn library, and can also, but is not limited to, adopt a machine learning algorithm based on support vector machine, K nearest neighbor method, stochastic gradient descent method, multivariate linear regression, multilayer perceptron, decision tree, back propagation neural network or radial basis function network.

[0140] S400. For each bare chip, a corresponding process cost prediction model is matched according to the corresponding chip model.

[0141] In the step S400, specific matching details can be found in the aforementioned step S4, which will not be described in detail here.

[0142] S500. Apply the yield prediction model corresponding to each bare chip, optimize the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtain the chip three-dimensional packaging process solution designed for the target product and output it, specifically including but not limited to: apply the yield prediction model and process cost prediction model corresponding to each bare chip, optimize the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtain the chip three-dimensional packaging process solution designed for the target product and output it.

[0143] In the step S500, the specific details of the above-mentioned optimization can be obtained by referring to the derivation of the above-mentioned step S5, which will not be repeated here. For example, the yield prediction model and process cost prediction model corresponding to each of the bare chips are applied, and the multiple three-dimensional packaging process parameters of each of the bare chips are optimized based on the particle swarm optimization algorithm or the gray wolf optimization algorithm to obtain the chip three-dimensional packaging process scheme designed for the target product; the above-mentioned step S502 can be derived and replaced as follows: for each of the particles, the corresponding initial positions on each of the bare chips are respectively input as parameter search results one by one into the yield prediction model corresponding to each of the bare chips, and the yield prediction value and confidence corresponding to each of the bare chips are output, and the corresponding initial positions on each of the bare chips are also respectively input as parameter search results one by one into the corresponding yield prediction model corresponding to each of the bare chips. The process cost prediction model outputs the process cost prediction value and process cost prediction confidence corresponding to each bare chip, and calculates the comprehensive evaluation index prediction value of the target product as the corresponding fitness F according to the yield prediction value and confidence and process cost prediction value and process cost prediction confidence corresponding to each bare chip; the above-mentioned calculation of the comprehensive evaluation index prediction value of the target product according to the yield prediction value and confidence and process cost prediction value and process cost prediction confidence corresponding to each bare chip specifically includes: according to the yield prediction value and confidence and process cost prediction value and process cost prediction confidence corresponding to each bare chip, the comprehensive evaluation index prediction value P′ of the target product is calculated according to the following formula:

[0144]

[0145] In the formula, p j represents the yield prediction value corresponding to the j-th bare chip, η j represents the confidence level corresponding to the j-th bare chip, cj represents the process cost prediction value corresponding to the j-th bare chip, γ j represents the confidence level of the process cost prediction corresponding to the j-th bare chip.

[0146] Therefore, based on the aforementioned possible design three, the packaging process can be optimized and designed comprehensively from the dimensions of finished product and process cost to further improve the excellence of the packaging process design results.

[0147] like Figure 3 As shown, the second aspect of this embodiment provides a virtual system for implementing the reliability data management method described in the first aspect or any possible design in the first aspect, including a data acquisition unit, a model building unit, a model acquisition unit, a model matching unit and a process optimization unit;

[0148] The data acquisition unit is used to acquire reliability data of all bare chip stacked three-dimensional packaging products, wherein the bare chip stacked three-dimensional packaging product includes at least two bare chips stacked from bottom to top, and the reliability data includes a chip three-dimensional packaging process scheme and a yield rate, and the chip three-dimensional packaging process scheme includes a plurality of three-dimensional packaging process parameters of each bare chip in the corresponding product;

[0149] The model building unit is communicatively connected to the data acquisition unit, and is used to perform calibration and verification modeling on a first machine learning model based on a first artificial intelligence algorithm for each type of bare chip with different chip models in all the bare chip stacked three-dimensional packaging products, using the multiple three-dimensional packaging process parameters of all the corresponding bare chips as first model input items, and using the yield of the packaging products to which all the corresponding bare chips belong as a first model output item, to obtain a corresponding yield prediction model;

[0150] The model acquisition unit is used to acquire the chip model of each bare chip in the target product to be packaged using the bare chip stacking three-dimensional packaging process;

[0151] The model matching unit is respectively connected to the model building unit and the model acquisition unit for matching and obtaining a corresponding yield prediction model for each bare chip according to the corresponding chip model;

[0152] The process optimization unit is communicatively connected to the model matching unit, and is used to apply the yield prediction model corresponding to each bare chip, optimize the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtain the chip three-dimensional packaging process solution designed for the target product and output it.

[0153] In a possible design, the process optimization unit is also communicatively connected to the model building unit, and is also used to apply the yield prediction model of each bare chip in the corresponding product to each product among all the bare chip stacked three-dimensional packaging products, optimize the multiple three-dimensional packaging process parameters of each bare chip in the corresponding product based on the optimization algorithm, obtain the chip three-dimensional packaging process plan newly designed for the corresponding product and output it as a chip three-dimensional packaging process optimization suggestion for the corresponding product.

[0154] In a possible design, the process optimization unit is further communicatively connected to the model building unit, and is further used to apply the yield prediction model of each bare chip in the corresponding combination to any chip combination composed of the various bare chips, and optimize the multiple three-dimensional packaging process parameters of each bare chip in the corresponding combination based on the optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the corresponding combination;

[0155] The model acquisition unit is also communicatively connected to the process optimization unit, and is also used to directly output the chip 3D packaging process plan designed for the certain chip combination as the chip 3D packaging process plan designed for the target product if the chip models of each bare chip in the target product to be equipped with the bare chip stacking 3D packaging process are matched to a certain chip combination.

[0156] In a possible design, when the chip three-dimensional packaging process solution further includes the process costs of the various bare chips in the corresponding product and corresponding to the multiple three-dimensional packaging process parameters, the model building unit is further used for taking the multiple three-dimensional packaging process parameters of all the corresponding bare chips as second model input items, and taking the process costs of all the corresponding bare chips and corresponding to the multiple three-dimensional packaging process parameters as second model output items, and importing them into a second machine learning model based on a second artificial intelligence algorithm for training, so as to obtain a corresponding process cost prediction model;

[0157] The model matching unit is also used to match each bare chip to obtain a corresponding process cost prediction model according to the corresponding chip model;

[0158] The process optimization unit is also used to apply the yield prediction model and process cost prediction model corresponding to each bare chip, optimize the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtain the chip three-dimensional packaging process plan designed for the target product and output it.

[0159] The working process, working details and technical effects of the aforementioned system provided in the second aspect of this embodiment can be referred to the first aspect or any possible design of the reliability data management method described in the first aspect, and will not be repeated here.

[0160] like Figure 4 As shown, the third aspect of this embodiment provides a computer device for executing the reliability data management method as described in the first aspect or any possible design in the first aspect, including a memory, a processor and a transceiver that are sequentially connected in communication, wherein the memory is used to store a computer program, the transceiver is used to send and receive messages, and the processor is used to read the computer program, and execute the reliability data management method as described in the first aspect or any possible design in the first aspect. Specifically, the memory may include, but is not limited to, a random access memory (Random-Access Memory, RAM), a read-only memory (Read-Only Memory, ROM), a flash memory (Flash Memory), a first-in-first-out memory (First Input First Output, FIFO) and / or a first-in-last-out memory (First Input Last Output, FILO), etc.; the processor may be, but is not limited to, a microprocessor of the STM32F105 series. In addition, the computer device may also include, but is not limited to, a power module, a display screen and other necessary components.

[0161] The working process, working details and technical effects of the aforementioned computer device provided in the third aspect of this embodiment can be referred to the reliability data management method described in the first aspect or any possible design in the first aspect, and will not be repeated here.

[0162] The fourth aspect of this embodiment provides a computer-readable storage medium storing instructions including the reliability data management method described in the first aspect or any possible design in the first aspect, that is, the computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the reliability data management method described in the first aspect or any possible design in the first aspect is executed. The computer-readable storage medium refers to a carrier for storing data, which may include but is not limited to computer-readable storage media such as floppy disks, optical disks, hard disks, flash memories, USB flash drives, and / or memory sticks, and the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0163] The working process, working details and technical effects of the aforementioned computer-readable storage medium provided in the fourth aspect of this embodiment can be referred to the reliability data management method described in the first aspect or any possible design in the first aspect, and will not be repeated here.

[0164] A fifth aspect of this embodiment provides a computer program product, including a computer program or instructions, wherein the computer program or instructions, when executed by a computer, implements the reliability data management method as described in the first aspect or any possible design in the first aspect. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0165] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A reliability data management method for chip three-dimensional packaging process technology, characterized in that: include: Obtaining reliability data of all bare chip stacked 3D packaging products, wherein the bare chip stacked 3D packaging product includes at least two bare chips stacked from bottom to top, the reliability data includes a chip 3D packaging process scheme and a yield rate, and the chip 3D packaging process scheme includes a plurality of 3D packaging process parameters of each bare chip in the corresponding product; For each type of bare chip with different chip models in all the bare chip stacked three-dimensional packaging products, the plurality of three-dimensional packaging process parameters of all the corresponding bare chips are used as first model input items, and the yield of the packaging products to which all the corresponding bare chips belong is used as a first model output item, and a first machine learning model based on a first artificial intelligence algorithm is calibrated and verified to obtain a corresponding yield prediction model; Obtaining chip models of each bare chip in a target product to be packaged using a bare chip stacking stereo packaging process; For each bare chip, a corresponding yield prediction model is matched according to the corresponding chip model, specifically including: according to the chip model of a bare chip in the target product, searching whether there is a bare chip with the chip model in all the bare chip stacked three-dimensional packaging products; if so, using the yield prediction model of the bare chip as the yield prediction model of the bare chip; if not, first obtaining the integrated circuit layout of the bare chip and the integrated circuit layout of each bare chip respectively, and then calculating the similarity between the bare chip and the integrated circuit layout of each bare chip respectively, and finally using the yield prediction model of any bare chip corresponding to the maximum similarity in all the bare chip stacked three-dimensional packaging products as the yield prediction model of the bare chip; A yield prediction model corresponding to each bare chip is applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on an optimization algorithm to obtain and output the chip three-dimensional packaging process solution designed for the target product.

2. The reliability data management method according to claim 1, characterized in that: The multiple three-dimensional packaging process parameters include the size of the bumps grown on the chip, the diffusion welding temperature of the bumps grown on the chip and the substrate, the melting welding temperature of the bumps grown on the chip and the substrate, the spacing between the chip and the substrate, the size of the bumps grown on the substrate, the melting welding temperature of the bumps grown on the substrate and the substrate and / or the bottom-up sequence number of the chip.

3. The reliability data management method according to claim 1, characterized in that: Applying the yield prediction model corresponding to each bare chip, optimizing the multiple three-dimensional packaging process parameters of each bare chip based on an optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the target product, including: The yield prediction model corresponding to each bare chip is applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on the particle swarm optimization algorithm or the gray wolf optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the target product.

4. The reliability data management method according to claim 3, characterized in that: Applying the yield prediction model corresponding to each bare chip, optimizing the multiple three-dimensional packaging process parameters of each bare chip based on the particle swarm optimization algorithm, and obtaining the chip three-dimensional packaging process solution designed for the target product, including the following steps S501-S512: S501. Initialize the algorithm parameters of the particle swarm optimization algorithm including the population size N, the maximum number of iterations T', the self-learning factor C1 and the global learning factor C2, and randomly generate the initial position of each particle in the particle population, and then execute step S502, wherein the initial position of each particle is randomly generated based on the following formula: In the formula, i' represents a positive integer, j represents a positive integer less than or equal to J, J represents the total number of bare chips in the target product, d represents a positive integer less than or equal to D, D represents the number of dimensions of the parameter vector to be optimized, and the parameter vector to be optimized includes the multiple three-dimensional packaging process parameters to be optimized. represents the initial position of the i'th particle in the particle population on the jth bare chip in the target product and on the dth dimension in the parameter vector to be optimized, u c,j,d represents the upper limit of the parameter search space on the j-th bare chip and in the d-th dimension, l c,j,d represents the lower limit of the parameter search space on the j-th bare chip and in the d-th dimension, and rand(0,1) represents a pure decimal random generation function; S502. For each particle, the corresponding initial position on each bare chip is used as the parameter search result and input into the yield prediction model corresponding to each bare chip one by one, and the yield prediction value and confidence level corresponding to each bare chip are outputted, and the yield comprehensive evaluation index prediction value of the target product is calculated according to the yield prediction value and confidence level corresponding to each bare chip as the corresponding fitness F, and then step S503 is executed; S503. Determine whether the maximum value among the fitness of each particle is greater than or equal to a preset threshold value. If so, the initial positions corresponding to the maximum value and on each bare chip are used as the multiple three-dimensional packaging process parameters designed for each bare chip, thereby obtaining the chip three-dimensional packaging process solution designed for the target product. Otherwise, execute step S504; S504. Take the initial position of a particle with the maximum fitness as the initial global optimal position G ini , the position of the i'th particle in the iteration process and corresponding to the maximum fitness is the local optimal position P reached by the i'th particle i’ , and the position of the particle population in the iteration process and corresponding to the maximum fitness is recorded as the global optimal position G reached by the particle population, and the moving speed of the i'th particle is recorded as V i’ , and finally initialize the local optimal position P i’ =G=G ini , and initialize the moving speed to V i’ is zero, and the particle movement inertia coefficient range is also set to [T min ,T max ], and initialize the period T of the periodic reduction of the inertia coefficient to a randomly selected value within the range of the particle movement inertia coefficient, and also initialize the particle movement inertia coefficient in the iteration process to a value greater than zero, and also initialize the current iteration number t' to 0, and then execute step S505; S505. Update the particle movement inertia coefficient of each particle, and then execute step S506, wherein the update formula of the particle movement inertia coefficient is as follows: In the formula, represents the particle movement inertia coefficient of the i'th particle on the jth bare chip and in the dth dimension obtained after the t'+1th iteration, represents the particle movement inertia coefficient of the i'th particle on the j'th bare chip and in the dth dimension before the t'+1th iteration, t'%T represents the modulo operation result of the previous iteration number t' on the period T, and if If it is less than 0, a new value is randomly selected within the range of the particle's inertia coefficient as the new period T, and the calculation is recalculated. until Not less than 0; S506. Update the moving speed of each particle, and then execute step S507, wherein the updating formula of the moving speed is as follows: In the formula, represents the moving speed of the i'th particle on the jth bare chip and in the dth dimension obtained after the t'+1th iteration, represents the moving speed of the i'th particle on the jth bare chip and in the dth dimension before the t'+1th iteration, γ1 represents the first random number uniformly distributed in (0,1), represents the local optimal position reached by the i'th particle on the j'th bare chip and in the dth dimension during the first t' iterations, represents the position of the i'th particle on the jth bare chip and in the dth dimension before the t'+1th iteration, γ2 represents a second random number uniformly distributed in (0,1), represents the global optimal position reached by the particle population on the j-th bare chip and in the d-th dimension during the first t' iterations; S507. Update the position of each particle, and then execute step S508, wherein the update formula of the position is as follows: In the formula, represents the position of the i'th particle on the jth bare chip and in the dth dimension obtained after the t'+1th iteration; S508. For each particle, the corresponding position on each bare chip is used as a parameter search new result, and is input into the yield prediction model corresponding to each bare chip one by one, and a new yield prediction value and a new confidence corresponding to each bare chip are output, and a new prediction value of the finished product comprehensive evaluation index of the target product is calculated according to the new yield prediction value and the new confidence corresponding to each bare chip as the corresponding fitness F, and then step S509 is executed; S509. Determine whether the maximum value among the current fitness of each particle is greater than or equal to the preset threshold value. If so, the initial positions corresponding to the maximum value and on each bare chip are used as the multiple three-dimensional packaging process parameters designed for each bare chip, thereby obtaining the chip three-dimensional packaging process solution designed for the target product. Otherwise, execute step S510; S510. Determine the local optimal position P i’ Is the corresponding fitness less than the current fitness of the i'th particle? If so, the local optimal position P i’ Update to the current position of the i'th particle, and then execute step S511, otherwise directly execute step S511; S511. Determine whether the fitness corresponding to the global optimal position G is less than the maximum value among the current fitness of each particle. If so, update the global optimal position G to the current position of any particle with the maximum value, and then execute step S512. Otherwise, directly execute step S512; S512. Increment the current number of iterations t' by 1, and determine whether the current number of iterations t' reaches the maximum number of iterations T'. If so, the initial positions corresponding to the global optimal fitness and on each bare chip are used one-to-one as the multiple three-dimensional packaging process parameters designed for each bare chip, and then the three-dimensional packaging process solution for the chip designed for the target product is obtained. Otherwise, return to step S505, wherein the global optimal fitness refers to the fitness corresponding to the global optimal position G.

5. The reliability data management method according to claim 4, characterized in that: According to the yield rate prediction value and confidence level corresponding to each bare chip, the prediction value of the finished product comprehensive evaluation index of the target product is calculated, including: According to the yield rate prediction value and confidence level corresponding to each bare chip, the finished product comprehensive evaluation index prediction value P of the target product is calculated according to the following formula: In the formula, p j represents the yield prediction value corresponding to the j-th bare chip, η j represents the confidence level corresponding to the j-th bare chip.

6. The reliability data management method according to claim 1, characterized in that: The method further comprises: For each product among all the bare chip stacked three-dimensional packaging products, the yield prediction model of each bare chip in the corresponding product is applied, and the multiple three-dimensional packaging process parameters of each bare chip in the corresponding product are optimized based on the optimization algorithm to obtain the newly designed chip three-dimensional packaging process solution for the corresponding product and output it as a chip three-dimensional packaging process optimization suggestion for the corresponding product.

7. The reliability data management method according to claim 1, characterized in that: The method further comprises: For any chip combination consisting of the various bare chips, a yield prediction model of each bare chip in the corresponding combination is applied, and the plurality of three-dimensional packaging process parameters of each bare chip in the corresponding combination are optimized based on an optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the corresponding combination; If a chip combination is matched to the chip models of each bare chip in the target product to which the bare chip stacking 3D packaging process is to be adopted, the chip 3D packaging process scheme designed for the chip combination will be directly regarded as the chip 3D packaging process scheme designed for the target product and output.

8. The reliability data management method according to claim 1, characterized in that: When the three-dimensional chip packaging process solution further includes process costs of each bare chip in the corresponding product and corresponding to the plurality of three-dimensional packaging process parameters, the method further includes: For each of the bare chips, the plurality of three-dimensional packaging process parameters of all the corresponding bare chips are used as second model input items, and the process costs of all the corresponding bare chips and corresponding to the plurality of three-dimensional packaging process parameters are used as second model output items, and are introduced into a second machine learning model based on a second artificial intelligence algorithm for training to obtain a corresponding process cost prediction model; For each bare chip, a corresponding process cost prediction model is matched according to the corresponding chip model; Applying the yield prediction model corresponding to each bare chip, optimizing the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtaining the chip three-dimensional packaging process solution designed for the target product and outputting it, including: The yield prediction model and process cost prediction model corresponding to each bare chip are applied, and the multiple three-dimensional packaging process parameters of each bare chip are optimized based on the optimization algorithm to obtain the chip three-dimensional packaging process solution designed for the target product and output it.

9. A reliability data management system for chip 3D packaging process technology, characterized in that: It includes a data acquisition unit, a model building unit, a model acquisition unit, a model matching unit and a process optimization unit; The data acquisition unit is used to acquire reliability data of all bare chip stacked three-dimensional packaging products, wherein the bare chip stacked three-dimensional packaging product includes at least two bare chips stacked from bottom to top, and the reliability data includes a chip three-dimensional packaging process scheme and a yield rate, and the chip three-dimensional packaging process scheme includes a plurality of three-dimensional packaging process parameters of each bare chip in the corresponding product; The model building unit is communicatively connected to the data acquisition unit, and is used to perform calibration and verification modeling on a first machine learning model based on a first artificial intelligence algorithm for each type of bare chip with different chip models in all the bare chip stacked three-dimensional packaging products, using the multiple three-dimensional packaging process parameters of all the corresponding bare chips as first model input items, and using the yield of the packaging products to which all the corresponding bare chips belong as a first model output item, to obtain a corresponding yield prediction model; The model acquisition unit is used to acquire the chip model of each bare chip in the target product to be packaged using the bare chip stacking three-dimensional packaging process; The model matching unit is respectively communicatively connected to the model building unit and the model acquisition unit, and is used for matching the corresponding yield prediction model for each bare chip according to the corresponding chip model, specifically including: according to the chip model of a bare chip in the target product, searching whether there is a bare chip with the chip model in all the bare chip stacked three-dimensional packaging products; if so, using the yield prediction model of the bare chip as the yield prediction model of the bare chip; if not, first respectively obtaining the integrated circuit layout of the bare chip and the integrated circuit layout of each bare chip, and then respectively calculating the similarity between the bare chip and the integrated circuit layout of each bare chip, and finally using the yield prediction model of any bare chip corresponding to the maximum similarity in all the bare chip stacked three-dimensional packaging products as the yield prediction model of the bare chip; The process optimization unit is communicatively connected to the model matching unit, and is used to apply the yield prediction model corresponding to each bare chip, optimize the multiple three-dimensional packaging process parameters of each bare chip based on the optimization algorithm, obtain the chip three-dimensional packaging process solution designed for the target product and output it.

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