A method and device for simplifying logic of multiplexer unit of FPGA synthesis tool

Abstract

The present application provides a method and device for simplifying the logic of a multiplexer unit of an FPGA synthesis tool, the method comprising: traversing the logic units in the circuit netlist, storing the mapping relationship of the output signal of the logic unit c to the logic unit c into the logic unit output signal mapping set, and storing the logic unit whose logic unit type is a multiplexer into the multiplexer unit set; traversing the multiplexer units in the multiplexer unit set, and performing basic logic simplification according to the input signal of the multiplexer unit; merging the branches with the same signal in the single-level structure of the multiplexer unit and merging the branches with the same signal in the left and right multiplexers in the hierarchical structure of the multiplexer unit. The present application can not only simplify the multiplexer unit quickly and accurately, but also merge the branches with the same signal in the hierarchical structure of the multiplexer unit, thereby reducing the number of multiplexer units.

Description

Technical Field

[0001] The present application belongs to the field of FPGA technology, and in particular, relates to a method and device for simplifying logic of a multiplexer unit of an FPGA synthesis tool. Background Art

[0002] Logic synthesis is an important step in the FPGA EDA software design process. It converts the Verilog / VHDL circuit files at the behavioral level or register transfer level (RTL) input by the user into a netlist file composed of FPGA basic logic units such as lookup tables (LUTs) and flip-flops (FFs). FPGA logic synthesis includes two stages: synthesis and mapping. Synthesis is to convert the circuit files at the behavioral level or RTL into a logic netlist composed of gate circuits; mapping is to map the logic netlist composed of gate circuits into a netlist file composed of FPGA basic logic units.

[0003] Area, that is, the number of resources, is an important indicator of FPGA logic synthesis tools. Reducing the number of resources after FPGA logic synthesis is very important to improve the routing rate and timing performance of FPGA software. The multiplexer (Mux) unit is one of the basic logic units in the FPGA synthesis netlist. The circuit netlist after synthesis of FPGA complex application circuits usually contains a large number of Mux units. Many Mux units can be logically simplified according to the input signal and hierarchical structure.

[0004] Therefore, it is necessary to improve the synthesis tool so that the logic synthesis tool can effectively simplify the Mux unit and reduce the consumption of logic resources. Summary of the invention

[0005] The present application discloses a method and device for simplifying the logic of a multiplexer unit of an FPGA synthesis tool, which can quickly and accurately simplify the multiplexer unit, merge branches with the same signal in the multiplexer unit hierarchy, and reduce the number of multiplexer units.

[0006] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0007] To achieve one or part or all of the above purposes or other purposes, in a first aspect, the present application provides a method for logic simplification of a multiplexer unit of an FPGA synthesis tool, comprising: traversing the logic units in a circuit netlist, determining the type of the logic unit, storing the mapping relationship between the output signal of the logic unit c and the logic unit c in a logic unit output signal mapping set, and storing the logic units whose logic unit type is a multiplexer in a multiplexer unit set; traversing each multiplexer unit in the multiplexer unit set, and performing basic logic simplification according to the input signal of each multiplexer unit; merging branches with the same signal in a single-level structure of the multiplexer unit and merging branches with the same signal in the left and right multiplexers in the hierarchical structure of the multiplexer unit.

[0008] In one implementation, if one or more of the input A-end signal, the input B-end signal, and the input S-end signal of the multiplexer unit is a constant signal, basic logic simplification is performed on the multiplexer unit.

[0009] In one implementation, the basic logic simplification of the multiplexer unit includes: if the input S-end signal of the multiplexer unit is a constant signal 0, the output signal of the multiplexer unit is replaced by the input A-end signal of the multiplexer unit, and the multiplexer unit is deleted; if the input S-end signal of the multiplexer unit is a constant signal 1, the output signal of the multiplexer unit is replaced by the input B-end signal of the multiplexer unit, and the multiplexer unit is deleted; if the input A-end signal of the multiplexer unit is a constant signal If the signal of the input terminal B of the multiplexer unit is constant signal 0 and the signal of the input terminal B of the multiplexer unit is constant signal 1, the output signal of the multiplexer unit is replaced by the signal of the input terminal S of the multiplexer unit, and the multiplexer unit is deleted; if the signal of the input terminal A of the multiplexer unit is constant signal 1 and the signal of the input terminal B of the multiplexer unit is constant signal 0, the type of the multiplexer unit is changed to NOT, and the signal of the input terminal A of the multiplexer unit is replaced by the signal of the input terminal S; if the signal of the input terminal A of the multiplexer unit is constant If the signal of the input terminal A of the multiplexer unit is constant signal 1 and the signal of the input terminal B of the multiplexer unit is constant signal 1, the output signal of the multiplexer unit is replaced by constant signal 1 and the multiplexer unit is deleted; if the signal of the input terminal A of the multiplexer unit is constant signal 0, the type of the multiplexer unit is modified is AND, and the input A-end signal of the multiplexer unit is replaced by the input S-end signal; if the input B-end signal of the multiplexer unit is the constant signal 1, the type of the multiplexer unit is changed to OR, and the input B-end signal of the multiplexer unit is replaced by the input S-end signal; if the input A-end signal of the multiplexer unit is the same as the input B-end signal of the multiplexer unit, the output signal of the multiplexer unit is replaced by the input A-end signal of the multiplexer unit, and the multiplexer unit is deleted.

[0010] In one implementation, branches with the same signal in a single-level structure of a multiplexer unit are merged, including obtaining a logic unit c1 whose output signal is an input A-end signal of the multiplexer unit from a logic unit output signal mapping set; if the type of the logic unit c1 is a multiplexer, and the input B-end signal of the logic unit c1 is the same as the input B-end signal of the multiplexer unit, then a new OR-type logic unit or1 is created, and the input S-end signal of the multiplexer unit and the input S-end signal of the logic unit c1 are used as the input signal of the logic unit or1; the input S-end signal of the multiplexer unit is replaced by the output signal of the logic unit or1, and the input A-end signal of the multiplexer unit is replaced by the input A-end signal of the logic unit c1.

[0011] In one implementation, the method further includes obtaining a logic unit c1 whose output signal is a multiplexer unit input A-end signal from a logic unit output signal mapping set; if the type of the logic unit c1 is a multiplexer, and the input A-end signal of the logic unit c1 is the same as the input B-end signal of the multiplexer unit, then creating a new OR-type logic unit or1, and using the input S-end signal of the multiplexer unit and the inverted signal of the input S-end signal of the logic unit c1 as the input signal of the logic unit or1; replacing the input S-end signal of the multiplexer unit with the output signal of the logic unit or1, and replacing the input A-end signal of the multiplexer unit with the input B-end signal of the logic unit c1.

[0012] In one implementation, the method further includes obtaining a logic unit c2 whose output signal is a multiplexer unit input B-end signal from a logic unit output signal mapping set; if the type of the logic unit c2 is a multiplexer, and the input A-end signal of the logic unit c2 is the same as the input A-end signal of the multiplexer unit, then creating a new AND-type logic unit and1, and using the input S-end signal of the multiplexer unit and the input S-end signal of the logic unit c2 as the input signal of the logic unit and1; replacing the input S-end signal of the multiplexer unit with the output signal of the logic unit and1, and replacing the input B-end signal of the multiplexer unit with the input B-end signal of the logic unit c2.

[0013] In one implementation, the method further includes obtaining a logic unit c2 whose output signal is a multiplexer unit input B-end signal from a logic unit output signal mapping set; if the type of the logic unit c2 is a multiplexer, and the input B-end signal of the logic unit c2 is the same as the input A-end signal of the multiplexer unit, then creating a new AND-type logic unit and1, and using the input S-end signal of the multiplexer unit and the inverted signal of the input S-end signal of the logic unit c2 as the input signal of the logic unit and1; replacing the input S-end signal of the multiplexer unit with the output signal of the logic unit and1, and replacing the input B-end signal of the multiplexer unit with the input A-end signal of the logic unit c2.

[0014] In one implementation, branches with the same signal of the left and right multiplexers in the multiplexer unit hierarchy are merged, including obtaining, from a logic unit output signal mapping set, a logic unit c1 whose output signal is the same as the signal of the input A end of the multiplexer unit c, and a logic unit c2 whose output signal is the same as the signal of the input B end of the multiplexer unit c; if the type of the logic unit c1 and the logic unit c2 are both multiplexers, and the logic unit c1 and the logic unit c2 have at least two branches with the same signal, then the branches with the same signal of the logic unit c1 and the logic unit c2 are merged.

[0015] In one implementation, the method further includes, if the input S-end signal of the logic unit c1 is the same as the input S-end signal of the logic unit c2, and the input A-end signal of the logic unit c1 is the same as the input A-end signal of the logic unit c2, then replacing the input S-end signal of the multiplexer unit c with the input S-end signal of the logic unit c1, and replacing the input A-end signal of the multiplexer unit with the input A-end signal of the logic unit c1; creating a new multiplexer unit c3, replacing the input S-end signal of the multiplexer unit c3 with the input S-end signal of the multiplexer unit c, replacing the input A-end signal of the multiplexer unit c3 with the input B-end signal of the logic unit c1, replacing the input B-end signal of the multiplexer unit c3 with the input B-end signal of the logic unit c2, and modifying the input B-end signal of the multiplexer unit c to the output signal of the multiplexer unit c3.

[0016] In one implementation, the method further includes, if the input S-end signal of the logic unit c1 is the same as the input S-end signal of the logic unit c2, and the input B-end signal of the logic unit c1 is the same as the input B-end signal of the logic unit c2, then replacing the input S-end signal of the multiplexer unit c with the input S-end signal of the logic unit c1, and replacing the input B-end signal of the multiplexer unit with the input B-end signal of the logic unit c1; creating a new multiplexer unit c3, replacing the input S-end signal of the multiplexer unit c3 with the input S-end signal of the multiplexer unit c, replacing the input A-end signal of the multiplexer unit c3 with the input A-end signal of the logic unit c1, replacing the input B-end signal of the multiplexer unit c3 with the input A-end signal of the logic unit c2, and modifying the input A-end signal of the multiplexer unit c to the output signal of the multiplexer unit c3.

[0017] In the second aspect, the present application provides a logic simplification device for a multiplexer unit of an FPGA synthesis tool, the device comprising: an acquisition module, used to traverse the logic units in the circuit netlist, determine the type of the logic unit, store the mapping relationship between the output signal of the logic unit c and the logic unit c in the logic unit output signal mapping set, and store the logic unit whose logic unit type is a multiplexer in the multiplexer unit set; a logic simplification module, used to traverse each multiplexer unit in the multiplexer unit set, and perform basic logic simplification according to the input signal of each multiplexer unit; a merging module, used to merge branches with the same signal in a single-level structure of the multiplexer and to merge branches with the same signal of the left and right multiplexers in the multiplexer unit hierarchical structure.

[0018] In a third aspect, the present application provides a computer-readable storage medium having program code stored therein, and the program code is called by a processor to execute the logic simplification method of a multiplexer unit of an FPGA synthesis tool according to any one of the first aspects.

[0019] In a fourth aspect, the present application also provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute a logic simplification method of a multiplexer unit of an FPGA synthesis tool as described in any one of the first aspects.

[0020] The logic simplification method and device of the multiplexer unit of the above-mentioned FPGA synthesis tool reduces the number of multiplexer units in the circuit netlist by quickly and accurately simplifying the branches with the same signal in the single-level structure of the multiplexer unit, and merging the branches with the same signal of the left and right multiplexers in the nested multiplexer unit hierarchy, thereby reducing the area of ​​the circuit netlist after logic synthesis.

[0021] In order to make the above and other purposes, features and advantages of the present application more obvious and understandable, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is a flow chart of a logic simplification method for a multiplexer unit of an FPGA synthesis tool of this application.

[0024] Figure 2 A flowchart that simplifies the basic logic of executing this application.

[0025] Figure 3 This is a flow chart of merging branches having the same signal as signal sig_b in a single-level structure of a multiplexer unit c in the present application.

[0026] Figure 4 This is a flow chart of merging branches having the same signal as signal sig_a in a single-level structure of a multiplexer unit c in the present application.

[0027] Figure 5A schematic diagram of a flow chart of the same signal between the left and right multiplexers in the hierarchical structure of the combined multiplexer unit for this application.

[0028] Figure 6 This is a structural block diagram of the logic simplification device of the multiplexer unit of the FPGA synthesis tool of this application. DETAILED DESCRIPTION

[0029] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0030] The present application provides a logic simplification method for a multiplexer unit of an FPGA synthesis tool. The method traverses the logic unit c in the circuit netlist, stores the mapping relationship between the output signal of the logic unit c and the logic unit c in the logic unit output signal mapping set out2cell; and stores the logic unit of the type of multiplexer Mux in the multiplexer unit set muxs. Traverse each multiplexer unit in the set muxs, and perform the basic logic simplification process according to the input A-end signal sig_a, the input B-end signal sig_b and the input S-end signal sig_s of the multiplexer unit c. Merge the branches with the same signal in the multiplexer unit hierarchy, merge the branches with the same signal in the left and right sub-multiplexers in the multiplexer unit hierarchy, realize the optimization for a specific multiplexer unit hierarchy, adjust the structure of the multiplexer unit hierarchy, reduce the number of multiplexer units in the circuit netlist, and thus reduce the area of ​​the circuit netlist after logic synthesis.

[0031] The present application is described in detail below with reference to the accompanying drawings.

[0032] refer to Figure 1 , an embodiment of the present application provides a logic simplification method for a multiplexer unit of an FPGA synthesis tool, the method comprising the following steps:

[0033] Step S101: traverse the logic cells in the circuit netlist, store the mapping relationship from the output signal of logic cell c to logic cell c in the logic cell output signal mapping set out2cell, and store the logic cells of the multiplexer type in the multiplexer cell set muxs.

[0034] Step S102: traverse each multiplexer unit c in the multiplexer unit set muxs, and perform basic logic simplification according to the input A-end signal sig_a, the input B-end signal sig_b, and the input S-end signal sig_s of the multiplexer unit c.

[0035] Step S103: merging signal branches in the multiplexer unit hierarchy structure that have the same signal as the input B-end signal.

[0036] Step S104: merging signal branches in the multiplexer unit hierarchy structure that have the same signal as the input A-end signal.

[0037] Step S105: merging branches with the same signal in the left and right multiplexers in the multiplexer unit hierarchy.

[0038] The logic simplification method and device of the multiplexer unit of the above-mentioned FPGA synthesis tool can not only quickly and accurately simplify the branches with the same signal in the single-level structure of the multiplexer unit, but also merge the branches with the same signal of the left and right multiplexers in the nested multiplexer unit hierarchy, thereby reducing the number of multiplexer units in the circuit netlist, reducing the area of ​​the circuit netlist after logic synthesis, and improving the performance of the circuit.

[0039] The process of basic logic simplification includes: determining whether the input A-end signal sig_a, the input B-end signal sig_b and the input S-end signal sig_s of the multiplexer unit c are constant signals, and performing basic logic simplification when at least one input-end signal is a constant signal.

[0040] refer to Figure 2 , the process of performing basic logic simplification specifically includes the following steps:

[0041] Step S201: if sig_s is a constant signal 0, the output signal sig_y of the multiplexer unit c is replaced by sig_a and the multiplexer unit c is deleted; otherwise, step S202 is executed.

[0042] Step S202: if sig_s is a constant signal 1, the output signal sig_y of the multiplexer unit c is replaced by sig_b and the multiplexer unit c is deleted; otherwise, step S203 is executed.

[0043] Step S203: if sig_a is a constant signal of 0 and sig_b is a constant signal of 1, the output signal sig_y of the multiplexer unit c is replaced by sig_s and the multiplexer unit c is deleted; otherwise, step S204 is executed.

[0044] Step S204: if sig_a is a constant signal 1 and sig_b is a constant signal 0, modify the type of the multiplexer unit c to not and the input A terminal signal of the multiplexer unit c to sig_s; otherwise, execute step S205.

[0045] Step S205: if sig_a is a constant signal of 0 and sig_b is a constant signal of 0, the output signal sig_y of the multiplexer unit c is replaced by the constant signal of 0 and the multiplexer unit c is deleted; otherwise, step S206 is executed.

[0046] Step S206: If sig_a is constant signal 1 and sig_b is constant signal 1, the output signal sig_y of the multiplexer unit c is replaced by the constant signal 1 and the multiplexer unit c is deleted; otherwise, execute step S207.

[0047] Step S207: If sig_a is a constant signal 0, modify the type of the multiplexer unit c to be modified = and and the input A-end signal of the multiplexer unit c to be = sig_s, and the input B-end signal remains unchanged; otherwise, execute step S208.

[0048] Step S208: If sig_b is a constant signal 1, modify the type of the multiplexer unit c to be modified = or and the input B-end signal of the multiplexer unit c to be = sig_s, and the input A-end signal remains unchanged; otherwise, execute step S209.

[0049] Step S209: If sig_a=sig_b, the output signal sig_y of the multiplexer unit c is replaced by sig_a and the multiplexer unit c is deleted.

[0050] By performing basic logic simplification on the multiplexer unit when one or more of the input A-end signal, the input B-end signal, and the input S-end signal of the multiplexer unit are constant signals, it is possible to quickly and accurately merge the input signals of the multiplexer unit as constant signals, thereby reducing the signal branches of the multiplexer unit.

[0051] Next, branches with the same signal in a single-level structure of a multiplexer unit are merged, and branches with the same signal in the left and right multiplexers in the multiplexer unit hierarchy are merged.

[0052] First, merge the branches with the same signal as signal sig_b in the single-level structure of the multiplexer unit c: obtain the logic unit c1 whose output signal is the multiplexer unit input A terminal signal from the logic unit output signal mapping set. Determine whether the type of the logic unit c1 is a multiplexer, and determine whether the input terminal signal of the logic unit c1 is the same as the input terminal signal of the multiplexer unit B. If any input terminal signal of the logic unit c1 is the same as the input terminal signal of the multiplexer unit c, merge the branches with the same signal in the logic unit c1 and the multiplexer unit c.

[0053] refer to Figure 3 , the merging process specifically includes the following steps:

[0054] Step S301: Obtain the logic cell c1 whose output signal is sig_a from the logic cell output signal mapping set out2cell. If the logic cell c1 type = multiplexer Mux, execute step S302; otherwise, exit this process.

[0055] Step S302: determine whether the input B-end signal sig_b1 of the logic unit c1 is equal to the signal sig_b; if they are the same, execute step S303; otherwise, execute step S305.

[0056] Step S303: create a new logic unit or1 of the or type, the input signal of or1 is sig_s and the input S-end signal sig_s1 of the logic unit c1.

[0057] Step S304: modify the input S-end signal of the multiplexer unit c = the output signal of or1, and the input A-end signal of the multiplexer unit c = the input A-end signal sig_a1 of the logic unit c1.

[0058] Step S305: determine whether the input A-end signal sig_a1 of the logic unit c1 is equal to the signal sig_b; if they are the same, execute step S306; otherwise, exit this process.

[0059] Step S306: create a new logic unit or1 of the or type, the input signals of or1 are the signal sig_s and the inverted signal of the signal sig_s1 at the S end of the logic unit c1.

[0060] Step S307: modify the input S-end signal of the multiplexer unit c = the output signal of or1, and the input A-end signal of the multiplexer unit c = the input B-end signal sig_b1 of the logic unit c1.

[0061] Then merge the branches with the same signal as signal sig_a in the single-level structure of the multiplexer unit c: obtain the logic unit c2 whose output signal is the signal of the multiplexer unit input B terminal from the logic unit output signal mapping set. Determine whether the type of the logic unit c2 is a multiplexer, and determine whether the input terminal signal of the logic unit c2 is the same as the input terminal signal of the multiplexer unit A. In the case that any input terminal signal of the logic unit c2 is the same as the input terminal signal of the multiplexer unit c, merge the branches with the same signal in the logic unit c2 and the multiplexer unit c.

[0062] refer to Figure 4 , the merging process includes the following steps:

[0063] Step S401: Obtain the logic cell c2 whose output signal is sig_b from the logic cell output signal mapping set out2cell. If the type of the logic cell c2 is a multiplexer Mux, execute step S402; otherwise, exit this process.

[0064] Step S402: determine whether the input A-end signal sig_a2 of the logic unit c2 is equal to sig_a; if they are the same, execute step S403; otherwise, execute step S405.

[0065] Step S403: create a new logic unit and1 of the AND type, the input signal of and1 is sig_s and the input S-end signal sig_s2 of the logic unit c2.

[0066] Step S404: modify the input S-end signal of the multiplexer unit c = the output signal of and1, and the input B-end signal of the multiplexer unit c = the input B-end signal sig_b2 of the logic unit c2.

[0067] Step S405: determine whether the input B-end signal sig_b2 of the logic unit c2 is equal to sig_a; if they are the same, execute step S406; otherwise, exit this process.

[0068] Step S406: create a new and-type logic unit and1, the input signal of and1 is sig_s and the inverted signal of the S-end signal sig_s2 of the logic unit c2 input.

[0069] Step S407: modify the input S-end signal of the multiplexer unit c = the output signal of and1, and the input B-end signal of the multiplexer unit c = the input A-end signal sig_a2 of the logic unit c2.

[0070] By using the above-mentioned processing method of merging branches with the same signal in the logic unit and the multiplexer unit when any input terminal signal of the logic unit is the same as the input terminal signal of the multiplexer unit, it is possible to merge branches with the same signal in a single-level structure of the multiplexer unit, thereby reducing the number of multiplexer units in the circuit netlist.

[0071] Finally, the branches with the same signal of the left and right multiplexers in the multiplexer unit hierarchy are merged: the logic unit c1 whose output signal is the same as the input A terminal signal of the multiplexer unit c, and the logic unit c2 whose output signal is the same as the input B terminal signal of the multiplexer unit c are obtained from the logic unit output signal mapping set, and the types of the logic unit c1 and the logic unit c2 are both multiplexers. In the case that the types of the logic unit c1 and the logic unit c2 are both multiplexers and the logic unit c1 and the logic unit c2 have at least two branches with the same signal, the branches with the same signal of the logic unit c1 and the logic unit c2 are merged.

[0072] refer to Figure 5 The process of merging branches of the left and right multiplexers with the same signal in the multiplexer unit hierarchy specifically includes the following steps:

[0073] Step S501: Obtain the logic cell c1 whose output signal is sig_a and the logic cell c2 whose output signal is sig_b from the logic cell output signal mapping set out2cell.

[0074] Step S502: If the types of c1 and c2 are both multiplexers Mux and the input S-end signal sig_s1 of c1 is equal to the input S-end signal sig_s2 of c2, then execute step S503; otherwise, exit this process.

[0075] Step S503: Determine whether the input A-end signal sig_a1 of c1 is equal to the input A-end signal sig_a2 of c2; if they are the same, execute step S504; otherwise, execute step S506.

[0076] Step S504: modify the input S-terminal signal of the multiplexer unit c = sig_s1, and the input A-terminal signal of the multiplexer unit c = sig_a1.

[0077] Step S505: create a new multiplexer unit c3, the input S-end signal of c3 = sig_s, the input A-end signal of c3 = the input B-end signal sig_b1 of c1, the input B-end signal of c3 = the input B-end signal sig_b2 of c2, and modify the input B-end signal of the multiplexer unit c = the output signal of c3.

[0078] Step S506: Determine whether sig_b1 is equal to sig_b2. If they are the same, execute step S507; otherwise, exit this process.

[0079] Step S507: modify the input S-end signal of the multiplexer unit c = sig_s1, and the input B-end signal of the multiplexer unit c = sig_b1.

[0080] Step S508: create a new multiplexer unit c3, the input S-end signal of c3 = sig_s, the input A-end signal of c3 = sig_a1, the input B-end signal of c3 = sig_a2, and modify the input A-end signal of the multiplexer unit c = the output signal of c3.

[0081] By means of the above-mentioned implementation method of merging the branches of the same signal of logic unit c1 and logic unit c2 when both logic unit c1 and logic unit c2 are of the type of multiplexers and logic unit c1 and logic unit c2 have at least two branches of the same signal, it is possible to quickly and accurately simplify and optimize the branches with the same signal in the hierarchy of the multiplexer units, reduce the number of multiplexer units in the circuit netlist, reduce the area of ​​the circuit netlist after logic synthesis, and improve the performance of the circuit.

[0082] In another aspect, reference Figure 6 The present application also provides a logic simplification device for a multiplexer unit of an FPGA synthesis tool, the device comprising:

[0083] The acquisition module is used to traverse the logic units in the circuit netlist, determine the type of the logic unit, store the mapping relationship between the output signal of the logic unit c and the logic unit c in the logic unit output signal mapping set, and store the logic unit whose logic unit type is a multiplexer in the multiplexer unit set.

[0084] The logic simplification module is used for traversing each multiplexer unit in the multiplexer unit set and performing basic logic simplification according to the input signal of each multiplexer unit.

[0085] The merging module is used to merge branches with the same signal in a single-level structure of multiplexers and to merge branches with the same signal in the left and right multiplexers in a multiplexer unit hierarchy.

[0086] It should be noted that the information interaction, execution process and other contents between the modules / units of the above-mentioned device are based on the same concept as the method embodiment of the present application, and the technical effects brought about are the same as those of the method embodiment of the present application. The specific contents can refer to the description in the method embodiment shown in the above embodiment of the present application, and will not be repeated here. It should also be noted that the device embodiment described above is only schematic, and some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiment provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0087] In another aspect, the present application also provides a computer-readable storage medium, in which a program code is stored, and the program code is called by a processor to execute any of the above-mentioned methods for simplifying the logic of a multiplexer unit of an FPGA synthesis tool.

[0088] In another aspect, the present application also provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute any of the above-mentioned logic simplification methods of a multiplexer unit of an FPGA synthesis tool.

[0089] It should be noted that, for those of ordinary skill in the art, several improvements and modifications may be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, various features of the present disclosure described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A method for simplifying logic of a multiplexer unit of an FPGA synthesis tool, characterized in that: The method comprises: Traversing the logic units in the circuit netlist, determining the type of the logic unit, storing the mapping relationship between the output signal of the logic unit c and the logic unit c in the logic unit output signal mapping set, and storing the logic unit whose type is a multiplexer in the multiplexer unit set; Traversing each multiplexer unit in the set of multiplexer units, and performing basic logic simplification according to an input signal of each multiplexer unit; Merging branches with the same signal in a single-level structure of a multiplexer unit and merging branches with the same signal in the left and right multiplexers in the multiplexer unit hierarchical structure; Wherein, the input signal of the multiplexer unit includes an input A-end signal, an input B-end signal and an input S-end signal, and the performing basic logic simplification according to the input signal of each multiplexer unit includes: if the input S-end signal of the multiplexer unit is a constant signal 0, the output signal of the multiplexer unit is replaced by the input A-end signal of the multiplexer unit, and the multiplexer unit is deleted; if the input S-end signal of the multiplexer unit is a constant signal 1, the output signal of the multiplexer unit is replaced by the input B-end signal of the multiplexer unit, and the multiplexer unit is deleted; if the input A-end signal of the multiplexer unit is a constant signal 0 and the input B-end signal of the multiplexer unit is a constant signal 1, the output signal of the multiplexer unit is replaced by the input S-end signal of the multiplexer unit, and the multiplexer unit is deleted; The branches with the same signal in the single-level structure of the merged multiplexer unit include: obtaining a logic unit c1 whose output signal is the input A-end signal of the multiplexer unit from the logic unit output signal mapping set; if the type of the logic unit c1 is a multiplexer, and the input B-end signal of the logic unit c1 is the same as the input B-end signal of the multiplexer unit, then creating a new OR-type logic unit or1, and using the input S-end signal of the multiplexer unit and the input S-end signal of the logic unit c1 as the input signal of the logic unit or1; replacing the input S-end signal of the multiplexer unit with the output signal of the logic unit or1, and replacing the input A-end signal of the multiplexer unit with the input A-end signal of the logic unit c1.

2. The method for simplifying logic of a multiplexer unit of an FPGA synthesis tool according to claim 1, characterized in that: The basic logic simplification of the multiplexer unit also includes: If the input A terminal signal of the multiplexer unit is a constant signal 1 and the input B terminal signal of the multiplexer unit is a constant signal 0, the type of the multiplexer unit is changed to NOT, and the input A terminal signal of the multiplexer unit is replaced by the input S terminal signal; If the input A-end signal of the multiplexer unit is a constant signal 0 and the input B-end signal of the multiplexer unit is a constant signal 0, the output signal of the multiplexer unit is replaced by the constant signal 0, and the multiplexer unit is deleted; If the input A-end signal of the multiplexer unit is the constant signal 1 and the input B-end signal of the multiplexer unit is the constant signal 1, the output signal of the multiplexer unit is replaced by the constant signal 1 and the multiplexer unit is deleted; If the input A-end signal of the multiplexer unit is a constant signal 0 and the input B-end signal of the multiplexer unit is not a constant signal 0 or a constant signal 1, the type of the multiplexer unit is changed to AND, and the input A-end signal of the multiplexer unit is replaced by the input S-end signal; If the input B-end signal of the multiplexer unit is a constant signal 1 and the input A-end signal of the multiplexer unit is not a constant signal 0 or a constant signal 1, the type of the multiplexer unit is changed to OR, and the input B-end signal of the multiplexer unit is replaced by the input S-end signal; If the input A-end signal of the multiplexer unit and the input B-end signal of the multiplexer unit are the same, and the input A-end signal of the multiplexer unit and the input B-end signal of the multiplexer unit are not constant signals 0 or constant signals 1, then the output signal of the multiplexer unit is replaced by the input A-end signal of the multiplexer unit, and the multiplexer unit is deleted.

3. The method for simplifying logic of a multiplexer unit of an FPGA synthesis tool according to claim 1, characterized in that: The method further comprises, Obtaining a logic unit c1 whose output signal is a signal at the input A end of a multiplexer unit from the logic unit output signal mapping set; if the type of the logic unit c1 is a multiplexer, and the input A end signal of the logic unit c1 is the same as the input B end signal of the multiplexer unit, then creating a new logic unit or1 of OR type, and using the input S end signal of the multiplexer unit and the inverted signal of the input S end signal of the logic unit c1 as the input signal of the logic unit or1; The input S-end signal of the multiplexer unit is replaced by the output signal of the logic unit or1, and the input A-end signal of the multiplexer unit is replaced by the input B-end signal of the logic unit c1.

4. The method for simplifying logic of a multiplexer unit of an FPGA synthesis tool according to claim 1, characterized in that: The method further comprises, Obtain a logic unit c2 whose output signal is a signal at the B-end of a multiplexer unit input from the logic unit output signal mapping set; if the type of the logic unit c2 is a multiplexer, and the signal at the A-end of the input of the logic unit c2 is the same as the signal at the A-end of the input of the multiplexer unit, then create a new logic unit and1 of AND type, and use the signal at the S-end of the input of the multiplexer unit and the signal at the S-end of the input of the logic unit c2 as the input signal of the logic unit and1; The input S-end signal of the multiplexer unit is replaced by the output signal of the logic unit and1, and the input B-end signal of the multiplexer unit is replaced by the input B-end signal of the logic unit c2.

5. A method for simplifying logic of a multiplexer unit of an FPGA synthesis tool according to any one of claims 1 or 4, characterized in that: The method further comprises, Obtain a logic unit c2 whose output signal is a signal at the input B end of a multiplexer unit from the logic unit output signal mapping set; if the type of the logic unit c2 is a multiplexer, and the input B end signal of the logic unit c2 is the same as the input A end signal of the multiplexer unit, then create a new logic unit and1 of AND type, and use the input S end signal of the multiplexer unit and the inverted signal of the input S end signal of the logic unit c2 as the input signal of the logic unit and1; The input S-end signal of the multiplexer unit is replaced by the output signal of the logic unit and1, and the input B-end signal of the multiplexer unit is replaced by the input A-end signal of the logic unit c2.

6. The method for simplifying logic of a multiplexer unit of an FPGA synthesis tool according to claim 1, characterized in that: The merging of the branches having the same signal of the left and right multiplexers in the multiplexer unit hierarchy structure includes: Obtain from the logic unit output signal mapping set a logic unit c1 whose output signal is the same as the input A terminal signal of the multiplexer unit c, and a logic unit c2 whose output signal is the same as the input B terminal signal of the multiplexer unit c; If the types of the logic unit c1 and the logic unit c2 are both multiplexers, and the logic unit c1 and the logic unit c2 have at least two branches of the same signal, the branches of the same signal of the logic unit c1 and the logic unit c2 are merged.

7. The method for simplifying logic of a multiplexer unit of an FPGA synthesis tool according to claim 6, characterized in that: The method further comprises, If the input S-end signal of the logic unit c1 is the same as the input S-end signal of the logic unit c2, and the input A-end signal of the logic unit c1 is the same as the input A-end signal of the logic unit c2, then the input S-end signal of the multiplexer unit c is replaced by the input S-end signal of the logic unit c1, and the input A-end signal of the multiplexer unit is replaced by the input A-end signal of the logic unit c1; Create a new multiplexer unit c3, replace the input S-end signal of the multiplexer unit c3 with the input S-end signal of the multiplexer unit c, replace the input A-end signal of the multiplexer unit c3 with the input B-end signal of the logic unit c1, replace the input B-end signal of the multiplexer unit c3 with the input B-end signal of the logic unit c2, and modify the input B-end signal of the multiplexer unit c to the output signal of the multiplexer unit c3.

8. A method for simplifying logic of a multiplexer unit of an FPGA synthesis tool according to any one of claims 6 or 7, characterized in that: The method further comprises, If the input S-end signal of the logic unit c1 is the same as the input S-end signal of the logic unit c2, and the input B-end signal of the logic unit c1 is the same as the input B-end signal of the logic unit c2, then the input S-end signal of the multiplexer unit c is replaced by the input S-end signal of the logic unit c1, and the input B-end signal of the multiplexer unit is replaced by the input B-end signal of the logic unit c1; Create a new multiplexer unit c3, replace the input S-end signal of the multiplexer unit c3 with the input S-end signal of the multiplexer unit c, replace the input A-end signal of the multiplexer unit c3 with the input A-end signal of the logic unit c1, replace the input B-end signal of the multiplexer unit c3 with the input A-end signal of the logic unit c2, and modify the input A-end signal of the multiplexer unit c to the output signal of the multiplexer unit c3.

9. A logic simplification device for a multiplexer unit of an FPGA synthesis tool, characterized in that: The device is used to execute the logic simplification method of the multiplexer unit of the FPGA synthesis tool according to any one of claims 1 to 8, and the device comprises: An acquisition module, configured to traverse the logic units in the circuit netlist, determine the type of the logic unit, store the mapping relationship between the output signal of the logic unit c and the logic unit c in a logic unit output signal mapping set, and store the logic unit whose type is a multiplexer in a multiplexer unit set; A logic simplification module, used for traversing each multiplexer unit in the multiplexer unit set, and performing basic logic simplification according to an input signal of each multiplexer unit; A merging module, used to merge branches with the same signal in a single-level structure of a multiplexer unit and to merge branches with the same signal in the left and right multiplexers in the hierarchical structure of the multiplexer unit; wherein the input signal of the multiplexer unit includes an input A-end signal, an input B-end signal and an input S-end signal, and the logic simplification module is used to perform basic logic simplification according to the input signal of each multiplexer unit, including: the logic simplification module is used to merge the multiplexer if the input S-end signal of the multiplexer unit is a constant signal 0 The output signal of the multiplexer unit is replaced by the input A-end signal of the multiplexer unit, and the multiplexer unit is deleted; if the input S-end signal of the multiplexer unit is a constant signal 1, the output signal of the multiplexer unit is replaced by the input B-end signal of the multiplexer unit, and the multiplexer unit is deleted; if the input A-end signal of the multiplexer unit is a constant signal 0 and the input B-end signal of the multiplexer unit is a constant signal 1, the output signal of the multiplexer unit is replaced by the input S-end signal of the multiplexer unit, and the multiplexer unit is deleted; The merging module is used to merge branches with the same signal in a single-level structure of a multiplexer unit, including: the merging module is used to obtain a logic unit c1 whose output signal is a multiplexer unit input A-end signal from the logic unit output signal mapping set; if the type of the logic unit c1 is a multiplexer, and the input B-end signal of the logic unit c1 is the same as the input B-end signal of the multiplexer unit, then a new OR-type logic unit or1 is created, and the input S-end signal of the multiplexer unit and the input S-end signal of the logic unit c1 are used as the input signal of the logic unit or1; the input S-end signal of the multiplexer unit is replaced by the output signal of the logic unit or1, and the input A-end signal of the multiplexer unit is replaced by the input A-end signal of the logic unit c1.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the logic simplification method of the multiplexer unit of the FPGA synthesis tool as described in any one of claims 1-8.

11. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the logic simplification method of the multiplexer unit of the FPGA synthesis tool as described in any one of claims 1-8.

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