Table fundamental frequency domain behavior model parameter extraction method and system

Abstract

The invention belongs to but not limited to the technical field of power amplifier chips, and particularly relates to a table fundamental frequency domain behavior model parameter extraction method and system, and the method comprises the steps: 1, testing the output characteristics of a chip under different input powers; 2, P2D model parameters of the power amplifier chip are extracted; 3, extracting a bias current and third-order intermodulation product model file; step 4, dynamic calculation of third-order intermodulation and power additional efficiency is realized; and 5, performing comparison verification on power amplifier chip P2D model simulation and actual measurement. Based on a table fundamental frequency domain P2D behavior model, the invention provides a behavior model parameter extraction method capable of representing the power additional efficiency and the third-order intermodulation, and by combining the actual measurement data of the dynamic drain current in the chip, the output power of the third-order intermodulation product of the chip and the simulation result of the fundamental wave output power of the chip, the power additional efficiency and the third-order intermodulation of the chip can be represented. A dynamic calculation method of the power additional efficiency and the third-order intermodulation is broken through, and simulation prediction of the chip power additional efficiency and the third-order intermodulation of the table fundamental frequency domain P2D model is achieved.

Description

Technical Field

[0001] The present invention belongs to but is not limited to the technical field of power amplifier chips, and in particular relates to a method and system for extracting table base frequency domain behavior model parameters. Background Art

[0002] Microwave power amplifier (PA) chips are important components of weapons and wireless communication systems. As the core device of the RF transceiver front-end system, their power characteristics and linearity play a decisive role in the performance of the whole machine. Therefore, how to establish a high-precision PA chip model, accurately characterize the RF power and third-order intermodulation characteristics of the PA chip, and then provide guidance for the high-precision simulation design of the overall system link is crucial to the development of high-performance RF front-end systems. RF PA chip models can be roughly divided into two categories according to their modeling methods: behavioral models and equivalent circuit models. Among them, the equivalent circuit model needs to first obtain the equivalent circuit model of the transistor inside the chip and the electromagnetic data of the passive matching circuit, and the parameter extraction process is complicated. As a black box model, the behavioral model only focuses on the mapping relationship between the chip input and output signals. It does not need to understand the working mechanism of the device or circuit and its interaction relationship. The model can be quickly obtained by combining a specific test system. In addition, in terms of model accuracy and convergence, the behavioral model has more advantages, so it is widely used in the modeling of various RF PA chips.

[0003] Behavioral models can be divided into time domain behavioral models that focus on the characterization of the input / output time domain waveforms of the communication system and frequency domain behavioral models that focus on describing port mismatch and high-order harmonic characteristics. Research on RF power amplifier chips mainly focuses on frequency domain behavioral models. Frequency domain behavioral models mainly include X-parameter models (Keysight, USA), Cardiff models (Focus, Canada and Cardiff University, UK), tabular fundamental frequency domain P2D models, and simplified polynomial S2D ​​models (Keysight, USA). Among them, the X-parameter model and the Cardiff model, as extensions of the classic S-parameter model, can characterize frequency domain nonlinear characteristics such as fundamental and high-order harmonic outputs. However, the parameter extraction of these two types of models requires the combination of dedicated test equipment, the modeling cost is high, and the parameter extraction process is complicated, so it is difficult to promote them in the modeling of RF power amplifier chips for actual engineering applications. In addition, the S2D model only requires S parameters at different input powers to complete the model parameter extraction, but does not support the accurate characterization of the nonlinear characteristics of the power amplifier under deep compression state, and does not have the simulation capability of power added efficiency. Different from the S2D behavior model, the tabular fundamental frequency domain P2D behavior model takes into account the incident and reflection characteristics of all ports under different input powers. Therefore, the P2D model can further simulate the fundamental amplitude phase of the power amplifier chip under deep compression, and has the ability to characterize output characteristics such as S parameters and noise. In terms of parameter extraction, the P2D model can complete the modeling of the power amplifier chip by combining the common vector network analyzer in the microwave and millimeter wave laboratory to measure the actual measured data of S parameters under different input powers. Therefore, it is an ideal solution for realizing fast behavior modeling of low-cost power amplifier chips. However, the traditional P2D model only considers the nonlinear relationship between the input and output fundamental frequency domain signals of the power amplifier chip, and does not have the ability to solve the intermodulation components of the power amplifier chip and the DC components at the static bias power supply, resulting in the model being unable to simulate the power added efficiency and third-order intermodulation indicators of the power amplifier chip. This problem is also one of the difficulties in the behavioral modeling of other RF chips. It is urgent to break through the P2D model parameter extraction method that can accurately characterize the third-order intermodulation and power added efficiency, and improve its characterization ability and accuracy in the modeling of nonlinear RF power amplifier chips.

[0004] In response to this problem, several behavioral modeling teams at home and abroad have carried out relevant research work. In 2009, H.Qi et al., Qi Hao from the Tasker team of Cardiff University in the UK proposed an improved Cardiff model that uses polynomial equations to describe the output characteristics of the device under test, and uses polynomial equations to simulate the harmonics of the device. In 2019, Bernhard Pichler et al. from the Vienna University of Technology compared the accuracy of the X-parameters and QPHD models under strong nonlinearity and load mismatch conditions under large signal excitation, and used the QPHD model to simulate the power added efficiency and third-order intermodulation during load pulling. In 2022, Ehsan M Azad et al. from the Tasker team of Cardiff University in the UK proposed a new mathematical formula for the Cardiff nonlinear behavioral model, and used the polynomial fitting method to expand the formula of the Cardiff nonlinear behavioral model, introducing the DC bias voltage (drain and gate) into the model to achieve the simulation of the power added efficiency. However, the above methods are difficult to test, require special instruments and have complex data processing, making it difficult to directly migrate and apply these methods to the tabular baseband P2D model. Therefore, how to further expand the simulation capabilities of power added efficiency and third-order intermodulation based on traditional modeling methods is an urgent problem to be solved in chip behavior modeling based on the tabular baseband P2D model.

[0005] In view of the above analysis, the technical problems that need to be solved urgently in the existing technology are: the existing methods are difficult to test, require special instruments and the data processing is relatively complex, and it is difficult to directly migrate and apply these methods to the table baseband domain P2D model. Therefore, how to further expand its power added efficiency and third-order intermodulation simulation capabilities based on the traditional modeling method is an urgent problem to be solved in chip behavior modeling based on the table baseband domain P2D model. Summary of the invention

[0006] In view of the problems existing in the prior art, the present invention provides a method and system for extracting table baseband frequency domain behavior model parameters, and improves the P2D model so that the improved P2D model can simulate power added efficiency and third-order intermodulation.

[0007] The present invention is implemented as follows: a method for extracting parameters of a table base frequency domain behavior model, comprising:

[0008] Step 1: Test chip output characteristics under different input powers;

[0009] Step 2: Extract the P2D model parameters of the power amplifier chip;

[0010] Step 3: Extract bias current and third-order intermodulation product model files;

[0011] Step 4: Dynamic calculation and implementation of third-order intermodulation and power added efficiency;

[0012] Step 5: Compare and verify the power amplifier chip P2D model simulation and actual measurement.

[0013] Further, step 1 specifically includes: performing vector calibration and power calibration on the vector network analyzer to ensure the accuracy of the excitation power Pin on the test reference plane of the vector network analyzer; the power range of the excitation power Pin should cover the input power of the saturation area of ​​the device under test, and save the calibration files at different excitation powers;

[0014] Scan the excitation power Pin of the vector network analyzer (for example, -15dBm to 30dBm), call the calibration file at the corresponding power to calibrate the vector network analyzer, read the DC voltage and current data on the DC source at different excitation powers and different frequencies (for example, 37GHz to 43GHz) (obtained by checking the readings of the DC source) and the S parameters and third-order intermodulation product power at different input powers on the vector network analyzer, and record them.

[0015] Further, step 2 specifically includes:

[0016] The parameter extraction of the P2D model in the table base frequency domain requires the S parameter files under different excitation powers obtained by the test, and the S parameters under the minimum excitation power are selected and placed in the front data block of the P2D model file as a small signal parameter module. The S parameters under other excitation powers are selected and placed in the AC data block of the P2D model file as a large signal parameter module, and the magnitude of the excitation power of the input and output ports is indicated;

[0017] The bias current data and the third-order intermodulation product data are saved as mdf type files, the input variable is the input power pin, and the output results are the bias current and the third-order intermodulation product power respectively; finally, the P2D model file and the mdf file containing the efficiency and third-order intermodulation product (IM3) information are respectively imported into the commercial simulation software through the DAC control in the commercial simulation software.

[0018] Further, step 3 specifically includes: writing the bias current information and third-order intermodulation product information measured in step 1 into the model file, the bias current lookup table file header is temperature and frequency, the first column of data is input power, and the second column of data is bias current information; the third-order intermodulation product lookup table file header is temperature and frequency, the first column of data is input power, and the second column of data is third-order intermodulation product power.

[0019] Further, step 4 specifically includes:

[0020] The P2D model simulation schematic diagram is constructed in the commercial SPICE simulation software, the output end is connected to a 50 ohm load, and the model input and output voltage and current wave characteristics are calculated based on the harmonic balance simulator in the software; the obtained results can be used to further obtain the simulation results of the fundamental output power Pout, fundamental gain Gain, third-order intermodulation IMD3 and power added efficiency PAE corresponding to the chip; wherein, the calculation of Pout can be based on the fundamental voltage and current components at the load end of the chip, as shown in formula (1); Gain is calculated based on the Pout calculated by formula (1) combined with the input power Pin, using formula (2); the calculation of the third-order intermodulation IMD3 requires the combination of Pout and the power of the third-order intermodulation product IM3 obtained by looking up the table, as shown in formula (3); the calculation of PAE requires the combination of Pout, Pin and the bias voltage U corresponding to Pin obtained by looking up the table d and bias current I d The calculation is as shown in formula (4);

[0021] Pout=0.5*real(V load [1]*conj(I load [1]))(1)

[0022] Gain=Pout-Pin(2)

[0023] IMD3=IM3-Pout(3)

[0024]

[0025] Further, step 5 specifically includes: since the P2D model file and the lookup table file store discrete points, the points not covered by the simulation can be interpolated in combination with cubic splines, calling the model data packet can simulate the third-order intermodulation and power added efficiency, and interpolation can be performed between the data in the model file, and a certain amount of internal extrapolation is performed. The Pout interpolation method uses linear interpolation, and the third-order intermodulation and power added efficiency use cubic spline interpolation.

[0026] Another object of the present invention is to provide a table base frequency domain behavior model parameter extraction system for implementing the table base frequency domain behavior model parameter extraction method, comprising:

[0027] Output characteristic test module: chip output characteristic test under different input power;

[0028] Model parameter extraction module: P2D model parameter extraction of power amplifier chip;

[0029] Model file extraction module: bias current and third-order intermodulation product model file extraction;

[0030] Dynamic calculation module: dynamic calculation of third-order intermodulation and power added efficiency;

[0031] Comparison and verification module: comparison and verification of power amplifier chip P2D model simulation and actual measurement.

[0032] Another object of the present invention is to provide a computer device, the computer device includes a memory and a processor, the memory stores a computer program, when the computer program is executed by the processor, the processor executes the steps of the table base frequency domain behavior model parameter extraction method.

[0033] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to execute the steps of the method for extracting table base frequency domain behavior model parameters.

[0034] Another object of the present invention is to provide an information data processing terminal, which includes the table fundamental frequency domain behavior model parameter extraction system.

[0035] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0036] First, the traditional frequency domain behavioral model parameter extraction does not consider the bias current DC component and the third-order intermodulation product component, resulting in the model not having the power added efficiency and third-order intermodulation prediction capabilities, making it difficult to be used for RF power amplifier chip modeling. In response to this, the present invention proposes a behavioral model parameter extraction method that can characterize power added efficiency and third-order intermodulation based on the table baseband domain P2D behavioral model. By combining the measured data of the dynamic drain current in the chip, the chip third-order intermodulation product output power and the chip fundamental wave output power simulation results, a breakthrough is made in the dynamic calculation method of power added efficiency and third-order intermodulation, and the simulation prediction of chip power added efficiency and third-order intermodulation of the table baseband domain P2D model is realized.

[0037] Second, the technical solution of the present invention fills the technical gap in the industry at home and abroad:

[0038] The current table baseband domain P2D model cannot realize the simulation prediction of chip power added efficiency and third-order intermodulation. The present invention realizes the simulation prediction of power added efficiency and third-order intermodulation characteristics by adding current and third-order intermodulation information on the basis of the traditional table baseband domain P2D model, filling the gap in the field of behavioral models.

[0039] The technical solution of the present invention solves a technical problem that people have been eager to solve but have never succeeded in solving: power added efficiency and third-order intermodulation characteristics are key indicators of radio frequency chips. In actual engineering applications, it is necessary to simulate and predict their power added efficiency and third-order intermodulation characteristics, while the current table baseband domain P2D model cannot realize the simulation prediction of chip power added efficiency and third-order intermodulation. The present invention realizes the simulation prediction of power added efficiency and third-order intermodulation characteristics by adding current and third-order intermodulation information on the basis of the traditional table baseband domain P2D model. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a flow chart of a method for extracting table base frequency domain behavior model parameters provided by an embodiment of the present invention;

[0041] Figure 2 is a test principle diagram provided by an embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of a model file provided by an embodiment of the present invention;

[0043] Figure 4 It is a structural diagram of a table base frequency domain behavior model parameter extraction system provided by an embodiment of the present invention;

[0044] Figure 5 It is a schematic diagram of output power simulation and actual measurement results provided by an embodiment of the present invention;

[0045] Figure 6 is a schematic diagram of gain simulation and measured results provided by an embodiment of the present invention;

[0046] Figure 7 It is a schematic diagram of PAE simulation and measured results provided by an embodiment of the present invention;

[0047] Figure 8 It is a schematic diagram of IMD3 simulation and measured results provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] Example 1: Extraction of table-based frequency domain behavior model parameters of power amplifier chip

[0050] When designing high-frequency communication equipment, the nonlinear behavior of the power amplifier chip needs to be accurately modeled to optimize the overall performance of the system. By extracting the tabular baseband frequency domain behavioral model parameters of the power amplifier, the output characteristics of the chip can be accurately simulated, thereby improving design efficiency.

[0051] 1. Chip output characteristics test:

[0052] The power amplifier chip is tested using a vector network analyzer (VNA). First, the VNA is calibrated for vector and power to ensure the accuracy of the excitation power. The test range covers the saturation region of the chip, and the S parameters, DC voltage and current data, and third-order intermodulation product power are collected at different input powers.

[0053] 2. P2D model parameter extraction:

[0054] The S parameters at the minimum excitation power are used as small signal parameter modules, and the S parameters at other powers are used as large signal parameter modules, which are stored in the P2D model file. The bias current and third-order intermodulation product data are saved as mdf files and then imported through the DAC control in the commercial simulation software.

[0055] 3. Simulation and verification:

[0056] A simulation schematic was built in the commercial SPICE simulation software to simulate the P2D model. The fundamental output power Pout, gain Gain, third-order intermodulation IMD3 and power added efficiency PAE of the chip were calculated and compared with the measured data to ensure the accuracy of the model.

[0057] 4. Results:

[0058] Through simulation analysis and verification of measured data, the behavior of the power amplifier chip under different working conditions is determined, providing accurate model support for the optimized design of communication equipment.

[0059] Example 2: Extraction and optimization of behavioral model parameters of RF power amplifier

[0060] In RF circuit design, the nonlinear effect of the power amplifier has a huge impact on system performance. By accurately extracting the behavioral model parameters of the RF power amplifier, the performance of the device can be effectively predicted and the circuit design can be optimized.

[0061] step:

[0062] 1. Test of RF amplifier:

[0063] Use a vector network analyzer to test the RF power amplifier, covering the input power range from small signals to large signals. After ensuring the accuracy of the calibration, collect S parameters, DC voltage and current, and power data of third-order intermodulation products.

[0064] 2. Parameter extraction and model construction:

[0065] According to the test data, extract the parameters of the table base frequency domain P2D model. Put the small signal S parameters into the model's front data block, and put the S parameters at other powers into the AC data block. Save the bias current and third-order intermodulation product power data as mdf files and import them into the simulation software.

[0066] 3. Simulation and optimization:

[0067] The power amplifier is simulated using SPICE simulation software based on the harmonic balance simulator to calculate key parameters such as Pout, Gain, IMD3 and PAE. Based on the simulation results, the amplifier performance is optimized by adjusting the circuit design and bias conditions.

[0068] By comparing the simulation results with the measured data, the accuracy of the model was verified, and the design of the RF power amplifier was optimized accordingly, improving the overall performance and efficiency of the RF circuit.

[0069] In the table base frequency domain behavior model parameter extraction method, the output characteristics of the power amplifier chip at different input powers are first tested by a vector network analyzer (VNA). To ensure the accuracy of the test, the VNA needs to perform vector calibration and power calibration to ensure the accuracy of the excitation power Pin. During the test, the VNA gradually scans different excitation powers and collects the chip's S parameters, DC voltage and current data, and the power of the third-order intermodulation product at each power level. These data will serve as the basis for subsequent P2D model parameter extraction and provide accurate characterization of the chip at different power levels.

[0070] After completing the output characteristic test, the next step is to extract the parameters of the P2D model. By classifying the collected S parameter data according to the different excitation powers, the S parameters at the minimum excitation power are used for small signal analysis, while the S parameters at other powers are used for large signal analysis. These data are sorted and written into the P2D model file, stored in the pre-data block and the AC data block respectively. In addition, the information of the bias current and the third-order intermodulation product are also stored as mdf files for subsequent simulation. Through the DAC control in the commercial simulation software, these model files are imported into the commercial simulation software, laying the foundation for subsequent simulation analysis.

[0071] Next, the P2D model is simulated and analyzed in commercial simulation software. By building a simulation schematic and connecting a suitable load, the simulator calculates the input and output voltage and current characteristics of the chip based on the harmonic balance method. Through these characteristics, the fundamental output power Pout, gain Gain, third-order intermodulation IMD3, and power added efficiency PAE are further calculated. In the specific calculation process, Pout is determined by the fundamental voltage and current components at the load end of the chip, Gain is calculated by the ratio of Pout and Pin, IMD3 is calculated by combining Pout with the power of the third-order intermodulation product IM3 obtained by looking up the table, and PAE is calculated by the relationship between Pout, Pin, and bias voltage and current.

[0072] Since the data points in the model file and the lookup table file are discrete, the uncovered points in the simulation process need to be processed by interpolation methods. For the output power Pout, linear interpolation is used; for the third-order intermodulation and power added efficiency, cubic spline interpolation is used. This interpolation process ensures the continuity and accuracy of the simulation results. Finally, combined with these interpolation processes, the simulation results are compared and verified with the measured data to ensure the accuracy and reliability of the model. Through this precise model and simulation, the behavior of the chip can be effectively predicted, providing a scientific basis for design and optimization.

[0073] like Figure 1 As shown, the table base frequency domain behavior model parameter extraction method provided by the embodiment of the present invention includes:

[0074] Step 1: Test chip output characteristics at different input powers

[0075] Perform vector calibration and power calibration on the vector network analyzer to ensure the accuracy of the excitation power Pin on the vector network analyzer test reference plane. The power range of the excitation power Pin should cover the input power of the saturation area of ​​the device under test. Save the calibration files at different excitation powers.

[0076] Scan the excitation power Pin of the vector network analyzer (for example, -15dBm to 30dBm), call the calibration file at the corresponding power to calibrate the vector network analyzer, read the DC voltage and current data on the DC source at different excitation powers and different frequencies (for example, 37GHz to 43GHz) (obtained by checking the readings of the DC source) and the S parameters and third-order intermodulation product power at different input powers on the vector network analyzer, and record them.

[0077] Step 2: Extraction of P2D model parameters of power amplifier chip

[0078] The parameter extraction of the P2D model in the table base frequency domain requires the S parameter files under different excitation powers obtained from the test. The S parameters under the minimum excitation power are selected and placed in the front data block of the P2D model file as a small signal parameter module. The S parameters under other excitation powers are selected and placed in the AC data block of the P2D model file as a large signal parameter module, and the size of the excitation power of the input and output ports is indicated.

[0079] In addition, the bias current data and the third-order intermodulation product data are saved as mdf type files, the input variable is the input power pin, and the output results are the bias current and the third-order intermodulation product power. Finally, the P2D model file and the mdf file containing efficiency and third-order intermodulation product (IM3) information are imported through the DAC control in the commercial simulation software.

[0080] Step 3: Extract bias current and third-order intermodulation product model files

[0081] Write the bias current information and third-order intermodulation product information measured in step 1 into the model file. The header of the bias current lookup table file is temperature and frequency, the first column of data is input power, and the second column of data is bias current information; the header of the third-order intermodulation product lookup table file is temperature and frequency, the first column of data is input power, and the second column of data is third-order intermodulation product power.

[0082] Step 4: Dynamic calculation and implementation of third-order intermodulation and power added efficiency

[0083] The P2D model simulation schematic is constructed in the commercial SPICE simulation software, the output end is connected to a 50 ohm load, and the model input and output voltage and current wave characteristics are calculated based on the harmonic balance simulator in the software. The results obtained can be used to further obtain the simulation results of the fundamental output power Pout, fundamental gain Gain, third-order intermodulation IMD3 and power added efficiency PAE corresponding to the chip. Among them, the calculation of Pout can be based on the fundamental voltage and current components at the load end of the chip, as shown in formula (1). Gain is calculated based on the Pout calculated by formula (1) combined with the input power Pin, using formula (2). The calculation of the third-order intermodulation IMD3 requires the combination of Pout and the power of the third-order intermodulation product IM3 obtained by table lookup, as shown in formula (3). The calculation of PAE requires the combination of Pout, Pin and the bias voltage U corresponding to Pin obtained by table lookup. d and bias current I d The calculation is shown in formula (4).

[0084] Pout=0.5*real(V load [1]*conj(I load [1]))(1)

[0085] Gain=Pout-Pin(2)

[0086] IMD3=IM3-Pout(3)

[0087]

[0088] Step 5: Comparison and verification of the P2D model of the power amplifier chip

[0089] Since the P2D model file and the lookup table file store discrete points, the points not covered by the simulation can be interpolated with cubic splines. The model data package can be called to simulate the third-order intermodulation and power added efficiency, and interpolation can be performed between the data in the model file. The Pout interpolation method uses linear interpolation, and the third-order intermodulation and power added efficiency use cubic spline interpolation.

[0090] like Figure 4 As shown, the table base frequency domain behavior model parameter extraction system provided by the embodiment of the present invention includes:

[0091] Output characteristic test module: chip output characteristic test under different input power;

[0092] Model parameter extraction module: P2D model parameter extraction of power amplifier chip;

[0093] Model file extraction module: bias current and third-order intermodulation product model file extraction;

[0094] Dynamic calculation module: dynamic calculation of third-order intermodulation and power added efficiency;

[0095] Comparison and verification module: comparison and verification of power amplifier chip P2D model simulation and actual measurement.

[0096] 1) Output characteristics test module

[0097] The core task of this module is to test the output characteristics of the power amplifier chip under different input power conditions. A series of signals with different powers are input through the system, and the output characteristic data of the chip, including output power, gain and other related parameters, are recorded. These data will be used in the subsequent model parameter extraction process to ensure that the model can accurately reflect the output behavior of the actual chip.

[0098] 2) Model parameter extraction module

[0099] After obtaining the output characteristic data under different input powers, the system inputs these data into the model parameter extraction module. This module is mainly responsible for extracting the P2D (power to current) model parameters of the power amplifier chip. Through advanced algorithms and data processing technology, the various parameters required for the P2D model are extracted to ensure that the model can accurately describe the output characteristics of the chip under various input conditions.

[0100] 3) Model file extraction module

[0101] Next, the system will use the P2D model parameters generated by the model parameter extraction module to further extract the model files of bias current and third-order intermodulation products. These files contain the behavior characteristics of the power amplifier chip under different bias current conditions, as well as the output characteristics under third-order intermodulation distortion. These model files provide necessary data support for subsequent dynamic calculations and simulation verification.

[0102] 4) Dynamic calculation and comparison verification module

[0103] Finally, the system enters the dynamic calculation module and comparison verification module stages. The dynamic calculation module uses the extracted model file to dynamically calculate the third-order intermodulation distortion and power added efficiency to evaluate the performance of the chip in actual work. The comparison verification module compares and verifies the simulation results of the P2D model with the actual test results to ensure the accuracy and reliability of the model. Through this closed-loop verification, the system can continuously optimize the model parameters to make it closer to the actual chip behavior and provide reliable data support and performance prediction.

[0104] In order to verify the accuracy of the model, the present invention simulates the power, gain and power added efficiency of the chip model in commercial simulation software under the conditions of ambient temperature of 25°C, frequency range of 38GHz-43GHz, and input power of 18dBm, and the results are as follows: Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, the circles are the measured results and the solid lines are the model simulation results. The average errors of PAE, IMD3, output power and gain simulation and measurement at 25°C are shown in Table 1. The error is calculated using the mean absolute error within the frequency band, which is calculated as follows

[0105]

[0106] Table 1 Maximum error between simulation and measurement

[0107]

[0108]

[0109] The results show that at 25°C, the maximum errors of IMD3 simulation and measurement are within 0.2dBc, the maximum errors of PAE simulation and measurement are within 0.1%, the maximum error of output power is within 0.02dBm, and the maximum error of gain is within 0.02dB, indicating that the method proposed in this patent has high accuracy.

[0110] An application embodiment of the present invention provides a computer device, which includes a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor executes the steps of the method.

[0111] An application embodiment of the present invention provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor executes the steps of the method.

[0112] An application embodiment of the present invention provides an information data processing terminal, which includes a system.

[0113] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. It can be understood by a person of ordinary skill in the art that the above-mentioned devices and methods can be implemented using computer executable instructions and / or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on the carrier medium. The device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, and can also be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0114] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection scope of the present invention.

Claims

1. A method for extracting parameters of a table base frequency domain behavior model, characterized in that: include: Step 1: Test chip output characteristics under different input powers; Step 2: Extract the P2D model parameters of the power amplifier chip; Step 3: Extract bias current and third-order intermodulation product model files; Step 4: Dynamic calculation and implementation of third-order intermodulation and power added efficiency; Step 5: Compare and verify the power amplifier chip P2D model simulation and actual measurement.

2. The method for extracting table base frequency domain behavior model parameters as claimed in claim 1, characterized in that: Step 1 specifically includes: performing vector calibration and power calibration on the vector network analyzer to ensure the accuracy of the excitation power Pin on the test reference plane of the vector network analyzer; the power range of the excitation power Pin should cover the input power of the saturation area of ​​the device under test, and save the calibration files at different excitation powers; Scan the excitation power Pin of the vector network analyzer, call the calibration file under the corresponding power to calibrate the vector network analyzer, read the DC voltage and current data on the DC source under different excitation powers and different frequencies, and the S parameters and third-order intermodulation product power under different input powers on the vector network analyzer, and record them.

3. The method for extracting table base frequency domain behavior model parameters as claimed in claim 1, characterized in that: Step 2 specifically includes: The parameter extraction of the P2D model in the table base frequency domain requires the S parameter files under different excitation powers obtained by the test, and the S parameters under the minimum excitation power are selected and placed in the front data block of the P2D model file as a small signal parameter module. The S parameters under other excitation powers are selected and placed in the AC data block of the P2D model file as a large signal parameter module, and the magnitude of the excitation power of the input and output ports is indicated; The bias current data and the third-order intermodulation product data are saved as mdf type files, the input variable is the input power pin, and the output results are the bias current and the third-order intermodulation product power respectively; finally, the P2D model file and the mdf file containing the efficiency and third-order intermodulation product information are imported through the DAC control in the commercial simulation software respectively.

4. The method for extracting table base frequency domain behavior model parameters as claimed in claim 1, characterized in that: Step 3 specifically includes: writing the bias current information and third-order intermodulation product information measured in step 1 into the model file, the bias current lookup table file header is temperature and frequency, the first column of data is input power, and the second column of data is bias current information; the third-order intermodulation product lookup table file header is temperature and frequency, the first column of data is input power, and the second column of data is third-order intermodulation product power.

5. The method for extracting table base frequency domain behavior model parameters as claimed in claim 1, characterized in that: Step 4 specifically includes: The P2D model simulation schematic diagram is constructed in the commercial SPICE simulation software, the output end is connected to a 50 ohm load, and the model input and output voltage and current wave characteristics are calculated based on the harmonic balance simulator in the software; the obtained results can be used to further obtain the simulation results of the fundamental output power Pout, fundamental gain Gain, third-order intermodulation IMD3 and power added efficiency PAE corresponding to the chip; wherein, the calculation of Pout can be based on the fundamental voltage and current components at the load end of the chip, as shown in formula (1); Gain is calculated based on the Pout calculated by formula (1) combined with the input power Pin, using formula (2); the calculation of the third-order intermodulation IMD3 requires the combination of Pout and the power of the third-order intermodulation product IM3 obtained by looking up the table, as shown in formula (3); the calculation of PAE requires the combination of Pout, Pin and the bias voltage U corresponding to Pin obtained by looking up the table d and bias current I d The calculation is as shown in formula (4); Pout=0.5*real(V load [1]*conj(I load [1])) (1) Gain=Pout-Pin (2) IMD3=IM3-Pout (3) 6. The method for extracting table base frequency domain behavior model parameters as claimed in claim 1, characterized in that: Step 5 specifically includes: Since the P2D model file and the lookup table file store discrete points, the points not covered by the simulation can be interpolated in combination with cubic splines. The model data package can be called to simulate the third-order intermodulation and power added efficiency, and interpolation can be performed between the data in the model file to perform certain internal extrapolation. The Pout interpolation method uses linear interpolation, and the third-order intermodulation and power added efficiency use cubic spline interpolation.

7. A table base frequency domain behavior model parameter extraction system for implementing the table base frequency domain behavior model parameter extraction method according to any one of claims 1 to 6, characterized in that: include: Output characteristic test module: chip output characteristic test under different input power; Model parameter extraction module: P2D model parameter extraction of power amplifier chip; Model file extraction module: bias current and third-order intermodulation product model file extraction; Dynamic calculation module: dynamic calculation of third-order intermodulation and power added efficiency; Comparison and verification module: comparison and verification of power amplifier chip P2D model simulation and actual measurement.

8. A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the method for extracting table base frequency domain behavior model parameters as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to execute the steps of the method for extracting table base frequency domain behavior model parameters as claimed in any one of claims 1 to 6.

10. An information data processing terminal, comprising the table fundamental frequency domain behavior model parameter extraction system according to claim 7.

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