Methods, apparatus, and storage media for interconnect evaluation

Abstract

According to exemplary embodiments of this disclosure, methods, apparatus, and storage media for interconnect evaluation are provided. The method includes: acquiring an interconnect network corresponding to the circuit structure of a target chip, the interconnect network including multiple nodes and multiple interconnects connecting the multiple nodes; and determining a first interconnect lifetime for each of the multiple interconnects based on the steady-state stress of each of the multiple nodes. In this manner, the accuracy, reliability, and efficiency of chip lifetime prediction can be improved.

Description

Technical Field

[0001] Embodiments of this disclosure relate primarily to the field of integrated circuits, and more specifically, to methods, apparatus, and storage media for interconnect evaluation. Background Technology

[0002] Interconnects are a crucial component of very large-scale integrated circuit (VLSI) chips, connecting the external power supply to the core logic circuitry and transmitting energy and signals. Currently, copper is commonly used as the interconnect material in chip manufacturing processes. However, metal interconnects exhibit electromigration under long-term current driving, where metal atoms diffuse and accumulate towards the high-voltage side of the interconnect, leaving vacancies at the low-voltage side. When the accumulation or vacancies reach a certain level, short circuits or open circuits occur in the interconnect. Accumulated interconnect failures can lead to the failure of the entire chip. With the reduction of integrated circuit feature sizes and the increase of device density, interconnect sizes are also decreasing, making current chip electromigration assessment methods insufficient to meet the needs of chip design and manufacturing. Summary of the Invention

[0003] In a first aspect of this disclosure, a method for interconnect evaluation is provided. The method includes: obtaining an interconnect network corresponding to a circuit structure of a target chip, the interconnect network including multiple nodes and multiple interconnects connecting the multiple nodes; and determining a first interconnect lifetime for each of the multiple interconnects based on the steady-state stress of each of the multiple nodes.

[0004] In a second aspect of this disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein, which, when executed by the processor, cause the electronic device to perform a method according to a first aspect of this disclosure.

[0005] In a third aspect of this disclosure, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When executed by a processor, the computer program implements the method according to a first aspect of this disclosure.

[0006] As will be understood from the following description, according to embodiments of this disclosure, an interconnect network corresponding to the circuit structure of a target chip is obtained, the interconnect network including multiple nodes and multiple interconnects connecting the multiple nodes; and a first interconnect lifetime for each of the multiple interconnects is determined based on the steady-state stress of each of the multiple nodes. In this way, the interconnect lifetime can be determined using the physical steady-state stress of the nodes and the interconnect network of the chip, thereby improving the accuracy, reliability, and efficiency of chip lifetime estimation.

[0007] It should be understood that the content described in this summary section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0008] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0009] Figure 1 A schematic diagram of an example environment in which the various embodiments of this disclosure can be implemented is shown;

[0010] Figure 2 A flowchart of a method for interconnect evaluation according to some embodiments of the present disclosure is shown;

[0011] Figure 3 A schematic diagram illustrating an example of the connection method of nodes and interconnects according to some embodiments of the present disclosure is shown;

[0012] Figure 4 A flowchart illustrating an example of a method for determining interconnect lifetime according to some embodiments of the present disclosure is shown;

[0013] Figure 5 A schematic diagram illustrating an example of the percentage relationship between chip lifetime and sample number according to some embodiments of the present disclosure;

[0014] Figure 6 A schematic diagram illustrating an example of the relationship between chip lifetime and cumulative probability according to some embodiments of the present disclosure is shown;

[0015] Figure 7 A flowchart illustrating an example of a method for determining the lifetime of an interconnect segment according to some embodiments of the present disclosure; and

[0016] Figure 8 A block diagram of an electronic device in which one or more embodiments of the present disclosure may be implemented is shown. Detailed Implementation

[0017] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0018] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0019] As briefly mentioned above, with the reduction of integrated circuit feature size and the increase of device density, the size of interconnects also decreases, and current chip electromigration evaluation methods are no longer sufficient to meet the needs of chip design and manufacturing.

[0020] Traditional methods can calculate the lifetime of each interconnect segment in a chip's interconnect network and take the minimum lifetime as the final predicted lifetime of the entire chip. However, chip interconnects typically employ a redundant network structure to improve interconnect reliability. Even if a few interconnect segments fail, it will not cause the entire chip to fail.

[0021] Because the above-mentioned lifetime calculation scheme does not take into account the actual network structure of the interconnects, it makes overly conservative predictions about chip lifespan. This leads to repeated iterations in chip design to modify interconnect geometry parameters and increase the number of vias in order to achieve the desired chip lifespan. This increases design and manufacturing complexity and may even cause the chip design to fail final approval, affecting the tape-out schedule.

[0022] According to some traditional methods, there are interconnect lifetime calculation methods based on transient physical models, which estimate the interconnect lifetime by establishing a stress balance physical model within the interconnect and solving differential equations.

[0023] Although the above scheme takes into account the actual interconnect network structure, it requires solving differential equations, which has low computational efficiency and is difficult to meet the requirements of large-scale chip electromigration failure assessment.

[0024] Therefore, embodiments of this disclosure propose a method for evaluating electromigration failure of chip interconnects. According to embodiments of this disclosure, an interconnect network corresponding to the circuit structure of a target chip is obtained. The interconnect network includes multiple nodes and multiple interconnects of the multiple nodes. Further, based on the steady-state stress of each of the multiple nodes, a first interconnect lifetime is determined for each of the multiple interconnects.

[0025] According to embodiments of this disclosure, when determining the interconnect lifetime, the interconnect network corresponding to the circuit structure of the target chip is considered, making the predicted interconnect closer to the actual result. At the same time, the steady-state stress on the nodes in the interconnect network is also considered, which avoids solving differential equations, thereby improving the accuracy, reliability and efficiency of interconnect lifetime prediction.

[0026] The following will describe in detail various example implementations of this scheme with reference to the accompanying drawings.

[0027] First see Figure 1 The illustration shows a schematic diagram of an example environment 100 in which various embodiments of the present disclosure can be implemented. The example environment 100 may generally include an electronic device 110.

[0028] like Figure 1 As shown, the electronic device 110 receives the interconnect network file 131 of the chip to be processed 130 as input. In some embodiments, the interconnect network file 131 may be an interconnect network netlist file or an interconnect network layout file (GDS file).

[0029] In some embodiments, the electronic device 110 can also interact with a client (not shown). For example, the electronic device 110 can receive input messages from the client and output feedback messages to the client. In some embodiments, the input messages from the client may specify the number of chips, the interconnect network file 131 of the chips, etc. The electronic device 110 can analyze the number of chips, the interconnect network file 131 of the chips, etc. specified in the input messages, for example, performing simulation calculations based on the interconnect network of the chips to determine the chip lifetime 140.

[0030] In some embodiments, an external power supply 120 can power the chip 130 to be processed during the chip lifetime 140 of the electronic device 110.

[0031] In example environment 100, electronic device 110 can be any type of computing-capable device, including terminal devices or server devices. Terminal devices can be any type of mobile terminal, fixed terminal, or portable terminal, including mobile phones, desktop computers, laptop computers, notebook computers, netbook computers, tablet computers, media computers, multimedia tablets, personal communication system (PCS) devices, personal navigation devices, personal digital assistants (PDAs), audio / video players, digital cameras / camcorders, positioning devices, television receivers, radio receivers, e-book devices, gaming devices, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. Server devices can include, for example, computing systems / servers, such as mainframes, edge computing nodes, computing devices in cloud environments, and so on.

[0032] It should be understood that the structure and function of environment 100 are described for illustrative purposes only and do not imply any limitation on the scope of this disclosure. Exemplary embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings.

[0033] Figure 2 A flowchart of a method 200 for interconnect evaluation according to some embodiments of the present disclosure is shown. In some embodiments, method 200 may be performed by, for example... Figure 1 The illustrated electronic device 110 performs this action. It should be understood that method 200 may also include additional boxes not shown and / or some (or some) of the boxes shown may be omitted, and the scope of this disclosure is not limited in this respect.

[0034] In block 210, electronic device 110 acquires an interconnect network corresponding to the circuit structure of the target chip. The interconnect network includes multiple nodes and multiple interconnects connecting the multiple nodes, with the multiple nodes indicating predetermined types of contacts or endpoints in the circuit structure.

[0035] In some embodiments, the electronic device 110 may acquire an interconnect network file representing the circuit structure of a target chip, such as an interconnect network netlist file or an interconnect network layout file. The electronic device 110 may then generate an interconnect network corresponding to the circuit structure of the target chip based on the interconnect network file.

[0036] For example, the top and bottom ends of vias, contact points connecting to external power supply 120, and contact points connecting to the core circuit layer of the chip can be equated to nodes in the interconnect network netlist file or interconnect network layout file. The resistance values ​​of the interconnects between nodes can be equated to the resistance in the interconnect network. The external power supply 120 can be considered as the power source in the interconnect network, connected to the interconnect network through nodes connected to the external power supply 120. The core logic layer of the chip can be simplified as an equivalent current source, connected to the interconnect network through nodes connecting the core logic circuit layer. Thus, an interconnect network corresponding to the chip circuit structure can be obtained.

[0037] In some embodiments, the chip is typically a multi-layered stacked structure, and the electronic device 110 can, based on the chip's hierarchical structure, divide the interconnect network into one or more interconnect networks corresponding to each layer. Furthermore, the electronic device 110 can further divide the interconnect network corresponding to each layer based on the circuit structure of each layer in the chip to obtain one or more sub-interconnect networks. In this document, "sub-interconnect network" is sometimes also referred to as "interconnect tree".

[0038] In some embodiments, the electronic device 110 may further subdivide the interconnect network corresponding to each layer using a breadth-first search approach. Alternatively or additionally, the interconnect network may be represented in the form of a graph structure; for example, nodes in the interconnect network may be represented as nodes in a graph structure, and interconnects in the interconnect network may be represented as edges in a graph structure. Correspondingly, the interconnect tree may also be represented in the form of a graph structure.

[0039] In the embodiments of this disclosure, there are no common nodes between different interconnect trees, and when the interconnect tree is represented in the form of a graph structure, the interconnect tree can be a connected graph.

[0040] In some embodiments, the electronic device 110 may use a random number generator to randomly generate a random number for each interconnect in a target chip within a predetermined numerical range, as a random sample of the target chip, i.e., the number of generated random numbers is the same as the number of interconnects in the target chip. Alternatively or additionally, the predetermined numerical range may be 0 to 1, and the random numbers may be generated uniformly within the numerical range of 0 to 1.

[0041] It should be noted that the method for determining the number of random samples will be introduced below, and will not be repeated here.

[0042] In box 220, electronic device 110 determines the first interconnect lifetime of each of the multiple interconnects based on the steady-state stress of each of the multiple nodes.

[0043] It should be understood that, since there are multiple nodes and multiple interconnects connecting these nodes in an interconnect network, and each node can be connected to one or more interconnects, the steady-state stress at each node can include compressive stress and tensile stress. Because compressive and tensile stresses have different directions, positive and negative signs can be used to represent the directions of tensile and compressive stresses respectively. For example, in this paper, positive steady-state stress is treated as tensile stress, and negative steady-state stress is treated as compressive stress.

[0044] Next, we will introduce how to determine the steady-state stress of a node in an interconnect network. (See also...) Figure 3 , Figure 3 An example of the connection method of nodes and interconnects according to some embodiments of this disclosure is shown. It should be understood that the steady-state stress at other nodes is determined in the same way as the steady-state stress at this node.

[0045] like Figure 3 As shown, interconnects 320, 330 and 340 are connected to node 310. Electronic device 110 can determine the steady-state stress at node 310 based on the voltage value at node 310 and the voltage values ​​at the nodes at both ends of interconnects 320, 330 and 340.

[0046] For example, the steady-state stress at a node in electronic device 110 can be determined by the following formula:

[0047]

[0048] in, For nodes The stress value at that point, The equivalent charge number of the interconnect. The charge of a single electron. The single-atom volume of the interconnect. Indicates the presence of nodes interconnect tree All interconnecting segments in , and Interconnection segments The cross-sectional area and length, and Interconnection segments The voltage values ​​at both ends, For nodes The voltage value at that point. It should be understood that, apart from the voltage value, the parameters in the above formula can be calibrated experimentally.

[0049] In some embodiments, the voltage value at each node in the interconnect network can be determined using nodal analysis, modified nodal analysis, or similar methods. Of course, other suitable methods can also be used to determine the voltage at the nodes, and the embodiments disclosed herein are not limiting.

[0050] Thus, the electronic device 110 can determine the voltage values ​​of multiple nodes in the interconnection network, and based on the voltage values ​​of multiple nodes, determine the steady-state stress of each node.

[0051] In the embodiments of this disclosure, determining the first interconnect lifetime can be divided into two cases: the case where there are failed interconnects in the interconnect network and the case where there are no failed interconnects in the interconnect network.

[0052] Next, we will first describe how electronic device 110 determines the first interconnect lifetime of an interconnect in the event of a failed interconnect in an interconnect network. See [link to documentation]. Figure 4 , Figure 4 An example of a method 400 for determining interconnect lifetime according to some embodiments of the present disclosure is shown. In some embodiments, method 400 may be provided by, for example Figure 1 The electronic device 110 shown is performing this action.

[0053] In box 410, electronic device 110 may update the interconnect network based on the failed interconnect network in response to determining that a failed interconnect network exists in the interconnect network.

[0054] Interconnects undergo electromigration under long-term current driving, where metal atoms diffuse and accumulate towards the high-voltage end of the interconnect, leaving vacancies at the low-voltage end. When the accumulation or vacancies reach a certain level, it will cause a short circuit or open circuit in the interconnect. A failed interconnect is one that has a short circuit or open circuit. Alternatively, the interconnect with the shortest lifespan among all interconnects in the interconnect network can be considered a failed interconnect.

[0055] In some embodiments, the electronic device 110 can remove failed interconnects from the interconnect network and update the interconnect network after removing the failed interconnects based on the circuit structure of the chip.

[0056] In block 420, electronic device 110 can determine the steady-state stress of each of the multiple nodes in the updated interconnect network based on the first voltage values ​​of each of the multiple nodes in the updated interconnect network.

[0057] It should be understood that the way electronic device 110 determines the first voltage value of each of the multiple nodes in the updated interconnect network and the steady-state stress of each of the multiple nodes in the updated interconnect network is the same as the way it determines the voltage value and steady-state stress at a single node, and will not be repeated here.

[0058] In box 430, electronic device 110 can determine a first average interconnect lifetime for each of the multiple interconnects in the updated interconnect network based on a first current value for each of the multiple interconnects in the updated interconnect network.

[0059] In some embodiments, the first current value of each of the multiple interconnects in the updated interconnect network can also be determined using nodal analysis, modified nodal analysis, or the like. Of course, other suitable methods can also be used to determine the current value at the interconnect, and the embodiments of this disclosure are not limiting.

[0060] Taking the determination of the first average interconnect lifetime of an interconnect as an example, electronic device 110 can determine the first average interconnect lifetime of the interconnect using the following formula:

[0061]

[0062] in, The mean-time-to-failure value of the interconnect. The cross-sectional area of ​​each interconnect segment to be evaluated. and These are the calibration parameters obtained from experimental data. The current density on the interconnect, The activation energy for electromigration of interconnects, Boltzmann's constant, This refers to the ambient temperature of the interconnects during chip operation. It should be understood that, apart from the current density on the interconnects, the parameters in the above formula can be calibrated experimentally.

[0063] In some embodiments, the current density on the interconnect can be determined based on the current value on the interconnect and the cross-sectional area of ​​the interconnect.

[0064] In box 440, electronic device 110 can determine the first interconnect lifetime of each of the multiple interconnects in the updated interconnect network based on steady-state stress, a first average interconnect lifetime, a second interconnect lifetime, and the lifetime of the failed interconnect.

[0065] Here, the second interconnect lifetime indicates the lifetime of multiple interconnects in the interconnect network before the update.

[0066] In some embodiments, the electronic device 110 may determine the lifetime of the failed interconnect as the minimum lifetime among the second interconnect lifetimes of each of the plurality of interconnects in the previous interconnect network.

[0067] In some embodiments, determining the first interconnect lifetime of each of a plurality of interconnects in an updated interconnect network may include: 1) In response to determining that the steady-state stress is greater than a steady-state stress threshold, the electronic device 110 determines the first interconnect lifetime of a plurality of interconnects in the updated interconnect network based on the lifetime of the failed interconnect, the second interconnect lifetime, and the first average interconnect lifetime.

[0068] For example, in this case, the electronic device 110 can determine the lifetime of the first interconnect using the following formula:

[0069]

[0070]

[0071]

[0072] Among them, indicators on variables Represents the existence of interconnected networks A failed interconnect segment, indicator under variable. Represents interconnection. For interconnects Existing in interconnected networks The time-to-failure lifespan of a single failed interconnect segment. For when the first one appears in the interconnected network The time of a failed interconnect, For interconnects Existing in interconnected networks The absolute value of tensile stress in the steady-state stress at the two ends of a failed interconnect segment. This is the absolute value of the tensile stress threshold. Interconnections generated for the random number generator random numbers, The lifetime of the interconnect follows a log-normal distribution with log variance. The current density on the interconnect, The activation energy for electromigration of interconnects, Boltzmann's constant, The temperature of the interconnect. A random sample from the target chip corresponds to a set of random numbers, the number of which is the same as the number of interconnect segments in the target chip.

[0073] Additionally, or alternatively, in some embodiments, determining the first interconnect lifetime of each of the plurality of interconnects in the updated interconnect network may include: 2) In response to determining that the steady-state stress is less than or equal to a steady-state stress threshold, the electronic device 110 determines the first interconnect lifetime of the plurality of interconnects in the updated interconnect network based on the lifetime of the failed interconnect and the second interconnect lifetime.

[0074] For example, in this case, the electronic device 110 can determine the lifetime of the first interconnect using the following formula:

[0075]

[0076]

[0077]

[0078] Among them, indicators on variables Represents the existence of interconnected networks A failed interconnect segment, indicator under variable. Represents interconnection. For interconnects Existing in interconnected networks The time-to-failure lifespan of a single failed interconnect segment. For when the first one appears in the interconnected network The time of a failed interconnect, For interconnects Existing in interconnected networks The absolute value of tensile stress in the steady-state stress at the two ends of a failed interconnect segment. This is the absolute value of the tensile stress threshold. Interconnections generated for the random number generator random numbers, The lifetime of the interconnect follows a log-normal distribution with log variance. The current density on the interconnect, The activation energy for electromigration of interconnects, Boltzmann's constant, The temperature of the interconnect. A random sample from the target chip corresponds to a set of random numbers, the number of which is the same as the number of interconnect segments in the target chip.

[0079] The above examples illustrate two methods (1) and (2) for the electronic device 110 to determine the first interconnect lifetime of each of multiple interconnects in an updated interconnect network. In some embodiments, either of the two methods or a combination of the two methods can be selected to determine the first interconnect lifetime. It should be understood that when determining the steady-state stress and steady-state stress threshold at each node, the above refers to determining whether there is a case where the absolute value of the steady-state stress of the interconnect is greater than the absolute value of the steady-state stress threshold, i.e., whether there exists a positive integer p such that... Thus determine The calculation formula is either the formula in 1) or the formula in 2), where the value of k can be 0 to the total number of failed interconnects in the chip when the chip finally fails.

[0080] In some embodiments, the electronic device 110 may determine the failed interconnect in the updated interconnect network based on the first interconnect lifetime of a plurality of interconnects in the updated interconnect network. For example, the electronic device 110 may determine the lifetime of the failed interconnect as the minimum lifetime value among the first interconnect lifetimes of a plurality of interconnects in the updated interconnect network.

[0081] Next, the first interconnect lifetime of the electronic device 110 is described in the case that there are no failed interconnects in the interconnect network.

[0082] Specifically, in response to determining that there are no failed interconnects in the interconnect network, the electronic device 110 determines a second current value for each of the plurality of interconnects. Further, based on the second current values, it determines a second average interconnect lifetime for each of the plurality of interconnects. Further, based on steady-state stress and the second average interconnect lifetime, it determines a first interconnect lifetime for each of the plurality of interconnects.

[0083] For example, an electronic device can use the following formula to determine the first interconnect lifetime of each of multiple interconnects:

[0084]

[0085] in, This refers to the lifetime of an interconnect when there are no failed interconnect segments in the interconnect network. Let be the absolute value of the tensile stress in the steady-state stress at both ends of the interconnect when there are no failed interconnect segments in the interconnect network. This is the absolute value of the tensile stress threshold. Random numbers generated for interconnects by a random number generator. The lifetime of the interconnect follows a log-normal distribution with log variance. This represents the average lifetime of an interconnect when there are no failed interconnects in the interconnect network.

[0086] It should be understood that the determination of the second current value and the second average interconnect lifetime can refer to the determination of the first current value and the first average interconnect lifetime described above, and will not be repeated here.

[0087] In some embodiments, the electronic device 110 may also determine the chip lifetime of a random sample of the target chip based on the lifetime of the first interconnect.

[0088] In some embodiments, when the electronic device 110 determines the chip lifetime of a random sample of the target chip based on the first interconnect lifetime, the minimum lifetime value among the first interconnect lifetimes of the multiple interconnects can be determined as the chip lifetime of a random sample of the target chip.

[0089] In this way, when determining the chip lifetime of a random sample of the target chip, the interconnect network corresponding to the circuit structure of the target chip is considered, making the predicted chip lifetime closer to the actual result. At the same time, the steady-state stress on the nodes in the interconnect network is also considered, which avoids solving differential equations, thereby improving the accuracy, reliability and efficiency of chip lifetime prediction.

[0090] As mentioned above, the electronic device 110 can use a random number generator to generate multiple random samples for the target chip. In some embodiments, the electronic device 110 can determine the chip lifetime of each of the multiple random samples, determine the standard deviation and mean of the chip lifetime of the multiple random samples based on the chip lifetime of each of the multiple random samples, and then determine the target number of random samples that meet the statistical requirements based on the standard deviation and mean, and perform statistical analysis on the chip lifetime of each of the multiple random samples in response to the number of multiple random samples being greater than or equal to the target number.

[0091] In some embodiments, in response to the number of multiple random samples being less than a target number, the electronic device 110 increases the number of random samples and determines the number corresponding to the increased random samples again until the number of increased random samples is greater than or equal to the target number. In some embodiments, when the number of multiple random samples is less than the target number, the electronic device 110 may use a random number generator to generate new random samples for the target chip to increase the number of random samples.

[0092] For example, the target number can be determined based on the following formula:

[0093]

[0094] in, For the target number, For the corresponding normal distribution Percentage coordinate values, For the sample size The sample standard deviation at that time For the sample size The average lifetime of the sample at that time This represents the upper limit of the deviation between the estimated average chip lifespan and the actual chip lifespan.

[0095] When the number of random samples of the target chip is greater than the target number, the upper limit of the deviation between the estimated average lifetime of the target chip and the actual chip lifetime is less than [a certain value]. The confidence level is .

[0096] For example, statistical results of chip lifetime for multiple random samples of the target chip can be referenced. Figure 5 and Figure 6 . Figure 5 An example of a percentage relationship between chip lifetime and sample number 500 according to some embodiments of this disclosure is shown. Figure 6 An example of the relationship between chip lifetime and cumulative probability 600 according to some embodiments of this disclosure is shown. Figure 5 In the diagram, the darker left half 510 represents the statistical results of chip lifespan obtained by conventional methods, and the lighter right half 520 represents the statistical results of chip lifespan obtained by the method provided in this embodiment. Figure 6 In the diagram, the darker left half (610) represents the statistical results of chip lifespan obtained by conventional methods, while the lighter right half (620) represents the statistical results of chip lifespan obtained by the method provided in this embodiment. In this way, chip lifespan can be predicted based on statistical methods and the aforementioned methods for determining chip lifespan, resulting in statistically accurate predictions and thus higher reliability.

[0097] In some embodiments, the target chip may be one of a group of chips, and each group of chips may include one or more target chips. Therefore, the electronic device 110 can determine the chip lifetime of each chip in each group of chips using the method described above, and statistically analyze the chip lifetimes of multiple groups of chips for use in large-scale chip-wide electromigration failure assessment. Examples include chip design approval and manufacturing layout verification.

[0098] In some embodiments, the methods for evaluating interconnects disclosed herein can be combined with conventional methods, allowing users to set a chip failure threshold between the chip lifetimes obtained by the two methods based on actual chip design and manufacturing requirements, thus providing users with more options.

[0099] The methods for evaluating interconnects disclosed herein can also be used to determine the lifetime of an interconnect. See also Figure 7 , Figure 7An example of a method 700 for determining the lifetime of an interconnect segment according to some embodiments of the present disclosure is shown. In some embodiments, the method 700 may be... Figure 1 The electronic device 110 shown is performing this action.

[0100] In block 710, electronic device 110 can determine the steady-state stress of each node in the interconnect tree based on the voltage of the nodes on the interconnect tree. In block 720, electronic device 110 can determine the method for calculating the interconnect lifetime based on the steady-state stress of each node in the interconnect tree. In block 730, electronic device 110 can determine the interconnect lifetime based on the interconnect current and the lifetime of failed interconnects in the interconnect tree. It should be understood that the implementation process of the above steps can refer to the relevant processes in the foregoing embodiments, and will not be repeated here.

[0101] In this way, the lifespan of each interconnect can be determined by considering the interconnect network corresponding to the chip's circuit structure and the tensile stress on the nodes in the interconnect network. This allows for accurate prediction of the interconnect lifespan and the chip's lifespan.

[0102] Figure 8 A block diagram is shown in which one or more embodiments of the present disclosure may be implemented. The electronic device 800 may, for example, be used to implement... Figure 1 The electronic device 110 shown. It should be understood that, Figure 8 The electronic device 800 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein.

[0103] like Figure 8 As shown, electronic device 800 is in the form of a general-purpose electronic device. Components of electronic device 800 may include, but are not limited to, one or more processors 810 or processing units, memory 820, storage device 830, one or more communication units 840, one or more input devices 850, and one or more output devices 860. The processing unit may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 820. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing capability of electronic device 800.

[0104] Electronic device 800 typically includes multiple computer storage media. Such media can be any available media accessible to electronic device 800, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 820 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 830 can be a removable or non-removable medium and can include machine-readable media, such as flash drives, disks, or any other media that can be used to store information and / or data (e.g., training data for training) and can be accessed within electronic device 800.

[0105] Electronic device 800 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 8 As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 820 may include computer program product 825 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0106] The communication unit 840 enables communication with other electronic devices via a communication medium. Additionally, the functionality of the components of the electronic device 800 can be implemented using a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, the electronic device 800 can operate in a networked environment using logical connections to one or more other servers, networked personal computers (PCs), or another network node.

[0107] Input device 850 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 860 can be one or more output devices, such as a monitor, speaker, printer, etc. Electronic device 800 can also communicate with one or more external devices (not shown) via communication unit 840 as needed. These external devices include storage devices, display devices, etc., and can communicate with one or more devices that enable user interaction with electronic device 800, or with any device that enables electronic device 800 to communicate with one or more other electronic devices (e.g., network card, modem, etc.). Such communication can be performed via input / output (I / O) interface (not shown).

[0108] According to an exemplary implementation of this disclosure, a computer-readable storage medium is provided that stores one or more computer instructions, wherein one or more computer instructions are executed by a processor to implement the methods described above.

[0109] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products implemented according to this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0110] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0111] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0112] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0113] Various implementations of this disclosure have been described above. The foregoing description is exemplary and not exhaustive, nor is it limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the implementations disclosed herein.

Claims

1. A method for interconnect evaluation, characterized in that, include: Obtain the interconnect network corresponding to the circuit structure of the target chip, wherein the interconnect network includes multiple nodes and multiple interconnects connecting the multiple nodes; In response to determining that there is a failed interconnect in the interconnect network, the interconnect network is updated based on the failed interconnect; Based on the first voltage values ​​of each of the multiple nodes in the updated interconnect network, the steady-state stress of each of the multiple nodes in the updated interconnect network is determined. Based on the first current value of each of the multiple interconnects in the updated interconnect network, the first average interconnect lifetime of each of the multiple interconnects in the updated interconnect network is determined. as well as Based on the steady-state stress, the first average interconnect lifetime, the second interconnect lifetime, and the lifetime of the failed interconnect, a first interconnect lifetime is determined for each of the multiple interconnects in the updated interconnect network, wherein the second interconnect lifetime indicates the lifetime of the multiple interconnects in the interconnect network before the update.

2. The method for interconnect evaluation according to claim 1, characterized in that, Based on the first voltage values ​​of each of the multiple nodes in the updated interconnect network, the steady-state stress of each of the multiple nodes in the updated interconnect network is determined, including: For a node among multiple nodes in the updated interconnect network, the steady-state stress of the node is determined based on the first voltage value of the node and the first voltage values ​​of the nodes at both ends of the interconnect connected to the node.

3. The method for interconnect evaluation according to claim 1, characterized in that, Based on the steady-state stress, the first average interconnect lifetime, the second interconnect lifetime, and the lifetime of the failed interconnect, the first interconnect lifetime of each of the plurality of interconnects in the updated interconnect network is determined to include at least one of the following: In response to determining that the steady-state stress is greater than the steady-state stress threshold, the first interconnect lifetime of each of the plurality of interconnects in the updated interconnect network is determined based on the lifetime of the failed interconnect, the second interconnect lifetime, and the first average interconnect lifetime. as well as In response to determining that the steady-state stress is less than or equal to the steady-state stress threshold, the first interconnect lifetime of each of the plurality of interconnects in the updated interconnect network is determined based on the lifetime of the failed interconnect and the second interconnect lifetime.

4. The method for interconnect evaluation according to claim 1, characterized in that, The lifetime of the failed interconnect is determined as follows: The lifetime of the failed interconnect is determined by the minimum lifetime value among the second interconnect lifetimes of each of the multiple interconnects in the interconnect network before the update.

5. The method for interconnect evaluation according to claim 1, characterized in that, Determining the first interconnect lifetime of each of the plurality of interconnects based on the steady-state stress of each of the plurality of nodes includes: In response to determining that there are no faulty interconnects in the interconnect network, a second current value is determined for each of the plurality of interconnects; Based on the second current value, determine the second average interconnect lifetime for each of the plurality of interconnects; and Based on the steady-state stress and the second average interconnect lifetime, the first interconnect lifetime of each of the plurality of interconnects is determined.

6. The method for interconnect evaluation according to claim 1, characterized in that, The method further includes: The chip lifespan of the target chip is determined based on the lifetime of the first interconnect.

7. The method for interconnect evaluation according to claim 6, characterized in that, The method further includes: Obtain multiple random samples of the target chip; The chip lifetime is determined for each of the multiple random samples; Based on the chip lifetime of each of the plurality of random samples, determine the standard deviation and average value of the chip lifetime of the plurality of random samples; Based on the standard deviation and the mean, determine the target number; and In response to the number of the plurality of random samples being greater than or equal to the target number, the chip lifetime of each of the plurality of random samples is statistically analyzed.

8. The method for interconnect evaluation according to claim 7, characterized in that, Also includes: In response to the fact that the number of the plurality of random samples is less than the target number, the number of the plurality of random samples is increased; as well as The target number corresponding to the additional random samples is determined again until the number of the additional random samples is greater than or equal to the target number.

9. The method for interconnect evaluation according to claim 1, characterized in that, The plurality of nodes indicate a predetermined type of contact point or endpoint in the circuit structure.

10. An electronic device, characterized in that, include: At least one processing unit; as well as At least one memory, coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, which, when executed by the at least one processing unit, cause the electronic device to perform the method according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that, It stores a computer program thereon, characterized in that the computer program can be executed by a processor to implement the method according to any one of claims 1 to 9.

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