Quantum computer benchmark test system and test method

Abstract

The invention provides a quantum computer benchmark test system, which is used for evaluating the performance of a quantum computer, and comprises a virtual quantum computer used for storing the information of a quantum computer to be tested; the test set generation module is used for constructing an initial test circuit set based on the to-be-tested quantum computer information stored by the virtual quantum computer; the test set preprocessing module is used for compiling circuits in the initial test circuit set to obtain a target test circuit set; the execution module is used for transmitting the target test circuit set to the quantum computer to be tested through a quantum computer interface arranged on the execution module so as to execute each circuit in the target test circuit set, and transmitting an execution result of each circuit to the evaluation module; and the evaluation module is used for evaluating the performance of the quantum computer to be tested.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing, and more specifically, to a benchmark testing technology in the field of quantum computing, and more specifically, to a quantum computer benchmark testing system and testing method. Background Art

[0002] With the rapid development of quantum computing technology, benchmarking, as a key technology to measure the performance of quantum processors, has occupied a core position in the field of quantum computing. Quantum computers, with their unique parallel computing capabilities and computing potential that surpasses traditional computers, have become a powerful tool for solving large-scale optimization problems, cryptographic problems, and physical problems. However, how to accurately and comprehensively evaluate the performance of quantum computers is a key challenge in the process of practical application and industrialization of quantum computing technology.

[0003] There are many existing quantum computing benchmarking methods, but each has certain limitations. For example, although quantum gate set tomography (GST) can provide in-depth performance analysis, it has extremely strict requirements on experimental scale and post-processing, making it difficult to achieve efficient and scalable benchmarking. Another example is the random benchmark (RB) test, which is favored for its scalability, but is mainly limited to the Clifford gate set and cannot fully reflect the universal gate set characteristics of quantum computing.

[0004] In order to overcome the limitations of the above benchmarks, researchers have comprehensively considered multiple key factors such as the number of quantum bits, quantum lifetime, gate fidelity, etc., and proposed evaluation indicators such as quantum volume (QV) and circuit-level operations per second (CLOPS) to evaluate the performance of quantum computers. In addition, some systems for practical applications have also proposed evaluation methods from an application perspective. These methods provide a single indicator and score to intuitively reflect the performance of quantum computers.

[0005] Although existing benchmarking methods can evaluate the performance of quantum computers, there are still two shortcomings. On the one hand, the test set in the existing benchmarking methods requires complex preprocessing to adapt to the operating environment of quantum computers, and the circuits in the test set after complex preprocessing may affect the operating efficiency of quantum computers. Current benchmarking methods generally use completely random circuits and classical quantum algorithm circuits as the main components of the test set to evaluate the performance of quantum computers. Among them, the random circuits in the test set are used to summarize the test results from the random distribution to obtain an overall evaluation of the performance of quantum computers. However, this general random circuit is not always directly applicable to the operating environment of quantum computers. It often requires a series of complex preprocessing steps to adapt to the operating environment of quantum computers, and the random circuits after complex preprocessing steps may affect the operating efficiency of quantum computers, thereby reducing the performance of quantum computers. On the other hand, the existing benchmarking methods fail to comprehensively evaluate the performance of quantum computers. Benchmarks should comprehensively consider the evaluation indicators of multiple key dimensions to ensure a comprehensive and in-depth evaluation of quantum computers, while existing benchmarking methods can often only evaluate the partial working performance of quantum computers by focusing on specific evaluation indicators, and fail to comprehensively evaluate the performance of quantum computers. For example, quantum volume (QV) is generally used as an evaluation indicator to evaluate the capabilities and maturity of quantum computers. Another example is that the number of circuit layer operations per second (CPS) is used to measure the number of circuit layers that a quantum computer can execute per unit time to evaluate the computing power and efficiency of a quantum computer.

[0006] In summary, although the existing benchmarking methods can evaluate the performance of quantum computers, they still have two shortcomings. On the one hand, the test set requires complex preprocessing steps to adapt to the operating environment of quantum computers, and the random circuits after the complex preprocessing steps may affect the operating efficiency of quantum computers. On the other hand, the existing benchmarking methods fail to comprehensively evaluate the performance of quantum computers.

[0007] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0008] Therefore, the object of the present invention is to overcome the defects of the prior art and provide a quantum computer benchmark testing system and a quantum computer benchmark testing method.

[0009] The objectives of the present invention are achieved through the following technical solutions.

[0010] According to a first aspect of the present invention, a quantum computer benchmark test system is provided, the system comprising: a virtual quantum computer for storing information of a quantum computer to be tested; a test set generation module for constructing an initial test circuit set based on the information of the quantum computer to be tested stored in the virtual quantum computer, wherein the initial test circuit set comprises an initial random physical machine circuit, an initial special benchmark circuit and an initial quantum algorithm circuit; a test set preprocessing module for preprocessing the circuits in the initial test circuit set to obtain a target test circuit set, wherein the preprocessing of the circuits in the initial test circuit set comprises mirroring the initial random physical machine circuit and the initial special benchmark circuit and combining the mirror result of the initial random physical machine circuit with the initial random physical machine circuit to obtain a target random physical machine circuit, and combining the mirror result of the initial special benchmark circuit with the initial special benchmark circuit to obtain a target A target special benchmark circuit, preprocessing the circuits in the initial test circuit set also includes optimizing, mapping and quantum gate conversion processing on the initial quantum algorithm circuit to compile the quantum algorithm circuit into a target circuit that conforms to the execution environment of the quantum computer to be tested; the target random physical machine circuit, the target special benchmark circuit and the target circuit constitute a target test circuit set; an execution module, used to transmit the target test circuit set to the quantum computer to be tested through the quantum computer interface set thereon to execute each circuit in the target test circuit set, and transmit the execution result of each circuit to the evaluation module; the evaluation module, used to evaluate the layering ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement and execution fidelity of the quantum computer to be tested executing different circuits according to the execution result of each circuit, so as to evaluate the performance of the quantum computer to be tested according to a preset method.

[0011] In some embodiments of the present invention, the special reference circuit includes a highly parallelized circuit, a highly serialized circuit, and a highly entangled circuit, wherein the ratio of the number of quantum gates in the highly parallelized circuit to the circuit depth and the circuit width is less than or equal to a preset ratio; the ratio of the two-bit quantum gates on the critical path in the highly serialized circuit to the total two-bit quantum gates is less than or equal to a preset ratio, and the critical path refers to the path with the longest operation-dependent span from the circuit input to the output in the circuit; and the ratio of the interaction between all quantum gates and the two-bit quantum gate in the highly entangled circuit is less than or equal to a preset ratio.

[0012] Preferably, the preset ratio is 1.

[0013] In some embodiments of the present invention, the stratification ratio is calculated as follows:

[0014]

[0015] Among them, LR represents the layer ratio of the circuit, n d Indicates the depth of the circuit, n q represents the number of qubits of the circuit, and max(LRs) represents the maximum ratio of the depth to the number of qubits of the target test circuit;

[0016] The quantum gate density is calculated as follows:

[0017]

[0018] Where GD represents the quantum gate density of the circuit, n1 represents the number of single-bit gates of the circuit, and n2 represents the number of double-bit gates of the circuit;

[0019] The cumulative fidelity is calculated as follows:

[0020]

[0021] Where CF represents the cumulative fidelity of the circuit, f1 represents the average single-bit gate fidelity of the quantum computer to be tested, f2 represents the average two-bit gate fidelity of the quantum computer to be tested, and n g Represents the total number of quantum gates of the circuit.

[0022] In some embodiments of the present invention, the degree of parallelism is calculated as follows:

[0023]

[0024] Among them, Par represents the parallelism of the circuit;

[0025] The serialization degree is calculated as follows:

[0026]

[0027] Where Ser represents the serial degree of the circuit, n2′ represents the number of two-bit gates on the target bit position in the circuit, and the target bit position represents the circuit where the degree of overlap between the two-bit gate control bit and the target bit is the highest;

[0028] The entanglement is calculated as follows:

[0029]

[0030] in,

[0031]

[0032] Among them, Ent represents the entanglement degree of the circuit, C i represents the clustering coefficient of the ith node represented by the quantum bit in the undirected graph composed of circuits, T irepresents the number of edges between neighboring nodes of the ith node represented by the quantum bit in the undirected graph composed of circuits, k i Represents the number of edges directly connected to the i-th node represented by the quantum bit in the undirected graph composed of the circuit.

[0033] In some embodiments of the present invention, the execution fidelity is calculated as follows: the probability that the actual execution result of each circuit is consistent with the predicted result after being repeatedly executed multiple times on the quantum computer to be tested is calculated, and the probability is used as the execution fidelity of each circuit.

[0034] In some embodiments of the present invention, the preset method is to evaluate each circuit in the following manner: calculate the mean of the circuit's layering ratio, quantum gate density and cumulative fidelity, and map the mean to obtain a basic score of the circuit greater than or equal to a preset threshold; calculate the mean of the circuit's parallelism, seriality and entanglement, and map the mean to obtain a difficulty coefficient of the circuit within a preset numerical range; multiply the circuit's basic score, difficulty coefficient and execution fidelity to obtain an evaluation score for the circuit, and the evaluation score represents the performance of the circuit executed by the quantum computer to be tested.

[0035] According to a second aspect of the present invention, a quantum computer benchmarking method is provided for evaluating the working performance of a quantum computer. The method comprises: step S1, obtaining a quantum computer to be tested and its information; step S2, based on the information of the quantum computer to be tested, using the system as described in the first aspect of the present invention to perform a benchmark test on the quantum computer to be tested to evaluate the working performance of the quantum computer to be tested.

[0036] Compared with the prior art, the advantages of the present invention are: (1) the circuit is preprocessed by mirroring so that the preprocessed circuit can output a unique error-free solution, thereby ensuring that the preprocessed circuit will not affect the operating efficiency of the quantum computer; (2) a special benchmark circuit is constructed to evaluate the performance of quantum computers in executing highly parallel, highly serial, and highly entangled circuits, making the benchmark test of quantum computers more comprehensive; (3) the performance of quantum computers is comprehensively evaluated using layering ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement, and execution fidelity as evaluation indicators, making the evaluation results of quantum computers more accurate and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0038] Figure 1 A schematic diagram of the structure of a quantum computer benchmark testing system according to an embodiment of the present invention;

[0039] Figure 2A schematic diagram showing an example of evaluation scores of a circuit according to an embodiment of the present invention;

[0040] Figure 3 A schematic diagram showing an example of evaluation indicators for a circuit according to an embodiment of the present invention;

[0041] Figure 4 A schematic diagram showing an example of evaluation scores of a random physical machine circuit according to an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of a flow chart of a quantum computer benchmark testing method according to an embodiment of the present invention;

[0043] Figure 6 The figure is a schematic diagram showing an example process of a quantum computer benchmark testing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0045] As mentioned in the background technology section, although existing benchmarking methods can evaluate the performance of quantum computers, they still have two shortcomings. On the one hand, the test set requires complex preprocessing steps to adapt to the operating environment of the quantum computer, and the circuits in the test set after complex preprocessing may affect the operating efficiency of the quantum computer. On the other hand, the existing benchmarking methods fail to comprehensively evaluate the performance of quantum computers.

[0046] In order to solve the defects of the prior art, the inventor analyzed the prior art and found that: the circuit in the test set cannot fix the number and size of solutions, and in order to meet the execution environment of quantum computing, it needs to be preprocessed, which makes the result of the circuit not "pure", thereby affecting the operation efficiency of the quantum computer. In order to make up for this defect, the inventor proposed that the circuit can be preprocessed by mirroring, so that the preprocessed circuit can output a unique error-free solution, so that the preprocessed circuit will not affect the operation efficiency of the quantum computer. Furthermore, in order to comprehensively evaluate the performance of quantum computers, the inventor proposed that the ability of quantum computers to perform specific tasks can be analyzed by constructing special benchmark circuits. Not only that, the inventor also proposed to use the layering ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement and execution fidelity obtained after the quantum computer executes the circuit as evaluation indicators to comprehensively evaluate the performance of quantum computers. Based on this, the inventor proposed a benchmark testing system, which includes a test set generation module, a test set preprocessing module, an execution module and an evaluation module, wherein an initial test circuit set is generated by the test set generation module, the initial test circuit set is preprocessed by the test set preprocessing module to obtain a target test circuit set, and the execution module executes the circuits in the target test circuit set, and the evaluation module executes the circuits of the execution module to obtain the layering ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement and execution fidelity to evaluate the working performance of the quantum computer.

[0047] In summary, if Figure 1As shown, the present invention provides a quantum computer benchmark test system for evaluating the performance of a quantum computer, the system comprising: a virtual quantum computer for storing information of a quantum computer to be tested; a test set generation module for constructing an initial test circuit set based on the information of the quantum computer to be tested stored in the virtual quantum computer, wherein the initial test circuit set comprises an initial random physical machine circuit, an initial special benchmark circuit and an initial quantum algorithm circuit; a test set preprocessing module for preprocessing the circuits in the initial test circuit set to obtain a target test circuit set, wherein the preprocessing of the circuits in the initial test circuit set comprises mirroring the initial random physical machine circuit and the initial special benchmark circuit and combining the mirror result of the initial random physical machine circuit with the initial random physical machine circuit to obtain the target random physical machine circuit, and combining the mirror result of the initial special benchmark circuit with the initial special benchmark circuit to obtain the target random physical machine circuit. The target special benchmark circuit is obtained by combining the target circuits in the initial test circuit set, and the circuits in the initial test circuit set are preprocessed, including optimizing the initial quantum algorithm circuit, mapping the circuit and converting the quantum gate to compile the quantum algorithm circuit into a target circuit that conforms to the execution environment of the quantum computer to be tested; the target random physical machine circuit, the target special benchmark circuit and the target circuit constitute the target test circuit set; the execution module is used to transmit the target test circuit set to the quantum computer to be tested through the quantum computer interface set thereon to execute each circuit in the target test circuit set, and transmit the execution result of each circuit to the evaluation module; the evaluation module evaluates the layering ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement and execution fidelity of the quantum computer to be tested executing different circuits according to the execution result of each circuit, so as to evaluate the performance of the quantum computer to be tested according to a preset method.

[0048] In order to better understand the present invention, each component of the benchmark testing system is described in detail below in conjunction with specific embodiments.

[0049] 1. Virtual Quantum Computer

[0050] When building a benchmark system, you need to use the Virtual Quantum Machine class to build a virtual quantum computer to store the information of the quantum computer to be tested, so as to generate a test set based on it to evaluate the performance of the quantum computer to be tested. The virtual quantum computer stores information such as the number of bits of the quantum computer to be tested, physical topology, quantum gate instruction set, single-bit quantum gate fidelity, and double-bit quantum gate fidelity.

[0051] 2. Test Set Generation Module

[0052] The test set generation module is used to construct an initial test circuit set based on the information of the quantum computer to be tested stored in the virtual quantum computer. In order to more comprehensively evaluate the working performance of the quantum computer to be tested, the constructed initial test circuit set includes an initial random physical machine circuit, an initial special benchmark circuit and an initial quantum algorithm circuit. These different test circuits are introduced below.

[0053] The initial random physical machine circuit is a multi-level circuit set based on the information stored in the virtual quantum computer, and the scale does not exceed the number of physical machine bits. The ratio of the two-bit quantum gates and the single-bit quantum gates in the circuits in the set is different, and it fully meets the operating standards of the quantum computer to be tested. There is no need to compile the initial random physical machine circuit twice, which realizes a more pure and direct test of the ability of the quantum computer to execute complex circuits. It should be noted that the ratio of the two-bit quantum gates and the single-bit quantum gates in the initial random physical machine circuit is set according to the actual test requirements, and the present invention does not impose any special restrictions. It should also be noted that the initial random physical machine circuit constructed by the present invention is different from the existing random gate set circuit, wherein the initial random physical machine circuit constructed by the present invention is a circuit constructed based on the information stored in the quantum virtual machine, which meets the operating conditions of the quantum computer to be measured, and after preprocessing, it will output a unique error-free solution; while the existing random gate set circuit cannot meet the conditions for the direct operation of the quantum computer, and the circuit needs to be preprocessed, that is, the gate set that cannot be operated and the "wrong" topological structure are processed, which will increase unnecessary time consumption and lose the characteristics of testing quantum computers to simulate random distribution.

[0054] The initial special benchmark circuit is a highly parallel, highly serialized, and highly entangled circuit generated based on the number of bits of the quantum computer to be tested, the quantum gate instruction set, and a sub-topology of the physical topology. Among them, a highly parallelized circuit is defined as a circuit that concentrates a large number of operations in a smaller depth to test the ability of quantum computer hardware to handle pressure. Therefore, when designing the circuit, the maximum proportion of two-bit gates will be added to each layer of the circuit as much as possible, and single-bit gates will be added to the spare bits of each layer of the circuit to make each layer of the circuit as free as possible. Based on this, the ratio of the number of quantum gates to the depth width (parallel characteristics) in the highly parallelized circuit is less than or equal to 1. In the actual design process, the ratio range is usually kept near the ratio of 1, such as between 0.8-1. A highly serialized circuit is defined as a circuit in which all two-bit gates are on the critical path, so that the circuit can shorten the running time during operation. Therefore, when designing the circuit, the maximum concentrated bit position of the topological midpoint and edge of the quantum computer to be tested is used as the target bit, and the two-bit gate is set at a certain ratio so that the control bit or target bit of the quantum gate is on the target bit, so that the ratio of the two-bit gate on the critical path to the total two-bit gate (the critical depth of the circuit) is less than or equal to 1. In the actual design process, the ratio range is usually kept near the ratio of 1, such as between 0.8-1, where the critical path refers to the path with the longest dependent operation span from the circuit input to the output in the circuit. A highly entangled circuit is defined as a circuit in which the interaction of two-bit gates reaches a large value. Therefore, when designing the circuit, a certain bit position will be randomly selected as idle, and the remaining bits will be entangled together through the two-bit gate, so that the ratio of all gates of the circuit to the two-bit gate (entanglement ratio) is less than or equal to 1. In the actual design process, the ratio range is usually kept near the ratio of 1, such as between 0.8-1. It should be noted that the initial special benchmark circuit is different from the initial random physical machine circuit. The position of the quantum gate in the initial special benchmark circuit needs to follow certain rules. These rules are specially designed to test the performance of quantum computers in handling specific situations, so as to comprehensively evaluate the performance of quantum computers. It should also be noted that highly parallelized circuits are designed because parallel operations put pressure on the quantum hardware in quantum computers. At this time, the related noise events are called "crosstalk" (crosstalk is usually caused by gates executed at the same time), and crosstalk will reduce the performance of quantum computers. Based on this, highly parallelized circuits are constructed to analyze the extent to which quantum computers are susceptible to crosstalk.It should also be noted that the design of highly serialized circuits is because the coherence time stored in quantum bits is limited. This limitation plus the accumulated gate error will lead to a decrease in the fidelity of circuit execution. Therefore, the duration of quantum circuits must be shortened as much as possible. Based on this, the present invention proposes the shortest duration of quantum circuits, and takes the longest dependent operation span from circuit input to output on the critical path as the shortest duration. By shortening the execution time of the circuit on the hardware, the hardware processing results of such circuits are tested. It should also be noted that the design of highly entangled circuits is because entanglement is a key feature of quantum computing, which gives quantum computing a great advantage and is also an effective indicator for measuring the performance of quantum computers. Entanglement can show quantum advantage computing tasks, such as Shor factorization, long-distance transmission, ultra-dense coding and quantum encryption protocols. Based on this, the ability of hardware to handle highly entangled states is tested by calculating the proportion of double quantum bit interactions in all gate operations.

[0055] The initial quantum algorithm circuit is a circuit generated based on the algorithm in the existing algorithm library. Among them, the existing algorithm library includes adder, multiplier, divider, variational quantum algorithm (vqe), maximum cut (maxcut), quantum neural network (qnn), quantum walk, satisfiability problem (cnf), Grover algorithm (grover), quantum Fourier transform (qft), quantum phase estimation (qpe) and other algorithms. These algorithms can be converted into circuits through QASM files, and the converted circuits can reflect the performance and capabilities of quantum computers when executing specific algorithms, and each algorithm-converted circuit has a fixed solution.

[0056] 3. Test set preprocessing module

[0057] The test set preprocessing module is used to preprocess the circuits in the initial test circuit set to obtain the target test circuit set. The following describes in detail how to preprocess the initial random physical machine circuit, the initial special benchmark circuit and the initial quantum algorithm circuit in the initial test circuit set.

[0058] For the initial random physical machine circuit and the initial special benchmark circuit, the preprocessing process is to mirror the initial random physical machine circuit and the initial special benchmark circuit, and combine the mirror result of the initial random physical machine circuit with the initial random physical machine circuit to obtain the target random physical machine circuit, and combine the mirror result of the initial special benchmark circuit with the initial special benchmark circuit to obtain the target special benchmark circuit. It should be noted that the target random physical machine circuit and the target special benchmark circuit obtained by preprocessing are mirror circuits. As a universal quality benchmark, the mirror circuit generates a unique and easy-to-calculate bit string by connecting the circuit with its reverse mirror copy, which helps to ensure that the quality and performance of the circuit meet the evaluation standards.

[0059] For the initial quantum algorithm circuit, in order to ensure that it can meet the execution environment of the quantum computer, it needs to be optimized, mapped and quantum gate converted during preprocessing. Among them, one or more existing optimization algorithms are used to optimize the initial quantum algorithm circuit during the optimization process, such as quantum gate merging and other operations to reduce the number of circuit gates and circuit depth; in the mapping process, the existing mapping algorithm is used to map the initial quantum algorithm circuit, and the mapping algorithm can use the sabre quantum bit mapping algorithm or the circuit mapping algorithm based on Monte Carlo tree search; in the quantum gate conversion process, the quantum instruction set conversion algorithm is used to perform quantum gate conversion on the initial quantum algorithm circuit. It should also be noted that during preprocessing, the initial quantum algorithm circuit is processed in the execution order of optimization-mapping-conversion-optimization. It should be noted that since the algorithm circuit can reflect the performance and ability of the quantum computer when executing a specific algorithm, and each algorithm has a fixed solution, there is no need to convert the initial quantum algorithm circuit into a mirror circuit. It only needs to be preprocessed so that the preprocessed circuit can be fully adapted and can be directly executed on the quantum computer.

[0060] It should also be noted that in order to facilitate the reading of data after the circuit is executed, measurement gates can be added at the end of the initial random physical machine circuit, the initial special benchmark circuit and the initial quantum algorithm circuit according to actual needs. The measurement gates can convert the state of the quantum bits into classical bits, which makes it easier to understand and read the execution results after the quantum computer executes the circuit, and is conducive to more accurate evaluation of the performance of the quantum computer and the accuracy and reliability of the evaluation results.

[0061] 4. Execution Module

[0062] The execution module is used to transmit the target test circuit set to the quantum computer to be tested through the quantum computer interface set thereon to execute each circuit in the target test circuit set. It should be noted that the input of the quantum computer interface is the circuit and the output is the amplitude result.

[0063] It should be noted that before the circuits in the target test circuit set are transmitted to the quantum computer to be tested through the quantum computer interface, each circuit in the target test circuit set needs to be encapsulated to create a data structure called BenchCirData, which will store the detailed information of the circuit with the circuit name as the keyword. Not only that, when the circuit executes the task on the quantum computer, the simulated results will also be stored in the corresponding BenchCirData data structure. In this way, it can be ensured that all circuits and their corresponding simulation results are organized and saved in an orderly manner, which is convenient for subsequent analysis and processing.

[0064] It should also be noted that when executing the circuits in the target test circuit set multiple times, there may be "redundancy". For example, when a quantum computer executes a large-scale circuit, if the fidelity test result is failed (in the absence of errors, after the quantum computer executes the circuit, it will output a unique, easily calculated bit string, and the first bit of the bit string will be used as the fidelity value. When the fidelity is 0, the test result is failed), then this execution will lose its meaning. In order to avoid unnecessary resource consumption, the present invention designs an intermediate review mechanism, which will perform real-time monitoring during the circuit execution process. If the fidelity test result is failed in three consecutive executions, the mechanism will automatically suspend the execution of subsequent circuits. Although the execution of subsequent circuits is suspended, the evaluation module will still analyze the execution results of the circuits that have been executed. It can be seen that the intermediate review mechanism can not only improve the efficiency of circuit execution and avoid the repetition of invalid experiments, but also ensure the rigor of the circuit execution process and the reliability of the results, thereby more accurately evaluating the performance of quantum computers and improving the overall quality of the evaluation process.

[0065] 5. Evaluation Module

[0066] The evaluation module is used to evaluate the layering ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement and execution fidelity of different circuits executed by the quantum computer to be tested according to the execution results of each circuit, so as to evaluate the performance of the quantum computer to be tested according to the preset method. According to one embodiment of the present invention, the preset method is to evaluate each circuit in the following manner: calculate the mean of the layering ratio, quantum gate density and cumulative fidelity of the circuit, and map the mean to obtain the basic score of the circuit greater than or equal to the preset threshold; calculate the mean of the parallelism, seriality and entanglement of the circuit, and map the mean to obtain the difficulty coefficient of the circuit in the preset numerical range; multiply the basic score, difficulty coefficient and execution fidelity of the circuit to obtain the evaluation score of the circuit, and the evaluation score represents the performance of the quantum computer to be tested to execute the circuit. It should be noted that the preset threshold and the preset numerical range are set according to actual needs. For example, the preset threshold can be set to 50 and the preset numerical range can be set to 1-2. The present invention does not impose any special restrictions on it.

[0067] It should be noted that the evaluation module will output a comprehensive quantitative evaluation result to evaluate the performance of quantum computers by combining the basic score, difficulty coefficient and execution fidelity. Among them, the basic score evaluates the performance of quantum computers when executing circuits; the difficulty coefficient evaluates the complexity of the circuits executed by quantum computers; and the execution fidelity evaluates the efficiency and accuracy of quantum computers when actually executing circuits.

[0068] The basic score evaluates the performance of a quantum computer when executing a circuit, which is determined by the circuit's layer ratio, gate density, and cumulative fidelity.

[0069] The layering ratio represents the comprehensive ratio of the number of quantum bits to the depth, where the depth is determined by the distribution of quantum gates on the quantum bits and the density of quantum gates. The layering ratio can indicate the complexity of the circuit and can also evaluate the time and resources required for the quantum hardware on the quantum computer to be tested to execute the circuit. The layering ratio is calculated as follows:

[0070]

[0071] Among them, LR represents the layer ratio of the circuit, n d Indicates the depth of the circuit, n q represents the number of quantum bits of the circuit, and max(LRs) represents the maximum ratio of the depth to the number of quantum bits in the target test circuit set.

[0072] The density of quantum gates focuses on the density of quantum gate operations in the entire computing process. The density of quantum gates can be used to evaluate the possible occupancy rate of the circuit when it is mapped to the quantum hardware on the quantum computer to be tested. The quantum gate density is the product of the single-bit and double-bit gates (n1, n2) and the corresponding weights and the number of quantum bits (n q ) and depth (n d ) is calculated by multiplying the product of, which is specifically expressed as follows:

[0073]

[0074] Where GD represents the quantum gate density of the circuit, n1 represents the number of single-bit gates of the circuit, and n2 represents the number of double-bit gates of the circuit;

[0075] Cumulative fidelity, the fidelity of the single-bit and two-bit gates of a quantum computer is an important indicator in the field of quantum computing, which directly reflects the performance and reliability of the quantum computer. The bit gate fidelity of a quantum computer indicates the similarity between the quantum bit and the ideal output state after the gate operation. Among them, the cumulative fidelity is obtained by adding the product of the average single-bit gate fidelity (f1) of the quantum computer to be tested and the number of single-bit gates in the circuit (n1) and the average two-bit gate fidelity (f2) and the number of two-bit gates in the circuit (n2) to obtain the average total fidelity, and then adding the average total fidelity to the total number of quantum gates (n g ) is roughly mapped to the standard circular curve in the (0, 1) interval and is calculated as follows:

[0076]

[0077] Where CF represents the cumulative fidelity of the circuit, f1 represents the average single-bit gate fidelity of the quantum computer to be tested, f2 represents the average two-bit gate fidelity of the quantum computer to be tested, and n g Represents the total number of quantum gates of the circuit.

[0078] The calculated layering ratio, quantum gate density and cumulative fidelity of each circuit are averaged and then linearly integrated to map a mean value in the range of 0 to 1 to a score above 50. The mapped score is used as the basic score to evaluate the performance of the quantum computer executing the corresponding circuit.

[0079] The difficulty coefficient measures the complexity of the circuit executed by the quantum computer, which is determined by the circuit's parallelism, seriality, and entanglement.

[0080] The degree of parallelism reflects the degree of parallel operations in quantum computing, which reveals the distribution of quantum gate operations among quantum bits in the circuit. A higher parallelism means that the number of quantum gate operations that can be performed simultaneously increases, which will improve computing efficiency and speed; at the same time, it will also increase the complexity and processing difficulty of the circuit. Among them, the degree of parallelism is calculated by comparing the number of quantum bits (n q ), the number of gates (n g ) and depth (n d ) is calculated, which is specifically expressed as follows:

[0081]

[0082] Wherein, Par represents the parallelism of the circuit.

[0083] Serialization reflects the degree of serial operation in quantum computing. A higher serialization rate indicates that more gate operations in the circuit are executed sequentially, which may limit the speed and efficiency of the calculation. Among them, serialization is calculated by calculating the ratio of the number of quantum gates on the highest coincidence bit to the total number of quantum gates, which is specifically expressed as follows:

[0084]

[0085] Wherein, Ser represents the serial degree of the circuit, n2′ represents the number of two-bit gates on the target bit position in the circuit, and the target bit position represents the circuit at which the degree of overlap between the two-bit gate control bit and the target bit is the highest.

[0086] The entanglement degree measures the distribution of entangled states in the circuit. When calculating the entanglement degree, first, the connections of each bit and each two-bit gate of the circuit need to be formed into an undirected graph, and the depth of each two-bit gate when inserted into the circuit is used as the weight of the corresponding edge to obtain a weighted undirected graph (the smaller the depth when inserted, the higher the entanglement depth of the circuit); then the weighted undirected graph is used to measure the tightness of the connection between the neighboring nodes of a node, and the clustering coefficient of each node is calculated. The clustering coefficient of each node is determined by the number of edges actually existing between the neighbors of the node and the number of edges directly connected to the node; then the entanglement degree is calculated based on the weighted undirected graph and the clustering coefficient. The specific process is shown as follows:

[0087]

[0088] in,

[0089]

[0090] Among them, Ent represents the entanglement degree of the circuit, C i represents the clustering coefficient of the ith node represented by the quantum bit in the undirected graph composed of circuits, T irepresents the number of edges between neighboring nodes of the ith node represented by the quantum bit in the undirected graph composed of circuits, k i represents the number of edges directly connected to the ith node represented by the quantum bit in the undirected graph composed of the circuit. It should be noted that in the weighted undirected graph composed of the connections between each bit and each two-bit gate of the circuit, if a node has only one critical point or no critical point (k i =0), the clustering coefficient of the node is 0, indicating that there are no interconnected edges between the neighboring nodes of the node, and when the clustering coefficient of the node is 1, it means that all neighboring nodes of the node are connected to each other to form a complete subgraph. It should also be noted that in quantum physics, entanglement is usually related to the non-locality of quantum systems, and the clustering coefficient should be able to capture this non-locality and reflect the global correlation between quantum bits. For example, if the clustering coefficient can group highly entangled quantum bits into the same cluster, then the "purity" of this cluster can be used as a measure of entanglement.

[0091] The parallelism, seriality and entanglement of each circuit calculated are averaged and then linearly integrated to linearly map the average to a numerical range of 1 to 2, and the mapped value is used as the difficulty coefficient to confirm the difficulty of the circuit executed by the quantum computer, and then evaluate the ability of the quantum computer to process complex circuits. It should be noted that when the difficulty coefficient is close to 1, it means that the circuit consumes too few resources in the execution of the quantum computer, and when the difficulty coefficient is close to 2, it means that the circuit consumes too many resources in the execution of the quantum computer.

[0092] Execution fidelity evaluates the efficiency and accuracy of a quantum computer when actually executing a circuit. According to one embodiment of the present invention, execution fidelity is calculated as follows: the probability that the actual execution result of each circuit is consistent with the predicted result after being repeatedly executed multiple times on the quantum computer to be tested is calculated, and the probability is used as the execution fidelity of each circuit. Although execution fidelity compares the consistency between the actual execution result and the predicted result, different methods are needed to calculate the probability that the actual execution result is consistent with the predicted result for different circuits.

[0093] For the target random physical machine circuit and the target special benchmark circuit, after the mirroring operation, the operation order and method of the quantum gate may be affected, so that the results of multiple executions still fall on a fixed point, and the probability result of this point is the execution fidelity of this type of circuit. For example, after executing the target random physical machine circuit or the target special benchmark circuit on the quantum computer to be tested, the execution results obtained include the results of 6 points (for example, [1,2,3,4,5,6]). Assuming that it is executed 500 times, 450 results fall on the first point, and 50 results fall on the third point, then the probability of falling on the sum of the first point and the third point is considered to be the execution fidelity of this type of circuit.

[0094] For the target quantum algorithm circuit, different algorithm circuits have different calculation methods. Among them, for certain algorithm circuits, such as circuits constructed by adder and multiplier algorithms, after circuit simulation, the result distribution of the algorithm will show that the probability amplitude of the target item is significantly higher than other items. Through measurement, a high probability result of the target item can be obtained. Suppose an algorithm circuit is simulated 1,000 times in a noise-free simulation environment, and the result falls on the second point. This is the expected result. The actual execution result is obtained by simulating a noisy quantum computer. The expected result is compared with the actual execution result to obtain the fidelity value ranging from 0 to 1. These values ​​are the execution fidelity of this type of circuit. For uncertain algorithm circuits, such as quantum Fourier transform algorithm circuits, after simulating such circuits, the results can be observed by measuring quantum bits. The measurement will cause the quantum superposition state to collapse to a specific computational ground state. The probability of each ground state being observed is determined by the square of the amplitude of the ground state. Therefore, if the quantum bits after quantum Fourier transform are measured multiple times, a probability distribution can be obtained, which reflects the amplitude of different computational ground states. However, this distribution is more scattered than other algorithm circuits, and it is not easy to locate when there are many bits. In order to locate the number of bits, the cross entropy loss function is introduced to determine the difference between the probability distribution of such circuits after being executed on a noisy real quantum computer and a noise-free full-amplitude simulator. In quantum computing, cross entropy can be used to measure the difference between two quantum states, and the cross entropy score is used as the execution fidelity of such circuits. For two probability distributions P and Q, cross entropy is defined as: H(P,Q) = -∑xP(x)logQ(x), where H(P,Q) is the cross entropy between distributions P and Q, P(x) is the actual probability (real distribution), and Q(x) is the predicted probability (predicted distribution). The core idea of ​​cross entropy is to approximate the real distribution with the predicted distribution, and the cross entropy measures the difference between the real distribution and the actual distribution. If the two distributions are exactly the same, then the cross entropy is the smallest, which is zero; if the two distributions are very different, the cross entropy will also be very large.

[0095] After calculating the basic score, difficulty coefficient and execution fidelity of each circuit using the above content, the basic score, difficulty coefficient and execution fidelity of the circuit are multiplied to obtain the evaluation score of the circuit. The larger the evaluation score, the better the performance of the quantum computer to be tested in executing the circuit. It should be noted that the evaluation score combines the basic score, difficulty coefficient and execution fidelity, and can more accurately evaluate the performance of quantum computers in executing specific circuits.

[0096] In addition to the virtual quantum computer, test set generation module, test set preprocessing module, execution module and evaluation module shown in the previous section, the quantum computer benchmark system is also equipped with a visual display module for converting the evaluation scores of each circuit obtained by the evaluation module into tables, text files, radar charts, bar charts, etc. Among them, the tables and text files show the details of the benchmark process, such as the category, depth, width, basic score, difficulty coefficient and execution fidelity of each circuit, which are used to record the information of each circuit during the execution process. Radar charts can be used to display the evaluation scores of different circuits and the hierarchical ratio LR, quantum gate density GD, cumulative fidelity CF, parallelism Par, seriality Ser and entanglement Ent of different circuits. Figure 2 The radar chart shown is used as an example to introduce the evaluation scores of the various circuits it shows. The chart includes three different circuits, one is a random physical machine circuit: random circuit; one is a special benchmark circuit: parallelized circuit, serialized circuit and entangled circuit; and the other is a quantum algorithm circuit: adder circuit (adder circuit), qft circuit (quantum Fourier transform algorithm circuit), cnf circuit (conjunctive normal form solution algorithm circuit), qnn circuit (quantum neural network algorithm circuit), vqecircuit (variational quantum algorithm circuit) and quantum_walk circuit (quantum random walk algorithm circuit). Figure 2It can be seen that the evaluation score of random circuit is 100, the evaluation score of parallelized circuit is 130, the evaluation score of serialized circuit is 125, the evaluation score of entangled circuit is 88, the evaluation score of addercircuit is 93, the evaluation score of qft circuit is 63, the evaluation score of cnf circuit is 104, the evaluation score of qnn circuit is 87, the evaluation score of vqe circuit is 124, and the evaluation score of quantum_walk circuit is 99. Among them, the evaluation score of parallelized circuit is 130, indicating that the quantum computer has the best performance when executing this circuit; the evaluation score of qft circuit is 63, indicating that the quantum computer has the worst performance when executing this circuit. Figure 3 The radar chart shown is used as an example to introduce the hierarchical ratio LR, quantum gate density GD, cumulative fidelity CF, parallelism Par, seriality Ser and entanglement Ent of each circuit shown. Figure 3 It can be seen that the quantum gate density and parallelism of parallelized circuit and entangled circuit are higher; the layer ratio and seriality of serialized circuit are higher; the quantum gate density and entanglement of adder circuit are higher, the quantum gate density of qft circuit is higher; the quantum gate density and seriality of cnf circuit are higher; the quantum gate density, parallelism and entanglement of qnn circuit are higher; the quantum gate density of vqe circuit is higher; the quantum gate density and entanglement of quantum_walk circuit are higher. The bar chart can be used to comprehensively represent the changes in the evaluation scores after the number of quantum gates in each circuit is changed, with Figure 4 The bar graph of the random physical machine circuit shown is an example to illustrate what the bar graph shows. Figure 4 The vertical axis is the evaluation score, and the vertical axis is the number of quantum gates. Figure 4 It can be seen that as the number of quantum gates in the random physical machine circuit continues to increase, the evaluation score shows a downward trend.

[0097] The quantum computer benchmark test system described in the above embodiment can be used to perform benchmark tests to evaluate the performance of quantum computers. Figure 5As shown, the present invention proposes a quantum computer benchmark test method for evaluating computer performance, the method comprising: step S1, obtaining a quantum computer to be tested and its information; step S2, based on the information of the quantum computer to be tested, using a quantum computer benchmark test system to perform a benchmark test on the quantum computer to be tested to evaluate the performance of the quantum computer to be tested. More specifically, Figure 6 As shown, the benchmark test can be performed according to the following steps: first, the quantum computer to be tested and its information are obtained; then, the obtained information of the quantum computer to be tested is stored in the virtual quantum computer of the system; then, the test set generation module of the system constructs an initial test circuit set according to the stored information of the quantum computer to be tested; then, the test set preprocessing module of the system preprocesses the circuits in the initial test circuit set to obtain a target test circuit set; then, the execution module of the system transmits the target test circuit set to the quantum computer to be tested through the quantum computer interface set thereon to execute each circuit in the target test circuit set, and transmits the execution result of each circuit to the evaluation module; then, the evaluation module of the system evaluates the hierarchical ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement and execution fidelity of the quantum computer to be tested executing different circuits according to the execution result of each circuit, and evaluates the performance of the quantum computer to be tested according to a preset method; finally, the evaluation result is displayed through the visual display module of the system.

[0098] Compared with the prior art, the present invention has the following beneficial effects: (1) the circuit is preprocessed by mirroring so that the preprocessed circuit can output a unique error-free solution, thereby ensuring that the preprocessed circuit will not affect the operating efficiency of the quantum computer; (2) a special benchmark circuit is constructed to evaluate the performance of quantum computers in executing highly parallel, highly serial, and highly entangled circuits, making the benchmark test of quantum computers more comprehensive; (3) the performance of quantum computers is comprehensively evaluated using layering ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement, and execution fidelity as evaluation indicators, making the evaluation results of quantum computers more accurate and reliable.

[0099] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0100] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0101] Computer readable storage medium can be a tangible device that holds and stores instructions used by an instruction execution device. Computer readable storage medium can include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0102] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A quantum computer benchmark system for evaluating the performance of a quantum computer, characterized in that: The system comprises: A virtual quantum computer, used to store information about the quantum computer to be tested; A test set generation module, used to construct an initial test circuit set based on the quantum computer information to be tested stored in the virtual quantum computer, wherein the initial test circuit set includes an initial random physical machine circuit, an initial special benchmark circuit and an initial quantum algorithm circuit; A test set preprocessing module is used to preprocess the circuits in the initial test circuit set to obtain a target test circuit set, wherein the preprocessing of the circuits in the initial test circuit set includes mirroring the initial random physical machine circuit and the initial special reference circuit and combining the mirror result of the initial random physical machine circuit with the initial random physical machine circuit to obtain a target random physical machine circuit, and combining the mirror result of the initial special reference circuit with the initial special reference circuit to obtain a target special reference circuit, and the preprocessing of the circuits in the initial test circuit set also includes optimizing, mapping and quantum gate conversion of the initial quantum algorithm circuit to compile the quantum algorithm circuit into a target circuit that conforms to the execution environment of the quantum computer to be tested; the target random physical machine circuit, the target special reference circuit and the target circuit constitute a target test circuit set; An execution module, used to transmit the target test circuit set to the quantum computer to be tested through a quantum computer interface provided thereon to execute each circuit in the target test circuit set, and transmit the execution result of each circuit to the evaluation module; The evaluation module is used to evaluate the layering ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement and execution fidelity of the quantum computer to be tested executing different circuits according to the execution results of each circuit, so as to evaluate the performance of the quantum computer to be tested according to a preset method.

2. The system according to claim 1, characterized in that Special benchmark circuits include highly parallelized circuits, highly serialized circuits and highly entangled circuits, wherein the ratios of the number of quantum gates to the circuit depth and circuit width in the highly parallelized circuits are all less than or equal to a preset ratio; the ratio of the two-bit quantum gates on the critical path in the highly serialized circuit to the total two-bit quantum gates is less than or equal to a preset ratio, and the critical path refers to the path with the longest operation-dependent span from the circuit input to the output in the circuit; and the ratio of the interaction between all quantum gates and the two-bit quantum gate in the highly entangled circuit is less than or equal to a preset ratio.

3. The system according to claim 2, characterized in that The preset ratio is 1.

4. The system according to claim 3, characterized in that The stratification ratio is calculated as follows: Among them, LR represents the layer ratio of the circuit, n d Indicates the depth of the circuit, n q represents the number of qubits of the circuit, and max(LRs) represents the maximum ratio of the depth to the number of qubits of the target test circuit; The quantum gate density is calculated as follows: Where GD represents the quantum gate density of the circuit, n1 represents the number of single-bit gates of the circuit, and n2 represents the number of double-bit gates of the circuit; The cumulative fidelity is calculated as follows: Where CF represents the cumulative fidelity of the circuit, f1 represents the average single-bit gate fidelity of the quantum computer to be tested, f2 represents the average two-bit gate fidelity of the quantum computer to be tested, and n g Represents the total number of quantum gates of the circuit.

5. The system according to claim 4, characterized in that The degree of parallelism is calculated as follows: Among them, Par represents the parallelism of the circuit; The serialization degree is calculated as follows: Where Ser represents the serial degree of the circuit, n2′ represents the number of two-bit gates on the target bit position in the circuit, and the target bit position represents the circuit where the degree of overlap between the two-bit gate control bit and the target bit is the highest; The entanglement is calculated as follows: in, Among them, Ent represents the entanglement degree of the circuit, C i represents the clustering coefficient of the ith node represented by the quantum bit in the undirected graph composed of circuits, T i represents the number of edges between neighboring nodes of the ith node represented by the quantum bit in the undirected graph composed of circuits, k i Represents the number of edges directly connected to the i-th node represented by the quantum bit in the undirected graph composed of the circuit.

6. The system according to claim 5, characterized in that The execution fidelity is calculated as follows: The probability that the actual execution result of each circuit is consistent with the predicted result after it is repeatedly executed multiple times on the quantum computer to be tested is calculated, and this probability is used as the execution fidelity of each circuit.

7. The system according to claim 6, characterized in that The preset method is to evaluate each circuit in the following manner: Calculating the mean of the layering ratio, quantum gate density and cumulative fidelity of the circuit, and mapping the mean to obtain a basic score of the circuit that is greater than or equal to a preset threshold; Calculating the mean of the parallelism, seriality and entanglement of the circuit, and mapping the mean to obtain the difficulty coefficient of the circuit in a preset value range; The circuit's basic score, difficulty coefficient, and execution fidelity are multiplied together to obtain the circuit's evaluation score, which represents the performance of the circuit executed by the quantum computer to be tested.

8. A quantum computer benchmarking method for evaluating the performance of a quantum computer, characterized in that: The method comprises: Step S1, obtaining the quantum computer to be tested and its information; Step S2: Based on the information of the quantum computer to be tested, a system as described in any one of claims 1 to 7 is used to perform a benchmark test on the quantum computer to be tested to evaluate the working performance of the quantum computer to be tested.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to claim 8.

10. An electronic device, characterized in that: include: one or more processors; and a memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of claim 8 by executing the executable instructions.

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