Display device

Abstract

A display device includes: a drive controller that receives an image signal and a signal including a command to enter a low power mode or a command to terminate the low power mode, and generates or receives a first synchronization signal and a second synchronization signal; a panel driver that operates in response to a control signal provided from the driving controller; and a display panel which is controlled by the panel driver. The panel driver includes a data driving circuit that provides a data signal to the display panel in synchronization with a first synchronization signal, and the driving controller, upon receiving a command to enter a low power mode or a command to terminate the low power mode, supplies the data signal to the display panel in synchronization with the first synchronization signal. The control signal is changed by counting a clock of the second synchronization signal.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0075555, filed on Jun. 13, 2023, and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a display device with reduced power consumption and improved performance. Background Art

[0003] An emissive display device in a display device generally displays an image by using a light emitting diode that emits light when electrons and holes are recombined with each other. An emissive display device can have a fast response speed and be driven with low power consumption. An emissive display device can include pixels connected to data lines and scan lines. Each pixel generally includes a light emitting diode and a circuit for controlling the amount of current flowing through the light emitting diode. The pixel circuit controls the amount of current corresponding to the data signal from a node provided with a first drive voltage through the light emitting diode to a node provided with a second drive voltage. In this case, light with a specific brightness is generated to correspond to the amount of current flowing through the light emitting diode. Summary of the invention

[0004] Embodiments of the present disclosure relate to a display device with reduced power consumption and improved performance.

[0005] According to an embodiment, a display device includes: a drive controller that receives an image signal and a signal including a command for entering a low power mode or a command for terminating the low power mode, and generates or receives a first synchronization signal and a second synchronization signal; a panel driver that operates in response to a control signal provided from the drive controller; and a display panel that is controlled by the panel driver, wherein the display panel selectively operates in a first mode for operating at a specific driving frequency or in a second mode for operating at a variable driving frequency. In such an embodiment, the panel driver includes: a data drive circuit that provides a data signal to the display panel in synchronization with the first synchronization signal, and the drive controller changes the control signal by counting a clock of the second synchronization signal when receiving a command for entering a low power mode or a command for terminating the low power mode.

[0006] In an embodiment, the frequency of the first synchronization signal may be changed to correspond to the driving frequency of the display panel.

[0007] In an embodiment, a maximum frequency of the first synchronization signal corresponding to a maximum frequency of the variable driving frequency may be equal to or less than a frequency of the second synchronization signal.

[0008] In an embodiment, the second synchronization signal may be different from the first synchronization signal.

[0009] In an embodiment, the driving controller may generate the second synchronization signal having a frequency obtained by multiplying the frequency of the first synchronization signal by the number of cycles included in one frame corresponding to the frequency of the first synchronization signal.

[0010] In an embodiment, the second synchronization signal and the first synchronization signal may be defined by the same signal.

[0011] In an embodiment, the driving controller may change a count reference value serving as a reference for changing a state of a control signal.

[0012] In an embodiment, the drive controller may designate a count reference value of the first synchronization signal at a maximum frequency corresponding to the maximum frequency of the variable drive frequency as a first count reference value, and the drive controller may generate a second count reference value less than the first count reference value based on an operating frequency of the first synchronization signal corresponding to the variable drive frequency when receiving a command for entering a low power mode or a command for terminating a low power mode.

[0013] In an embodiment, the second count reference value may be obtained based on a value obtained by multiplying a value obtained by dividing the operating frequency by the maximum frequency of the first synchronization signal by the first count reference value.

[0014] In an embodiment, the driving controller may generate the second synchronization signal by changing an operating frequency of the first synchronization signal corresponding to the variable driving frequency when receiving a command for entering the low power mode or a command for terminating the low power mode.

[0015] In an embodiment, the driving controller may generate the second synchronization signal by changing the operating frequency of the first synchronization signal to the maximum frequency of the variable driving frequency when the operating frequency of the first synchronization signal is lower than a maximum frequency of the first synchronization signal corresponding to the maximum frequency of the variable driving frequency.

[0016] In an embodiment, the driving controller may change the control signal from the first state to a second state different from the first state by counting a clock of the second synchronization signal when receiving a command for entering the low power mode.

[0017] In an embodiment, the driving controller may change the control signal from the second state to the first state by counting a clock of the second synchronization signal when receiving a command for terminating the low power mode.

[0018] According to an embodiment, a display device may include: a drive controller that receives an image signal and a signal including a command for entering a low power mode or a command for terminating a low power mode, and generates a synchronization signal; a panel driver that operates in response to a control signal provided from the drive controller; and a display panel that is controlled by the panel driver. In such an embodiment, the drive controller generates a count value by counting a clock of a synchronization signal when receiving a command for entering or terminating a low power mode, and changes a control signal from a first state to a second state different from the first state when the count value is equal to or greater than a count reference value. In such an embodiment, at least one of the frequency of the synchronization signal and the count reference value is constant.

[0019] In an embodiment, the panel driver may include a data driving circuit that provides a data signal to the display panel in synchronization with a synchronization signal, and the display panel may selectively operate in a first mode for operating at a specific driving frequency or a second mode for operating at a variable driving frequency.

[0020] In an embodiment, the drive controller may designate a count reference value of the synchronization signal at a maximum frequency corresponding to the maximum frequency of the variable drive frequency as a first count reference value, and the drive controller may generate a second count reference value less than the first count reference value based on an operating frequency of the synchronization signal corresponding to the variable drive frequency when receiving a command for entering a low power mode or a command for terminating a low power mode.

[0021] In an embodiment, the drive controller may change the operating frequency of the synchronization signal to the maximum frequency of the variable drive frequency when the operating frequency of the synchronization signal corresponding to the variable drive frequency is lower than the maximum frequency of the synchronization signal corresponding to the maximum frequency of the variable drive frequency, and when a command for entering a low power mode or a command for terminating a low power mode is received.

[0022] In an embodiment, the panel driver may include a data driving circuit that provides a data signal to the display panel in synchronization with a vertical synchronization signal, the display panel may selectively operate in a first mode for operating at a specific driving frequency or in a second mode for operating at a variable driving frequency, and a maximum frequency of the vertical synchronization signal corresponding to the maximum frequency of the variable driving frequency may be equal to or less than the frequency of the synchronization signal.

[0023] According to an embodiment, a display device may include: a driving controller that receives an image signal and a signal including a command for entering a low power mode or a command for terminating the low power mode, and generates a synchronization signal; a panel driver that operates in response to a control signal provided from the driving controller; and a display panel that is controlled by the panel driver, wherein the display panel selectively operates in a first mode for operating at a specific driving frequency or a second mode for operating at a variable driving frequency. In such an embodiment, the panel driver includes: a data driving circuit that provides a data signal to the display panel in synchronization with the synchronization signal, and the driving controller changes the control signal after a specific period of time based on the synchronization signal when receiving the command for entering the low power mode or the command for terminating the low power mode, and when receiving the command for entering the low power mode or the command for terminating the low power mode, the frequency of the synchronization signal is changed from a first frequency to a second frequency equal to or greater than the first frequency.

[0024] In an embodiment, the driving controller may change the first frequency to the maximum frequency of the variable driving frequency when the first frequency is lower than a maximum frequency of the synchronization signal corresponding to the maximum frequency of the variable driving frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features of embodiments of the present disclosure will become apparent by describing the embodiments of the present disclosure in detail with reference to the attached drawings.

[0026] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0027] Figure 2 is a block diagram of a display device according to an embodiment of the present disclosure.

[0028] Figure 3 is a view illustrating a period included in each of a first frame and a second frame according to an embodiment of the present disclosure.

[0029] Figure 4 is a flowchart illustrating the operation of the display device according to an embodiment of the present disclosure.

[0030] Figure 5A is a timing diagram illustrating the operation of the display device according to an embodiment of the present disclosure.

[0031] Figure 5B is a timing diagram illustrating the operation of the display device according to an embodiment of the present disclosure.

[0032] Figure 5C is a timing diagram illustrating the operation of the display device according to an embodiment of the present disclosure.

[0033] Figure 6 is a flowchart illustrating the operation of the display device according to an embodiment of the present disclosure.

[0034] Figure 7 is a timing diagram illustrating the operation of the display device according to an embodiment of the present disclosure.

[0035] Figure 8 is a flowchart illustrating the operation of the display device according to an embodiment of the present disclosure.

[0036] Fig. 9A is a timing diagram illustrating the operation of the display device according to an embodiment of the present disclosure.

[0037] Fig. 9B is a timing diagram illustrating the operation of the display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The present invention will now be more fully described below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and these embodiments will fully convey the scope of the present invention to those skilled in the art.

[0039] In the specification, the statement that a first component (or region, layer, part, portion, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is inserted between the first and second components.

[0040] The same reference numerals will be assigned to the same components. In addition, in the drawings, the thickness, proportion, and size of components may be exaggerated to effectively describe the technical features.

[0041] Although the terms "first", "second", etc. can be used to describe various components, these components should not be interpreted as being limited by these terms. These terms are only used to distinguish one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope and spirit of the present disclosure.

[0042] In addition, the terms "below", "at the lower part", "above", "upper" are used to describe the relationship between the components illustrated in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0043] The terms used in this article are only for the purpose of describing a specific embodiment, and are not intended to be limited. As used in this article, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and unless the context clearly indicates otherwise, it is intended to include both singular and plural. Therefore, the reference to "one" element in the claim (followed by the reference to "the" element) includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "one element" has the same meaning as "at least one element". "At least one" is not interpreted as limiting "one". "Or" means "and / or". As used in this article, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the term "includes", "comprising" or "having" and its variants specify the existence of stated features, quantities, steps, operations, components, parts or their combinations, but does not exclude the existence or addition of one or more other features, quantities, steps, operations, components, parts and / or their combinations.

[0044] The terms "component" and "unit" refer to software components or hardware components for performing specific functions. Hardware components may include field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Software components may indicate data used by executable code and / or executable code in a storage medium that can be addressed. Accordingly, software components may be, for example, object-oriented software components, class components, and task components, and may include processes, functions, attributes, procedures, subroutines, program code segments, driver data, firmware, microcode, circuits, data, databases, data structures, tables, arrangements, or variables.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as the context in the relevant technical field, and should not be interpreted as having an ideal or overly formal meaning unless clearly defined herein.

[0046] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 is a perspective view of an electronic device ED according to an embodiment of the present disclosure.

[0048] refer to Figure 1 In an embodiment, the electronic device ED may be activated in response to an electrical signal. For example, the electronic device ED may be a cellular phone, a foldable phone, a laptop computer, a television, a tablet computer, a vehicle navigation system, a game console, or a wearable device, but the present disclosure is not limited thereto. For example, Figure 1 An embodiment in which the electronic device ED is a laptop computer is illustrated.

[0049] The electronic device ED may include a display device DD and a processing unit PU.

[0050] The display device DD may be a component that actually generates an image. The display device DD may be an emissive display device. In an embodiment, for example, the display device DD may be an organic light-emitting display device, an inorganic light-emitting display device, an organic-inorganic light-emitting display device, a quantum dot display device, a micro light-emitting diode (LED) display device, or a nano LED display device. In addition, according to an embodiment of the present disclosure, the display device DD may further include a function of sensing an external input. For example, the display device DD may be configured to sense at least any one of an active input of an input device and a passive input of a touch. The touch may include an input unit such as a user's body or an input device (e.g., a pen) to provide a change in capacitance.

[0051] The processing unit PU may control a driving controller TC (see Figure 2 ) and panel driver P-DV (see Figure 2 According to an embodiment of the present disclosure, the processing unit PU may include a graphics controller.

[0052] Figure 2 is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0053] refer to Figure 2 In an embodiment, the display device DD may include a display panel DP, a driving controller TC, and a panel driver P-DV. According to an embodiment of the present disclosure, the panel driver P-DV may include a data driving circuit 100 (or a data driver), a driving circuit 200, and a voltage generator 300.

[0054] The display panel DP may include a display area DA and a non-display area NDA. The display panel DP may include a plurality of pixels PX disposed in the display area DA. Each of the pixels PX includes a light emitting element and a pixel circuit for controlling light emission from the light emitting element in a third direction DR3. The pixel circuit may include at least one transistor and at least one capacitor.

[0055] The display panel DP further includes initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, write scan lines GWL1 to GWLn, bias scan lines GBL1 to GBLn, light emission control lines EML1 to EMLn, and data lines DL1 to DLm. Here, n and m are natural numbers. However, the present disclosure is provided for illustrative purposes only, and the signal lines included in the display panel DP are not limited to the above examples.

[0056] The driving controller TC receives the image signal RGB, the control signal CTRL and the mode control signal M-CTRL. The driving controller TC generates the image data signal by converting the data format of the image signal RGB to match the data driving circuit 100 and the interface specification. The driving controller TC can output the first control signal SCS, the second control signal DCS and the third control signal VCS.

[0057] The display panel DP may be configured to selectively operate in a first mode for operating at a specific driving frequency (e.g., a specific constant driving frequency of 60 Hz, 120 Hz, or 240 Hz) or in a second mode for operating at a variable driving frequency. In an embodiment, for example, the variable driving frequency may be changed within a range of 1 Hz to 240 Hz, but the range of the driving frequency is not limited thereto.

[0058] In an embodiment, the image signal RGB can be input with a random cycle in a second mode (e.g., a gaming environment) for operating with a variable drive frequency. In such an embodiment, the drive controller TC can perform a periodic operation to correspond to the random input frequency. In an embodiment, for example, when the input cycle of the image signal RGB is increased, the number of retention cycles included in a frame can be increased. When the input cycle of the image signal RGB is reduced, the number of retention cycles included in a frame can be reduced.

[0059] The mode control signal M-CTRL may be a signal from the processing unit PU (see Figure 1 ). The mode control signal M-CTRL may be a signal including a command for low power operation. In an embodiment, for example, the mode control signal M-CTRL may be a signal including a command for entering a low power mode and a command for terminating the low power mode.

[0060] When an event of the low power mode occurs, the processing unit PU may output a mode control signal M-CTRL including a command for entering the low power mode to the driving controller TC. In an embodiment, for example, the event of the low power mode may occur when the user is not using the electronic device ED (see Figure 1 When there is no input (e.g., input through a touch pad, a mouse, a touch screen, or a keyboard) to the electronic device ED for a preset time, or when no action of the user is recognized by a camera included in the electronic device ED, an event of the low power mode is determined to be occurring.

[0061] The driving controller TC may turn off the screen of the display panel DP in response to (or upon receiving) the mode control signal M-CTRL including a command for entering a low power mode by controlling the first control signal SCS, the second control signal DCS, and the third control signal VCS supplied to the panel driver P-DV. Accordingly, the power consumption of the electronic device ED (see Figure 1 ) power consumption. Even if the screen of the display panel DP is turned off, the driving controller TC may be kept turned on. An operation for turning off the screen of the display panel DP and for keeping the driving controller TC turned on may be referred to as a zero refresh operation.

[0062] When an event for terminating the low power mode occurs, the processing unit PU may output a mode control signal M-CTRL including a command for terminating the low power mode to the driving controller TC. The driving controller TC may turn on the screen of the display panel DP by controlling the first control signal SCS, the second control signal DCS, and the third control signal VCS provided to the panel driver P-DV.

[0063] The operation for entering or terminating the low power mode may occur in the second mode in which the display device DD operates at a variable driving frequency. According to an embodiment of the present disclosure, after receiving a command for entering or terminating the low power mode, the drive controller TC may always maintain the time interval between the time point when the command for entering or terminating the low power mode or the command for terminating the low power mode is received and the "on" or "off" operation of the display panel DP, and the details thereof will be described below. In other words, when the operation for entering or terminating the low power mode occurs in the second mode for operating at a variable driving frequency, the time difference between the time point when the command for entering or terminating the low power mode is received and the "on" or "off" operation of the display panel DP may be eliminated or reduced. Accordingly, the electronic device ED (see Figure 1 )’s operation consistency improves product quality.

[0064] The data driving circuit 100 receives a second control signal DCS and an image data signal DATA from a driving controller TC. The data driving circuit 100 may convert the image data signal DATA into a data signal and output the data signal to the data lines DL1 to DLm. The data signal is an analog voltage corresponding to a grayscale value of the image data signal DATA. The data lines DL1 to DLm may be arranged in a second direction DR2, and each of the data lines DL1 to DLm may extend in a first direction DR1.

[0065] The driving circuit 200 may be disposed in the non-display area NDA of the display panel DP, but the present disclosure is not limited thereto. In an embodiment, for example, at least a portion of the driving circuit 200 may be disposed in the display area DA. The driving circuit 200 may include a transistor formed by the same process as that of the pixel circuit of the pixel PX.

[0066] The driving circuit 200 may receive the first control signal SCS and may output scan signals and emission signals to the initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, the bias scan lines GBL1 to GBLn, and the emission control lines EML1 to EMLn.

[0067] In an embodiment, the driving circuit 200 may be provided in plurality, that is, a plurality of driving circuits 200 may be provided. In an embodiment, for example, the plurality of driving circuits 200 may be spaced apart from each other while the display area DA is interposed between the plurality of driving circuits 200. The initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, the bias scan lines GBL1 to GBLn, and the emission control lines EML1 to EMLn may be electrically connected to the driving circuits 200, respectively, to receive signals from the driving circuits 200.

[0068] In such an embodiment, each of the driving circuits 200 may include a scan driving circuit connected to the initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, and the bias scan lines GBL1 to GBLn, and a light emission control driving circuit connected to the light emission control lines EML1 to EMLn. One initialization scan line GIL1, one compensation scan line GCL1, one write scan line GWL1, one bias scan line EBL1, and one light emission control line EML1 may receive the same signal from two driving circuits 200. However, this is provided for illustration purposes only and may be omitted. Figure 2 Alternatively, the scan driving circuit and the light emission control driving circuit may be spaced apart from each other while inserting the display area DA between the scan driving circuit and the light emission control driving circuit.

[0069] Each of the initialization scan lines GIL1 to GILn, the compensation scan lines GCL1 to GCLn, the write scan lines GWL1 to GWLn, the bias scan lines GBL1 to GBLn, and the emission control lines EML1 to EMLn may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0070] Each of the plurality of pixels PX may be electrically connected to four scan lines, one light emission control line, and one data line. Figure 2 , the pixels in the first row (i.e., pixel row) may be connected to the scan lines GIL1, GCL1, GWL1, and GBL1 and the emission control line EML1. In an embodiment, for example, the pixels in the first column may be connected to the data line DL1. In addition, the pixels in the j-th row may be connected to the scan lines GILj, GCLj, GWLj, and GBLj and the emission control line EMLj.

[0071] The voltage generator 300 receives the third control signal VCS and generates voltages for operation of the display panel DP. According to an embodiment, the voltage generator 300 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vint1, a second initialization voltage Vint2, and a bias voltage Vbs.

[0072] Figure 3 is a view illustrating a period included in each of a first frame FR1 and a second frame FR2 according to an embodiment of the present disclosure.

[0073] refer to Figure 3 In the embodiment, the display panel DP (see Figure 2 ) can operate with a variable driving frequency including a first frame frequency and a second frame frequency lower than the first frame frequency. Figure 3 A first frame FR1 when the display panel DP operates at a first frame frequency and a second frame FR2 when the display panel DP operates at a second frame frequency are illustrated.

[0074] The first frame frequency may be different from the second frame frequency. In an embodiment, for example, the first frame frequency may be higher than the second frame frequency. Accordingly, the duration of the second frame FR2 may be longer than the duration of the first frame FR1. In an embodiment, for example, the first frame frequency of the first frame FR1 may be 120 Hz, and the second frame frequency of the second frame FR2 may be 40 Hz.

[0075] Each of the first frame FR1 and the second frame FR2 may include a plurality of cycles (or durations or periods). The number of blank durations (or periods) BP included in one frame may be changed depending on the frame frequency of the display panel DP. For example, as the frame frequency is reduced, the number of blank durations BP may be increased. For example, the first frame FR1 may include one active duration AP and one blank duration BP. The second frame FR2 may include one active duration AP and a plurality of blank durations BP. The pixels PX (see FIG. 1 ) in the blank duration BP may be changed. Figure 2) may emit light corresponding to data written for the effective duration AP. The effective duration AP may be referred to as a write duration or a write cycle. The blank duration BP may be referred to as a hold duration, a hold cycle, or a self-scan duration.

[0076] Figure 4 is a diagram illustrating a display device DD according to an embodiment of the present disclosure (see Figure 2 ) operation flowchart.

[0077] refer to Figure 1 , Figure 2 and Figure 4 In an embodiment, the driving controller TC receives a mode control signal M-CTRL from the processing unit PU. The mode control signal M-CTRL may include a command for entering a low power mode or a command for terminating a low power mode.

[0078] The drive controller TC determines whether a command for entering the low power mode is input (step S100). When a command for entering the low power mode is input, the drive controller TC may turn off the display panel DP (step S110). Even if the screen of the display panel DP is turned off, the drive controller TC may be kept turned on. The drive controller TC determines whether a command for terminating the low power mode is input (step S120). When a command for terminating the low power mode is input, the drive controller TC may turn on the display panel DP (step S130).

[0079] Will refer to FIG. 5A to FIG. 5C Describing references in more detail Figure 4 Describes the operation.

[0080] Figure 5A is a diagram illustrating a display device DD according to an embodiment of the present disclosure (see Figure 2 ) operation flowchart. Figure 5B is a timing chart illustrating the operation of the display device DD according to an embodiment of the present disclosure. Figure 5C is a timing chart illustrating the operation of the display device DD according to an embodiment of the present disclosure.

[0081] refer to Figure 1 , Figure 2 , Figure 4 and Figure 5A In an embodiment, the driving controller TC may receive a mode control signal M-CTRL including a command ZRE for entering a low power mode, and may be configured to receive or generate a first synchronization signal Vsync_FR1 and a second synchronization signal Ssync.

[0082] The operation of the panel driver P-DV may be controlled by control signals CTSa and CTSb provided from the driving controller TC. Each of the control signals CTSa and CTSb may be included in the first control signal SCS, the second control signal DCS, and the third control signal VCS.

[0083] The panel driver P-DV may include a data driving circuit 100 for providing a data signal to the display panel DP in synchronization with a first synchronization signal Vsync_FR1. The first synchronization signal Vsync_FR1 may be a vertical synchronization signal.

[0084] When receiving the command ZRE for entering the low power mode, the drive controller TC may be configured to change the states of the control signals CTSa and CTSb after a specific period of time based on the second synchronization signal Ssync. When receiving the command ZRE for entering the low power mode, the drive controller TC may be configured to count the clocks of the second synchronization signal Ssync and change the states of the control signals CTSa and CTSb.

[0085] refer to Figure 5A , Figure 5B and Figure 5C , the first synchronization signal Vsync_FR1 may correspond to the vertical synchronization signal. Accordingly, the first synchronization signal Vsync_FR1 may be changed to correspond to the driving frequency of the display panel DP. Figure 5A and Figure 5C The frequency of the first synchronization signal Vsync_FR1 illustrated in FIG. 1 may correspond to the maximum frequency of the variable driving frequency of the display panel DP. For example, Figure 5A and Figure 5C The first synchronization signal Vsync_FR1 illustrated in FIG. 1 has a frequency corresponding to 120 Hz, and Figure 5B The first synchronization signal Vsync_FR2 illustrated in FIG. 4 may have a frequency corresponding to 40 Hz, but the present disclosure is not limited thereto.

[0086] The drive controller TC may be configured to generate a second synchronization signal Ssync having a frequency obtained by multiplying the frequency of the first synchronization signal Vsync_FR1 or Vsync_FR2 by the number of cycles included in a frame under the relevant frequency. Accordingly, the frequency of the second synchronization signal Ssync may be higher than the frequency of the first synchronization signal Vsync_FR1 or Vsync_FR2. The second synchronization signal Ssync may be different from the first synchronization signal Vsync_FR1 or Vsync_FR2. In other words, the second synchronization signal Ssync may be a signal having a constant frequency without a change in the frequency corresponding to the variable drive frequency.

[0087] refer to Figure 3 , Figure 5A and Figure 5B , the frequency of the first synchronization signal Vsync_FR1 may be 120 Hz, and at the relevant frequency, the number of cycles included in one frame FR1 may be two in one frame FR1. Accordingly, the frequency of the second synchronization signal Ssync may be 240 Hz. In addition, the frequency of the first synchronization signal Vsync_FR2 may be 40 Hz, and at the relevant frequency, the number of cycles included in one frame FR2 may be six in one frame FR2. Accordingly, the frequency of the second synchronization signal Ssync may be 240 Hz.

[0088] According to an embodiment of the present disclosure, when a command ZRE for entering a low power mode is received, the drive controller TC may be configured to count the clock of the second synchronization signal Ssync having a constant frequency and change the state of the control signals CTSa and CTSb. In such an embodiment, the count reference value serving as a reference for changing the state of the control signals CTSa and CTSb may be fixed or constant. In an embodiment, for example, when the value obtained by counting the clock of the second synchronization signal Ssync is 18, the drive controller TC may change the state of each of the control signals CTSa and CTSb from a first state to a second state different from the first state.

[0089] According to an embodiment of the present disclosure, even if the display panel DP operates at a variable driving frequency, the driving controller TC can maintain the time interval TPa or TPb between the "off" operations of the display panel DP after receiving the command ZRE for entering the low power mode. Accordingly, the efficiency of the electronic device ED (see Figure 1 )’s operation consistency improves product quality.

[0090] Hereinafter, the control signals CTSa and CTSb may be referred to as the first control signal CTSa and the second control signal CTSb, respectively. For example, the first state of the first control signal CTSa may be a switching state, and the second state of the first control signal CTSa may be a state having a direct current (DC) value. The first state of the second control signal CTSb may be a high level, and the second state of the second control signal CTSb may be a low level. However, this is provided for illustration purposes only. As long as the first state is a signal state for turning on the display panel DP and the second state is a signal state for turning off the display panel DP, the first state and the second state may be variously defined.

[0091] In addition, although Figure 5AThe diagram illustrates a case where the first control signal CTSa and the second control signal CTSb are changed from the first state to the second state in the same timing, but the present disclosure is not limited thereto. For example, the timing of changing the state of the first control signal CTSa and the timing of changing the state of the second control signal CTSb may be different from each other. In addition, the state of the same signal may be changed at the same timing. For example, even for frames for operating at different drive frequencies, the state of the first control signal CTSa may be changed at the same timing.

[0092] refer to Figure 1 , Figure 2 and Figure 5C , the drive controller TC may receive a mode control signal M-CTRL including a command ZREX for terminating the low power mode. When receiving the command ZREX for terminating the low power mode, the drive controller TC may be configured to count the clock of the second synchronization signal Ssync and change the states of the control signals CTSa and CTSb.

[0093] According to an embodiment of the present disclosure, the second synchronization signal Ssync may be a signal having a constant frequency without a change in frequency corresponding to a variable driving frequency of the display panel DP. In addition, a count reference value serving as a reference for changing the state of the control signals CTSa and CTSb may be fixed or constant. For example, when the value obtained by counting the clock of the second synchronization signal Ssync is "18", the drive controller TC may change the state of the control signals CTSa and CTSb from the second state to the first state. In other words, even if the display panel DP operates at a variable driving frequency, the drive controller TC may always maintain the time interval TPc between the "on" operations of the display panel DP after receiving the command ZREX for terminating the low power mode. Accordingly, the power consumption of the electronic device ED (see Figure 1 )’s operation consistency improves product quality.

[0094] Figure 6 is a diagram illustrating a display device DD according to an embodiment of the present disclosure (see Figure 2 ) operation flowchart. Figure 7 is a timing chart illustrating the operation of the display device DD according to an embodiment of the present disclosure.

[0095] refer to Figure 1 , Figure 2 , Figure 6 and Figure 7 In an embodiment, the driving controller TC receives a mode control signal M-CTRL from the processing unit PU. The mode control signal M-CTRL may include a command ZRE for entering a low power mode and a command for terminating the low power mode.

[0096] The driving controller TC determines whether the command ZRE for entering the low power mode is input (step S200). When the command ZRE for entering the low power mode is input, the driving controller TC may compare the operating frequency of the vertical synchronization signal Vsync with the maximum frequency of the vertical synchronization signal Vsync (step S210).

[0097] The operating frequency of the vertical synchronization signal Vsync may correspond to the driving frequency of the display panel DP. The maximum frequency of the vertical synchronization signal Vsync may have a constant value corresponding to the maximum frequency of the variable driving frequency of the display panel DP.

[0098] According to an embodiment of the present disclosure, when the operating frequency of the vertical synchronization signal Vsync is lower than the maximum frequency of the vertical synchronization signal Vsync, the drive controller TC may change the frequency of the vertical synchronization signal Vsync (step S220). In an embodiment, for example, the drive controller TC may change the frequency of the vertical synchronization signal Vsync to the maximum frequency. The vertical synchronization signal Vsync having an operating frequency corresponding to the operating frequency of the display panel DP may be referred to as a first synchronization signal, and the vertical synchronization signal Vsync having a frequency changed to the maximum frequency may be referred to as a second synchronization signal. In other words, according to an embodiment of the present disclosure, the first synchronization signal and the second synchronization signal may be defined by the same signal (e.g., the vertical synchronization signal Vsync), that is, may be parts of the same signal.

[0099] When the operating frequency of the vertical synchronization signal Vsync is equal to or greater than the maximum frequency of the vertical synchronization signal Vsync, in other words, when the operating frequency of the vertical synchronization signal Vsync is the maximum frequency, the driving controller TC may not change the frequency of the vertical synchronization signal Vsync.

[0100] exist Figure 7 In the embodiment, before the command ZRE for entering the low power mode is input, the frequency of the vertical synchronization signal Vsync may be 40 Hz. After the command ZRE for entering the low power mode is input, the frequency of the vertical synchronization signal Vsync may be changed from 40 Hz to 120 Hz, which is the maximum frequency. However, the maximum frequency is provided only for the purpose of illustration, but the present disclosure is not limited thereto.

[0101] The driving controller TC may count the clock of the vertical synchronization signal having the maximum frequency (step S230). The driving controller TC compares the count value obtained by counting the clock of the vertical synchronization signal Vsync with the count reference value (step S240). The driving controller TC determines whether the count value is equal to or greater than the count reference value. When the count value is equal to or greater than the count reference value, the driving controller TC may turn off the display panel DP (step S250).

[0102] According to an embodiment of the present disclosure, when a command ZRE for entering a low power mode is received, the drive controller TC may be configured to count the clock of the vertical synchronization signal Vsync having a frequency changed to a maximum frequency from a time point EP when the command ZRE is received to change the state of the control signals CTSa and CTSb. In an embodiment, for example, when a value obtained by counting the vertical synchronization signal Vsync is 9, the drive controller TC may change the state of the control signals CTSa and CTSb from a first state to a second state different from the first state.

[0103] According to an embodiment of the present disclosure, when a command ZRE for entering a low power mode is received, since the frequency of the vertical synchronization signal Vsync is changed to a maximum frequency, a portion of the vertical synchronization signal Vsync serving as a reference for the "off" operation of the display panel DP may be a signal having a constant frequency. In addition, a count reference value serving as a reference for changing the states of the control signals CTSa and CTSb may be constant. In other words, even if the display panel DP operates at a variable driving frequency, the drive controller TC may always maintain the time interval TP between the "off" operations of the display panel DP after receiving the command ZRE for entering a low power mode. Accordingly, the efficiency of the electronic device ED (see Figure 1 )’s operation consistency improves product quality.

[0104] Even if the screen of the display panel DP is turned off, the drive controller TC can be kept turned on. The drive controller TC determines whether a command for terminating the low power mode is input (step S260). When a command for terminating the low power mode is input, the drive controller TC can count the clock of the vertical synchronization signal Vsync (step S270). The drive controller TC compares the count value obtained by counting the clock of the vertical synchronization signal Vsync with the count reference value (step S280). The timing controller TC determines whether the count value is equal to or greater than the count reference value. When the count value is equal to or greater than the count reference value, the drive controller TC can turn on the display panel DP (step S290).

[0105] Figure 8is a diagram illustrating a display device DD according to an embodiment of the present disclosure (see Figure 2 ) operation flowchart. Fig. 9A is a timing chart illustrating the operation of the display device DD according to an embodiment of the present disclosure. Fig. 9B is a timing chart illustrating the operation of the display device DD according to an embodiment of the present disclosure.

[0106] refer to Figure 1 , Figure 2 , Figure 8 , Fig. 9A and Fig. 9B In an embodiment, the driving controller TC receives a mode control signal M-CTRL from the processing unit PU. The mode control signal M-CTRL may include a command ZRE for entering a low power mode and a command for terminating the low power mode.

[0107] The driving controller TC determines whether the command ZRE for entering the low power mode is input (step S300 ). When the command ZRE for entering the low power mode is input, the driving controller TC may change the count reference value based on the operating frequency of the vertical synchronization signal Vsync_FR1 or Vsync_FR2 (step S310 ).

[0108] refer to Fig. 9A , the frequency of the vertical synchronization signal Vsync_FR1 may be 120 Hz. In this case, the count reference value may be 9. Fig. 9B , the frequency of the vertical synchronization signal Vsync_FR2 may be 40 Hz. In this case, the count reference value may be 3. In other words, according to an embodiment of the present disclosure, after receiving the command ZRE for entering the low power mode, by changing the count reference value without changing the operating frequency of the vertical synchronization signal Vsync_FR1 or Vsync_FR2, the time difference Tpa1 and Tpb1 between the "off" operations of the display panel DP may be reduced.

[0109] In an embodiment, for example, the drive controller TC may store a count reference value at a maximum frequency of the vertical synchronization signal Vsync_FR1 or Vsync_FR2 corresponding to the maximum frequency of the variable driving frequency as a first count reference value. When a command ZRE for entering the low power mode or a command for terminating the low power mode is received, the drive controller TC may generate a second count reference value equal to or less than the first count reference value depending on an operating frequency of the vertical synchronization signal corresponding to the variable driving frequency.

[0110] The second count reference value may be obtained based on a value obtained by multiplying a value obtained by dividing the operating frequency by the maximum frequency by the first count reference value. For example, when the vertical synchronization signal Vsync_FR2 is input, the operating frequency may be 40 Hz. Accordingly, "3" obtained by multiplying a value obtained by dividing the operating frequency of 40 Hz by the maximum frequency of 120 Hz by the reference value "9" becomes the second count reference value. When the second count reference value includes a decimal point depending on the operating frequency, the value below the decimal point may be truncated. Accordingly, the second count reference value may have an integer value of "0" or greater.

[0111] The driving controller TC may count the clock of the vertical synchronization signal Vsync_FR1 or Vsync_FR2 (step S320). The driving controller TC compares the count value obtained by counting the clock of the vertical synchronization signal Vsync_FR1 or Vsync_FR2 with the count reference value (step S330). The timing controller TC determines whether the count value is equal to or greater than the count reference value. When the count value is equal to or greater than the count reference value, the driving controller TC may turn off the display panel DP (step S340).

[0112] Even if the screen of the display panel DP is turned off, the drive controller TC can also be kept turned on. The drive controller TC determines whether a command for terminating the low power mode is input (step S350). When a command for terminating the low power mode is input, the drive controller TC can count the clock of the vertical synchronization signal Vsync_FR1 or Vsync_FR2 (step S360). The drive controller TC compares the count value obtained by counting the clock of the vertical synchronization signal Vsync with the count reference value (step S370). The count reference value can be a value based on the operating frequency of the vertical synchronization signal Vsync_FR1 or Vsync_FR2 that is changed. The timing controller TC determines whether the count value is equal to or greater than the count reference value. When the count value is equal to or greater than the count reference value, the drive controller TC can turn on the display panel DP (step S380).

[0113] According to an embodiment of the present disclosure, when a command ZRE for entering a low power mode is received, although the operating frequency of the vertical synchronization signal Vsync_FR1 or Vsync_FR2 may be maintained, the count reference value serving as a reference for changing the states of the control signals CTSa and CTSb may be changed depending on the operating frequency of the vertical synchronization signal Vsync_FR1 or Vsync_FR2. In other words, even if the display panel DP operates at a variable driving frequency, after receiving the command ZRE for entering a low power mode, the drive controller TC may always reduce the time differences TPa1 and TPb1 between the "on" operations of the display panel DP. Accordingly, the efficiency of the electronic device ED (see Figure 1 )’s operation consistency improves product quality.

[0114] In an embodiment of the present disclosure, as described above, a drive controller having a mode control signal received in a drive controller and including a command for entering a low power mode can control a control signal provided to a panel driver, thereby turning off the screen of a display panel. Accordingly, the power consumption of the electronic device can be reduced. In such an embodiment, the drive controller can reduce or eliminate the time difference between the time point when a command for entering or terminating a low power mode is received and the "on" operation or "off" operation of the display panel after receiving the command. In addition, when the operation for entering a low power mode and the operation for terminating a low power mode occur in a mode driven by a variable drive frequency, since the time difference is reduced when switching the "on" operation and the "off" operation of the display panel, the consistency of the operation of the electronic device can be improved, thereby improving the product quality.

[0115] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the concept of the present invention to those skilled in the art.

[0116] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, include: a driving controller that receives an image signal and a signal including a command for entering a low power mode or a command for terminating the low power mode, and generates or receives a first synchronization signal and a second synchronization signal; a panel driver that operates in response to a control signal provided from the drive controller; as well as a display panel controlled by the panel driver, wherein the display panel selectively operates in a first mode for operating at a specific driving frequency or in a second mode for operating at a variable driving frequency, Wherein, the panel driver comprises: a data driving circuit that provides a data signal to the display panel in synchronization with the first synchronization signal, and When receiving the command for entering the low power mode or the command for terminating the low power mode, the driving controller changes the control signal by counting the clock of the second synchronization signal.

2. The display device according to claim 1, in, The frequency of the first synchronization signal is changed to correspond to a driving frequency of the display panel.

3. The display device according to claim 1, in, A maximum frequency of the first synchronization signal corresponding to a maximum frequency of the variable driving frequency is equal to or smaller than a frequency of the second synchronization signal.

4. The display device according to claim 1, in, The second synchronization signal is different from the first synchronization signal.

5. The display device according to claim 1, in, The drive controller generates the second synchronization signal having a frequency obtained by multiplying a frequency of the first synchronization signal by a number of cycles included in one frame corresponding to the frequency of the first synchronization signal.

6. The display device according to claim 1, in, The second synchronization signal and the first synchronization signal are defined by the same signal.

7. The display device according to claim 6, in, the drive controller changes a count reference value serving as a reference for changing a state of the control signal, wherein the drive controller designates a count reference value at a maximum frequency of the first synchronization signal corresponding to a maximum frequency of the variable drive frequency as a first count reference value, and When the drive controller receives the command for entering the low power mode or the command for terminating the low power mode, it generates a second count reference value less than the first count reference value based on the operating frequency of the first synchronization signal corresponding to the variable drive frequency.

8. The display device according to claim 7, in, The second count reference value is obtained based on a value obtained by multiplying a value obtained by dividing the operating frequency and the maximum frequency of the first synchronization signal by the first count reference value.

9. The display device according to claim 6, in, The drive controller generates the second synchronization signal by changing the operating frequency of the first synchronization signal corresponding to the variable driving frequency when receiving the command for entering the low power mode or the command for terminating the low power mode, and Wherein, when the operating frequency of the first synchronization signal is lower than the maximum frequency of the first synchronization signal corresponding to the maximum frequency of the variable driving frequency, the driving controller generates the second synchronization signal by changing the operating frequency of the first synchronization signal to the maximum frequency of the variable driving frequency.

10. The display device according to any one of claims 1 to 9, in, The drive controller, upon receiving the command for entering the low power mode, changes the control signal from a first state to a second state different from the first state by counting the clock of the second synchronization signal.

Images