Memory and manufacturing method thereof, reading and writing method, and electronic device

Abstract

A memory and its manufacturing method, reading and writing method, and electronic device, involving but not limited to semiconductor technology, wherein the memory comprises: a first transistor, a second transistor, and a storage node electrode; the bit line is connected in series with the storage node electrode through the first transistor and the second transistor in sequence; the word line is electrically connected to the first transistor and the second transistor, respectively; the second transistor is a dual-gate transistor, comprising a first gate and a second gate; the first gate is electrically connected to the word line; the storage node electrode is the second gate, and the storage node electrode is electrically connected to the first gate; leakage is effectively reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a memory and a manufacturing method thereof, a reading and writing method, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

[0003] Taking DRAM as an example, conventional DRAM has multiple repetitive "memory cells," each containing a capacitor and a transistor. A capacitor can store one bit of data. After charging and discharging, the amount of charge stored in the capacitor corresponds to the binary data "1" and "0," respectively. The transistor acts as a switch that controls the charging and discharging of the capacitor.

[0004] With the continuous development of Dynamic Random Access Memory (DRAM) technology, there is a demand for semiconductor device designs with new structures and simple processes in order to obtain higher storage capacitance, lower leakage, and higher integration in a planar 1T1C structure. Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] An embodiment of the present disclosure provides a memory, comprising: one or more memory cells disposed on a substrate, and bit lines and word lines;

[0007] The memory cell includes: a first transistor, a second transistor and a storage node electrode;

[0008] The bit line is connected in series with the storage node electrode through the first transistor and the second transistor in sequence;

[0009] The word lines are electrically connected to the first transistor and the second transistor respectively;

[0010] The second transistor is a dual-gate transistor including a first gate and a second gate; the first gate is electrically connected to the word line; the storage node electrode is the second gate, and the storage node electrode is electrically connected to the first gate.

[0011] In some embodiments, the memory cell further includes a first connecting electrode, the first connecting electrode being electrically connected to the first transistor and the second transistor respectively, and at least a portion of the first connecting electrode being disposed opposite to the storage node electrode to form a capacitor.

[0012] In some embodiments, the first connecting electrode extends in a direction parallel to the substrate and is located between the bit line and the storage node electrode. The storage node electrode extends in a direction parallel to the substrate, and at least a portion of the first connecting electrode is arranged face to face with the storage node electrode.

[0013] In some embodiments, the storage node electrode is in a closed loop shape, or the storage node electrode is a ring with at least one opening, or the storage node electrode has two lines extending in a direction parallel to the substrate.

[0014] In some embodiments, a second connecting electrode is further included, wherein the second connecting electrode electrically connects the storage node electrode and the first gate.

[0015] In some embodiments, the second connecting electrode extends in a direction parallel to the substrate and is located on a side of the storage node electrode close to the substrate. The second connecting electrode is connected to the storage node electrode through a via.

[0016] In some embodiments, a groove body extending in a direction perpendicular to the substrate is further included, the word line is arranged in the groove body, the first transistor includes a third gate, and the third gate and the first gate are respectively different regions of the word line extending in a direction perpendicular to the substrate.

[0017] In some embodiments, a conductive film is further included, which is arranged on the side walls and bottom walls of the groove body, and the conductive film surrounds the side walls and bottom walls of the word line through a gate insulating layer. The first transistor includes a first electrode, a second electrode and a first channel, and the first electrode is electrically connected to the second electrode through the first channel; the second transistor includes a third electrode, a fourth electrode and a second channel, and the third electrode is electrically connected to the fourth electrode through the second channel; the first electrode, the first channel, the second electrode, the third electrode and the second channel are respectively different areas of the side walls of the conductive film, and the fourth electrode at least includes the bottom wall of the conductive film.

[0018] In some embodiments, the area where the side wall of the conductive film is connected to the bit line is the first electrode, the area where the side wall of the conductive film is opposite to the third gate is the first channel, and the area where the side wall of the conductive film is connected to the first channel and is located close to the substrate is the second electrode; the area where the side wall of the conductive film is opposite to the first gate is the second channel, and the area where the side wall of the conductive film is located between the second channel and the second electrode is the third electrode.

[0019] In some embodiments, the bit lines extend in a direction parallel to the substrate; and the word lines extend in a direction perpendicular to the substrate.

[0020] The present disclosure also provides a method for manufacturing a memory, wherein the memory includes one or more memory cells disposed on a substrate, as well as a bit line and a word line. The memory cell includes: a first transistor, a second transistor, and a storage node electrode; the bit line is connected in series with the storage node electrode through the first transistor and the second transistor in sequence; the word line is electrically connected to the first transistor and the second transistor, respectively; the second transistor is a dual-gate transistor including a first gate and a second gate; the first gate is electrically connected to the word line; the storage node electrode is the second gate, and the storage node electrode is electrically connected to the first gate. The memory manufacturing method includes:

[0021] forming a storage node electrode on the substrate;

[0022] forming a bit line on a side of the storage node electrode away from the substrate;

[0023] forming a groove body extending in a direction perpendicular to the substrate;

[0024] A conductive film, a gate insulating layer and a word line are sequentially formed in the trough body, and different regions of the conductive film respectively form two electrodes and a channel of the first transistor, and two electrodes and a channel of the second transistor; different regions of the word line form the gate of the first transistor and the first gate of the second transistor.

[0025] The present disclosure also provides a method for reading and writing a memory, including:

[0026] When writing to the memory, a first turn-on potential is applied to the word line, turning on the first transistor and the second transistor; the stored information passes through the bit line, the first transistor and the second transistor in sequence, and is input into the storage node electrode;

[0027] When the memory is read, a second turn-on potential is applied to the word line to turn on the first transistor and the second transistor; the storage information of the storage node electrode is output in sequence through the second transistor, the first transistor and the bit line.

[0028] An embodiment of the present disclosure further provides an electronic device, characterized in that it includes any of the aforementioned memories.

[0029] The bit line of the memory in the embodiment of the present disclosure is connected in series with the storage node electrode through the first transistor and the second transistor. The first transistor and the second transistor have a switching function. When the memory is turned off, the first transistor and the second transistor have a turning-off function at the same time, which effectively reduces leakage.

[0030] The memory of the embodiment of the present disclosure is composed of a word line, a bit line, a first transistor and a second transistor, and has a simple structure and high integration.

[0031] The word lines of the memory in the embodiment of the present disclosure are electrically connected to the gate of the first transistor and the two gates of the second transistor, respectively, so that the word lines can simultaneously control the gate of the first transistor and the two gates of the second transistor, so that the first transistor and the second transistor can be turned on or off at the same time, effectively reducing memory leakage.

[0032] The second transistor of the memory in the embodiment of the present disclosure is a dual-gate structure, which provides the gate control capability of the first transistor by using the storage node electrode as the second gate of the memory, and at least part of the storage node electrode is arranged opposite to the first gate of the first transistor, thereby increasing the capacitance of the storage node electrode.

[0033] The memory of the embodiment of the present disclosure forms a capacitor through the storage node electrode and the first connection electrode, thereby increasing the capacitance of the storage node electrode.

[0034] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0035] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution.

[0037] Figure 1 An equivalent circuit diagram of a memory provided for an exemplary embodiment;

[0038] Figure 2 A schematic cross-sectional view of a memory provided as an exemplary embodiment;

[0039] Figure 3a A schematic diagram of a memory device after forming a second connection electrode during manufacturing of the memory device according to an exemplary embodiment;

[0040] Figure 3b A schematic diagram of a memory after a storage node electrode is formed during the manufacturing process of the memory provided by the exemplary embodiment;

[0041] Figure 3c A schematic diagram of a memory device after forming a second isolation layer and a via hole in a manufacturing process provided by an exemplary embodiment;

[0042] Figure 3d A schematic diagram of a memory device after forming a third connection electrode during the manufacturing process of the memory device according to an exemplary embodiment;

[0043] Figure 3e A schematic diagram of a memory device after forming a third insulating layer, a first connecting electrode, a fourth insulating layer, a bit line, and a fifth insulating layer during manufacturing of the memory device according to an exemplary embodiment;

[0044] Figure 3f A schematic diagram of a memory after a slot is formed during the manufacturing process of an exemplary embodiment is provided. DETAILED DESCRIPTION

[0045] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0046] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0047] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0048] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0049] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0050] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0051] In this disclosure, a transistor refers to an element including at least three terminals: a gate, a drain electrode, and a source electrode. A transistor has a first channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the first channel region, and the source electrode. In this disclosure, the first channel region refers to the region through which current primarily flows.

[0052] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0053] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0054] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0055] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0056] As used herein, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0057] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0058] Conventional memory cells contain either 2T0C or 1T1C circuits. In 2T0C circuits, a write word line, write bit line, read word line, and read bit line are required to read and write stored information. Furthermore, the storage node is typically located between two transistors, resulting in high leakage current, necessitating strict leakage requirements for the write transistor. In 1T1C circuits, the storage capacitor also exhibits high leakage current.

[0059] The embodiments of the present disclosure provide a novel memory, comprising: one or more novel memory cells disposed on a substrate, as well as bit lines and word lines;

[0060] The memory cell includes: a first transistor, a second transistor and a storage node electrode;

[0061] The bit line is connected in series with the storage node electrode through the first transistor and the second transistor in sequence; it can be understood that the bit line is connected to the first transistor, the first transistor and the second transistor are connected in series, and the back gate of the second transistor is connected to the source or drain electrode of the second transistor.

[0062] The word line is electrically connected to the first transistor and the second transistor at the same time;

[0063] The second transistor is a dual-gate transistor, including a first gate and a second gate; the first gate is electrically connected to the word line; the second gate is the back gate; the storage node electrode is the second gate, and the storage node electrode is electrically connected to the first gate (source or drain electrode); structurally, the storage node electrode is located outside the channel of the second transistor, forming a storage capacitor with the side wall of the first gate.

[0064] In some embodiments, the memory cell further includes a first connecting electrode, the first connecting electrode being electrically connected to the first transistor and the second transistor respectively, and at least a portion of the first connecting electrode being disposed opposite to the storage node electrode to form a capacitor.

[0065] In some embodiments, the first connecting electrode extends in a direction parallel to the substrate and is located between the bit line and the storage node electrode. The storage node electrode extends in a direction parallel to the substrate, and at least a portion of the first connecting electrode is arranged face to face with the storage node electrode.

[0066] The memory disclosed herein is described below by way of some exemplary embodiments.

[0067] Figure 1 An equivalent circuit diagram of a memory provided for an exemplary embodiment. In an exemplary embodiment, as Figure 1 As shown, the memory cell can be a 2T0C structure. The memory cell includes: a bit line BL, a word line WL, a first transistor T1, a second transistor T2, and a storage node electrode N. The second transistor T2 has a dual-gate structure. The bit line BL is connected in series with the storage node electrode N through the first transistor T1 and the second transistor T2.

[0068] Figure 1 The two transistors are p-type transistors, however, the inventive concept of the present application is also applicable to the case where the two transistors are n-type transistors, or one transistor is n-type and the other is p-type.

[0069] In an exemplary embodiment, Figure 1 As shown, the word line WL is electrically connected to the gate of the first transistor T1 and one gate of the second transistor T2, respectively; the first end (first electrode) of the first transistor T1 is electrically connected to the bit line BL, the second end (second electrode) of the first transistor T1 is electrically connected to the first end (third electrode) of the second transistor T2, and the gate of the first transistor T1 is electrically connected to the word line WL; the first end (third electrode) of the second transistor T2 is electrically connected to the second end (second electrode) of the first transistor T1, the second end (fourth electrode) of the second transistor T2 is electrically connected to the storage node electrode N, the first gate of the second transistor T2 is electrically connected to the word line WL, and the second gate of the second transistor T2 is electrically connected to the storage node electrode N. The storage node electrode N can serve as the second gate of the second transistor T2, and the second end (fourth electrode) of the second transistor T2 is electrically connected to the second gate of the second transistor T2.

[0070] The bit line of the memory in the embodiment of the present disclosure is connected in series with the storage node electrode through the first transistor and the second transistor. The first transistor and the second transistor have a switching function. When the memory is turned off, the first transistor and the second transistor have a turning-off function at the same time, which effectively reduces leakage.

[0071] The memory of the embodiment of the present disclosure is composed of a word line, a bit line, a first transistor and a second transistor, and has a simple structure and high integration.

[0072] The word lines of the memory in the embodiment of the present disclosure are electrically connected to the gate of the first transistor and the two gates of the second transistor, respectively, so that the word lines can simultaneously control the gate of the first transistor and the two gates of the second transistor, so that the first transistor and the second transistor can be turned on or off at the same time, effectively reducing memory leakage.

[0073] Figure 2 A schematic cross-sectional view of a memory cell of a memory provided in an exemplary embodiment. In an exemplary embodiment, Figure 2 As shown, the memory of the present application includes: one or more memory cells arranged on a substrate 101, as well as a bit line 1 and a word line 2. In a direction perpendicular to the substrate, a memory cell includes: a first insulating layer 11 arranged on the substrate 101, a second connecting electrode 22 arranged on a side of the first insulating layer 11 away from the substrate 101, a second insulating layer 12 arranged on a side of the second connecting electrode 22 away from the substrate 101, a storage node electrode N arranged on a side of the second insulating layer 12 away from the substrate 101, a third insulating layer 13 arranged on a side of the storage node electrode N away from the substrate 101, a first connecting electrode 21 arranged on a side of the third insulating layer 13 away from the substrate 101, a fourth insulating layer 14 arranged on a side of the first connecting electrode 21 away from the substrate 101, a bit line 1 arranged on a side of the fourth insulating layer 14 away from the substrate 101, a fifth insulating layer 15 arranged on a side of the bit line 1 away from the substrate 101, and a first isolation layer 31 arranged on a side of the fifth insulating layer 15 away from the substrate 101.

[0074] In an exemplary embodiment, Figure 2 As shown, a memory cell further includes a trench 40 extending in a direction perpendicular to the substrate 101. The trench 40 extends from the surface of the fifth insulating layer 15 away from the substrate 101, sequentially passes through the fifth insulating layer 15, the bit line 1, the fourth insulating layer 14, the first connecting electrode 21, the third insulating layer 13, and the second insulating layer 12, and extends to the surface of the second connecting electrode 22 away from the substrate 101, exposing at least a portion of the surface of the second connecting electrode 22 away from the substrate 101. The trench 40 includes sidewalls and a bottom wall. The bottom wall of the trench 40 is the surface of the second connecting electrode 22 away from the substrate 101. The sidewalls of the trench 40 expose the side surfaces of the first connecting electrode 21 and the side surfaces of the bit line 1.

[0075] In an exemplary embodiment, Figure 2As shown, a memory cell further includes a conductive film 50 and a gate insulating layer 60. The conductive film 50 covers at least the sidewalls and bottom wall of the groove body 40. Different regions of the conductive film 50 are in contact with the side surface of the exposed first connection electrode 21 and the side surface of the bit line 1, respectively. The gate insulating layer 60 is disposed on the conductive film 50 and covers the sidewalls and bottom wall of the groove body 40 via the conductive film 50. The conductive film 50 and the gate insulating layer 60 can be sequentially formed on the sidewalls and bottom wall of the groove body 40 using an atomic deposition process.

[0076] In an exemplary embodiment, Figure 2 As shown, the word line 2 is filled in the groove 40 via a conductive film 50 and a gate insulating layer 60. The word line 2 is insulated from the conductive film 50 by the gate insulating layer 60, and different regions of the word line 2 are connected to the side surface of the exposed first connection electrode 21 and the side surface of the bit line 1 through the gate insulating layer 60 and the conductive film 50, respectively. The conductive film 50 surrounds the sidewalls and bottom wall of the word line 2 via the gate insulating layer 60.

[0077] In an exemplary embodiment, Figure 2 As shown, the first transistor T1 includes a third gate, a first electrode, a second electrode and a first channel, and the first electrode is electrically connected to the second electrode through the first channel; the second transistor T2 includes a first gate, a second gate, a third electrode, a fourth electrode and a second channel, and the third electrode is electrically connected to the fourth electrode through the second channel; the third gate of the first transistor T1 and the first gate of the second transistor T2 are respectively different regions of the word line 2 extending in a direction perpendicular to the substrate 101, and the third gate is located on the side of the first gate away from the substrate, so that one word line 2 can control the first transistor T1 and the second transistor T2 at the same time.

[0078] In an exemplary embodiment, Figure 2 As shown, the first electrode, the first channel, and the second electrode of the first transistor T1, and the third electrode and the second channel of the second transistor T2 are different regions arranged in sequence along the side wall of the conductive film 50 in a direction close to the substrate 101, and the fourth electrode of the second transistor T2 includes at least the bottom wall of the conductive film 50.

[0079] In an exemplary embodiment, Figure 2As shown, the area where the side wall of the conductive film 50 is connected to the bit line 1 is the first electrode of the first transistor T1; the area where the side wall of the conductive film 50 is opposite to the third gate is the first channel of the first transistor T1; the area where the side wall of the conductive film 50 is connected to the first connecting electrode 21 is the second electrode of the first transistor T1, and the second electrode is located on the side of the first channel close to the substrate and is connected to the first channel; the area where the side wall of the conductive film 50 is opposite to the first gate is the second channel of the second transistor T2, and the area where the side wall of the conductive film 50 is located between the second channel and the second electrode is the third electrode of the second transistor T2.

[0080] In an exemplary embodiment, the conductive film 50 may be a metal oxide conductive film layer.

[0081] In one exemplary embodiment, the metal oxide layer may be made of indium gallium zinc oxide (IGZO), InGaO, ITO, IZO, or a metal oxide containing In and / or Sn. When the metal oxide material is IGZO, the transistor has a low leakage current (less than or equal to 1E-15A to 1E-10A), where 1E-15A refers to 10 to the negative 15th power of amperes and 1E-10A refers to 10 to the negative 10th power of amperes, thereby ensuring a low refresh rate for the dynamic memory. It should be noted that the material of the metal oxide can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0082] In an exemplary embodiment, Figure 2 As shown, the second transistor T2 is a dual-gate transistor including a first gate and a second gate. The first gate is a portion of the word line 2. The storage node electrode N is the second gate. The storage node electrode N is located outside the second channel of the second transistor T2 and is insulated from the second channel by a second isolation layer 32. At least a portion of the sidewall of the storage node electrode N is disposed opposite the first gate of the second transistor T2, forming a storage capacitor for storing information.

[0083] The second transistor of the memory of the embodiment of the present disclosure has a dual-gate structure, and the storage node electrode is used as the second gate of the memory, thereby providing the gate control capability of the first transistor and increasing the capacitance of the storage node electrode.

[0084] In an exemplary embodiment, Figure 2 As shown, the second connection electrode 22 extends in a direction parallel to the substrate 101 and is located between the storage node electrode N and the second insulating layer 12. A via is provided in the second insulating layer 12, and the storage node electrode N is connected to the second connection electrode 22 through the via. The second connection electrode 22 is connected to the bottom wall of the conductive film 50. The storage node electrode N is electrically connected to the bottom wall of the conductive film 50 through the second connection electrode 22, so that the storage node electrode N is electrically connected to the fourth electrode of the second transistor T2.

[0085] In an exemplary embodiment, Figure 2 As shown, the first connection electrode 21 is electrically connected to the second electrode of the first transistor T1 and the third electrode of the second transistor T2. At least a portion of the first connection electrode 21 is disposed opposite to the storage node electrode N to form a capacitor.

[0086] The memory of the embodiment of the present disclosure forms a capacitor through the storage node electrode and the first connection electrode, thereby increasing the capacitance of the storage node electrode.

[0087] In an exemplary embodiment, Figure 2 As shown, the first connecting electrode 21 extends in a direction parallel to the substrate and is located between the bit line 1 and the storage node electrode N. The storage node electrode N extends in a direction parallel to the substrate. At least a portion of the first connecting electrode 21 is arranged to be opposite to the storage node electrode N to increase the capacitance of the capacitor.

[0088] In an exemplary embodiment, the storage node electrode N surrounds a portion or all of a sidewall of the second channel, and the surrounding area is parallel to the substrate.

[0089] In an exemplary embodiment, the storage node electrode N can be a closed loop, and the storage node electrode N surrounds the second channel sidewall of the second transistor T2 to form a ring gate. Alternatively, the storage node electrode N can be a ring with at least one opening. For example, the storage node electrode N surrounds the second channel sidewall of the second transistor T2 to form a "U"-shaped gate.

[0090] In an exemplary embodiment, the storage node electrode N is a single-side gate in the second channel corresponding region, or the storage node electrode N has two lines extending in a direction parallel to the substrate and is a double-side gate in the second channel corresponding region.

[0091] In an exemplary embodiment, the storage node electrode N surrounds a portion of the sidewall of the second channel, and the surrounding area is parallel to the substrate.

[0092] In an exemplary embodiment, Figure 2 As shown, the bit line 1 extends in a direction parallel to the substrate 101 ; the word line 2 extends in a direction perpendicular to the substrate 101 , and the extending directions of the bit line 1 and the word line 2 are perpendicular.

[0093] The present disclosure also provides a method for manufacturing a memory, wherein the memory includes one or more memory cells disposed on a substrate, as well as a bit line and a word line. The memory cell includes: a first transistor, a second transistor, and a storage node electrode; the bit line is connected in series with the storage node electrode through the first transistor and the second transistor in sequence; the word line is electrically connected to the first transistor and the second transistor, respectively; the second transistor is a dual-gate transistor including a first gate and a second gate; the first gate is electrically connected to the word line; the storage node electrode is the second gate, and the storage node electrode is electrically connected to the first gate. The memory manufacturing method includes:

[0094] forming a storage node electrode on the substrate;

[0095] forming a bit line on a side of the storage node electrode away from the substrate;

[0096] forming a groove body extending in a direction perpendicular to the substrate;

[0097] A conductive film, a gate insulating layer and a word line are sequentially formed in the trough body, and different regions of the conductive film respectively form two electrodes and a channel of the first transistor, and two electrodes and a channel of the second transistor; different regions of the word line form the gate of the first transistor and the first gate of the second transistor.

[0098] The technical solution of this embodiment will be further explained below using the manufacturing process of the memory device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can use known coating processes; and etching can use known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin layer of a certain material produced on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, it is referred to as a "thin film" before patterning and a "layer" after patterning. The "layer" after patterning or photolithography contains at least one "pattern."

[0099] In an exemplary embodiment, the memory may be any of the above-mentioned memories, and the manufacturing process of the memory may include:

[0100] Step 101: forming a second connecting electrode.

[0101] Forming the second connection electrode includes: forming a first insulating film and a first conductive film on the substrate 1 in sequence, and forming the first insulating film into a first insulating layer 11 and the first conductive film into a second connection electrode 22 through a patterning process. Figure 3a shown.

[0102] Step 102: forming a storage node electrode.

[0103] The formation of the storage node electrode includes: forming a second insulating film and a second conductive film on the second connection electrode 22 on the basis of the substrate 1 having the aforementioned pattern, forming the second insulating film into a second insulating layer 12 through a patterning process, and forming the second conductive film into a storage node electrode N, as shown in FIG. Figure 3b The storage node electrode N is ring-shaped, and a groove 60 is formed in the storage node electrode N and the second insulating layer 12 , and the groove 60 exposes the surface of the second connection electrode 22 .

[0104] Step 103: forming a second isolation layer and vias.

[0105] The formation of the second isolation layer and the via hole includes: forming a first isolation film on the storage node electrode N on the basis of the substrate 1 having the aforementioned pattern, forming the first isolation film into a second isolation layer 32 through a patterning process, and forming a via hole 70 in the storage node electrode N and the second insulating layer 12, the second isolation layer 32 filling the groove 60, the surface of the second isolation layer 32 being substantially flush with the surface of the storage node electrode N, the via hole 70 penetrating the storage node electrode N and the second insulating layer 12, exposing the surface of the second connection electrode 22, as shown in FIG. Figure 3c shown.

[0106] Step 104: forming a third connecting electrode.

[0107] Forming the third connection electrode includes: forming a third connection electrode 80 in the via hole 70 on the basis of the substrate 1 having the aforementioned pattern, the third connection electrode 80 filling the via hole 70, and connecting the storage node electrode N with the second connection electrode 22, as shown in FIG. Figure 3d shown.

[0108] Step 105 , forming a third insulating layer, a first connecting electrode, a fourth insulating layer, a bit line, and a fifth insulating layer.

[0109] The formation of the third insulating layer, the first connecting electrode, the fourth insulating layer, the bit line and the fifth insulating layer includes: on the basis of the substrate 1 formed with the aforementioned pattern, sequentially forming a third insulating film, a third conductive film, a fourth insulating film, a fourth conductive film and a fifth insulating film on the storage node electrode N, and through a patterning process, forming the third insulating film into the third insulating layer 13, forming the third conductive film into the first connecting electrode 21, forming the fourth insulating film into the fourth insulating layer 14, forming the fourth conductive film into the bit line 1, and forming the fifth insulating film into the fifth insulating layer 15, as shown in FIG. Figure 3e shown.

[0110] Step 106: forming a tank body.

[0111] The formation of the groove body includes: forming a groove body 40 by a patterning process on the substrate 1 formed with the aforementioned pattern, wherein the groove body 40 extends from the surface of the fifth insulating layer 15 away from the substrate 101, sequentially penetrates the fifth insulating layer 15, the bit line 1, the fourth insulating layer 14, the first connecting electrode 21, the third insulating layer 13 and the second insulating layer 12, and extends to the surface of the second connecting electrode 22 away from the substrate 101, as shown in FIG. Figure 3f shown.

[0112] Step 107: forming a conductive film and a gate insulating layer.

[0113] The formation of the conductive film and the gate insulating layer includes: forming a conductive film 50 on the sidewalls and bottom wall of the groove body 40 by an atomic deposition process on the substrate 1 having the aforementioned pattern formed thereon; subsequently, forming a gate insulating layer 60 on the conductive film 50 by an atomic deposition process, the gate insulating layer 60 covering the sidewalls and bottom wall of the groove body 40 via the conductive film 50; subsequently, forming a word line 2 in the groove body 40 where the gate insulating layer 60 remains, filling the groove body 40 via the conductive film 50 and the gate insulating layer 60; subsequently, forming a first isolation layer 31 on the word line 2, the first isolation layer 31 covering at least the sidewalls of the region where the word line 2 is located on the groove body 40, as shown in FIG. Figure 2 shown.

[0114] The word line 2 forms the third gate of the first transistor T1 and the first gate of the second transistor T2 in different regions within the tank 40. The storage node electrode N serves as the second gate of the second transistor T2. The first and second gates form a dual-gate structure for the second transistor T2. The conductive film 50 forms the first electrode, first channel, and second electrode of the first transistor T1, as well as the third electrode and second channel of the second transistor T2, in different regions along the sidewalls of the tank 40. The fourth electrode of the second transistor T2 comprises at least the bottom wall of the conductive film 50 within the tank 40.

[0115] The manufacturing method of the memory of the present application simplifies the production process, reduces production costs, and is easy to manufacture.

[0116] Taking the case where both transistors are p-type transistors as an example, the memory reading and writing method of the exemplary embodiment of the present application includes:

[0117] When writing to the memory of the present application, a first turn-on potential is applied to the word line WL. The word line WL inputs the first turn-on potential into the gate of the first transistor T1 and the two gates of the second transistor T2 (the first gate and the second gate), turning on the first transistor T1 and the second transistor T2. The stored information (for example, 1 or 0) is sequentially transmitted from the bit line BL through the first transistor T1 and the second transistor T2 and input into the storage node electrode N. A first turn-off potential is applied to the word line WL. The word line WL inputs the first turn-off potential into the two gates of the first transistor T1 and the second transistor T2 (the first gate and the second gate), turning off the first transistor T1 and the second transistor T2. The stored information (for example, 1 or 0) is stored in the storage node electrode N, completing the process of writing the stored information. The first turn-on potential can be a low potential, and the first turn-off potential can be a high potential.

[0118] When reading from the memory of the present application, a second turn-on potential is applied to the word line WL. The word line WL inputs the second turn-on potential into the gate of the first transistor T1 and the two gates of the second transistor T2 (the first gate and the second gate), turning on the first transistor T1 and the second transistor T2. The stored information (e.g., 1 or 0) of the storage node electrode N passes through the second transistor T2 and the first transistor T1 in sequence and is output from the bit line BL, thereby realizing the reading of the stored information. The second turn-on potential can be a low potential.

[0119] In some embodiments, when both transistors are n-type transistors, the first turn-on potential and the second turn-on potential are both high potentials, and the first turn-off potential may be a low potential.

[0120] The present disclosure also provides an electronic device comprising the memory device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0121] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A memory, characterized in that: include: One or more memory cells, bit lines, and word lines disposed on a substrate; The memory cell includes: a first transistor, a second transistor and a storage node electrode; The bit line is connected in series with the storage node electrode through the first transistor and the second transistor in sequence; The word lines are electrically connected to the first transistor and the second transistor respectively; The second transistor is a dual-gate transistor, including a first gate and a second gate; the first gate is electrically connected to the word line; the storage node electrode is the second gate, and the storage node electrode is electrically connected to the first gate; The storage node electrode is in a closed loop shape, or the storage node electrode is a ring with at least one opening, or the storage node electrode is a line having two lines extending in a direction parallel to the substrate.

2. The memory according to claim 1, wherein: The memory cell further includes a first connection electrode electrically connected to the first transistor and the second transistor respectively. At least a portion of the first connection electrode is disposed opposite to the storage node electrode to form a capacitor.

3. The memory according to claim 2, wherein: The first connecting electrode extends in a direction parallel to the substrate and is located between the bit line and the storage node electrode. The storage node electrode extends in a direction parallel to the substrate, and at least a portion of the first connecting electrode is arranged face to face with the storage node electrode.

4. The memory according to claim 1, wherein: A second connecting electrode is further included, and the second connecting electrode electrically connects the storage node electrode and the first gate.

5. The memory according to claim 4, wherein: The second connecting electrode extends in a direction parallel to the substrate and is located on a side of the storage node electrode close to the substrate. The second connecting electrode is connected to the storage node electrode through a via hole.

6. The memory according to any one of claims 1 to 5, characterized in that: It also includes a groove body extending in a direction perpendicular to the substrate, the word line is arranged in the groove body, the first transistor includes a third gate, and the third gate and the first gate are respectively different regions of the word line extending in a direction perpendicular to the substrate.

7. The memory according to claim 6, wherein: It also includes a conductive film, which is arranged on the side walls and bottom walls of the groove body, and the conductive film surrounds the side walls and bottom walls of the word line through the gate insulation layer. The first transistor includes a first electrode, a second electrode and a first channel, and the first electrode is electrically connected to the second electrode through the first channel; the second transistor includes a third electrode, a fourth electrode and a second channel, and the third electrode is electrically connected to the fourth electrode through the second channel; the first electrode, the first channel, the second electrode, the third electrode and the second channel are respectively different areas of the side walls of the conductive film, and the fourth electrode at least includes the bottom wall of the conductive film.

8. The memory according to claim 7, wherein: The area where the side wall of the conductive film is connected to the bit line is the first electrode, the area where the side wall of the conductive film is opposite to the third gate is the first channel, and the area where the side wall of the conductive film is connected to the first channel and is located close to the substrate is the second electrode; the area where the side wall of the conductive film is opposite to the first gate is the second channel, and the area where the side wall of the conductive film is located between the second channel and the second electrode is the third electrode.

9. The memory according to any one of claims 1 to 5, characterized in that: The bit lines extend in a direction parallel to the substrate; and the word lines extend in a direction perpendicular to the substrate.

10. A method for reading and writing a memory according to any one of claims 1 to 9, characterized in that: include: When the memory is written, a first turn-on potential is applied to the word line to turn on the first transistor and the second transistor; Allowing storage information to pass through the bit line, the first transistor, and the second transistor in sequence and be input into the storage node electrode; When the memory is read, a second turn-on potential is applied to the word line to turn on the first transistor and the second transistor; The storage information of the storage node electrode is outputted through the second transistor, the first transistor and the bit line in sequence.

11. A method for manufacturing a memory, characterized in that: The memory includes one or more memory cells disposed on a substrate, as well as a bit line and a word line. The memory cell includes: a first transistor, a second transistor, and a storage node electrode; the bit line is connected in series with the storage node electrode through the first transistor and the second transistor in sequence; the word line is electrically connected to the first transistor and the second transistor, respectively; the second transistor is a dual-gate transistor including a first gate and a second gate; the first gate is electrically connected to the word line; the storage node electrode is the second gate, and the storage node electrode is electrically connected to the first gate; a method for manufacturing the memory includes: A storage node electrode is formed on a substrate; the storage node electrode is in a closed loop, or a ring with at least one opening, or two lines extending in a direction parallel to the substrate; forming a bit line on a side of the storage node electrode away from the substrate; forming a groove body extending in a direction perpendicular to the substrate; A conductive film, a gate insulating layer and a word line are sequentially formed in the trough body, and different regions of the conductive film respectively form two electrodes and a channel of the first transistor, and two electrodes and a channel of the second transistor; different regions of the word line form the gate of the first transistor and the first gate of the second transistor.

12. An electronic device, characterized in that: The method comprises the memory according to any one of claims 1 to 9.

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