System and method for testing memory

Abstract

The invention provides a system for testing a memory. The system includes a memory device and a processor. The memory device operates at a supply voltage having a first value. The processor is operatively coupled to the memory device and is configured to: generate a write instruction to write first data to the memory device; generating a first read instruction to read the second data from the memory device and compare the first data with the second data; adjusting the supply voltage to have a second value different from the first value; and generating a second read instruction to read the third data from the memory device and compare the first data with the third data to generate a test result. The system provided by the invention is helpful for improving the testing efficiency.

Description

Technical Field

[0001] The present disclosure relates to a system and method for testing a memory, and more particularly to a system and method for testing a memory operating at different voltages. Background Art

[0002] With the rapid development of memory technology, memories are designed with smaller sizes and higher density circuits. Increasing the density of circuits is beneficial to the speed and performance of memories, but higher error rates and manufacturing difficulties arise. Generally speaking, in order to ensure the reliability and yield of products, memory testing is indispensable. Summary of the invention

[0003] In one embodiment of the present disclosure, a system for testing a memory is provided. The system includes a memory device and a processor. The memory device operates with a supply voltage having a first value. The processor is operatively coupled to the memory device and is used to: generate a write instruction to write first data to the memory device; generate a first read instruction to read second data from the memory device and compare the first data with the second data; adjust the supply voltage to a second value different from the first value; and generate a second read instruction to read third data from the memory device and compare the first data with the third data to generate a test result.

[0004] In some embodiments, the processor is further configured to: adjust the supply voltage to a third value having a value different from the first value and the second value, wherein the second value is a minimum operating voltage value specified by the memory device and the third value is a maximum operating voltage value specified by the memory device; and generate a third read instruction to read fourth data from the memory device and compare the first data and the fourth data.

[0005] In some embodiments, the processor is further used to: adjust the supply voltage to have a third value, the second value is the first value plus the increased value, and the third value is the second value plus the increased value; and generate a third read instruction to read fourth data from the memory device and compare the first data and the fourth data.

[0006] In some embodiments, the processor is further configured to determine whether the memory device complies with the specification based on a comparison between the first data and the second data, and a comparison between the first data and the third data.

[0007] In some embodiments, reading the second data from the memory device includes performing a read operation on a memory cell into which the first data is written to obtain the second data.

[0008] In one embodiment of the present disclosure, a method for testing a memory is provided, comprising: initializing a memory device; operating the memory device with a first voltage group and writing write data to the memory device; performing a first read operation on the memory device to compare the write data and the first read data; after performing the first read operation, directly operating the memory device with a second voltage group different from the first voltage group and performing a second read operation on the memory device to obtain second read data; and comparing the write data and the second read data to generate a test result.

[0009] In some embodiments, the method further includes: operating the memory device with a third voltage group different from the first and second voltage groups and performing a third read operation on the memory device to obtain third read data, wherein each of the second voltage groups is less than a corresponding one of the first voltage group, and each of the third voltage group is greater than a corresponding one of the first voltage group; and comparing the write data and the third read data.

[0010] In some embodiments, the method further includes: generating an instruction to terminate the test of the memory device according to comparing the written data with the first read data and comparing the written data with the second read data.

[0011] In some embodiments, the first and second read operations correspond to the same memory address.

[0012] In some embodiments, each voltage in the second voltage group is higher than the corresponding voltage in the first voltage group and the method further includes: operating the memory device with a third voltage group and performing a third read operation on the memory device to obtain third read data, each voltage in the third voltage group is higher than the corresponding voltage in the second voltage group; and comparing the write data and the third write data.

[0013] In some embodiments, the method further includes: when the write data is not equal to the first read data, recording the value of the first voltage group in the test result; and when the write data is not equal to the second read data, recording the value of the second voltage group in the test result.

[0014] In one embodiment of the present disclosure, a method for testing a memory is provided, comprising: (a) generating a first list of multiple voltage values; (b) initializing a memory device and setting a supply voltage of the memory device according to the first list; (c) performing a first write operation of first write data on the memory device; (d) reading the memory device; (e) changing the value of the supply voltage according to the first list and reading the memory device; and (f) repeating step (e) according to the first list.

[0015] In some embodiments, step (d) includes recording the read data in a second list and step (e) includes adding the new read data to the second list.

[0016] In some embodiments, step (f) includes terminating the repeating when the new read data is not equal to the first write data.

[0017] In some embodiments, the method further includes: comparing each of the plurality of data in the second list with the first write data and when the data in the second list is not equal to the first write data, adding a value corresponding to the supply voltage to a third list; and determining whether the memory device has a defect according to the third list.

[0018] In some embodiments, the first list is a series of these voltage values.

[0019] In some embodiments, the method, wherein step (e) further comprises: after the read operation, directly changing the value of the supply voltage according to the first list and reading the memory device.

[0020] In some embodiments, the first write operation corresponds to a first memory address and the method further includes: changing a value of a supply voltage and performing a second write operation of the first write data, the second write operation corresponding to a memory address of the memory device.

[0021] In some embodiments, the order of the voltage values ​​in the first list is based on the failure rates of the memory devices when operating at the voltage values ​​respectively.

[0022] In some embodiments, the method further includes: after step (f), directly operating the memory device with a third voltage group different from the first and second voltage groups and writing second write data into the memory device; performing a third read operation on the memory device to obtain third read data; and comparing the second write data and the third read data to generate a test result. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The aspects of one embodiment of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0024] Figure 1 is a schematic diagram of a system according to some embodiments of the present disclosure.

[0025] Figure 2 According to some embodiments of the present disclosure, Figure 1 A flowchart of an example of a systematic method. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples of different features for achieving the provided objectives. The following describes specific examples of components and arrangements to simplify an embodiment of the present invention. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include an embodiment in which the first and second features are directly contacted to form, and may also include an embodiment in which additional features are formed between the first and second features so that the first and second features may not be directly contacted. In addition, the present disclosure may repeat component symbols or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself specify the relationship between the various embodiments or configurations discussed.

[0027] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any term discussed herein, is illustrative only and in no way limits the scope and meaning of an embodiment of the case or any exemplary term. Likewise, an embodiment of the case is not limited to the various embodiments given in this specification.

[0028] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0029] The reference to "one embodiment" or "some embodiments" in the specification means that the specific features, structures, implementations or characteristics described in the embodiment are included in at least one embodiment of the present invention. Therefore, when "in one embodiment" or "in some embodiments" is mentioned in different places in the specification, it does not necessarily refer to the same embodiment. These features, structures, implementations or characteristics can be combined into one or more embodiments in any suitable manner.

[0030] Further, for ease of description, spatially relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] As used herein, "approximately", "about", "approximately" or "substantially" shall generally refer to any approximation of a given value or range, where it varies depending on the various fields involved, and its scope shall be consistent with the broadest interpretation understood by those skilled in the art to cover all such modifications and similar structures. In some embodiments, it shall generally refer to within 20 percent of a given value or range, preferably within 10 percent, and more preferably within 5 percent. The numerical values ​​given herein are approximate, meaning that if not explicitly stated, the terms "approximately", "about", "approximately" or "substantially" can be inferred, or other approximate values ​​are meant.

[0032] refer to Figure 1 . Figure 1 FIG. 1 is a schematic diagram of a system 100 according to some embodiments of the present disclosure. For illustration, the system 100 includes a processor 110, a memory device 120, and a power supply 130. Figure 1 As shown, according to some embodiments, the processor 110 is operatively coupled to the memory device 120 and the power supply 130, and the memory device 120 is operatively coupled to the power supply 130. In some embodiments, the system 100 is used to test the memory device 120. For example, the system 100 is used to test the effect of changing the operating voltage of the memory device 120, or to test the effective operating voltage of the memory device 120 (the supply voltage that enables the memory device 120 to operate correctly). Further details will be discussed in the following paragraphs.

[0033] In some embodiments, the processor 110 includes a central processing unit (CPU), or other programmable general-purpose or special-purpose micro control unit (MCU), microprocessor, digital signal processor (DSP), programmable controller, application specific integrated circuit (ASIC), graphics processing unit (GPU), arithmetic logic unit (ALU), complex programmable logic device (CPLD), field programmable gate array (FPGA), or other similar components or combinations of the above components.

[0034] In some embodiments, memory device 120 is a hardware component that stores data. Figure 1 As shown, according to some embodiments, the memory device 120 includes a memory array 121 and a memory controller 122. The memory array 121 includes a plurality of memory cells 123 (storage circuits) arranged in a two-dimensional or three-dimensional array. According to different embodiments, the memory cells 123 include volatile memory cells, non-volatile memory cells, or a combination thereof. In some embodiments, each memory cell 123 is implemented as a dynamic random-access memory cell (DRAM).

[0035] In practice, the memory array 121 further includes word lines WL0, WL1, ... WLJ and bit lines BL0, BL1, ... BLK. In some embodiments, the word lines WL0-WLJ and the bit lines BL0-BLK include conductive metal or conductive rails. For illustration, each of the memory cells 123 is coupled to a corresponding word line WL (one of the word lines WL0-WLJ) and a corresponding bit line BL (one of the bit lines BL0-BLK). In some embodiments, the memory array 121 includes additional lines, such as a select line, a reference line, a reference control line, and a power rail.

[0036] According to some embodiments of the present disclosure, the memory controller 122 is a hardware component that performs operations on the memory array 121 according to commands from the processor 110. For example, in some embodiments, the memory controller 122 performs a write operation or a read operation on the memory array 121 according to the commands from the processor 110. In some embodiments, the memory controller 122 is used to write data to the memory array 121 or read data from the memory array 121 through word lines WL and bit lines BL.

[0037] In some embodiments, the power supply 130 is a programmable or controllable power supply. In some embodiments, the power supply 130 provides a rectified DC output. In some embodiments, the power supply 130 provides multiple outputs with different voltages. In some embodiments, the voltage of the output of the power supply 130 is controlled by the processor 110.

[0038] As described above, the system 100 is used to test the memory device 120. For example, the effective operating voltage of the memory device 120 is tested. According to some embodiments of the present disclosure, to test the memory device 120, the processor 110 first controls the power supply 130 to provide an output with an initial supply voltage to operate the memory device 120. For example, in some embodiments, the memory device 120 is a low-power fourth generation double data rate synchronous dynamic random access memory (LPDDR4 SDRAM) or LPDDR4xSDRAM and the processor 110 controls the initial supply voltage of the output of the power supply 130 to be approximately 1.8 volts, 1.1 volts, and 0.6 volts, wherein the voltage values ​​1.8 volts, 1.1 volts, and 0.6 volts are nominal voltage values ​​of the supply voltage VDD1, the supply voltage VDD2, and the supply voltage VDDQ. In some embodiments, the supply voltage is defined by a standard such as JESD209-4-1 or JESD209-4c.

[0039] Next, the processor 110 generates and transmits an initialization instruction to the memory device 120. In response to the initialization instruction, the memory device 120 performs an initialization operation. For example, in some embodiments, the memory device 120 is powered during the initialization operation. In some embodiments, the initialization operation includes read / write training and / or signal calibration, such as calibration of a reference voltage (Vref) of a data query (DQ) bus. In various embodiments, the initialization operation of the DRAM includes a fully defined sequence of steps recorded in a JEDEC standard such as JESD209-4-1 or JESD209-4c.

[0040] After the initialization instruction, the processor 110 generates and transmits a write instruction to the memory device 120 to perform a write operation on the memory device 120. In some embodiments, the write instruction includes data to be written into the memory device 120 and addresses corresponding to one or more memory cells 123 where the data will be stored. In response to the write instruction, when the memory device 120 operates at the initial supply voltage, the memory controller 122 performs a write operation according to the address to write the data into the memory cell 123.

[0041] Next, the processor 110 generates and transmits a read instruction to the memory device 120 to perform a read operation on the memory device 120. In some embodiments, the read instruction includes a memory address corresponding to the write instruction (i.e., a memory address of the memory unit 123 storing the written data). In response to the read instruction, the memory controller 122 performs a read operation corresponding to the memory address. In some embodiments, the memory controller 122 performs the read operation to obtain read data while operating at an initial supply voltage.

[0042] In some embodiments, the memory device 120 transmits read data to the processor 110 and the processor 110 compares the read data and the write data (the data written to the memory device 120). In some embodiments, through this comparison, the processor 110 determines whether the initial supply voltage is a valid operating voltage for the memory device 120 (i.e., determines whether the memory device 120 operates correctly when operating with the initial supply voltage). For example, when the read data and the write data are determined to be equal to each other through comparison, the processor 110 determines that the initial supply voltage is a valid supply voltage for the memory device 120. On the contrary, when the read data and the write data are determined to be different from each other through comparison, the processor 110 determines that the initial supply voltage is an invalid supply voltage for the memory device 120.

[0043] After the above-mentioned read operation (the read operation performed when the memory device 120 operates with the initial supply voltage), the processor 110 controls the power supply 130 to provide an output with an updated supply voltage to operate the memory device 120. The updated supply voltage is different from the initial voltage. For example, the updated supply voltage is less than the initial voltage. In some embodiments, the processor 110 adjusts the output of the power supply 130 from approximately 1.8 volts, 1.1 volts, and 0.6 volts to 1.7 volts, 1.06 volts, and 0.57 volts, respectively. In some embodiments, the voltage values ​​1.7 volts, 1.06 volts, and 0.57 volts are the minimum voltage values ​​of the supply voltages VDD1, VDD2, and VDDQ.

[0044] Next, when the memory device 120 operates at the updated supply voltage (such as the supply voltages of about 1.7, 1.06, and 0.57 volts mentioned above), the processor 110 generates and transmits a read instruction to the memory device 120. In some embodiments, the read instruction corresponding to the updated supply voltage includes a memory address, which is equal to the memory address in the read instruction corresponding to the initial supply voltage. In response to the read instruction corresponding to the updated supply voltage, the memory controller 122 performs a read operation to obtain read data when the memory device 120 operates at the updated supply voltage. In some embodiments, no initialization operation is performed between the two read operations corresponding to the initial supply voltage and the updated supply voltage. In some embodiments, the memory device 120 directly performs a read operation corresponding to the updated supply voltage after the read operation corresponding to the initial supply voltage.

[0045] In some embodiments, the initialization operation is not performed after the read operation corresponding to the initial supply voltage. After the processor 110 controls the power supply 130 to output the updated supply voltage to replace the initial supply voltage, in each write operation corresponding to the memory address of the write operation of the write data, the supply voltage to the memory device 120 will be different from the initial supply voltage.

[0046] In some embodiments, the memory device 120 transmits read data corresponding to the updated supply voltage to the processor 110 and the processor 110 compares the read data corresponding to the updated supply voltage with the write data (the data written to the memory device 120). In some embodiments, the processor 110 determines whether the updated supply voltage is a valid operating voltage for the memory device 120 through this comparison (i.e., determines whether the memory device 120 operates correctly when operating with the updated supply voltage). For example, when the read data and the write data corresponding to the updated supply voltage are determined to be the same through comparison, the processor 110 determines that the updated supply voltage is a valid operating voltage for the memory device 120. On the contrary, when the read data and the write data corresponding to the updated supply voltage are determined to be different through comparison, the processor 110 determines that the updated supply voltage is an invalid operating voltage for the memory device 120.

[0047] According to some embodiments of the present disclosure, after a read operation corresponding to the updated supply voltage, the processor 110 controls the power supply 130 to provide an output having a re-updated voltage to operate the memory device 120. The re-updated voltage is different from the updated voltage. For example, the re-updated voltage is greater than the initial supply voltage. In some embodiments, the processor 110 adjusts the output of the power supply 130 from approximately 1.7 volts, 1.06 volts, and 0.57 volts to approximately 1.95 volts, 1.17 volts, and 0.65 volts, respectively. In some embodiments, the voltage values ​​of 1.95, 1.17, and 0.65 volts are the maximum voltage values ​​of the supply voltages VDD1, VDD2, and VDDQ.

[0048] Next, when the memory device 120 operates with the re-updated supply voltage (e.g., the supply voltages having voltage values ​​of about 1.95, 1.17, and 0.65 as described above), the processor 110 generates and transmits a read instruction to the memory device 120. In some embodiments, the read instruction corresponding to the re-updated supply voltage includes a memory address, which is equal to the corresponding updated supply voltage (e.g., the supply voltages having voltage values ​​of about 1.7, 1.06, and 0.57 as described above). In response to the read instruction corresponding to the re-updated supply voltage, the memory controller 122 performs a read operation to obtain read data when the memory device 120 operates with the re-updated supply voltage. In some embodiments, no initialization operation is performed between the read operation corresponding to the updated supply voltage and the read operation corresponding to the re-updated supply voltage. In some embodiments, the memory device 120 performs the read operation corresponding to the re-updated supply voltage directly after the read operation corresponding to the update.

[0049] In some embodiments, the memory device 120 transmits read data corresponding to the re-update supply voltage to the processor 110 and the processor 110 compares the read data corresponding to the re-update supply voltage with the write data (the data written to the memory device 120). In some embodiments, through this comparison, the processor 110 determines whether the re-update supply voltage is a valid operating voltage for the memory device 120 (i.e., determines whether the memory device 120 operates correctly when the memory device 120 operates with the re-update supply voltage). For example, when the read data and the write data corresponding to the re-update supply voltage are determined to be the same as each other through comparison, the processor 110 determines that the re-update supply voltage is a valid operating voltage for the memory device 120. On the contrary, when the read data and the write data corresponding to the re-update supply voltage are determined to be unequal to each other through comparison, the processor 110 determines that the re-update supply voltage is an invalid operating voltage for the memory device 120.

[0050] In some embodiments, the initial supply voltage is a normal operating voltage set of the memory device 120. For example, the normal operating voltage set may be a voltage set that is most stable and / or has the best performance for the operation of the memory device 120. For example, in some embodiments, when the memory device 120 is a low operating voltage memory device, such as an LPDDR4 memory device, the initial supply voltage is approximately equal to a voltage set having voltage values ​​of 1.8, 1.1, and 0.6 volts. In some embodiments, the updated supply voltage is set lower than the initial supply voltage and the re-updated supply voltage is set higher than the initial supply voltage. For example, the updated supply voltage is approximately equal to the minimum supply voltage specified in the operating instructions of the memory device 120, such as a voltage set having voltage values ​​of 1.7, 1.06, and 0.57 volts, and the re-updated supply voltage is approximately equal to the maximum supply voltage specified in the operating instructions of the memory device 120, such as a voltage set having voltage values ​​of 1.95, 1.17, and 0.65 volts.

[0051] In various embodiments, the processor 110 adjusts only the output or a portion of the output of the power supply 130 at a time instead of adjusting all the outputs of the power supply 130. For example, in some embodiments, the processor 110 adjusts only the supply voltage VDD1 of the supply voltages VDD1, VDD2, and VDDQ between two read operations or between a write operation and a read operation. In some embodiments, the supply voltages VDD1, VDD2, and VDDQ are changed from initial voltages having voltage values ​​of 1.8, 1.1, and 0.6 volts to updated supply voltages having voltage values ​​of 1.7, 1.1, and 0.6 volts. In various embodiments, the updated supply voltage is higher than the initial supply voltage and the updated supply voltage is higher than the updated supply voltage. For example, in some embodiments, supply voltages VDD1, VDD2, and VDDQ are increased from initial supply voltages having voltage values ​​of 1.7, 1.06, and 0.57 volts to updated supply voltages having voltage values ​​of 1.8, 1.1, and 0.6 volts, and further increased to re-updated supply voltages having voltage values ​​of 1.95, 1.17, and 0.65 volts.

[0052] In some embodiments, the processor 110 repeatedly adjusts the output of the power supply 130 and transmits the read command to the memory device 120 multiple times (may be more than three times) after the write operation. In some embodiments, adjusting the output of the power supply 130 is to increase the voltage value of one of the outputs by an incremental value (e.g., about 0.01 volts).

[0053] In some embodiments, the processor 110 is also used to generate a list of voltage values. In some embodiments, the processor 110 adjusts the output of the power supply 130 according to the list of voltage values. For example, in some embodiments, the processor 110 first controls the power supply 130 to output a supply voltage having a first voltage value in the list of voltage values. Then, the processor 110 controls the power supply 130 to directly adjust the supply voltage to a second voltage value in the list of voltage values ​​after the first read operation. Then, the processor 110 controls the power supply 130 to directly adjust the supply voltage to a third voltage value in the list of voltage values ​​after the second read operation, and so on.

[0054] In some embodiments, the voltage value list includes a sequence of numbers representing voltage values. For example, according to some embodiments, the voltage value list includes a sequence of numbers having a difference of 0.025 (volts). In different embodiments, the order of the voltage values ​​in the voltage value list is based on the probability of failure of the memory device 120 when operating at these voltage values. For example, the first voltage value (i.e., the initial voltage) in the voltage value list is the most stable supply voltage for operating the memory device 120, and this most stable supply voltage may be recorded in the operating instructions of the memory device 120. The second voltage value in the voltage value list is higher than the first voltage value and the probability of failure when operating the memory device 120 with the supply voltage having the second voltage value is greater than the probability of failure when operating the memory device 120 with the supply voltage having the first voltage value.

[0055] In operation, according to some embodiments of the present disclosure, the processor 110 stops repeatedly adjusting the output of the power supply 130 and stops transmitting the read command to the memory device 120 according to the comparison result between the data read from the memory device 120 and the data written thereto. For example, when the comparison result indicates that the data read from the memory device 120 and the data written thereto are different from each other, the processor 110 stops repeatedly adjusting the output of the power supply 130 and stops transmitting the read command to the memory device 120.

[0056] In some embodiments, after repeated operations of adjusting the output of the power supply 130 and transmitting the read command to the memory device 120, the processor 110 generates a write command to enable the memory controller 122 to perform a write operation, which is different from the aforementioned write operation directly performed after the initialization operation. In some embodiments, after repeated operations of adjusting the output of the power supply 130 and transmitting the read command to the memory device 120, the processor 110 directly controls the power supply 130 to change the output of the operating memory device 120 and generates a write command to enable the memory controller 122 to perform a write operation, which is different from the aforementioned write operation directly performed after the initialization operation.

[0057] In some embodiments, the memory address corresponding to the write operation performed directly after the initialization operation is different from the memory address corresponding to the write operation after the repeated operation of adjusting the power supply 130 and transmitting the read command to the memory device 120. In some embodiments, the write data performed directly after the initialization operation is different from the write data of the write operation after the repeated operation of adjusting the power supply 130 and transmitting the read command to the memory device 120.

[0058] In some embodiments, the processor 110 generates a read instruction to enable the memory controller 122 to perform a read operation of a memory address corresponding to a write operation after repeated operations of adjusting the power supply 130 and transmitting the read instruction to the memory device 120, and the processor 110 compares the read data of this read operation with the write data of the write operation after repeated operations of adjusting the power supply 130 and transmitting the read instruction to the memory device 120 to test the memory device 120.

[0059] In some embodiments, after the write operation after the repeated operations of adjusting the power supply 130 and transmitting the read command to the memory device 120 , the processor 110 further repeatedly adjusts the power supply 130 and transmits the read command to the memory device 120 to test the memory device 120 .

[0060] According to various embodiments of the present disclosure, the processor 110 is further configured to determine whether the memory device 120 complies with the specification based on the comparison result of each read data and the write data. For example, in some embodiments, the processor 110 determines whether each read data is equal to the corresponding write data. In some embodiments, when it is determined that each read data is equal to the corresponding write data, the processor 110 determines that the memory device 120 is a valid memory device (i.e., a memory device that operates correctly or normally).

[0061] In some embodiments, the processor 110 records the read data of each read operation in a form as a test result. In some embodiments, the processor 110 compares each read data in the read data form with the corresponding write data to determine whether the memory device 120 complies with the specification as described above. In some embodiments, the processor 110 compares each read data in the read data form with the corresponding write data and when it is determined that the read data in the read data form is not equal to the write data, the processor 110 adds the voltage value of the corresponding supply voltage to the invalid supply voltage form. In some embodiments, the processor 110 determines whether the memory device 120 is defective according to the invalid supply voltage form. For example, in some embodiments, when the invalid supply voltage form includes at least one voltage value, the processor 110 determines that the memory device 120 has a defect.

[0062] In various embodiments, processor 110 records the result of each comparison (eg, Boolean data indicating whether the data read from memory device 120 and the written data are equal to each other) in a table as a test result. In some embodiments, processor 110 determines whether memory device 120 meets the aforementioned specifications.

[0063] Figure 1 The configuration is given for illustrative purposes. Figure 1 Various implementations are within the expected scope of an embodiment of the present invention. For example, in some embodiments, the system 100 further includes a storage device, such as a solid state drive or a mechanical hard drive. In some embodiments, the storage device is used to store the read data, comparison results or the form of each read operation.

[0064] refer to Figure 2 . Figure 2 is a flow chart of an example of a method 200 corresponding to system 100 according to some embodiments of the present disclosure. It should be understood that additional operations / steps may be provided in Figure 2 Before, between, and after the operations / steps shown. Some of the operations / steps described below may be replaced or removed to implement other embodiments of method 200. The order of the operations / steps may be changed. In different views and embodiments, the same reference numerals are used to indicate similar elements. Method 200 includes the following references Figure 1 Described operations 201-205.

[0065] In operation 201 , the memory device 120 is initialized. For example, the processor 110 generates an initialization instruction to initialize the memory device 120 .

[0066] In operation 202, write data is written to the memory device 120 while the memory device 120 is operating at a first voltage set (eg, having voltage values ​​of 1.8, 1.1, and 0.6 volts).

[0067] In operation 203 , a first read operation is performed to compare the written data and the first read data. For example, in some embodiments, the processor 110 determines whether the written data is equal to the first read data obtained by the first read operation on the memory device 120 .

[0068] In operation 204 , after performing the first read operation, the memory device 120 is directly operated with a second voltage group different from the first voltage group (eg, a voltage group having voltage values ​​of 1.7, 1.06, and 0.57) and a second read operation is performed on the memory device 120 to obtain second read data.

[0069] In operation 205, the write data and the second read data are compared to obtain a test result. For example, according to some embodiments, the processor 110 determines whether the write data is equal to the second read data obtained by the second read operation on the memory device 120. When the write data and the second read data are determined to be equal to each other, the processor 110 generates a test result indicating that the second voltage group is a valid operating voltage for the memory device 120. Conversely, when the write data and the second read data are determined to be different from each other, the processor 110 generates a test result indicating that the second voltage group is an invalid operating voltage for the memory device 120.

[0070] In some embodiments, the method 200 further includes operating the memory device 120 with a third voltage group different from the first and second voltage groups and performing a third read operation on the memory device 120 to obtain third read data, wherein each of the second voltage groups is lower than a corresponding one of the low voltage groups, and each of the third voltage groups is higher than a corresponding one of the low voltage groups. For example, the voltage values ​​of the first voltage group are 1.8, 1.1, and 0.6 volts, the voltage values ​​of the second voltage group are 1.7, 1.06, and 0.57 volts, and the voltage values ​​of the third voltage group are 1.95, 1.17, and 0.65 volts. In some embodiments, the method 200 further includes comparing the write data and the third read data.

[0071] In some embodiments, the method 200 further includes generating an instruction to terminate the test of the memory device 120 according to the comparison result of the write data and the first read data and the comparison result of the write data and the second read data. For example, in some embodiments, the processor 110 generates an instruction to terminate the test (a test for determining whether the voltage operating the memory device 120 is a valid supply voltage) to the memory device 120 when the write data and the read data are determined to be unequal or when the write data and the second read data are determined to be unequal.

[0072] In some embodiments, the first read operation and the second read operation correspond to the same memory address. In other words, the first and second read operations are performed on the same one or more memory cells 123.

[0073] In some embodiments, each voltage of the second voltage group is higher than the corresponding voltage of the first voltage group and the method 200 further includes operating the memory device 120 with a third voltage group and performing a third read operation on the memory device 120 to obtain third read data, wherein each voltage of the third voltage group is higher than the corresponding voltage of the second voltage group. For example, the voltage values ​​of the first voltage group are 1.7, 1.06 and 0.57 volts, the voltage values ​​of the second voltage group are 1.8, 1.1 and 0.6 volts, and the voltage values ​​of the third voltage group are 1.95, 1.17 and 0.65 volts. In some embodiments, the method 200 further includes comparing the write data and the third read data.

[0074] In some embodiments, method 200 further includes recording the value of the first voltage group in the test result when the write data is not equal to the first read data, and recording the value of the second voltage group in the test result when the write data is not equal to the second read data. For example, in some embodiments, the test result is a window and when the write data is not equal to the first read data, the processor 110 records the value of the first voltage group in the window and when the write data is not equal to the second read data, the processor 110 stores the value of the second voltage group in the window.

[0075] As described above, the system and method provided by the present disclosure help to quickly test the impact of voltage changes on memory devices. By directly adjusting the supply voltage between read operations and / or write operations, the test time is effectively shortened. In addition, since repetitive manual operations are avoided, human resources are effectively utilized. Therefore, R&D personnel can spend their time on more important projects in product development.

[0076] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of an embodiment of the present invention. Those skilled in the art should understand that an embodiment of the present invention can be easily used as a basis for designing or modifying other processes and structures to implement the same purpose and / or achieve the same advantages of the embodiments introduced in the present invention. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment of the present invention, and various changes, substitutions and modifications can be performed in an embodiment of the present invention without departing from the spirit and scope of an embodiment of the present invention.

[0077]

Explanation of symbols

[0078] 100: System

[0079] 110: Processor

[0080] 120: memory device

[0081] 121:Memory array

[0082] 122:Memory controller

[0083] 123: memory unit

[0084] 130: Power supply

[0085] 201: Steps

[0086] 202: Steps

[0087] 203: Steps

[0088] 204: Steps

[0089] 205: Steps

[0090] BL0: bit line

[0091] BL1: Bit line

[0092] BL2: Bit Line

[0093] BLK: Bit Line

[0094] WL0: word line

[0095] WL1: character line

[0096] WL2: Character Line

[0097] WLJ: character line.

Claims

1. A system for testing a memory, characterized in that: Include: a memory device to operate with a supply voltage having a first value; as well as A processor operatively coupled to the memory device and configured to: generating a write command to write first data into the memory device; generating a first read instruction to read second data from the memory device and compare the first data with the second data; adjusting the supply voltage to have a second value different from the first value; as well as A second read instruction is generated to read third data from the memory device and compare the first data with the third data to generate a test result.

2. The system according to claim 1, wherein the processor is further configured to: adjusting the supply voltage to a third value different from the first value and the second value, wherein the second value is a minimum operating voltage value of the memory device as specified and the third value is a maximum operating voltage value of the memory device as specified; and A third read command is generated to read fourth data from the memory device and compare the first data with the fourth data.

3. The system according to claim 1, wherein the processor is further configured to: adjusting the supply voltage to have a third value, wherein the second value is the first value plus an incremented value, and the third value is the second value plus the incremented value; and A third read command is generated to read fourth data from the memory device and compare the first data with the fourth data. 4 . The system according to claim 1 , wherein the processor is further configured to determine whether the memory device complies with specifications based on the comparison between the first data and the second data and the comparison between the first data and the third data. 5 . The system of claim 1 , wherein the reading the second data from the memory device comprises performing a read operation on a memory cell into which the first data is written to obtain the second data.

6. A method for testing a memory, characterized in that: Include: Initializing a memory device; operating the memory device with a first voltage set and writing write data to the memory device; performing a first read operation on the memory device to compare the write data with the first read data; After performing the first read operation, directly operating the memory device with a second voltage group different from the first voltage group and performing a second read operation on the memory device to obtain second read data; and The written data and the second read data are compared to generate a test result.

7. The method according to claim 6, wherein: Also includes: operating the memory device with a third voltage group different from the first and second voltage groups and performing a third read operation on the memory device to obtain third read data, wherein each of the second voltage group is less than a corresponding one of the first voltage group, and each of the third voltage group is greater than a corresponding one of the first voltage group; as well as The write data and the third read data are compared.

8. The method according to claim 6, wherein: Also includes: An instruction to terminate the test of the memory device is generated according to the comparison between the write data and the first read data and the comparison between the write data and the second read data.

9. The method of claim 6, wherein the first and second read operations correspond to the same memory address.

10. The method of claim 6, wherein each voltage in the second voltage group is higher than a corresponding voltage in the first voltage group and the method further comprises: operating the memory device with a third voltage group and performing a third read operation on the memory device to obtain third read data, wherein each voltage in the third voltage group is higher than a corresponding voltage in the second voltage group; and The written data and the third written data are compared.

11. The method according to claim 6, wherein: Also includes: When the written data is not equal to the first read data, recording the value of the first voltage group in the test result; as well as When the written data is not equal to the second read data, the value of the second voltage group is recorded in the test result.

12. A method for testing a memory, characterized in that: Include: (a) generating a first list of a plurality of voltage values; (b) initializing the memory device and setting the supply voltage of the memory device according to the first table; (c) performing a first write operation of first write data on the memory device; (d) reading the memory device; (e) changing the value of the supply voltage according to the first table and reading the memory device; as well as (f) Repeat step (e) based on the first list.

13. The method of claim 12, wherein step (d) comprises recording the read data in a second list and step (e) comprises adding the new read data to the second list.

14. The method of claim 13, wherein step (f) comprises terminating the repeating when the new read data is not equal to the first write data.

15. The method according to claim 13, wherein: Also includes: Comparing each of the plurality of data in the second list with the first written data and when the data in the second list is not equal to the first written data, adding the value corresponding to the supply voltage to the third list; as well as Determine whether the memory device has a defect according to the third list. The method according to claim 12 , wherein the first list is a sequence of voltage values.

17. The method of claim 12, wherein step (e) further comprises: After a read operation, the value of the supply voltage is directly changed according to the first table and the memory device is read.

18. The method of claim 12, wherein the first write operation corresponds to a first memory address and the method further comprises: The value of the supply voltage is changed and a second write operation of the first write data is performed, the second write operation corresponding to a memory address of the memory device.

19. The method of claim 12, wherein the order of the voltage values ​​in the first list is based on a plurality of failure rates of the memory device when operating at the voltage values ​​respectively.

20. The method according to claim 12, wherein: Also includes: After step (f), directly operating the memory device with a third voltage group different from the first and second voltage groups and writing second write data into the memory device; performing a third read operation on the memory device to obtain third read data; as well as The second write data and the third read data are compared to generate a test result.

Images