Test method, test device, electronic device and storage medium

Abstract

At least one embodiment of the invention provides a test method, a test device, an electronic device and a storage medium. The testing method comprises the following steps: performing data communication with tested equipment through a double-rate physical layer interface to transmit target data; and performing read-write processing on target data, the target data being used for executing data verification to test the performance of the tested device. The test method can get rid of dependence on a third-party indicator property (IP) supplier.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a testing method, a testing device, an electronic device, and a storage medium. Background Art

[0002] Memory controllers are usually used to control memory modules in computer systems, such as managing memory access, data transmission, and address decoding. For example, the double data rate (DDR) controller is located between the computer system bus and DRAM, responsible for instruction parsing, data transmission, timing matching, power consumption management, etc. Multiple synchronous dynamic random access memory (DRAM) particles are arranged on dual in-line memory modules (DIMMs) to form a memory bar. The DDR controller and the DIMM memory bar are connected through the DDR port physical layer (DDR PHY). Summary of the invention

[0003] At least one embodiment of the present disclosure provides a testing method, comprising: performing data communication with a device under test via a double-rate physical layer interface to transmit target data; and performing read and write processing on the target data, wherein the target data is used to perform data verification to test the performance of the device under test.

[0004] At least one embodiment of the present disclosure provides a testing device, comprising: a data communication unit, configured to perform data communication with a device under test via a double-rate physical layer interface to transmit target data; and a read-write unit, configured to perform read and write processing on the target data, wherein the target data is used to perform data verification to test the performance of the device under test.

[0005] At least one embodiment of the present disclosure provides an electronic device, comprising at least one processing unit and a memory; wherein the memory stores computer-readable instructions and is communicatively connected to the at least one processing unit; and the at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement a testing method according to at least one embodiment of the present disclosure.

[0006] At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions. When a processor executes the computer-readable instructions, a testing method according to at least one embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure are briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0008] Figure 1 An exemplary DQMap process schematic diagram is shown;

[0009] Figure 2 A schematic diagram of an exemplary CRC data verification is shown;

[0010] Figure 3 A flow chart showing a testing method according to at least one embodiment of the present disclosure is shown;

[0011] Figure 4 A schematic diagram of a testing device according to at least one embodiment of the present disclosure is shown;

[0012] Figure 5 A schematic diagram of a DDR memory CRC data test device according to at least one embodiment of the present disclosure is shown;

[0013] Figure 6 A schematic diagram showing a write channel data processing flow according to at least one embodiment of the present disclosure is shown;

[0014] Figure 7 A schematic diagram of a write channel CRC code processing flow according to at least one embodiment of the present disclosure is shown;

[0015] Figure 8 A schematic diagram of a write channel CRC comparison process according to at least one embodiment of the present disclosure is shown;

[0016] Fig. 9 A schematic diagram showing a read channel CRC code processing flow according to at least one embodiment of the present disclosure is shown;

[0017] Fig.10 A schematic diagram showing a read channel data processing flow according to at least one embodiment of the present disclosure is shown;

[0018] Fig.11 A schematic diagram showing an electronic device according to at least one embodiment of the present disclosure;

[0019] Fig.12 A schematic diagram showing a computer-readable storage medium according to at least one embodiment of the present disclosure;

[0020] Fig.13 A schematic diagram of another electronic device according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0021] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. On the contrary, it is intended to cover changes, modifications and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0022] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0023] Note that the examples to be introduced below are only specific examples, and are not intended to limit the embodiments of the present disclosure to the specific shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct more embodiments not mentioned in the present description by reading the present description.

[0024] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0025] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0026] First, the abbreviations and related terms involved in this application are defined and explained.

[0027] DDR SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory, or DDR memory, is the main memory of computer systems.

[0028] DIMM: Dual-Inline-Memory-Modules, is a memory stick that uses dual inline memory modules, and DRAM particles are arranged on the DIMM stick.

[0029] DDR PHY: DDR Port Physical Layer, also known as DDR port physical layer, is used to connect DRAM particles (through DIMM and motherboard connector) and DDR controller.

[0030] DFI: DDR PHY Interface, double rate physical layer interface, also known as interface protocol, defines the signals, timing parameters, and programmable parameters required for transmitting instructions and data between the DDR controller and DDR PHY.

[0031] DDR Controller: Memory controller, responsible for data transmission and verification between the system and DRAM memory, protocol analysis, timing control, power consumption management, etc.

[0032] CRC: Cyclic Redundancy Check is a fast algorithm that generates a short fixed-bit check code based on a data packet. It is mainly used to detect or verify errors that may occur after data transmission or storage.

[0033] DQMap: DQ Mapping, data bit line mapping, also known as digital relationship mapping, is a technology used for communication between memory controller and DRAM. For example, in DDR DIMM, DQMap can refer to "DDR DIMM DQ Pins Map", or "mapping between data bit lines DQ of DDR memory sticks". For example, when DRAM is wired on an actual PCB board, the traces between the particles and the connector may not be strictly equal in length, which may cause some bits of data to be mistransmitted due to signal integrity reasons. When DIMM minimizes the length of signal traces in order to maximize signal integrity, it may adjust the connection or mapping relationship between the DQ bits on some DIMMs and the DRAM DQ bits. The two are no longer in a sequential one-to-one correspondence. This mapping relationship is called DQMap, which is a means to enhance DDR signal integrity.

[0034] It is understandable that the terms defined above are only exemplary definitions in specific application scenarios to facilitate a better understanding of the present application, and the present disclosure is not limited thereto. For example, the exemplary definitions in the application scenarios for memory described above can be extended to other memories.

[0035] The frequency of DDR memory is increasing day by day, and the data transmission between DRAM and DDR controller will inevitably produce some unforeseen errors due to electromagnetic interference. In this case, it is necessary to introduce a data verification method. For example, DDR introduces CRC to detect data errors. Exemplarily, at the DDR controller end, CRC check bits (herein referred to as CRC code) are generated for write data, and the CRC code of read data can also be checked. In addition, at the DRAM end, there is also a CRC check on write data and a function to generate a CRC code for read data.

[0036] In actual PCB board wiring, for signal integrity considerations, DDR signal lines are usually required to be equal length to ensure impedance continuity. However, due to various reasons, the signal routing impedance cannot be strictly continuous. In order to avoid signal integrity problems caused by impedance discontinuity, DDR introduces the DQMap feature. Usually CRC does not change the digital relationship between the data source and the data target (that is, the corresponding relationship of the data bits), but DQMap will adjust the corresponding relationship of the data bits between the DIMM and DRAM particles, which will cause changes between the original data in the DRAM and the data received by the DDR controller.

[0037] Figure 1 An exemplary DQMap process schematic is shown. Figure 1 The DQMap process diagram shows two DQMap processes.

[0038] See also Figure 1 , the right side is the actual DRAM, and the left side is the data converted by digital relationship mapping (abbreviated as DQMap converted data). Exemplarily, the DQMap conversion is performed with 4 bits as a basic unit. Figure 1 The 1 on the upper side is a DQMap mode, which is applied to byte 0 of SDRAM Rank 0 and implements half-byte swap. In this mode, DQ0-3 are converted to DQ4 0 ~7 3 , DQ4~7 are converted to DQ0 0 ~3 3 . Figure 1 2 on the lower side is another DQMap method, which is applied to byte 1 of SDRAM Rank 0 and does not swap half bytes. In this method, DQ0-3 are converted to DQ8 0 ~11 3 , DQ4~7 are converted to DQ12 0 ~15 3 The specific correspondence is given by Figure 1 The various connections are shown in Figure 1 There is no conversion between the two base units.

[0039] exist Figure 1 In the figure, the process of DQMap conversion from the left DIMM (more specifically, DIMM connector or gold finger) to the right SDRAM can be called forward DQMap conversion, and the process of DQMap conversion from the right SDRAM to the left DIMM can be called reverse DQMap conversion.

[0040] Understandably, Figure 1 The DQMap process in is only exemplary, and the present disclosure is not limited thereto. For example, Figure 1 The DQMap process in may also include other correspondences. For example, conversion may be performed between two basic units.

[0041] When the above-mentioned CRC and DQMap are introduced, when data is written (for example, DDR4 and DDR5 both support write operations with CRC enabled) and data is read (for example, DDR5 both support read operations with CRC enabled), the data will change due to the mapping relationship of DQMap. The DDR controller needs to obtain the DQMap information and complete the data remapping before calculating the CRC, so that the CRC of the write data is consistent with the CRC generated by the DRAM particle's own verification logic, and the read CRC is consistent with the CRC calculated by the controller itself.

[0042] The inventors of the present disclosure recognize that there is a need for data verification technology with digital relationship mapping and CRC. CRC data verification with digital relationship mapping can be performed on software platforms and hardware platforms.

[0043] In terms of software platform, due to the complexity of DQMap processing of data when the CRC function is turned on, it is generally only possible to verify the CRC and DQMap features separately, or use a few fixed DQMap configurations, or directly use a third-party DIMM model to complete the verification.

[0044] In terms of hardware platform, Figure 2 A schematic diagram of an exemplary CRC data verification is shown. Figure 2 , the controller (such as a memory controller or a CPU) needs to connect to the DIMM (shown as DIMM VIP, i.e., DIMM verification IP) through the DDR PHY, and the DIMM completes the work of DQMap, write CRC check, read data, and CRC generation.

[0045] In other aspects, when writing data, the device under test (e.g., memory controller) can transmit random data generated by the system from the system bus to the DDR PHY in the test device, so that the DDR PHY transmits the write data received by the DDR PHY and the CRC received by the DDR PHY to the DIMM to complete the CRC data verification (CRC check) of the write data. When reading data, the DDRPHY can obtain the read data and CRC from the DIMM and send them as the read data sent by the DDR PHY and the CRC sent by the DDR PHY to the device under test for CRC check, and then the device under test can transmit the read data to the system bus as the read data returned to the system.

[0046] The inventors of the present disclosure have realized that there are shortcomings in the above-mentioned software platform aspects and hardware platform aspects.

[0047] For example, in terms of software platforms, when the DQMap function is not supported or only a few fixed configurations are verified, the DQMap and CRC functions of the controller cannot be fully verified, especially when, for example, DDR5 no longer needs to store the DQMap configuration information in the Serial Presence Detect (SPD) unit of the DIMM. This solution cannot cover more or even randomly combined DQMap configurations. In addition, when using DIMM for testing, additional costs are required to purchase dedicated DIMM models, and there is a higher risk in obtaining relevant technical support. Moreover, the use of this solution also relies on DDR PHY, which will also bring more verification costs. Most DIMM models only open some interfaces and functions, and the internal code is encrypted, which limits the flexibility of verification and is not conducive to function development and debugging. In addition, the model has a lag in supporting new features, which is not conducive to debugging and verification of new features.

[0048] For example, in terms of hardware platforms, the types of DQMaps that can be tested depend on the DIMM itself and are very limited due to the implementation of DDR PHY and DIMM. For example, the x4 / x8 / x16 DIMMs of common DRAM vendors on the market can only support a limited number of DQMap configurations, making it difficult to cover as many or all situations as possible.

[0049] At least one embodiment of the present invention provides a testing method, a testing device, an electronic device, and a computer-readable storage medium, which can get rid of the dependence on a third-party intellectual property (IP) supplier.

[0050] For example, at least one embodiment of the present disclosure relates to a technical solution for CRC memory data verification based on a DFI interface, which realizes DQMap mapping and CRC checking of DDR read and write data through independently developed data conversion and verification processes and equipment, and completes random verification of DQMap and CRC of the DDR controller. This technical solution can, for example, achieve one or more of the following technical effects or other technical effects: get rid of dependence on third-party IP suppliers, solve the limitations of their implementation solutions and version iterations, be highly flexible and fully autonomous and controllable, save a lot of costs and keep up with the latest technical features in a timely manner, etc.

[0051] Figure 3 FIG. 3 is a flow chart of a testing method 300 according to at least one embodiment of the present disclosure. Figure 3 The test method 300 and its additional aspects described can be found below. Figure 4 The test device 400 described in Figure 5 The described test device, electronic device, hardware structure, software structure or hardware structure and software structure are implemented.

[0052] It can be understood that the following combined with exemplary drawings (such as Figure 5 ) is only for ease of understanding, and the various aspects of the exemplary drawings should not be used as limitations of the test method. For example, the test method can be changed according to different application scenarios (for example, different data verification, whether DQMap is enabled, whether targeted testing or random testing is required, etc.).

[0053] See also Figure 3 , the testing method 300 includes steps S310 to S320.

[0054] In step S310, data communication is performed with the device under test via a double rate physical layer interface (DFI) to transmit target data.

[0055] The device under test may be an electronic device whose performance is measured. Performance may include stability, signal integrity, etc. For example, see Figure 5 , the device under test may include a DDR controller. Of course, the embodiment is not limited thereto, and the device under test may also be a HDD controller, a NAND controller, an HBM controller, or two interfaces in a communication link.

[0056] In step S320, the target data is read and written, wherein the target data is used to perform data verification to test the performance of the device under test.

[0057] As described above, the test method according to at least one embodiment of the present disclosure can implement the read and write processing of target data via DFI, implement data verification based on the target data, and thus test the device under test. Figure 2 Compared with the test device described above, which needs to purchase DDR PHY from a third-party IP supplier, the test method according to at least one embodiment of the present disclosure can get rid of the dependence on the third-party IP supplier.

[0058] Some exemplary additional aspects of the testing method according to at least one embodiment of the present disclosure are described below.

[0059] For example, according to the test method of at least one embodiment of the present disclosure, the data check includes a cyclic redundancy check (CRC). However, the embodiments of the present disclosure are not limited thereto, for example, the data check may also include a parity check, a Hamming code check, an RS check, a checksum, etc.

[0060] For example, see Figure 5 , which exemplarily shows the case where the data check is a cyclic redundancy check. However, the embodiment is not limited thereto, Figure 5 Adaptive changes can be made to suit other data validations.

[0061] For example, according to the testing method of at least one embodiment of the present disclosure, the target data includes write data and a write cyclic redundancy check code (CRC code) of the write data, and data communication is performed with the device under test via a double rate physical layer interface to transmit the target data, including: receiving the write data and the write cyclic redundancy check code from the device under test via the DFI; and reading and writing processing of the target data includes: performing a cyclic redundancy check on the write data based on the write data and the write cyclic redundancy check code.

[0062] For example, see Figure 5 According to at least one embodiment of the present disclosure, the test method may receive DFI write data and DFI write CRC code from the device under test via DFI. In subsequent operations, the DFI write data and DFI write CRC code may be used for cyclic redundancy check in the test device, for example.

[0063] In this way, the testing method according to at least one embodiment of the present disclosure can test the device under test based on the cyclic redundancy check of data written from the device under test to the testing apparatus, thereby implementing the test of the write channel.

[0064] For example, according to the testing method of at least one embodiment of the present disclosure, a cyclic redundancy check is performed on the write data based on the write data and the write cyclic redundancy check code, including: in response to whether the digital relationship mapping (DQMap) is enabled, selectively performing a forward digital relationship mapping conversion (DQMap Do-Swap) on the write data and the write cyclic redundancy check code, respectively, to obtain target data to be processed and a target cyclic redundancy check code to be processed; performing a cyclic redundancy check calculation on the target data to be processed to obtain a calculated cyclic redundancy check code; and comparing whether the calculated cyclic redundancy check code and the target cyclic redundancy check code to be processed are consistent.

[0065] For example, DQMap may be enabled or disabled according to whether a DQMap test needs to be performed on the device under test.

[0066] For example, see Figure 5 , the write data 1.10 from the DFI and the CRC code 1.9 from the DFI can be selectively converted to a forward digital relationship mapping (shown as DQMap Do-Swap 1.13) by the demultiplexing units 1.11 and 1.12. The data output by the multiplexing units 1.16 and 1.17 can correspond to the target data to be processed and the target cyclic redundancy check code to be processed above. Then, the cyclic redundancy check calculation can be performed on the target data to be processed via the CRC calculator 1.18 to obtain the calculated cyclic redundancy check code 1.19. In box 1.20, the calculated cyclic redundancy check code 1.19 can be compared with the target cyclic redundancy check code to be processed to see if they are consistent.

[0067] In this way, the testing method according to at least one embodiment of the present disclosure can perform cyclic redundancy check with DQMap according to actual application needs.

[0068] For example, according to the testing method of at least one embodiment of the present disclosure, in response to whether DQMap is enabled, the write data and the write cyclic redundancy check code are selectively converted by forward digital relationship mapping to obtain the target data to be processed and the target cyclic redundancy check code to be processed, including: in response to DQMap being enabled, the write data and the write cyclic redundancy check code are selectively converted by forward digital relationship mapping to obtain the target data to be processed and the target cyclic redundancy check code to be processed.

[0069] For example, see Figure 5In box 1.13, the forward digital relationship mapping conversion (DQMap Do-SWAP) of the write data 1.10 from the DFI and the CRC code 1.9 from the DFI can be implemented to obtain the forward digital relationship mapping converted data (Do-SwappedWrData) 1.14 and the forward digital relationship mapping converted CRC code (Do-Swapped CRC Bits) 1.15, which correspond to the above-mentioned target data to be processed and the target cyclic redundancy check code to be processed respectively.

[0070] In this way, the testing method according to at least one embodiment of the present disclosure can perform a cyclic redundancy check with a DQMap.

[0071] For example, according to the testing method of at least one embodiment of the present disclosure, in response to whether DQMap is enabled, the write data and the write cyclic redundancy check code are selectively converted by forward digital relationship mapping to obtain the target data to be processed and the target cyclic redundancy check code to be processed, including: in response to DQMap not being enabled, the write data is directly used as the target data to be processed and the write cyclic redundancy check code is directly used as the target cyclic redundancy check code to be processed.

[0072] For example, see Figure 5 , the DFI write data 1.10 and the DFI write CRC code 1.9 may be transmitted via a path shown by an arrow directly connected between the demultiplexing unit 1.11 and the multiplexing unit 1.16 and a path shown by an arrow directly connected between the demultiplexing unit 1.12 and the multiplexing unit 1.17.

[0073] In this way, the testing method according to at least one embodiment of the present disclosure can perform a cyclic redundancy check without a DQMap.

[0074] For example, the testing method according to at least one embodiment of the present disclosure further includes: returning the comparison result to the DFI.

[0075] For example, see Figure 5 , the result of the CRC comparison in block 1.20 may be returned to the DFI.

[0076] In this way, the test method according to at least one embodiment of the present disclosure can return the result of CRC comparison, which is beneficial for the tested device and the uplink system to run related functions.

[0077] For example, the testing method according to at least one embodiment of the present disclosure further includes: storing the write data in a data storage device inside the testing device that executes the testing method.

[0078] For example, see Figure 5 , the data output by the multiplexing unit 1.16 can be stored in the data storage device, thereby storing the data written by the system.

[0079] Thus, the test method according to at least one embodiment of the present disclosure can store the data written by the system. In other aspects, the data storage device can be used as a data source of the read channel.

[0080] For example, according to a testing method of at least one embodiment of the present disclosure, storing write data in a data storage device includes: receiving a write address of the write data via a DFI, and converting the write address into an internal format address of the data storage device; and writing the target data to be processed into the data storage device based on the internal format address.

[0081] For example, see Figure 5 The address converter 1.21 may convert the write address of the write data received via the DFI into an internal format address of the data storage device, and then may write the data output by the multiplexing unit 1.16 into the data storage device based on the internal format address.

[0082] In this way, the testing method according to at least one embodiment of the present disclosure can implement the storage of data written to the system.

[0083] For example, according to the testing method of at least one embodiment of the present disclosure, the target data includes read data and a read cyclic redundancy check code of the read data, and data communication is performed with the device under test via a double rate physical layer interface to transmit the target data, including: sending the read data and the read cyclic redundancy check code to the device under test via the DFI, wherein the testing device performs a cyclic redundancy check on the read data based on the read data and the read cyclic redundancy check code; and reading and writing processing of the target data includes: generating the read data and the read cyclic redundancy check code.

[0084] For example, see Figure 5 The test device may send DFI read data 1.7 (e.g., corresponding to the read data above) and DFI read CRC code 1.6 (e.g., corresponding to the read cyclic redundancy check code above) to the device under test via the DFI, so as to perform a cyclic redundancy check in the device under test (based on Figure 5 In other aspects, the test device may generate DFI read data 1.7 and DFI read CRC code 1.6.

[0085] In this way, the testing method according to at least one embodiment of the present disclosure can test the device under test based on transmitting the read data and the read cyclic redundancy check code to the device under test, thereby implementing the test of the read channel.

[0086] For example, according to a testing method of at least one embodiment of the present disclosure, generating read data and read cyclic redundancy check codes includes: selecting a target data source from at least one data source; and obtaining read data and read cyclic redundancy check codes based on target source data of the target data source.

[0087] For example, according to a testing method of at least one embodiment of the present disclosure, generating read data and read cyclic redundancy check codes includes: selecting a target data source from a data source; and obtaining read data and read cyclic redundancy check codes based on target source data of the target data source.

[0088] For example, the one data source may be a data storage device. Figure 2 When the test device described performs write channel testing and read channel testing, the writing and storage of data corresponds to a single address, that is, it has the limitation of single address reading and writing. In contrast, the test method according to at least one embodiment of the present disclosure breaks through the limitation of single address reading and writing through a data storage device, and can continuously perform random reading and writing on random addresses, thereby achieving more realistic and complex data consistency checks, which helps to enrich test scenarios.

[0089] For other aspects, see Figure 5 , target source data can be selected from the data storage device, and the data storage device can store read mode data 1.22 at an address different from the address of the write mode data 1.23, so that the read mode data 1.22 can be selected as the target data. In this way, targeted testing can be achieved by pre-storing data for a specific application scenario in the data storage device as target source data. In addition, the data storage device can also store other data for other purposes.

[0090] For another example, the one data source may be a random data generator. Usually, when performing a read channel test, it is necessary to read the data in the data storage device to generate read data and a read cyclic redundancy check code, which requires first performing a write channel test to write data in the data storage device. In this case, the sequential test is limited to first performing the write channel test and then performing the read channel test, and the read channel test cannot be implemented without the write channel test. For example, in this case, the data read from the memory may be all 0 or all F, and the purpose of the test cannot be achieved. In contrast, the test method according to at least one embodiment of the present disclosure can implement the read channel test without the write channel test.

[0091] For example, according to a testing method of at least one embodiment of the present disclosure, generating read data and read cyclic redundancy check codes includes: selecting a target data source from multiple data sources; and obtaining read data and read cyclic redundancy check codes based on target source data of the target data source.

[0092] For example, the plurality of sources may be a plurality of data storage devices, a plurality of random data generators, or a combination of at least one data storage device and at least one random generator.

[0093] In this way, the testing method according to at least one embodiment of the present disclosure can provide a rich data source, implement more realistic and complex data consistency checks, and help enrich testing scenarios.

[0094] For example, according to the testing method of at least one embodiment of the present disclosure, the multiple data sources include a data storage device and a random data generator inside a testing device that executes the testing method.

[0095] In this way, the testing method according to at least one embodiment of the present disclosure can be applied to application scenarios that require both targeted testing and random testing.

[0096] For example, according to a testing method of at least one embodiment of the present disclosure, the random data generator includes a first random data generator and a second random data generator, and selects target source data from a plurality of data sources, including: selecting one of the data storage device and the first random data generator as an intermediate target data source based on a first data source selection signal; and selecting one of the intermediate target data source and the second random data generator as a target data source based on a second data source selection signal, and obtaining read data and a read cyclic redundancy check code based on the target source data of the target data source, including: in response to the target data source being the first random data generator or the data storage device, performing a reverse DQMap conversion on the target source data to generate a reverse The target source data of the DQMap conversion is used as the read data; a cyclic redundancy check calculation is performed on the target source data to generate a first intermediate cyclic redundancy check code; and a reverse DQMap conversion is performed on the first intermediate cyclic redundancy check code to obtain a read cyclic redundancy check code; and in response to the target source data being a second random data generator, the target source data is used as the read data; a forward DQMap conversion is performed on the target source data to obtain the forward DQMap converted target source data; a cyclic redundancy check calculation is performed on the forward DQMap converted target source data to generate a second intermediate cyclic redundancy check code; and a reverse DQMap conversion is performed on the second intermediate cyclic redundancy check code to obtain a read cyclic redundancy check code.

[0097] For example, see Figure 5 , the multiple data sources may include a data storage device, a random write data generator 1.29, and a random write data generator 1.26. One of the data storage device and the random data generator 1.29 may be selected as an intermediate target data source based on a data source selection signal acting on a multiplexing unit 1.30, and one of the intermediate target data source and the random data generator 1.26 may be selected as a target data source based on a data source selection signal for multiplexing units 1.25 and 1.31.

[0098] In the case where the target data source is a random data generator 1.29 or a data storage device. For the acquisition of read data, the target source data can be subjected to reverse DQMap conversion (such as DQMap De-Swap shown in box 1.27) to generate reverse DQMap converted target source data, which is then transmitted to the DFI as DFI read data 1.7 through the multiplexing unit 1.25. For the acquisition of the read cyclic redundancy check code, a cyclic redundancy check calculation can be performed on the target source data through a CRC calculator 1.33 to generate an intermediate cyclic redundancy check code 1.32, and then a reverse DQMap conversion can be performed on the intermediate cyclic redundancy check code (such as DQMap De-Swap shown in box 1.27) to obtain a CRC code 1.24 to the DFI, which is then transmitted to the DFI as a DFI read CRC code 1.6.

[0099] In the case where the target source data is a random data generator 1.26. For the acquisition of read data, the target source data can be transmitted to the DFI through the multiplexing unit as the DFI read data 1.7. For the acquisition of the read cyclic redundancy check code, a forward DQMap conversion (DQMap Do-Swap as shown in box 1.28) can be performed on the target source data to obtain the target source data of the forward DQMap conversion. Then, the target source data of the forward DQMap conversion is multiplexed to the CRC calculator 1.33 through the multiplexing unit 1.31 to perform a cyclic redundancy check calculation on the target source data of the forward DQMap conversion to generate an intermediate cyclic redundancy check code (i.e., the intermediate CRC code 1.32). Then, a reverse DQMap conversion can be performed on the intermediate cyclic redundancy check code (as shown in box 1.27) to obtain the CRC code 1.24 to the DFI, and then transmitted to the DFI as the DFI read CRC code 1.6.

[0100] In this way, the testing method according to at least one embodiment of the present disclosure can implement a complete test of random DQMap, specific and random data's CRC data.

[0101] In other aspects, selecting the first random data generator as the target data source can support the test of the read-only scenario. Since the data storage device has not written data in the read-only test scenario, the value read from the data storage device is either the initial value (all 0 or all F) or the uninitialized indeterminate state, which will result in the same value returned when reading different addresses, which is not conducive to fully verifying the correctness of the read channel. The test equipment generates different random data for different addresses through the first random data generator, and completes the complete test of the correctness of the read channel data and the correctness of the CRC check code. Selecting the data storage device as the target data source can support the closed-loop test of writing and reading, indexing the data in the data storage device according to the address, completing the data loading and updating during the write operation, and the data reading during the read operation, and realizing the data consistency verification of random read and write operations on continuous random addresses. Selecting the second random data generator as the target data source can support the test of the read-only scenario. In addition, the data generated by the second random data generator can be directly observed through the DFI interface, realizing the WYSIWYG of the read data, which is convenient for users to perform necessary tests on the CRC calculation logic of the device under test, for example.

[0102] Of course, the embodiment is not limited thereto and may include more or less data storage devices and / or random data generators. For example, the first random data generator and the second random data generator may be the same random data generator, and the corresponding data transmission path may be adaptively changed. For another example, one or more of the data storage devices and / or random data generators may be omitted, and the corresponding data transmission path may be adaptively changed.

[0103] In addition, the above embodiment can realize the complete test of CRC data with DQMap, for example. Of course, there is also a need for complete test of CRC data without DQMap.

[0104] For example, according to the testing method of at least one embodiment of the present disclosure, read data and a read cyclic redundancy check code of the read data are obtained based on target source data of a target data source, including: taking the target source data of the target data source as read data, and performing a cyclic redundancy check calculation on the target source data of the target data source to obtain a read cyclic redundancy check code.

[0105] In this way, the testing method according to at least one embodiment of the present disclosure can implement a complete test of CRC data without DQMap.

[0106] Exemplarily, in the case of a complete test of CRC data without DQMap, the setting of its data source may be the same as the test of the data source of the complete test of CRC data with DQMap, and the forward and reverse DQMap conversion functions are disabled. Of course, the embodiment is not limited to this. For example, in the case of a complete test of CRC data without DQMap, the setting of its data source may also be one or more of the data sources mentioned above.

[0107] Corresponding to the testing method 300 according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a testing device.

[0108] It can be understood that the following combined with exemplary drawings (such as Figure 5 ) is only for ease of understanding, and the various aspects of the exemplary drawings should not be used as limitations of the test device. For example, the test device can be changed according to different application scenarios (for example, different data verification, whether to enable DQMap, whether targeted testing or random testing is required, etc.).

[0109] Figure 4 FIG. 4 is a schematic diagram of a testing device 400 according to at least one embodiment of the present disclosure.

[0110] See also Figure 4 , the testing device includes a data communication unit 410 and a read-write unit 420 .

[0111] The data communication unit 410 is configured to perform data communication with the device under test via a double rate physical layer interface to transmit target data.

[0112] The read / write unit 420 is configured to perform read / write processing on target data, wherein the target data is used to perform data verification to test the performance of the device under test.

[0113] Exemplarily, the data communication unit may correspond to Figure 5 In the DFI, the read and write units can correspond to Figure 5 One or both of (1) a write monitor together with a CRC calculator 1.18, a calculated CRC code 1.19 and a CRC comparison 1.20 and (2) a read driver.

[0114] As described above, the test device according to at least one embodiment of the present disclosure can implement the read and write processing of target data via DFI, implement data verification based on the target data, and thus test the device under test. Figure 2 Compared with the test device described above, which needs to purchase DDR PHY from a third-party IP supplier, the test device according to at least one embodiment of the present disclosure can get rid of the dependence on the third-party IP supplier.

[0115] It is understood that the test device 400 may also include one or more additional modules or units for implementing one or more steps or functions corresponding to the test method 300 and its additional aspects. To avoid repetition or ambiguity of the description, some exemplary additional aspects of the test device according to at least one embodiment of the present disclosure are described below.

[0116] For example, in the test device according to at least one embodiment of the present disclosure, data verification includes a cyclic redundancy check, and the target data includes write data and a write cyclic redundancy check code of the write data. The data communication unit includes: a receiving unit, configured to: receive the write data and the write cyclic redundancy check code from the tested device via the DFI, and the read-write unit includes: a write unit, configured to: perform a cyclic redundancy check on the write data based on the write data and the write cyclic redundancy check code.

[0117] For example, according to the test device of at least one embodiment of the present disclosure, the write unit includes: a digital relationship mapping conversion unit, configured to: in response to whether DQMap is enabled, selectively perform forward digital relationship mapping conversion on the write data and the write cyclic redundancy check code, respectively, to obtain the target data to be processed and the target cyclic redundancy check code to be processed; a cyclic redundancy check calculation unit, configured to: perform cyclic redundancy check calculation on the target data to be processed to obtain a calculated cyclic redundancy check code; and a comparison unit, configured to: compare whether the calculated cyclic redundancy check code and the target cyclic redundancy check code to be processed are consistent.

[0118] Exemplarily, the mapping conversion unit may be Figure 5 A write monitor described, including a write monitor or a portion of a write monitor.

[0119] For example, in a test device according to at least one embodiment of the present disclosure, data verification includes a cyclic redundancy check, and the target data includes read data and a read cyclic redundancy check code of the read data, the data communication unit includes: an output unit, configured to: send the read data and the read cyclic redundancy check code to the tested device via the DFI, wherein the test device performs a cyclic redundancy check on the read data based on the read data and the read cyclic redundancy check code, and the read-write unit includes: a read unit, configured to: generate read data and a read cyclic redundancy check code.

[0120] For example, according to the test device of at least one embodiment of the present disclosure, the reading unit includes: a target data source selection unit, configured to: select a target data source from multiple data sources; and a generation unit, configured to: read data and read cyclic redundancy check codes based on target source data of the target data source.

[0121] Exemplarily, the mapping conversion unit may be Figure 5 The described read driver includes a read driver or a portion of a read driver.

[0122] For example, in a test device according to at least one embodiment of the present disclosure, the multiple data sources include a data storage device and a first random data generator and a second random data generator inside the test device, and the target data source selection unit includes: a first target data source selection unit, configured to: select one of the data storage device and the first random data generator as an intermediate target data source based on a first data source selection signal; and a second target data source selection unit, configured to: select one of the intermediate target data source and the second random data generator as a target data source based on a second data source selection signal, and the generation unit includes: a first generation unit, configured to: in response to the target data source being the first random data generator or the data storage device, perform reverse DQM on the target source data; ap conversion, generating reverse DQMap converted target source data as read data; performing cyclic redundancy check calculation on the target source data to generate a first intermediate cyclic redundancy check code; and performing reverse DQMap conversion on the first intermediate cyclic redundancy check code to obtain a read cyclic redundancy check code; or a second generating unit, configured to: in response to the target source data being a second random data generator, use the target source data as read data; perform forward DQMap conversion on the target source data to obtain forward DQMap converted target source data; perform cyclic redundancy check calculation on the forward DQMap converted target source data to generate a second intermediate cyclic redundancy check code; and perform reverse DQMap conversion on the second intermediate cyclic redundancy check code to obtain a read cyclic redundancy check code.

[0123] The above-mentioned additional aspects of the testing device 400 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the testing method 300 according to at least one embodiment of the present disclosure. Therefore, the technical effects of the additional aspects of the testing method 300 according to at least one embodiment of the present disclosure may also be mapped to the additional aspects of the testing device 400 according to at least one embodiment of the present disclosure, which will not be repeated here.

[0124] The following describes the above combination with an example application scenario. Figure 3 and Figure 4 It is understood that the example application scenarios described below are only examples and not limitations, and are intended to implement the above combination in specific application scenarios. Figure 3 and Figure 4 One or more aspects of the present invention, and the various aspects described below in conjunction with the example application scenario can be combined with the above Figure 3 and Figure 4 one or more aspects of a combination.

[0125] The example application scenario involves, for example, a test device for CRC data verification based on a DFI interface, which can freely verify CRC data verification in complex scenarios including DQMap.

[0126] Figure 5 A schematic diagram of a DDR memory CRC data testing device according to at least one embodiment of the present disclosure is shown. Figure 5 The described DDR memory CRC data test device mainly involves a write channel data processing flow and device, a read channel data processing flow and device, thereby functionally replacing the data storage, digital conversion, and CRC calculation functions of the real DDR PHY and DIMM.

[0127] See also Figure 5 , the system bus is responsible for sending data (such as Figure 5 Random write data in 1.1), and read the data returned by the tested device (such as Figure 5 The system reads data in 1.2).

[0128] The data written to the system bus has a write CRC calculated in the device under test (for example, by performing CRC calculation on the data), and after reverse DQMap conversion, the device under test sends it to the test device. The device under test and the test device achieve data communication via DFI.

[0129] After receiving the data, the test device first performs a forward DQMap on the write data (such as Figure 5 1.13 in the figure), complete the data recovery, and then use the recovered write data to perform CRC calculation (for example, via CRC calculator 1.18), and compare the obtained CRC check bits (shown as calculated CRC code 1.19) with the CRC sent by the tested device (as shown in the figure). Figure 5 1.20 in the example), the write CRC check is completed, and the alert_n signal is driven according to the check result to complete the result feedback.

[0130] When the system reads back, the test device generates read data (DFI read data 1.7) and read CRC code (DFI read CRC code), which are transmitted to the device under test. Data parsing and CRC comparison are performed in the device under test, and the results are returned to the upper-level system.

[0131] See also Figure 5 ,The test device also includes a data storage device for storing the data written by the ,system, and can also be used as a data source for the read channel, e.g. Figure 3 The read and write addresses of the data storage device are determined by the information carried by the read and write commands through the address converter (such as Figure 5 1.21 in the figure).

[0132] By configuring the read and write commands, you can implement random read and write test scenarios, and also support the tested device to complete data consistency verification. Compared with traditional tested devices, this example application scenario breaks through the limitations of single address reading and writing, and can achieve more realistic and complex data consistency checks, which helps to enrich test scenarios.

[0133] The test device in the example application scenario can achieve one or more of the following effects. For example, a memory is designed in the test device, so that the test device can break through the limitation of single address reading and writing, which helps to enrich the test scenario. For another example, adding the drive of the alert_n signal in the write data channel to simulate the behavior of the real DRAM can be used to provide support for system process testing.

[0134] Combine the following Figures 6 to 10 Specifically, the following describes the above-mentioned reference 1 and reference 2 in terms of the write channel and the read channel, respectively. Figure 5 The test setup is described, and Figures 6 to 10 Involved Figure 5 One or more aspects of the test apparatus are described in greater detail.

[0135] The following describes the entire data processing flow and device of the write channel. Figures 6 to 8 hereinafter are described exemplary aspects of a read channel.

[0136] Figure 6 A schematic diagram of a write channel data processing flow according to at least one embodiment of the present disclosure is shown.

[0137] Back to Figure 5 , data (e.g., random write data 1.1) is generated from the system bus and transferred to the device under test. Figure 6 In block 2.1, the test device may obtain a write address from the DFI interface. In block 2.2, the test device may obtain write data from the DFI interface.

[0138] After the test device receives the write data, since the write data obtained on the DFI interface may have undergone a reverse DQMap operation, the test device needs to be designed for this situation before calculating the CRC. For example, in order to support random testing of DQMap and increase the test range, the test device adopts an optional DQMap design. Figure 6 The two gating devices (demultiplexing 2.4 and multiplexing 2.6) shown in blocks 2.4 and 2.6 are implemented together. For example, in block 2.4, the write data obtained from the DFI interface can form two data paths via demultiplexing.

[0139] If DQMap is not enabled, the first path (block 2.4 - directly connected path of block 2.6) may be selected. In block 2.6, via the first path, the write data may be directly multiplexed to, for example, a CRC calculator (by Figure 5 1.18 in the figure), so that in box 2.7, a cyclic check code algorithm can be called to calculate the CRC code of the write data. If DQMap is enabled, the second path (the path from 2.4 to 2.5 and then to 2.6) can be selected. In the second path, in box 2.5, a forward DQMap conversion can be performed on the write data according to the DQMap configuration to generate forward DQMap converted write data (i.e., data recovery is achieved), and then the forward DQMap converted write data can be multiplexed to, for example, a CRC calculator, so that in box 2.7, a cyclic check code algorithm can be called to calculate the CRC code of the write data. In some embodiments, the DQMap configuration here is consistent with the device under test.

[0140] The test device can support multiple CRC algorithms, and the CRC algorithm can be customized according to the requirements of the device under test. For example, if the CRC algorithm of the device under test is CRC-8, the CRC algorithm in the test device is also CRC-8. In other aspects, when the algorithm of the device under test changes, the processing flow of the test device does not need to be changed, and only the CRC algorithm needs to be changed.

[0141] After calculating the CRC code, in block 2.9, the calculated CRC code (e.g., corresponding to Figure 5 1.19 or the target cyclic redundancy check code to be processed above). It can be understood that the calculated CRC code is generated in the test environment in the test device.

[0142] Back to Figure 6 The write data obtained from the DFI interface can be written into the data storage device 2.8 inside the test device through the first path or the second path. Exemplarily, the data storage device can be a memory or other suitable data storage device for storing data.

[0143] The address of the data storage device is obtained from the DFI interface (ie, as shown in block 2.1). In block 2.3, the address obtained from the DFI interface is converted into a format inside the data storage device. Then, the write data is written into the corresponding address.

[0144] In an additional aspect, the device under test can use the same address to read back the written data. In this way, the test apparatus can implement verification of the original data by the device under test.

[0145] Figure 7A schematic diagram of a write channel CRC code processing flow according to at least one embodiment of the present disclosure is shown.

[0146] The process of writing CRC code can be similar to writing data. Figure 7 In block 3.1, the test device obtains the write CRC code from the DFI interface. Similar to writing data, the test device adopts the design of optional DQMap. Figure 7 The two selection devices (demultiplexing 3.2 and multiplexing 3.4) shown in boxes 3.2 and 3.4 are implemented together. Among them, if DQMap is not enabled, the first path (the directly connected path of box 3.2-box 3.4) can be selected. If DQMap is enabled, the second path (the path of 3.2-3.3-3.4) can be selected. In the second path, in box 3.3, according to the DQMap configuration, the received CRC code is converted to a forward DQMap converted CRC code to generate a forward DQMap converted CRC code (that is, CRC recovery is implemented). Then, in box 3.5, depending on the selection of the first path and the second path, the received CRC code or the forward DQMap converted CRC code is obtained. The CRC code received in box 3.5 or the CRC code after the forward DQMap conversion) can be used to Figure 6 Compare with the CRC check code obtained in box 2.9.

[0147] Figure 8 A schematic diagram of a write channel CRC comparison process according to at least one embodiment of the present disclosure is shown.

[0148] See also Figure 8 , Box 4.1 can correspond to Figure 6 The calculated CRC code obtained in box 2.9 in box 4.2 may correspond to Figure 7 The CRC code received in box 3.5 or the CRC code converted by the forward DQMap. In box 4.3, the calculated CRC code and the received CRC code or the CRC code converted by the forward DQMap can be compared to see if they are equal. If they are equal, the comparison is successful, indicating that the CRC check has passed. If they are not equal, the comparison fails, indicating that the CRC check has failed.

[0149] In block 4.4, the comparison result can be returned to the DFI interface. According to the standard DDR protocol, when the CRC check fails, the DRAM will pull down the alret_n signal as a notification of comparison failure to the upper system for subsequent processing. After the comparison fails, the test device can also pull down the alert_n signal as a sign of comparison failure. In this way, the subsequent processing flow of the upper system will not be interfered with, and system-level testing can be supported.

[0150] Through the above-mentioned write channel, the test device in the example application scenario can achieve one or more of the following effects. For example, the write channel data processing flow of the test device and the design of the device can replace the functions of the real DIMM or DIMM model, and support more and more flexible DQMap configurations. For another example, the test device can support random configuration of DQMap, which helps to improve coverage. For another example, the test device can declare the timing of CRC calculation in the data processing flow, which can only be done after the forward DQMap conversion of the data is completed. The CRC code cannot be directly calculated for the received data, otherwise the result will be wrong, because the written data may undergo a reverse DQMap operation, and is therefore applicable to possible DQMap situations. For another example, the test device can support multiple CRC algorithms (such as CRC-8, CRC-16, etc.), which can be consistent with the CRC algorithm adopted by the device under test.

[0151] The entire data processing flow and device of the read channel are described below.

[0152] The read channel is mainly used to obtain read data, calculate the CRC code of the read data, and perform DQMap operations on the read data and CRC code. The generated read data and CRC code are read back by the device under test to complete the CRC check of the read data. In addition, it can also support the device under test to check the correctness of reading and writing.

[0153] The following will be combined Fig. 9 and Fig.10 hereinafter are described exemplary aspects of a read channel.

[0154] Fig. 9 A schematic diagram of a read channel CRC code processing flow according to at least one embodiment of the present disclosure is shown. Fig.10 A schematic diagram of a read channel data processing flow according to at least one embodiment of the present disclosure is shown.

[0155] In terms of the read channel, multiple data generation modes for read data can be implemented. For example, the multiple data generation modes may include a random data generation mode and a data storage device generation mode. The random data generation mode may be generated by, for example, a random data generator (e.g. Figure 5 1.29 and 1.26 in Figure 1.29) to achieve random data generation ( Fig.10 The data storage device generation mode can read data from the data storage device inside the test device. The selection of multiple data generation modes can be performed by the data source selection signal (e.g. Fig.10 This can be achieved as shown in Boxes 6.4 and 6.8 in FIG.

[0156] The random data generation mode may include two random data generation methods. The corresponding data processing flows of the two random data generation methods are described below.

[0157] One way to generate random data is to send the generated random data directly to the DFI as read data. For example, see Fig.10 In terms of generating read data, in block 6.6, the environment randomly generates source data 2 5.5 to be read back (eg, generated by random data generator 1.26). Then, the source data 2 can be multiplexed to the DFI interface through the multiplexing unit 6.7 via the data selection signal 2.

[0158] In this case, since the upper device (for example, the device under test) will think that the read data sent to the DFI is after reverse DQMap, when using this method, before calculating the CRC code, it is necessary to restore the randomly generated data to the original data after forward DQMap before calculating the CRC code. For example, see Fig. 9 In block 5.6, a forward DQMap transformation may be performed on the source data 2 shown in block 5.5 according to the DQMap configuration to generate target source data of the forward DQMap transformation.

[0159] This method can support the test of read-only scenarios. In addition, due to the existence of reverse DQMap conversion, there may be a delay between the generation of read data and the generation of CRC code. This method can be used in test scenarios that are not sensitive to delay.

[0160] Another way to generate random data is to send the generated random data to the DFI as the original read data. When using this method, the target source data can be directly used for CRC calculation. For example, see Fig. 9 The environment randomly generates source data 1 5.2 to be read back (for example, generated by random data generator 1.29) and can be selected via multiplexing units 5.3 and 5.7 via data source selection signal 1 and data source selection signal 2. Subsequently, in block 5.10, a cyclic checksum algorithm can be called to calculate the CRC value of source data 1 5.2.

[0161] In this case, the source data 1 5.2 needs to be reverse DQMapped before being sent to the DFI. For example, see Fig.10 , in box 6.5, the source data 1 5.2 can be subjected to reverse DQMap transformation according to the DQMap configuration to generate reverse DQMap transformed target source data.

[0162] This method can also support the test of read-only scenarios. In addition, since there is no DQMap transformation of the original data, there is no delay in data generation and CRC generation, which is more suitable for test scenarios with requirements on latency.

[0163] For the data storage device generation mode, its implementation is similar to the other random data generation mode mentioned above, except that the data source is the data storage device. For example, the test device can store the data received from the device under test and use it as the read data source. The test device considers the data read back from the data storage device as the original data and can directly calculate the CRC. For example, see Fig. 9 The target source data to be read back in the data storage device 5.1 can be selected via the multiplexing units 5.3 and 5.7 via the data source selection signal 1 and the data source selection signal 2. Subsequently, in block 5.10, a cyclic checksum algorithm can be called to calculate the CRC value of the target source data.

[0164] In this case, the target source data needs to be reverse-DQMapped and sent to the DFI as read data. For example, see Fig.10 , in block 6.5, the source data 15.2 may be subjected to a reverse DQMap transformation according to the DQMap configuration to generate reverse DQMap transformed target source data.

[0165] The random data generation mode and the data storage device generation mode can be implemented by the data source selection signal 1 and the data source selection signal, so that the data / data 1 / data 2 of the data storage device can be selected as the target source data in block 5.9. For example, see Figure 5 and Fig.10 , the multiplexing unit can be controlled by the data source selection signal 1 6.4 ( Figure 5 Multiplexing unit 1.30 or Fig.10 The multiplexing unit (6.3) in the data storage device or random data generator 1.29 is selected as the intermediate target data source, that is, the data from the data storage device or random data generator 1.29 is selected. Then, the multiplexing unit (6.3) can be controlled by the data source selection signal 26.8. Figure 5 Multiplexing units 1.25 and 1.31 or Fig.10 The multiplexing unit 6.7 in the middle is used to select the intermediate target data source or the random data generator 1.26 as the target data source, thereby selecting the data from the intermediate target data source or the random data generator 1.29 to facilitate the generation of read data and read cyclic redundancy code.

[0166] Subsequently, in block 5.10, the cyclic check code algorithm can be called in the CRC calculator 1.33 to calculate the CRC code of the target source data or the forward DQMap conversion, thereby obtaining the intermediate CRC code in block 5.11. In block 5.12, the CRC code is subjected to reverse DQMap conversion according to the DQMap configuration to generate the reverse DQMap converted CRC code. In block 5.13, the reverse DQMap converted CRC code is transmitted back to the DFI interface (i.e., the DFI reads the CRC code, corresponding to the read cyclic redundancy code above).

[0167] The address used to read the data storage device can also come from the DFI, and after address conversion, it can be used to read the read data from the data storage device of the test device. This design can directly verify the correctness of the read and write data by the upper system, which is helpful for testing the system process. For example, when the read and write addresses are set to be the same, a closed-loop data verification test can be completed.

[0168] Through the above-mentioned read channel, the test device in the example application scenario can achieve one or more of the following effects. For example, it can replace the function of a real DIMM or DIMM model and support more and more flexible DQMap configurations. For another example, by designing DQMap selection to support random configuration of DQMap, more scenarios can be covered and the coverage rate can be improved. For another example, the choice of read data source is increased to support a variety of test scenarios, such as read-only, write first and read later, etc. For another example, when DQMap is disabled, it is compatible to avoid two consecutive data conversions, reduce channel delays, and reduce the probability of errors introduced by data conversion. For another example, it can support situations where DQMap is disabled and randomly configured, so that a set of devices can be compatible with the testing of all scenarios of DQMap and CRC verification.

[0169] In the above example application scenario, the device under test may be a DDR controller. In this case, the test device may achieve one or more of the following effects.

[0170] For example, the test device of the DDR controller usually needs to build a real DDR PHY and DIMM in it to access the DDR controller. This causes problems such as high purchase cost and heavy debugging workload. In contrast, the test device in this example application scenario is based on the DFI interface design, which saves a lot of money and time costs. In addition, the test device in this example application scenario provides high flexibility, supports random data injection, random DQMap loading and data conversion, and can fully verify the CRC and DQMap design of the DDR controller.

[0171] For example, in the simulation verification of DDR controller, it is usually necessary to purchase DDR PHY design or DDR PHY model, and then purchase DIMM model, which is very costly. In addition, there are risks in terms of technical support and upgrading of third-party design or verification components. In addition, some third-party components are encrypted, which severely limits the debugging space of users and is not conducive to the flexibility of verification. In addition, the function release of third parties generally lags behind the latest industry specifications and cannot verify the latest features. In contrast, the data conversion mechanism, data calculation process, and verification process of the test device in this example application scenario can also be used in simulation verification work. Moreover, based on the DFI interface implementation, it completely eliminates the dependence on third-party DDR PHY design or verification components and DIMM models, and can achieve completely independent development and verification, give full play to the advantages of random verification, and fully verify the completeness of the DQMap and CRC functions of the DDR controller. For example, the correctness of the DQMap implementation can also be used as the object of test. For example, when DQMap is enabled or not enabled, check whether the CRC function of the tested device is correct. For example, detect the data correctness of the data reading and writing path of the tested device. For example, stress testing of continuous transmission of large amounts of data, etc.; in addition, the test device in this example application scenario can timely implement the latest technical specifications in the industry on the simulation platform, do preliminary research, and is conducive to the design and implementation of the latest technology for DDR controllers.

[0172] More generally, in combination with the write channel and the read channel, the test device in the example application scenario can achieve one or more of the following effects. For example, the test device is based on the DFI interface protocol. From a hardware perspective, there is no need to purchase and produce DDRPHY, purchase and install DIMM; from a software perspective, there is no need to purchase and install DDR PHY design or test components, DIMM design or test components, which can greatly save procurement funds, shorten the production, installation and debugging cycle of related hardware equipment, reduce related manpower investment, and obtain benefits in multiple dimensions of funds, manpower, and time. For another example, it can get rid of the dependence on related third-party hardware and software and can be completely independently developed. For another example, the test device can track and implement the latest technology and support the tested equipment to implement cutting-edge technology. For another example, the test device can perform complete testing of random DQMap and CRC data of random data, and can fully test and evaluate the design indicators and actual performance of the tested equipment.

[0173] It is understood that the above example application scenarios are only exemplary and the present disclosure is not limited thereto. Various aspects involved in the above example application scenarios can be applied to other scenarios.

[0174] For example, the test device and corresponding method or concept in the example application scenario can be applicable to situations where data mapping exists and certain operations are performed on the mapped data. It can include a DDR controller and other media, such as an HDD controller, a NAND controller, an HBM controller, and two interfaces in a communication link.

[0175] For another example, the test device and corresponding method or concept in the example application scenario is applicable to a wide range of hardware implementations, including but not limited to Sillicon, FPGA, CPLD, ASIC including a programmable array, etc.

[0176] For another example, the test device and corresponding methods or concepts in the example application scenario are suitable for implementation in the software field, including but not limited to verification test environment, and the implementation tools include but are not limited to UVM, SystemVerilog, Verilog, C, C++, etc.

[0177] For another example, the data transformation, conversion, calculation, processing, and detection process for DQMap and CRC in the example application scenario is also applicable to other application scenarios where data mapping exists and the mapped data undergoes transformation, conversion, calculation, processing, and detection.

[0178] For example, the testing device and corresponding methods or concepts in the example application scenario are suitable for data operations and verification checks of various sequential / non-sequential systems involving data transformation and conversion involving changes in digital relationship mapping relationships, including but not limited to storage systems, communications between different interfaces, and data transmission systems.

[0179] Fig.11 A schematic diagram of an electronic device 1100 according to at least one embodiment of the present disclosure is shown.

[0180] like Fig.11 As shown, the electronic device 1100 includes at least one processing unit 1120 and a memory 1110. The memory 1110 stores computer-readable instructions and is in communication with the processing unit 1120. The processing unit 1120 executes the computer-readable instructions stored in the memory 1110 to implement the test method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0181] For example, the memory 1110 and the processing unit 1120 may communicate with each other directly or indirectly. Fig.11As shown, the electronic device 1100 may further include a system bus 1130, and the memory 1110 and the processing unit 1120 may communicate with each other through the system bus 1130. For example, the processing unit 1120 may access the memory 1110 through the system bus 1130. For example, in other examples, components such as the memory 1110 and the processing unit 1120 may communicate through a network on chip (NOC) connection.

[0182] For example, the processing unit 1120 can control other components in the electronic device 1100 to perform desired functions. The processing unit 1120 can be a device with data processing capabilities and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU), and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0183] For example, the memory 1110 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc.

[0184] For example, one or more computer-readable instructions may be stored on the memory 1110, and the processing unit 1120 may execute the computer-readable instructions to implement various functions. Various applications and various data may also be stored in the computer-readable storage medium, such as instruction processing codes and various data used and / or generated by the application.

[0185] For example, some computer instructions stored in the memory 1110 may be executed by the processing unit 1120 to perform one or more steps in the testing method described above.

[0186] For example, Fig.11As shown, the electronic device 1100 may further include an input interface 1140 that allows an external device to communicate with the electronic device 1100. For example, the input interface 1140 may be used to receive instructions from an external computer device, from a user, etc. The electronic device 1100 may further include an output interface 1150 that interconnects the electronic device 1100 and one or more external devices. For example, the electronic device 1100 may output a signal to the user through the output interface 1150, etc.

[0187] It should be noted that the electronic device 1100 according to at least one embodiment of the present disclosure is illustrative rather than restrictive, and according to actual application requirements, the electronic device 1100 may also include other conventional components or structures. For example, to realize the necessary functions of the electronic device, those skilled in the art may set other conventional components or structures according to the specific application scenario, and the embodiments of the present disclosure are not limited to this.

[0188] At least one embodiment of the present disclosure further provides a processor, such as an SMT processor, which includes an electronic device according to at least one embodiment of the present disclosure. The maximum number of threads that the SMT processor can support can be, for example, 2, 4, 8, etc., and can be a single-core or multi-core processor. For example, the processor core can adopt a micro-architecture such as X86, ARM, RISC-V, etc., and can include a first-level or multi-level cache, which is not limited by the embodiments of the present disclosure.

[0189] At least one embodiment of the present disclosure also provides a computer-readable storage medium. Fig.12 A schematic diagram of a computer-readable storage medium 1200 is shown, in accordance with at least one embodiment of the present disclosure.

[0190] For example, Fig.12 As shown, the computer-readable storage medium 1200 stores computer-readable instructions 1210 , and when the computer-readable instructions 1210 are executed by a computer (including a processor), the testing method and additional aspects thereof according to at least one embodiment of the present disclosure can be implemented.

[0191] For example, one or more computer-readable instructions may be stored on the computer-readable storage medium 1200. Some of the computer-readable instructions stored on the computer-readable storage medium 1200 may be, for example, instructions for implementing one or more steps in the above-mentioned testing method.

[0192] For example, the computer-readable storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above computer-readable storage media, or other applicable storage media. For example, the computer-readable storage medium 1200 may include the memory 1110 in the above electronic device 1100.

[0193] At least some embodiments of the present disclosure also provide an electronic device. Fig.13 A schematic diagram of another electronic device 1300 is shown in accordance with at least one embodiment of the present disclosure.

[0194] The electronic device according to at least one embodiment of the present disclosure can be implemented as but not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc.

[0195] Fig.13 The electronic device 1300 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0196] For example, Fig.13 As shown, in some examples, the electronic device 1300 includes a processor 1301, which may include a processor of any of the above embodiments (e.g., an SMT processor), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1302 or a program loaded from a storage device 1308 to a random access memory (RAM) 1303. Various programs and data required for the operation of the computer system are also stored in the RAM 1303. The processor 1301, the ROM 1302, and the RAM 1303 are connected to each other via a bus 1304. An input / output (I / O) interface 1305 is also connected to the bus 1304.

[0197] For example, the following components may be connected to the I / O interface 1305: an input device 1306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1309 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1309 may allow the electronic device 1300 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. The drive 1310 is also connected to the I / O interface 1305 as needed. Removable media 1311, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1310 as needed, so that the computer program read therefrom can be installed into the storage device 1308 as needed. Although Fig.13 The electronic device 1300 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0198] For example, the electronic device 1300 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1309 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0199] In addition to the above exemplary descriptions, the following points need to be explained for this disclosure:

[0200] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0201] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0202] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A testing method comprising: Performing data communication with the device under test via a double rate physical layer interface to transmit target data; as well as Read and write processing is performed on target data, wherein the target data is used to perform data verification to test the performance of the device under test.

2. The testing method according to claim 1, wherein: The data check includes a cyclic redundancy check.

3. The testing method according to claim 2, wherein: The target data includes write data and a write cyclic redundancy check code of the write data, Performing data communication with a device under test via a double rate physical layer interface to transmit target data, comprising: receiving the write data and the write cyclic redundancy check code from the device under test via the double rate physical layer interface; and The reading and writing processing of the target data includes: performing a cyclic redundancy check on the write data based on the write data and the write cyclic redundancy check code.

4. The testing method according to claim 3, wherein: Performing a cyclic redundancy check on the write data based on the write data and the write cyclic redundancy check code includes: In response to whether the digital relationship mapping is enabled, selectively performing forward digital relationship mapping conversion on the write data and the write cyclic redundancy check code to obtain target data to be processed and target cyclic redundancy check code to be processed; Performing cyclic redundancy check calculation on the target data to be processed to obtain a calculated cyclic redundancy check code; and Compare the calculated cyclic redundancy check code with the target cyclic redundancy check code to be processed to see if they are consistent.

5. The testing method according to claim 4, wherein: In response to whether the digital relationship mapping is enabled, selectively performing forward digital relationship mapping conversion on the write data and the write cyclic redundancy check code to obtain target data to be processed and target cyclic redundancy check code to be processed, including: In response to the digital relationship mapping being enabled, forward digital relationship mapping conversion is performed on the write data and the write cyclic redundancy check code respectively to obtain target data to be processed and target cyclic redundancy check code to be processed.

6. The testing method according to claim 4, wherein: In response to whether the digital relationship mapping is enabled, selectively performing forward digital relationship mapping conversion on the write data and the write cyclic redundancy check code to obtain target data to be processed and target cyclic redundancy check code to be processed, including: In response to the bit relationship mapping being not enabled, the write data is directly used as the target data to be processed and the write cyclic redundancy check code is directly used as the target cyclic redundancy check code to be processed.

7. The testing method according to claim 4, further comprising: The result of the comparison is returned to the double rate physical layer interface.

8. The testing method according to claim 4, further comprising: The write data is stored in a data storage device inside a test device that executes the test method.

9. The testing method according to claim 8, wherein: Storing the write data in the data storage device comprises: receiving a write address of the write data via the double rate physical layer interface and converting the write address into an internal format address of the data storage device; and The target data to be processed is written into the data storage device based on the internal format address.

10. The test method according to claim 2, wherein: The target data includes read data and a read cyclic redundancy check code of the read data, Performing data communication with a device under test via a double rate physical layer interface to transmit target data, comprising: sending the read data and the read cyclic redundancy check code to the device under test via the double rate physical layer interface, wherein the test device performs a cyclic redundancy check on the read data based on the read data and the read cyclic redundancy check code; and The reading and writing processing of the target data includes: generating the read data and the read cyclic redundancy check code.

11. The testing method according to claim 10, wherein: Generating the read data and the read cyclic redundancy check code comprises: Selecting a target data source from among a plurality of data sources; and The read data and the read cyclic redundancy check code are obtained based on the target source data of the target data source.

12. The testing method according to claim 11, wherein: The plurality of data sources include a data storage device and a random data generator inside a test device that executes the test method.

13. The testing method according to claim 12, wherein: The random data generator includes a first random data generator and a second random data generator, and selects target source data from a plurality of data sources, including: selecting one of the data storage device and the first random data generator as an intermediate target data source based on a first data source selection signal; and selecting one of the intermediate target data source and the second random data generator as the target data source based on a second data source selection signal, and Obtaining read data and the read cyclic redundancy check code based on target source data of the target data source includes: In response to the target data source being the first random data generator or the data storage device, performing a reverse digital relationship mapping conversion on the target source data to generate reverse digital relationship mapping converted target source data as the read data; performing a cyclic redundancy check calculation on the target source data to generate a first intermediate cyclic redundancy check code; and performing a reverse digital relationship mapping conversion on the first intermediate cyclic redundancy check code to obtain the read cyclic redundancy check code; and In response to the target source data being the second random data generator, the target source data is used as the read data; a forward digital relationship mapping conversion is performed on the target source data to obtain the target source data of the forward digital relationship mapping conversion; a cyclic redundancy check calculation is performed on the target source data of the forward digital relationship mapping conversion to generate a second intermediate cyclic redundancy check code; And performing a reverse digital relationship mapping conversion on the second intermediate cyclic redundancy check code to obtain the read cyclic redundancy check code.

14. The testing method according to claim 13, wherein: Obtaining read data and a read cyclic redundancy check code of the read data based on target source data of the target data source includes: The target source data of the target data source is used as the read data, and a cyclic redundancy check calculation is performed on the target source data of the target data source to obtain the read cyclic redundancy check code.

15. A testing device comprising: a data communication unit configured to perform data communication with the device under test via a double rate physical layer interface to transmit target data; as well as The read / write unit is configured to perform read / write processing on target data, wherein the target data is used to perform data verification to test the performance of the device under test.

16. The testing device according to claim 15, wherein: The data check includes a cyclic redundancy check, and the target data includes write data and a write cyclic redundancy check code of the write data, The data communication unit comprises: a receiving unit, configured to: receive the write data and the write cyclic redundancy check code from the device under test via the double rate physical layer interface, The read-write unit comprises: The write unit is configured to perform a cyclic redundancy check on the write data based on the write data and the write cyclic redundancy check code.

17. The testing device according to claim 16, wherein: The writing unit comprises: The digital relationship mapping conversion unit is configured to: in response to whether the digital relationship mapping is enabled, selectively perform forward digital relationship mapping conversion on the write data and the write cyclic redundancy check code to obtain target data to be processed and target cyclic redundancy check code to be processed; A cyclic redundancy check calculation unit is configured to: perform a cyclic redundancy check calculation on the target data to be processed to obtain a calculated cyclic redundancy check code; and The comparison unit is configured to compare whether the calculated cyclic redundancy check code is consistent with the target cyclic redundancy check code to be processed.

18. The testing device according to claim 15, wherein: The data check includes a cyclic redundancy check, and the target data includes read data and a read cyclic redundancy check code of the read data, The data communication unit comprises: an output unit, configured to: send the read data and the read cyclic redundancy check code to the device under test via the double rate physical layer interface, wherein the test device performs a cyclic redundancy check on the read data based on the read data and the read cyclic redundancy check code, The read-write unit comprises: The read unit is configured to generate the read data and the read cyclic redundancy check code.

19. The testing device according to claim 18, wherein: The reading unit comprises: a target data source selection unit, configured to: select a target data source from a plurality of data sources; and The generating unit is configured to: read the data and the read cyclic redundancy check code based on the target source data of the target data source.

20. The testing device according to claim 19, wherein: The plurality of data sources include a data storage device and a first random data generator and a second random data generator inside the test device, and the target data source selection unit includes: A first target data source selection unit is configured to: select one of the data storage device and the first random data generator as an intermediate target data source based on a first data source selection signal; and a second target data source selection unit, configured to: select one of the intermediate target data source and the second random data generator as the target data source based on a second data source selection signal, and The generating unit comprises: A first generating unit is configured to: in response to the target data source being the first random data generator or the data storage device, perform a reverse digital relationship mapping conversion on the target source data to generate the reverse digital relationship mapping converted target source data as the read data; perform a cyclic redundancy check calculation on the target source data to generate a first intermediate cyclic redundancy check code; and perform a reverse digital relationship mapping conversion on the first intermediate cyclic redundancy check code to obtain the read cyclic redundancy check code; or The second generation unit is configured to: in response to the target source data being the second random data generator, use the target source data as the read data; perform a forward digital relationship mapping conversion on the target source data to obtain the target source data of the forward digital relationship mapping conversion; perform a cyclic redundancy check calculation on the target source data of the forward digital relationship mapping conversion to generate a second intermediate cyclic redundancy check code; and perform a reverse digital relationship mapping conversion on the second intermediate cyclic redundancy check code to obtain the read cyclic redundancy check code.

21. An electronic device comprising at least one processing unit and a memory; wherein: The memory stores computer-readable instructions and is communicatively connected to the at least one processing unit; The at least one processing unit is configured to execute the computer-readable instructions stored in the memory to implement the testing method according to any one of claims 1-14.

22. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer-readable instructions. When a processor executes the computer-readable instructions, the testing method according to any one of claims 1 to 14 is implemented.

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