Semiconductor package and method of forming same

Abstract

A method of forming a semiconductor package is provided. The method includes forming a microlens recessed from a top surface of a substrate, a concave region being formed between a surface of the microlens and the top surface of the substrate. The method includes depositing a first dielectric material filling a portion of the concave region using a spin-coating process. The method includes depositing a second dielectric material filling a remaining portion of the concave region and covering a top surface of the substrate using the chemical vapor deposition process. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and over a top surface of the substrate. The method includes bonding a semiconductor wafer to a substrate via a bonding layer.

Description

Technical Field

[0001] The disclosed embodiments relate to a semiconductor manufacturing technology, and more particularly to a semiconductor package including a microlens and a method for forming the same. Background Art

[0002] One technology for signal transmission and processing is electrical signaling and processing. In addition, in recent years, optical signaling and processing has been used in an increasing number of applications, especially due to the use of optical fiber related applications to transmit signals.

[0003] The transmission and processing of optical signals are often combined with the transmission and processing of electrical signals to provide mature applications. For example, optical fibers can be used for long-distance signal transmission, while electrical signals can be used for short-distance signal transmission and processing and control. Therefore, devices integrating optical components and electrical components are produced for conversion between optical signals and electrical signals and processing of optical signals and electrical signals. Therefore, a package (also called a photonic package) can include an optical (photonic) die and an electronic die, wherein the optical (photonic) die includes an optical device and the electronic die includes an electronic device. However, the manufacture of photonic packages faces many challenges. Summary of the invention

[0004] Some embodiments of the present disclosure provide a method for forming a semiconductor package. The method includes forming a microlens recessed from the top surface of a substrate, wherein a concave region is formed between the surface of the microlens and the top surface of the substrate. The method includes using a spin coating process to deposit a first dielectric material that fills a portion of the concave region. The method includes using a chemical vapor deposition process to deposit a second dielectric material that fills the remaining portion of the concave region and covers the top surface of the substrate. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and on the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.

[0005] Some embodiments of the present disclosure provide a method for forming a semiconductor package. The method includes forming a microlens recessed from the top surface of a substrate, wherein a concave region is formed between the surface of the microlens and the top surface of the substrate. The method includes using a spin coating process to deposit a dielectric material that fills the concave region and covers the top surface of the substrate. The method includes using a lithography process to pattern the dielectric material, leaving only a portion of the dielectric material in the concave region. The method includes planarizing the patterned dielectric material. The method includes forming a bonding layer on the planarized dielectric material and on the top surface of the substrate. The method includes bonding a semiconductor wafer to a substrate via the bonding layer.

[0006] Some embodiments of the present disclosure provide a semiconductor package, including a substrate, a microlens, a first dielectric material, a second dielectric material, a bonding layer, and a semiconductor wafer. The microlens is recessed from the top surface of the substrate, wherein a concave area is formed between the surface of the microlens and the top surface of the substrate. The first dielectric material is disposed on the concave area and adjacent to the surface of the microlens. The second dielectric material fills the concave area and is located above the first dielectric material, wherein the second dielectric material is different from the first dielectric material. The bonding layer is formed on the top surface of the substrate and contacts the second dielectric material. The semiconductor wafer is bonded to the bonding layer, wherein the semiconductor wafer includes an optical component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The concepts of the disclosed embodiments are better understood with reference to the following detailed description and the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features in the drawings are not necessarily drawn to scale. In fact, the sizes of the various features may be arbitrarily enlarged or reduced to make a clear description.

[0008] Figures 1 to 16 A cross-sectional view illustrating an intermediate stage in the formation process of a photonic package according to some embodiments.

[0009] Figure 10-1 A cross-sectional view illustrating an intermediate stage in the formation process of a photonic package according to some embodiments.

[0010] Figures 17 to 21 A cross-sectional view illustrating an intermediate stage in the formation process of a photonic package according to some embodiments.

[0011] Figure 22 to Figure 26 A cross-sectional view illustrating an intermediate stage in the formation process of a photonic package according to some embodiments.

[0012] Figure 24-1 A cross-sectional view illustrating an intermediate stage in the formation process of a photonic package according to some embodiments.

[0013] The reference numerals are described as follows:

[0014] 10: Photonic Packaging

[0015] 20: Photonic Packaging

[0016] 30: Photonic Packaging

[0017] 100: First (semiconductor) wafer

[0018] 102: Buried Oxide Substrate

[0019] 102A: Silicon layer

[0020] 102B: Oxide layer

[0021] 102C: Substrate / wafer

[0022] 104: (Silicon) waveguide

[0023] 106: Photon Components

[0024] 107: Grating Coupler

[0025] 108: Dielectric layer

[0026] 110: Photonic Routing Structure

[0027] 113: Contact

[0028] 114: Conductive characteristics

[0029] 118: Dielectric layer

[0030] 120: Redistribution structure

[0031] 122: Electronic grains

[0032] 124: Die connector

[0033] 126: Dielectric Materials

[0034] 127: Through hole

[0035] 128: Passivation layer

[0036] 130: Under Bump Metal Layer

[0037] 132: Conductive connector

[0038] 200: Second (semiconductor) wafer

[0039] 202: Substrate

[0040] 202A: Top surface

[0041] 204: Microlens

[0042] 205: Concave area

[0043] 206: Anti-reflective coating

[0044] 206A: Part I

[0045] 206B: Part 2

[0046] 208: (First) Dielectric Materials

[0047] 208A: Part I

[0048] 208B: Part 2

[0049] 210: (Second) Dielectric Materials

[0050] 212: Bonding layer

[0051] 212': Bonding layer

[0052] 230: Photosensitive dielectric materials

[0053] 230A: Part I

[0054] 230B: Part 2

[0055] 235: Photopatterning process

[0056] 240: Photomask

[0057] DR: Opaque Region

[0058] 310: Photonic Routing Structure

[0059] 312: Dielectric layer

[0060] 314: Nitride waveguide / Silicon nitride waveguide

[0061] 316: Fiber Optic

[0062] 318: Optical adhesive

[0063] G: Groove DETAILED DESCRIPTION

[0064] The following disclosure provides many different embodiments or examples to implement different features of the embodiments of the present disclosure. The following describes specific examples of components and configurations to simplify the description of the embodiments of the present disclosure. Of course, these specific examples are only for demonstration and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first feature is formed on or above the second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself limit the relationship between the various embodiments and / or configurations described.

[0065] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature(s) depicted in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in different orientations (rotated 90 degrees or at other orientations) and the spatially relative terms used herein interpreted similarly.

[0066] According to some embodiments of the present disclosure, a photonic package and a method for forming the same are provided. The photonic package may include a lens substrate and a semiconductor wafer bonded to the lens substrate, wherein the lens substrate may include a recessed micro lens that is optically coupled to an optical component within the semiconductor wafer. In some embodiments, during the formation of the lens substrate, the concave region (or gap) of the micro lens may be partially filled with a first dielectric material formed by a spin coating process and then completely filled with a second dielectric material formed by a chemical vapor deposition (CVD) process. In this way, due to the fluidity of the spin coating process, the first dielectric material may effectively reduce the surface morphology (i.e., surface height difference) of the top surface of the lens substrate. In this way, the second dielectric material subsequently formed may have a correspondingly reduced surface morphology, which helps to improve the performance of the subsequent planarization process (e.g., may reduce process time and cost). In some other embodiments, during the formation of the lens substrate, the concave area of ​​the microlens can be filled only by a single photosensitive dielectric material formed by a spin coating process. In this way, due to the fluidity of the spin coating process, the photosensitive dielectric material can also effectively reduce the surface topography (i.e., surface height difference) of the top surface of the lens substrate, and the planarized area of ​​the photosensitive dielectric material can be pre-defined by the photo patterning process. Therefore, the gap filling process is simplified and the performance of the subsequent planarization process is improved.

[0067] The embodiments discussed herein provide examples of the subject matter that can be implemented or used in the present disclosure, and those of ordinary skill in the art will readily appreciate that modifications can be made while remaining within the intended scope of the different embodiments. In each view and illustrative embodiment, similar reference symbols are used to indicate similar elements. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0068] Figures 1 to 16 A photonic package 10 is shown according to some embodiments (see Fig.16) is a cross-sectional view of an intermediate stage of the formation process of a photonic package 10. In some cases, the photonic package 10 can be a part of a semiconductor package or another structure. The photonic package 10 can provide an input / output (I / O) interface between optical signals and electrical signals in the semiconductor package. In some embodiments, the photonic package 10 provides an optical network for signal communication between components within the photonic package 10 (e.g., photonic components, integrated circuits, coupling with external optical fibers, etc.). In some cases, the photonic package 10 can be considered an "optical engine".

[0069] First reference Figure 1 According to some embodiments, a buried oxide (BOX) substrate 102 is provided. The buried oxide substrate 102 includes an oxide layer 102B formed on a substrate 102C, and a silicon layer 102A formed on the oxide layer 102B. The oxide layer 102B may include or be formed of, for example, silicon oxide. The substrate 102C may include materials such as glass, ceramics, dielectrics, semiconductors, etc., or a combination thereof. In some embodiments, the substrate 102C is a semiconductor substrate, such as a bulk semiconductor substrate, etc., which may be doped or undoped. In some embodiments, the semiconductor material of the substrate 102C may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium in phosphide and / or gallium indium arsenide phosphide; or a combination thereof. In Figure 1 In the illustrated embodiment, the substrate 102C is a wafer, such as a silicon wafer. The substrate / wafer 102C includes an edge portion ( Figure 1 Not shown in Figure 5 ), and when viewed from the top, the edge portion forms a complete ring. In other embodiments, other substrates, such as multilayer or gradient substrates, may also be used.

[0070] exist Figure 2In some embodiments, the silicon layer 102A is patterned to form silicon regions for a plurality of waveguides 104, a plurality of photonic components 106, and a plurality of grating couplers 107 (only one waveguide 104, one photonic component 106, and one grating coupler 107 are shown). In this way, the silicon layer 102A may be considered an "optical layer" in some cases. The silicon layer 102A may be patterned using suitable lithography and etching techniques. For example, in some embodiments, a hard mask layer (e.g., a nitride layer, etc., not shown) may be formed on the silicon layer 102A and patterned. However, an etching process may be used to transfer the pattern of the hard mask layer to the silicon layer 102A. The etching process may include a dry etching process and / or a wet etching process, which may include an anisotropic etching process. In some embodiments, more than one lithography and etching process may be used to pattern the silicon layer 102A.

[0071] The waveguide 104 may be formed from a patterned silicon layer 102A. For example, the silicon layer 102A may be etched to form a recessed portion defining the waveguide 104, wherein the remaining non-recessed portion defines the sidewalls of the waveguide 104. In some embodiments where a plurality of waveguides 104 are formed, the plurality of waveguides 104 may be separate waveguides 104 or connected into a single continuous structure. In some embodiments, one or more waveguides 104 form a continuous loop.

[0072] The photonic component 106 may be integrated with the waveguide 104 and may be formed with the waveguide 104. The photonic component 106 may be optically coupled to the waveguide 104 and may interact with an optical signal within the waveguide 104. The photonic component 106 may include a photonic device, such as a photodetector, a modulator, other photonic devices, etc. For example, a photodetector may be optically coupled to the waveguide 104 to detect an optical signal within the waveguide 104 and generate an electrical signal corresponding to the optical signal. As another example, a modulator may be optically coupled to the waveguide 104 to receive an electrical signal and generate a corresponding optical signal within the waveguide 104 by modulating the optical power within the waveguide 104. In this way, the photonic component 106 may facilitate input / output (I / O) of optical signals to or from the waveguide 104. In other embodiments, the photonic component 106 may include other active or passive components, such as laser diodes, optical signal splitters (splitters), phase shifters, interferometers, oscillators, or other types of photonic structures or devices.

[0073] In some embodiments, a photodetector may be formed by partially etching a region of the waveguide 104 and growing an epitaxial material on the remaining silicon in the etched region. The waveguide 104 may be etched using acceptable lithography and etching techniques. The epitaxial material may include a semiconductor material such as germanium, which may be doped or undoped. In some embodiments, as part of the formation of the photodetector, an implantation process may be performed to introduce a dopant (e.g., a p-type dopant, an n-type dopant, or a combination of both) into the silicon in the etched region. In some embodiments, a modulator may be formed by, for example, partially etching a region of the waveguide 104 and then implanting an appropriate dopant (e.g., a p-type dopant, an n-type dopant, or a combination of both) into the remaining silicon in the etched region. In some embodiments, the etched region for the photodetector and the etched region for the modulator may be formed using one or more of the same lithography or etching steps. In some embodiments, the etched region for the photodetector and the etched region for the modulator may be implanted using one or more of the same implantation steps.

[0074] The grating coupler 107 may be formed with the waveguide 104. The grating coupler 107 is a device that allows an optical signal and / or optical power to be coupled between the waveguide 104 and another photonic component (e.g., a vertically mounted optical fiber (e.g., Fig.16 104) or a photonic structure for transmitting between waveguides of another photonic system. The grating coupler 107 may be formed using acceptable lithography and etching techniques. In some embodiments, the grating coupler 107 is formed after the waveguide 104 is defined. For example, a photoresist may be formed on the waveguide 104 and patterned, wherein the pattern of the photoresist corresponds to the grating coupler 107. The waveguide 104 may then be subjected to one or more etching processes using the patterned photoresist as an etching mask to form the grating coupler 107. The etching process may include one or more dry etching processes and / or wet etching processes, which may include an anisotropic etching process.

[0075] In some embodiments, other types of couplers (not shown for simplicity) may be formed, such as between the waveguide 104 and other waveguides of the photonic package 10 (e.g., Fig.14 In some embodiments, an edge coupler (not shown for simplicity) may also be formed that allows optical signals and / or optical power to be transmitted between the waveguide 104 and a photonic component (not shown) mounted horizontally to the sidewall of the photonic package 10. These and other photonic structures are also within the contemplated scope of the present disclosure.

[0076] In some cases, the waveguide 104, the photonic component 106, and the grating coupler 107 may be collectively referred to as a "photonic layer" or a "photonic integrated circuit (PIC)". Other configurations or arrangements of the waveguide 104, the photonic component 106, and / or the grating coupler 107 are also possible and are not limited to Figure 2 Those shown in .

[0077] exist Figure 3 According to some embodiments, at the front side of the buried oxide substrate 102 (eg, Figure 3 The dielectric layer 108 is formed on the waveguide 104, the photonic component 106, the grating coupler 107, and the oxide layer 102B to form a photonic routing structure 110. The dielectric layer 108 is formed on the waveguide 104, the photonic component 106, the grating coupler 107, and the oxide layer 102B. The dielectric layer 108 may be formed of one or more layers of silicon oxide, silicon nitride, etc., or a combination thereof, and may be formed by any acceptable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), lamination, etc., or a combination thereof. Other dielectric materials formed by any acceptable process may also be used.

[0078] In some embodiments, the dielectric layer 108 is then thinned using a planarization process such as a chemical-mechanical polish (CMP) process, a grinding process, or the like. In some cases, a thinner dielectric layer 108 can allow the grating coupler 107 to be aligned with a vertically mounted photonic component (e.g., Fig.16 In other embodiments, the planarization process may expose the surface of the waveguide 104, the photonic component 106 and / or the grating coupler 107.

[0079] Due to the different refractive indices of the materials of the waveguide 104 and the dielectric layer 108, the waveguide 104 can have a high internal reflection such that light is substantially confined within the waveguide 104, depending on the wavelength of the light and the refractive indices of the respective materials. In some embodiments, the refractive index of the material of the waveguide 104 is higher than the refractive index of the material of the dielectric layer 108. For example, the waveguide 104 can include silicon, and the dielectric layer 108 can include silicon oxide and / or silicon nitride. Therefore, the waveguide 104 can be referred to herein as a "silicon waveguide".

[0080] Still refer to Figure 3According to some embodiments, a redistribution structure 120 is formed on top of the dielectric layer 108. The redistribution structure 120 is an interconnect structure that includes one or more dielectric layers (collectively referred to as "dielectric layers 118") and includes conductive features 114 formed in the dielectric layers 118 that provide interconnect and circuit routing. For example, the conductive features 114 of the redistribution structure 120 may provide connections to, for example, the photonic components 106 and the vias 127 (see Fig.16 ) and / or such lower components as electronic chips (see Figure 4 ) and other upper components.

[0081] Dielectric layer 118 may be, for example, an insulating layer or a passivation layer and may include one or more materials similar to dielectric layer 108 described above, such as silicon oxide or silicon nitride, or may include different materials. Dielectric layer 118 and / or dielectric layer 108 may be suitable for wavelengths suitable for coupling between grating coupler 107 and a vertically mounted optical fiber (e.g., Fig.16 The dielectric layer 118 may be transparent or nearly transparent to light transmitting optical signals or optical power between optical fibers 316 shown in FIG. 1 and FIG. 2 . The dielectric layer 118 may be formed using similar techniques as described above for the dielectric layer 108 or using different techniques.

[0082] Conductive features 114 may include conductive lines and vias and may be formed by a damascene process, such as single damascene, dual damascene, etc. For example, conductive features 114 may be formed by depositing a dielectric layer 118 and then forming an opening extending through dielectric layer 118. Acceptable lithography and etching techniques may be used to form the opening. According to some embodiments, a conductive material may then be formed in the opening, thereby forming conductive features 114 in dielectric layer 118. In some embodiments, a liner layer (not shown) such as a diffusion barrier layer (e.g., a layer made of tantalum, tantalum nitride, titanium, titanium nitride, etc.) may be formed in the opening and may be formed using a suitable deposition process (e.g., ALD, etc.). In some embodiments, a seed layer (not shown) including copper or a copper alloy may then be deposited in the opening. The conductive material of conductive features 114 may be formed in the opening using, for example, an electroplating process. The conductive material may include a metal or a metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, or an alloy thereof. A planarization process (e.g., a CMP process or a grinding process) may be performed to remove excess conductive material along the top surface of the dielectric layer 118 so that the conductive features 114 are flush with the top surface of the dielectric layer 118. Another dielectric layer 118 may then be deposited over the conductive features 114, and a similar process may be performed to form additional conductive features 114. In this manner, this process may be repeated to form multiple layers of dielectric layers 118 and conductive features 114. In other embodiments, other techniques or materials may be used to form the conductive features 114.

[0083] In some embodiments, the topmost conductive feature 114 of the redistribution structure 120 may include conductive pads, bonding pads, etc. The topmost conductive feature 114 may be formed in the topmost dielectric layer 118 of the redistribution structure 120. A planarization process (e.g., a CMP process, etc.) may be performed after forming the topmost conductive feature 114 so that the topmost conductive feature 114 is substantially level or coplanar with the surface of the topmost dielectric layer 118. In some embodiments, the bottommost conductive feature 114 of the redistribution structure 120 may include conductive pads, etc. The bottommost conductive feature 114 may be formed in the bottommost dielectric layer 118 of the redistribution structure 120. The redistribution structure 120 may include a conductive pad, etc. Figure 3 More or fewer dielectric layers 118 or conductive features 114 are shown.

[0084] In some embodiments, the bottom-most conductive feature 114 of the redistribution structure 120 also includes a contact 113 that extends through the dielectric layer 108 and is electrically connected to the photonic component 106. The contact 113 allows electrical power or electrical signals to be transmitted to and from the photonic component 106. In this way, the photonic component 106 can convert electrical signals into optical signals transmitted by the waveguide 104, and / or can convert optical signals from the waveguide 104 into electrical signals. The contact 113 can be formed before or after forming the other bottom-most conductive features 114 of the redistribution structure 120. In some embodiments, the contact 113 can be formed using techniques or materials similar to those described above for the other bottom-most conductive features 114.

[0085] exist Figure 4 , according to some embodiments, a plurality of electronic dies 122 (only one electronic die 122 is shown) are bonded to a redistribution structure 120. Each electronic die 122 may be, for example, a semiconductor device, die, or wafer that may communicate with the photonic component 106 using electrical signals. In some embodiments, the electronic die 122 may process electrical signals received from the photonic component 106 or may generate electrical signals that are converted by the photonic component 106 into optical signals. The electronic die 122 includes a die connector 124, which may be, for example, a conductive pad, a conductive column, etc. The electronic die 122 is bonded to the topmost conductive feature 114 (e.g., a bonding pad) of the redistribution structure 120 via the die connector 124.

[0086] The electronic die 122 may include an integrated circuit (not shown) for controlling the operation of the photonic component 106. For example, the electronic die 122 may include a controller, a driver, etc., or a combination thereof. In some embodiments, the electronic die 122 may include a central processing unit (CPU) or a memory function. In some embodiments, the electronic die 122 includes an integrated circuit for processing an electrical signal received from the photonic component 106 (e.g., a photodetector). In some embodiments, the electronic die 122 may control the high-frequency signal transmission of the photonic component 106 according to an electrical signal received from another device or die. In some embodiments, the electronic die 122 may be an electronic integrated circuit (EIC) that provides a serializer / deserializer (SerDes) function, etc. In this way, the electronic die 122 may serve as part of an I / O interface between optical signals and electrical signals within the photonic package 10. In some cases, the photonic package 10 described herein may be considered a system-on-chip (SoC) or system-on-integrated-circuit (SoIC) device. The electronic die 122 may be obtained, for example, by sawing or cutting a semiconductor wafer (having a plurality of integrated circuit dies formed thereon) along scribe lines to separate the semiconductor wafer into a plurality of individual semiconductor dies. The details of the electronic die 122 will not be further described herein.

[0087] In some embodiments, dielectric-to-dielectric bonding and / or metal-to-metal bonding are used to bond the electronic die 122 to the redistribution structure 120. In such embodiments, dielectric-to-dielectric bonding may occur between the topmost dielectric layer 118 and a bonding layer (not separately shown) of the electronic die 122. During the bonding process, metal-to-metal bonding may also occur between the die connector 124 of the electronic die 122 and the topmost conductive feature 114 of the redistribution structure 120.

[0088] In some embodiments, the redistribution structure 120 and / or the electronic die 122 are subjected to surface treatment before the bonding process is performed. In some embodiments, the bonding surface of the redistribution structure 120 and / or the electronic die 122 may be first treated by, for example, dry treatment, wet treatment, plasma treatment, exposure to an inert gas, exposure to hydrogen (H 2 ), exposure to nitrogen (N 2 ), exposure to oxygen (O2 ) or a combination thereof. However, any suitable activation process may be utilized. After the activation process, the redistribution structure 120 and / or the electronic die 122 may be cleaned using, for example, a chemical rinse. The electronic die 122 may then be aligned with the redistribution structure 120 and placed in physical contact with the redistribution structure 120 using, for example, a pick-and-place process. The redistribution structure 120 and the electronic die 122 may then be heat treated and / or brought into close proximity with each other (e.g., by applying contact pressure) to bond the redistribution structure 120 and the electronic die 122. For example, the redistribution structure 120 and the electronic die 122 may be subjected to a pressure of about 200 kPa or less and to a temperature in the range of about 200° C. to about 400° C. The redistribution structure 120 and the electronic die 122 can then be subjected to a temperature at or above the eutectic point of the materials of the topmost conductive feature 114 and the die connector 124 (e.g., a temperature in the range of about 150° C. to about 650° C.) to fuse the topmost conductive feature 114 to the die connector 124. In this way, the dielectric-to-dielectric bonding and metal-to-metal bonding of the redistribution structure 120 and the electronic die 122 form a bonded structure. In some embodiments, the bonded structure is further baked, annealed, pressed, or otherwise processed to strengthen or finalize the bonds.

[0089] exist Figure 5 In some embodiments, a dielectric material 126 is formed over the electronic grains 122 and the redistribution structure 120. The dielectric material 126 may be formed of silicon oxide, silicon nitride, polymer, etc., or a combination thereof, and may be formed by CVD, PVD, ALD, spin coating processes, etc., or a combination thereof. In some embodiments, the dielectric material 126 is a gap filling material, which may include one or more of the above-mentioned example materials. In some embodiments, the dielectric material 126 may be a dielectric material having a wavelength suitable for the optical fiber (e.g., 102) mounted vertically between the grating coupler 107 and the vertically mounted optical fiber. Fig.16 In some embodiments, dielectric material 126 may be a material that is substantially transparent to light for transmitting optical signals or optical power between optical fibers 316 shown in FIG. 1 and FIG. 2 . In some embodiments, dielectric material 126 may be a material similar to the material of dielectric layer 118 and / or dielectric layer 108. Other dielectric materials formed by any acceptable process may also be used. A planarization process such as a CMP process, a grinding process, etc. may then be used to planarize dielectric material 126. In some embodiments, the planarization process may expose electronic grains 122 so that the electronic grains 122 are coplanar with the surface of dielectric material 126.

[0090] It is important to understand that Figure 5The resulting structure shown in is in the form of a wafer (i.e., not yet singulated), so for the purpose of illustration, this resulting structure is also referred to as the first (semiconductor) wafer 100 below, which includes multiple electronic dies and multiple photonic dies (only one electronic die 122 and one corresponding photonic die (i.e., the structure below the electronic die 122) are shown). The above features can be parts of the same device die among the multiple device dies of the first wafer 100 (including the multiple photonic dies and the multiple electronic dies 122 bonded thereto).

[0091] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allow the 3D package or 3DIC to be tested, probes and / or probe cards may be used, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods for intermediate verification of known good dies to improve yield and reduce costs.

[0092] In some embodiments, Figure 5 At the stage shown in FIG. 1 (i.e., before bonding to another wafer), an edge trimming process (not shown separately) may be performed to trim the Figure 5 The edge portion of the substrate (ie, wafer) 102C of the resulting structure shown in FIG. 1 is formed to form a groove G (which is a groove ring). In some embodiments, the first wafer 100 may be bonded to another wafer (eg, Fig.12 The edge trimming process is then performed on the second wafer 200 shown in FIG. The edge trimming process can be performed by an etching process, which can be a plasma etching process. In some embodiments, other suitable edge trimming processes, such as mechanical trimming processes, can also be used. The function of the groove G will be described later.

[0093] Next, refer to Figure 6 According to some embodiments, a Figure 5 The substrate 202 of the first wafer 100 is shown. The substrate 202 can be a rigid structure that can provide structural or mechanical stability. The use of the substrate 202 can reduce the warping or bending of the first wafer 100, thereby improving the performance of optical structures such as the waveguide 104 or the photonic component 106. In some embodiments, the substrate 202 is formed of a material (e.g., silicon) that is transparent to light of the relevant wavelength, so that optical signals can be transmitted through the substrate 202. Figure 6In the illustrated embodiment, the substrate 202 is a wafer, such as a silicon wafer. In other embodiments, other suitable materials (eg, silicon oxide, metal, organic core material, etc.) may be used for the substrate 202 .

[0094] Figure 6 Also shown is the formation of a plurality of microlenses 204 (for simplicity, only one microlens 204 is shown) within a substrate 202 (also referred to as a lens substrate 202) according to some embodiments. The microlenses 204 can facilitate the grating coupler 107 (see FIG. 1 ) in the photonic package 10. Figure 2 ) with vertically mounted optical fibers (e.g. Fig.16 2A ) between the optical fibers 316 shown in FIG. 2A and the optical fibers 316 shown in FIG. 2A . In some embodiments, the microlenses 204 are formed on the top surface 202A of the substrate 202 (e.g., recessed from the top surface 202A), and a concave region (concavearea) 205 is formed between the surface of each microlens 204 and the top surface 202A of the substrate 202. The microlenses 204 may be formed using acceptable lithography and etching techniques. For example, in some embodiments, a hard mask layer (e.g., a nitride layer, etc., not shown) may be formed on the top surface 202A of the substrate 202 and patterned, wherein the pattern of the hard mask layer corresponds to the microlenses 204. An etching process may then be performed on the substrate 202 using the patterned hard mask layer as an etching mask to form the microlenses 204. The etching process may be a dry etching process or a wet etching process, which may include an isotropic etching process. In some embodiments, more than one lithography and etching process may be used to form the microlenses 204. In some embodiments, after forming the microlenses 204, the hard mask layer may be removed from the substrate 202 using an ashing process or other acceptable etching process. Alternatively, after forming the microlenses 204, the hard mask layer may still remain.

[0095] exist Figure 7In the embodiment of the present invention, an anti-reflection coating (ARC) 206 is conformally formed on the top surface 202A of the substrate 202 including the recessed microlens 204. The anti-reflection coating 206 may include a first portion 206A formed on the top surface 202A of the substrate 202, and a second portion 206B formed on the surface of the microlens 204 and the sidewall of the recessed region 205. The anti-reflection coating 206 is present to reduce light reflection occurring on these surfaces (i.e., reduce light loss), thereby improving the optical coupling efficiency within the photonic package 10. Although illustrated as a single layer, the anti-reflection coating 206 is a multi-layer structure in some embodiments. The anti-reflection coating 206 may include multiple layers (e.g., two layers, three layers, or more layers) made of silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination thereof. Each of these layers may be formed to have a suitable thickness by any acceptable process (e.g., CVD, PVD, ALD, or other acceptable deposition processes). In some cases, the anti-reflective coating 206 can also serve as a subsequent planarization process (see Fig.10 In other embodiments, the anti-reflective coating 206 may also be omitted.

[0096] exist Figure 8 In some embodiments, after forming the anti-reflective coating 206, a dielectric material 208 is deposited in the concave region 205 (of each microlens 204). In some embodiments, the dielectric material 208 (also referred to as a gap filling material) is formed to fill a portion of the concave region 205 (e.g., 70% or more of the volume of the concave region 205, but the present disclosure is not limited thereto) without extending above the top surface 202A of the substrate 202. In some embodiments, the dielectric material 208 is a silicon-oxygen-carbon based compound and is deposited using a spin coating process. For example, the dielectric material 208 may include silicon (Si), oxygen (O), carbon (C), any other suitable element, or a combination thereof. In some embodiments, the silicon concentration in the dielectric material 208 is about 5 weight percent (wt%) to about 30 weight percent, the oxygen concentration in the dielectric material 208 is about 5 weight percent to about 60 weight percent, and / or the carbon concentration in the dielectric material 208 is about 5 weight percent to about 90 weight percent. In some embodiments, the dielectric material 208 is composed of silicon, oxygen, and carbon, such that the total concentration of silicon, oxygen, and carbon in the dielectric material 208 is substantially 100%. In some embodiments, the dielectric material 208 can be a material that is substantially transparent to light of a wavelength suitable for transmitting an optical signal or optical power between the grating coupler 107 and a vertically mounted optical fiber (e.g., carbon-doped silicon oxide).

[0097] During the spin coating process, the dielectric material 208 is applied in a liquid state over the top surface 202A of the substrate 202 and in the concave regions 205. A spin coater (not shown) holding the substrate 202 may then be rotated at a suitable speed until the desired thickness of the dielectric material 208 is achieved. Figure 8 In the illustrated embodiment, the spin coater can rotate at a relatively high speed so that all the dielectric material 208 on the top surface 202A of the substrate 202 is thrown off, leaving only a portion of the dielectric material 208 in the concave region 205. Due to the fluidity of the spin coating process, the dielectric material 208 can well fill the concave region 205, thereby reducing the formation of voids or cracks at the interface between the substrate 202 and the dielectric material 208 during the subsequent thermal treatment process. In some embodiments, after the dielectric material 208 reaches a desired thickness (as described above), a curing process (e.g., a thermal curing process) is performed to cure the dielectric material 208. For illustration, the dielectric material 208 is also referred to as the first dielectric material 208 hereinafter.

[0098] exist Fig. 9 In some embodiments, a second dielectric material 210 is conformally deposited over the top surface 202A of the substrate 202 and over the first dielectric material 208 in the concave region 205. In some embodiments, the second dielectric material 210 (also referred to as a gap filler material) is formed to fill the remaining portion of the concave region 205 and cover the top surface 202A of the substrate 202. In some embodiments, the second dielectric material 210 includes silicon and oxygen and is deposited using a CVD process. In some embodiments, the second dielectric material 210 can also be a material (e.g., silicon oxide) that is substantially transparent to light of a wavelength suitable for transmitting an optical signal or optical power between the grating coupler 107 and the vertically mounted optical fiber.

[0099] Due to the isotropic deposition nature of the CVD process, the second dielectric material 210 is formed to have a surface topography that matches the surface topography of the underlying structure. In this regard, since the concave region 205 in the top surface 202A of the substrate 202 has been partially filled with the first dielectric material 208 in the previous step, the surface topography (i.e., the surface height difference) of the top surface 202A is reduced, as shown in FIG. Fig. 9 As shown in . Therefore, compared with the case where the first dielectric material 208 is not filled in the concave region 205, the surface morphology of the second dielectric material 210 thereon is correspondingly reduced. This helps to improve the performance of the subsequent planarization process.

[0100] exist Fig.10 According to some embodiments, a planarization process such as a CMP process, a grinding process, etc. is used (eg Fig.10The second dielectric material 210 is planarized (or thinned) by the planarization process (as indicated by the solid arrow in FIG. 2 ). In some embodiments, the planarization process may expose the first portion 206A of the anti-reflective coating 206 above the top surface 202A of the substrate 202, so that the first portion 206A of the anti-reflective coating 206 is substantially horizontal or coplanar with the top surface of the remaining second dielectric material 210. In this case, the anti-reflective coating 206 may serve as a stop layer for the planarization process. In some embodiments, after the planarization process, a thin film of the second dielectric material 210 remains on the top surface 202A of the substrate 202, which is conducive to forming a bonding layer 212 on the top surface 202A in a subsequent process (see FIG. 2 ). Fig.11 ).exist Fig.10 In the example of FIG. 1 , the concave region 205 (of the microlens 204 ) is filled with two dielectric materials (ie, the dielectric material 208 and the dielectric material 210 ) after the planarization process.

[0101] As described above, since the second dielectric material 210 has a reduced surface topography (compared to the case where a single oxide material is deposited only in the concave region 205 using a CVD process), it can be planarized more easily and quickly. Therefore, the performance of the planarization process is improved (e.g., the process time and cost are reduced).

[0102] exist Figure 10-1 In some embodiments shown, after the second dielectric material 210 covering the first portion 206A of the anti-reflective coating 206 is planarized (i.e., removed), a planarization process such as a CMP process, a grinding process, etc. (e.g., Figure 10-1 The planarization process may expose the top surface 202A of the substrate 202, so that the top surface of the remaining second dielectric material 210 is flush with the top surface 202A of the substrate 202. In some embodiments, the planarization process for the first portion 206A of the anti-reflective coating 206 may be omitted, as shown in FIG. Fig.10 For simplicity, the following reference is made to Figures 11 to 16 The process described in some embodiments is followed by Fig.10 Then, these processes can also be followed by Figure 10-1 Execute after the example.

[0103] exist Fig.11In some embodiments, a bonding layer 212 is deposited on the planarized second dielectric material 210 and on the top surface 202A of the substrate 202 (and on the first portion 206A of the anti-reflective coating 206, if any). The bonding layer 212 may be formed of or include, for example, a silicon-based dielectric material, such as silicon oxide ((SiO2), SiN, SiON, SiOCN, SiC, SiCN, etc. or a combination thereof, and may be formed using high-density plasma chemical vapor deposition (HDPCVD), plasma enhanced chemical vapor deposition (PECVD), CVD, low-pressure chemical vapor deposition (LPCVD), ALD, etc.

[0104] It is important to understand that Fig.11 The resulting structure shown in FIG. 1 is in wafer form (i.e., has not yet been singulated), and thus for purposes of illustration, this resulting structure is also referred to hereinafter as a second (semiconductor) wafer 200, which includes a plurality of dies (only one die is shown, including one or more microlenses 204 embedded in a substrate 202). The above-mentioned features may be parts of the same die among the plurality of dies of the second wafer 200. The lateral dimensions (e.g., length, width, and / or area) of the second wafer 200 may be greater than, approximately the same as, or less than Figure 5 The lateral dimensions (eg, length, width and / or area) of the first wafer 100 are shown in FIG.

[0105] exist Fig.12 In some embodiments, Figure 5 The first wafer 100 shown in FIG. 1 is flipped and bonded to the second wafer 200 using a “wafer-on-wafer (WoW)” bonding process. In some embodiments, the first wafer 100 is bonded to the bonding layer 212 of the second wafer 200 using a bonding layer 212. In some embodiments, before the bonding process, the exposed surfaces (e.g., Figure 5 A bonding layer 212 ′ (similar to the bonding layer 212 ) is formed on the upper surface of the second wafer 200 . Dielectric-to-dielectric bonding may occur between the bonding layer 212 of the second wafer 200 and the bonding layer 212 ′ of the first wafer 100 .

[0106] In some embodiments, before performing the WoW bonding process, the first wafer 100 and / or the second wafer 200 are subjected to surface treatment. In some embodiments, the bonding surface of the first wafer 100 and / or the second wafer 200 may be first treated by, for example, dry treatment, wet treatment, plasma treatment, exposure to an inert gas, exposure to hydrogen (H 2 ), exposure to nitrogen (N 2 ), exposure to oxygen (O 2 ) or the like or a combination thereof for activation. However, any suitable activation process may be utilized. After the activation process, the first wafer 100 and / or the second wafer 200 may be cleaned using, for example, chemical rinsing. The first wafer 100 is then aligned with the second wafer 200 (e.g., the device die of the first wafer 100 is aligned with the die of the second wafer 200, and the grating coupler 107 is aligned with the microlens 204) and placed in physical contact with the second wafer 200. The first wafer 100 may be placed on the second wafer 200 using, for example, a pick-and-place process. The first wafer 100 and the second wafer 200 may then be brought close to each other (e.g., by applying contact pressure) to bond the first wafer 100 and the second wafer 200. For example, the first wafer 100 and the second wafer 200 may be subjected to a pressure of about 200 kPa or less at about room temperature. In this way, the dielectric-to-dielectric bonding of the first wafer 100 and the second wafer 200 forms a bonding structure. In other embodiments, other suitable WoW bonding processes may also be used.

[0107] exist Fig.13 In some embodiments, a removal process is used to thin the substrate 102C of the first wafer 100. In some cases, thinning the substrate 102C can improve the waveguide 104 and the additional nitride waveguide 314 (see Fig.14 ) between the substrate / wafer 102C. The removal process may include a planarization process (e.g., CMP or grinding process), an etching process, etc., or a combination thereof. In some embodiments, after the removal process, the substrate 102C may be completely removed from the underlying structure, or a portion of the substrate 102C may remain. In some embodiments, by providing a groove G at an edge portion of the substrate / wafer 102C (see Figure 5 )(due to the edge trimming process), stress issues that may occur during substrate removal can be reduced or avoided.

[0108] In some embodiments, one or more reflectors (not shown) may be formed in the thinned substrate 102C and adjacent to the grating coupler 107 to direct light from one or more vertically mounted optical fibers 316 (e.g., see Fig.16 ) is reflected into the grating coupler 107. These and other photonic structures are also within the intended scope of the present disclosure.

[0109] exist Fig.14 102B (or thinned substrate 102C, if any) according to some embodiments. Photonic routing structure 310 includes one or more dielectric layers (collectively referred to as "dielectric layer 312") and includes a plurality of silicon nitride waveguides 314 formed in dielectric layer 312. In some embodiments, silicon nitride waveguide 314 provides additional optical signal routing and can be optically coupled with waveguide 104. In some cases, a waveguide formed of silicon nitride (e.g., nitride waveguide 314) can have advantages over a waveguide formed of silicon (e.g., waveguide 104). For example, silicon nitride has a higher dielectric constant than silicon, and thus a nitride waveguide can have greater internal confinement of light than a silicon waveguide. This can also make the performance or leakage of the nitride waveguide less sensitive to process variations, less sensitive to dimensional uniformity, and less sensitive to surface roughness (e.g., edge roughness or line width roughness). The method of forming the silicon nitride waveguide 314 may be similar to the method described above for forming the silicon waveguide 104 .

[0110] exist Fig.15 In some embodiments, a via 127 is formed extending through the dielectric layer 312, the thinned substrate 102C (if any), the oxide layer 102B, and the dielectric layer 108 to physically and electrically contact the conductive feature 114 of the redistribution structure 120. The via 127 may be formed using techniques and materials similar to those described above for forming the conductive feature 114.

[0111] Still refer to Fig.15, according to some embodiments, a conductive connector 132 is then formed over the via 127. The conductive connector 132 can be used to electrically connect the photonic package 10 to an external structure, such as a package substrate, an interposer, etc. In some embodiments, an optional passivation layer 128 is formed over the dielectric layer 312. The passivation layer 128 can include, for example, a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene BCB, etc., and can be formed by spin coating, lamination, CVD, PVD, ALD, etc. In some embodiments, under-bump metallizations (UBMs) 130 can be formed within the passivation layer 128 to make physical and electrical contact with the via 127. The under-bump metallization layer 130 can be formed of one or more suitable conductive materials using a suitable process such as electroplating. According to some embodiments, a conductive connector 132 is then formed on the underbump metallization layer 130 using a suitable process (e.g., electroplating, printing, solder transfer, ball placement, etc.). The conductive connector 132 may be, for example, a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. The conductive connector 132 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof.

[0112] exist Fig.16 In some embodiments, Fig.15 The resulting package structure shown in FIG. 1 is flipped and attached to a temporary carrier (e.g., a glass carrier, a ceramic carrier, etc., not shown). In some embodiments, a singulation process is then performed by, for example, sawing along scribe lines (not shown) of the package structure to separate the plurality of photonic packages within the package structure into individual photonic packages 10 (e.g., Fig.16 ). A de-bonding process may then be performed to peel or remove the carrier from the photonic package 10 after the singulation process. The carrier may be removed by any acceptable process, such as an etching process, a CMP process, a grinding process, or other acceptable removal process.

[0113] Still refer to Fig.16According to some embodiments, the photonic package 10 is shown coupled to a vertically mounted optical fiber 316. In other embodiments, other numbers of vertically mounted optical fibers 316 may be coupled to the photonic package 10. The optical fibers 316 may be mounted to the photonic package 10 (e.g., an outer surface of the substrate 202) using optical glue 318 or the like. In some embodiments, the optical fibers 316 are optically coupled to the grating coupler 107 within the photonic package 10 (via the microlens 204) to support optical communication between the photonic package 10 and an external optical device or system. Fig.16 In the illustrated embodiment, optical signals and / or optical power are transmitted between the vertically mounted optical fiber 316 and the grating coupler 107 and through the substrate 202 and any other intervening layers.

[0114] Figures 17 to 21 A photonic package 20 is shown according to some embodiments (see Fig.21 ). Photonic package 20 is similar to photonic package 10 described above, except that first dielectric material 208 further extends above top surface 202A of substrate 202. In some cases, forming first dielectric material 208 to cover top surface 202A of substrate 202 can allow first dielectric material 208 to serve as a subsequent planarization process after curing (see Fig.19 ) The photonic package 20 may be formed using materials or process steps similar to those previously described for the photonic package 10, so some details will not be repeated below.

[0115] Fig.17 Shown with Figure 8 The structure shown is similar to that shown in FIG. 2 , except that the first dielectric material 208 further extends from the concave region 205 to cover the top surface 202A of the substrate 202 . Fig.17 In the illustrated embodiment, the first dielectric material 208 is formed to include a first portion 208A deposited on the top surface 202A of the substrate 202 (and the first portion 206A of the anti-reflective coating 206), and a second portion 208B filling a portion of the concave region 205 (e.g., 90% or more of the volume of the concave region 205, but the present disclosure is not limited thereto) and deposited on the second portion 206B of the anti-reflective coating 206. In some embodiments, a method similar to that previously described for depositing the first dielectric material 208 is used. Figure 8 The first dielectric material 208 is deposited by a spin coating technique (i.e., spin coating deposition) as shown. By controlling a spin coater (not shown) to rotate at an appropriate speed, the deposited first dielectric material 208 can reach a desired thickness, wherein the first dielectric material 208 partially fills the concave region 205 and also covers the top surface 202A of the substrate 202.

[0116] Due to the fluidity of the spin coating process, the first dielectric material 208 can well fill the concave area 205, thereby reducing the formation of voids or cracks at the interface between the substrate 202 and the first dielectric material 208 during the subsequent thermal treatment process. In addition, compared with the case where the first dielectric material 208 isotropically deposited using a CVD process, the first portion 208A of the first dielectric material 208 deposited using spin coating deposition (i.e., a material flowable process) can have a reduced thickness. This helps to improve the performance of the subsequent planarization process. In some embodiments, a curing process (e.g., a thermal curing process) is then performed to cure the first dielectric material 208. As described above, the cured first dielectric material 208 can act as a stop layer for the subsequent planarization process.

[0117] exist Fig.18 According to some embodiments, the second dielectric material 210 (similar to Fig. 9 205) is conformally deposited on the first dielectric material 208, which is formed on the top surface 202A of the substrate 202 and in the concave region 205. In some embodiments, the second dielectric material 210 is formed to fill the remaining portion of the concave region 205 and cover the first dielectric material 208 (i.e., the first portion 208A) on the top surface 202A of the substrate 202. In some embodiments, a method similar to that previously described for depositing the second dielectric material 210 is used. Fig. 9 The second dielectric material 210 is deposited using the same technique as shown (ie, CVD).

[0118] Since the concave region 205 in the top surface 202A of the substrate 202 has been partially filled with the first dielectric material 208 (i.e., the second portion 208B) in the previous step, and the thickness of the first portion 208A of the first dielectric material 208 above the top surface 202A is relatively small, the surface topography (i.e., the surface height difference) of the top surface 202A is reduced, as shown in FIG. Fig.18 As shown in . Therefore, compared with the case where the first dielectric material 208 is not filled in the concave region 205, the surface morphology of the second dielectric material 210 thereon is correspondingly reduced. This helps to improve the performance of the subsequent planarization process.

[0119] exist Fig.19 According to some embodiments, a planarization process such as a CMP process, a grinding process, etc. is used (eg Fig.192 (as indicated by the solid arrow in FIG. 2 ) to planarize (or thin) the second dielectric material 210. In some embodiments, the planarization process may expose the first portion 208A of the first dielectric material 208 above the top surface 202A of the substrate 202, such that the first portion 208A of the first dielectric material 208 is substantially horizontal or coplanar with the top surface of the remaining second dielectric material 210. In this case, the first dielectric material 208 may serve as a stop layer for the planarization process. Fig.19 In the example of FIG. 1 , the concave region 205 (of the microlens 204) is filled with two dielectric materials (i.e., dielectric material 208 and dielectric material 210) after the planarization process. Although not shown, when viewed from the top, the first dielectric material 208 may laterally surround the second dielectric material 210 within the concave region 205. Fig.10 For similar reasons as described in the example Fig.19 In the example, the performance of the planarization process is also improved (eg, process time and cost are reduced).

[0120] exist Fig. 20 In some embodiments, the bonding layer 212 (similar to Fig.11 The bonding layer 212 shown in FIG. 1 is deposited on (eg, in direct contact with) the planarized second dielectric material 210 and the exposed first dielectric material 208 to form the second wafer 200. The bonding layer 212 may be formed by the same method as described above for forming the second dielectric material 210. Fig.11 The method of bonding layer 212 shown in FIG. 2 is similar. Then, a similar method is performed on the second wafer 200. Figures 12 to 16 The manufacturing process shown in the Fig.21 The photonic package 20 is shown in FIG.

[0121] Figure 22 to Figure 26 A photonic package 30 is shown according to some embodiments (see Fig.26 ) is a cross-sectional view of an intermediate stage of the formation process of the photonic package 30. The photonic package 30 is similar to the above-mentioned photonic package 10, except that the concave area 205 (of the microlens 204) is filled only by a single photosensitive dielectric material 230, wherein the photosensitive dielectric material 230 can be patterned by a lithography process to define the flattened area (i.e., the area that needs to be flattened) before the flattening process. In some embodiments, filling the concave area 205 with only a single photosensitive dielectric material 230 can simplify the gap filling process, and pre-defining the flattened area using a lithography process also helps to improve the performance of the flattening process. The photonic package 30 can be formed using materials or process steps similar to those previously described for the photonic package 10, so some details will not be repeated below.

[0122] exist Fig. 22 According to some embodiments, providing or receiving a signal similar to Figure 7 . Then, according to some embodiments, a photosensitive dielectric material 230 is deposited over the top surface 202A of the substrate 202 including the recessed microlenses 204. The photosensitive dielectric material 230 can be similar to the first dielectric material 208 described above (e.g., a silicon-oxygen-carbon based compound), except that the photosensitive dielectric material 230 further includes a photosensitive additive (to enable photopatterning). Fig. 22 In the illustrated embodiment, the photosensitive dielectric material 230 is formed to include a first portion 230A deposited on the first portion 206A of the anti-reflective coating 206 on the top surface 202A of the substrate 202, and a second portion 230B filling the entire concave region 205 and deposited on the second portion 206B of the anti-reflective coating 206. The photosensitive dielectric material 230 is formed using a method similar to that previously described for depositing the photosensitive dielectric material 230. Figure 8 The first dielectric material 208 is deposited by the technique (i.e., spin coating deposition) shown in FIG. By controlling the spin coater (not shown) to rotate at an appropriate speed, the deposited photosensitive dielectric material 230 can reach a desired thickness, wherein the photosensitive dielectric material 230 fills the entire concave region 205 and also covers the top surface 202A of the substrate 202.

[0123] Due to the fluidity of the spin coating process, the photosensitive dielectric material 230 can well fill the concave region 205, thereby reducing the formation of voids or cracks at the interface between the substrate 202 and the photosensitive dielectric material 230 during subsequent thermal processing. In addition, compared with the case where the photosensitive dielectric material 230 isotropically deposited using a CVD process, the portion of the photosensitive dielectric material 230 deposited above the top surface 202A of the substrate 202 using spin coating deposition (i.e., a material flowable process) can have a reduced thickness. Due to the reduced surface topography, this helps to improve the subsequent planarization process (see Fig.24 In some embodiments, a curing process (eg, a thermal curing process) is then performed to cure the photosensitive dielectric material 230.

[0124] Still refer to Fig. 22 According to some embodiments, after the photosensitive dielectric material 230 is deposited, it is developed by a photopatterning process 235 (illustrated as light passing through a photomask 240), and then cured (e.g., thermally cured). Fig. 22 In the illustrated embodiment, the photosensitive dielectric material 230 is a negative tone dielectric material so that all portions exposed to light will be removed during the development process, and the mask 240 may have an opaque region DR corresponding to the second portion 230B of the photosensitive dielectric material 230 above the microlens 204. In this way, based on Fig. 22 The results of the photopatterning process 235 are shown in Fig.23, wherein the photosensitive dielectric material 230 has been developed (e.g., the first portion 230A exposed to light has been removed) and cured, leaving only the second portion 230B of the photosensitive dielectric material 230 in the concave region 205. In some alternative embodiments (not shown), the photosensitive dielectric material 230 can be a positive tone dielectric material, so that all portions not exposed to light will be removed during the development process, and the opaque region DR of the mask 240 corresponds to the first portion 230A of the photosensitive dielectric material 230 above the top surface 202A. In this way, a Fig.23 The same results are shown in .

[0125] exist Fig.24 According to some embodiments, a planarization process such as a CMP process, a grinding process, etc. is used (eg Fig.24 206) to planarize (or thin) the patterned photosensitive dielectric material 230. In some embodiments, the planarization process may remove excess portions of the photosensitive dielectric material 230 above the first portion 206A of the anti-reflective coating 206, such that the first portion 206A of the anti-reflective coating 206 is substantially level or coplanar with the top surface of the remaining photosensitive dielectric material 230. In this case, the anti-reflective coating 206 may serve as a stop layer for the planarization process.

[0126] As described above, since the photosensitive dielectric material 230 deposited using the spin coating process may have a reduced surface topography and the planarization area may be predefined by the photopatterning process, the process time and cost of the planarization process are reduced. Therefore, the performance of the planarization process is improved.

[0127] exist Figure 24-1 In some embodiments shown, after the photosensitive dielectric material 230 covering the first portion 206A of the anti-reflective coating 206 is planarized (i.e., removed), a planarization process such as a CMP process, a grinding process, etc. (e.g., Figure 24-1 The planarization process may expose the top surface 202A of the substrate 202, so that the top surface of the remaining photosensitive dielectric material 230 is flush with the top surface 202A of the substrate 202. In some embodiments, the planarization process for the first portion 206A of the anti-reflective coating 206 may be omitted, as shown in FIG. Fig.24 The embodiment shown in .

[0128] exist Fig.25 In some embodiments, the bonding layer 212 (similar to Fig.11The bonding layer 212 shown in FIG. 1 is deposited on the planarized photosensitive dielectric material 230 and on the top surface 202A of the substrate 202 (and on the first portion 206A of the anti-reflective coating 206, if any), thereby forming the second wafer 200. The bonding layer 212 can be formed by the same method as described above for forming the second wafer 200. Fig.11 The method of bonding layer 212 shown in FIG. 2 is similar. Then, a similar method is performed on the second wafer 200. Figures 12 to 16 The manufacturing process shown in the Fig.26 The photonic package 30 is shown in FIG.

[0129] It should be understood that the structures, configurations, and manufacturing methods described herein are illustrative only and are not intended to and should not be interpreted as limiting the present disclosure. Once informed of the present disclosure, many alternatives and modifications will be apparent to those skilled in the art. For example, Figure 5 The structure of the first semiconductor wafer 100 shown in is only an illustrative example and is not intended to and should not be interpreted as limiting the present disclosure. In different embodiments, other suitable structures of the first semiconductor wafer 100 may be used as long as there are optical components that can be aligned and optically coupled with the microlenses 204 of the second wafer 200. These wafer structures are also within the intended scope of the present disclosure.

[0130] Embodiments of the present disclosure can achieve advantages. In some embodiments, the concave area of ​​the microlens can be filled with two dielectric material layers, and since the first dielectric material is first deposited in the concave area using a spin coating process (i.e., a material flowable process) rather than a CVD process (i.e., an isotropic deposition process), it can effectively reduce the surface morphology of the top surface of the substrate due to its fluidity. Therefore, the second dielectric material subsequently deposited (e.g., deposited by CVD) has a correspondingly reduced surface morphology, which helps to improve the performance of the subsequent planarization process (e.g., process time and cost reduction). In some embodiments, the concave area of ​​the microlens can be filled with only a single photosensitive dielectric material deposited by a spin coating process, which can also effectively reduce the surface morphology of the top surface of the substrate due to its fluidity, and the planarized area of ​​the photosensitive dielectric material can be pre-defined by a photopatterning process. Therefore, the gap filling process is simplified and the performance of the subsequent planarization process is improved.

[0131] Some embodiments of the present disclosure provide a method for forming a semiconductor package. The method includes forming a microlens recessed from a top surface of a substrate, wherein a concave region is formed between a surface of the microlens and the top surface of the substrate. The method includes using a spin coating process to deposit a first dielectric material that fills a portion of the concave region. The method includes using a chemical vapor deposition process to deposit a second dielectric material that fills the remaining portion of the concave region and covers the top surface of the substrate. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and on the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.

[0132] In some embodiments, the first dielectric material includes silicon, carbon, and oxygen. In some embodiments, the second dielectric material includes silicon and oxygen. In some embodiments, depositing the first dielectric material includes only partially filling the concave region with the first dielectric material. In some embodiments, depositing the first dielectric material includes partially filling the concave region with the first dielectric material and covering the top surface of the substrate, and depositing the second dielectric material includes filling the remaining portion of the concave region with the second dielectric material and covering the first dielectric material above the top surface of the substrate. In some embodiments, planarizing the second dielectric material includes planarizing the second dielectric material so that the first dielectric material above the top surface of the substrate is exposed, and the top surface of the first dielectric material is flush with the top surface of the second dielectric material. In some embodiments, the method further includes, before depositing the first dielectric material and the second dielectric material, conformally depositing an anti-reflective coating on the surface of the microlens, the sidewalls of the concave region, and the top surface of the substrate. In some embodiments, planarizing the second dielectric material includes planarizing the second dielectric material so that the anti-reflective coating above the top surface of the substrate is exposed. In some embodiments, the method further includes, after planarizing the second dielectric material, thinning the anti-reflective coating so that the top surface of the substrate is exposed. In some embodiments, the semiconductor wafer includes an optical component therein, wherein the optical component is aligned with the microlens after bonding the semiconductor wafer.

[0133] Other embodiments of the present disclosure provide a method for forming a semiconductor package. The method includes forming a microlens recessed from the top surface of a substrate, wherein a concave region is formed between the surface of the microlens and the top surface of the substrate. The method includes using a spin coating process to deposit a dielectric material that fills the concave region and covers the top surface of the substrate. The method includes using a lithography process to pattern the dielectric material, leaving only a portion of the dielectric material in the concave region. The method includes planarizing the patterned dielectric material. The method includes forming a bonding layer on the planarized dielectric material and on the top surface of the substrate. The method includes bonding a semiconductor wafer to a substrate via the bonding layer.

[0134] In some embodiments, the dielectric material is a photosensitive dielectric material and includes silicon, carbon, oxygen, and a photosensitive additive. In some embodiments, the method further includes, before depositing the dielectric material, conformally depositing an anti-reflective coating on the surface of the microlens, the sidewalls of the concave region, and the top surface of the substrate. In some embodiments, planarizing the dielectric material includes planarizing the dielectric material so that the anti-reflective coating on the top surface of the substrate is exposed. In some embodiments, after planarizing the dielectric material, the method further includes thinning the anti-reflective coating so that the top surface of the substrate is exposed.

[0135] Other embodiments of the present disclosure provide a semiconductor package, including a substrate, a microlens, a first dielectric material, a second dielectric material, a bonding layer, and a semiconductor wafer. The microlens is recessed from the top surface of the substrate, wherein a concave area is formed between the surface of the microlens and the top surface of the substrate. The first dielectric material is disposed on the concave area and adjacent to the surface of the microlens. The second dielectric material fills the concave area and is located above the first dielectric material, wherein the second dielectric material is different from the first dielectric material. The bonding layer is formed on the top surface of the substrate and contacts the second dielectric material. The semiconductor wafer is bonded to the bonding layer, wherein the semiconductor wafer includes an optical component.

[0136] In some embodiments, a portion of the first dielectric material extends above the top surface of the substrate and is located between the top surface of the substrate and the bonding layer, and the bonding layer is in direct contact with both the first dielectric material and the second dielectric material. In some embodiments, the first dielectric material includes silicon, carbon and oxygen, and the second dielectric material includes silicon and oxygen. In some embodiments, the semiconductor package further includes an anti-reflective coating formed on the surface of the microlens and the sidewalls of the concave region. In some embodiments, a portion of the anti-reflective coating extends above the top surface of the substrate.

[0137] The features of many embodiments are summarized above so that those with ordinary knowledge in the technical field to which the present disclosure belongs can better understand the various embodiments of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that other processes and structures can be easily designed or changed based on the embodiments of the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure. Various changes, substitutions and modifications may be made to the embodiments of the present disclosure without departing from the spirit and scope of the appended claims.

Claims

1. A method of forming a semiconductor package, comprising: forming a microlens recessed from a top surface of a substrate, wherein a concave region is formed between a surface of the microlens and the top surface of the substrate; Depositing a first dielectric material filling a portion of the concave region using a spin coating process; depositing a second dielectric material filling a remaining portion of the concave region and covering the top surface of the substrate using a chemical vapor deposition process; planarizing the second dielectric material; forming a bonding layer on the planarized second dielectric material and over the top surface of the substrate; as well as A semiconductor wafer is bonded to the substrate via the bonding layer.

2. The method of forming a semiconductor package as claimed in claim 1, wherein the first dielectric material comprises silicon, carbon and oxygen. 3 . The method for forming a semiconductor package as claimed in claim 1 , wherein the second dielectric material comprises silicon and oxygen. 4 . The method of forming a semiconductor package as claimed in claim 1 , wherein depositing the first dielectric material comprises only partially filling the concave region with the first dielectric material.

5. The method of forming a semiconductor package as claimed in claim 1, wherein depositing the first dielectric material comprises partially filling the concave area with the first dielectric material and covering the top surface of the substrate, and wherein depositing the second dielectric material comprises filling the remaining portion of the concave area with the second dielectric material and covering the first dielectric material above the top surface of the substrate.

6. The method for forming a semiconductor package as claimed in claim 1, further comprising: Prior to depositing the first dielectric material and the second dielectric material, an anti-reflection coating is conformally deposited on the surface of the microlens, the sidewalls of the concave region, and the top surface of the substrate.

7. The method for forming a semiconductor package as claimed in claim 6, further comprising: After planarizing the second dielectric material, the anti-reflective coating is thinned such that the top surface of the substrate is exposed.

8. A method of forming a semiconductor package, comprising: forming a microlens recessed from a top surface of a substrate, wherein a concave region is formed between a surface of the microlens and the top surface of the substrate; depositing a dielectric material filling the concave region and covering the top surface of the substrate using a spin coating process; patterning the dielectric material using a lithography process to leave only a portion of the dielectric material in the concave region; planarizing the patterned dielectric material; forming a bonding layer on the planarized dielectric material and over the top surface of the substrate; as well as A semiconductor wafer is bonded to the substrate via the bonding layer.

9. The method of forming a semiconductor package as claimed in claim 8, wherein the dielectric material is a photosensitive dielectric material and comprises silicon, carbon, oxygen and a photosensitive additive.

10. A semiconductor package, comprising: a substrate; a micro lens recessed from a top surface of the substrate, wherein a concave region is formed between a surface of the micro lens and the top surface of the substrate; a first dielectric material disposed on the concave region and adjacent to the surface of the microlens; a second dielectric material filling the concave region and located above the first dielectric material, wherein the second dielectric material is different from the first dielectric material; a bonding layer formed on the top surface of the substrate and in contact with the second dielectric material; and A semiconductor wafer is bonded to the bonding layer, wherein the semiconductor wafer includes an optical component.

Images