Semiconductor package including stiffener structure

Abstract

A semiconductor package is provided. The semiconductor package includes a package substrate, a chip structure on the package substrate, a peripheral structure disposed on the package substrate and disposed around the chip structure, and a stiffener structure disposed at an edge of the package substrate and surrounding the peripheral structure and the chip structure. The stiffener structure includes a first stiffener and a second stiffener sequentially stacked, the second stiffener including a material different from the material of the first stiffener, and the second stiffener having a second width wider than the first width of the first stiffener and vertically overlapping the peripheral structure.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2023-0075005 filed in the Korean Intellectual Property Office on June 12, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a reinforcement structure. Background Art

[0003] Integrated circuit chips are usually provided with semiconductor packages to be appropriately applied to circuit boards of electronic products or otherwise combined in electronic systems. In general semiconductor packages, integrated circuit chips (or semiconductor chips) can be mounted on printed circuit boards (PCBs) and can be electrically connected to the PCBs through bonding wires or bumps. With the development of the electronics industry, various studies have been conducted to improve the reliability and durability of semiconductor packages. Summary of the invention

[0004] An object of the present disclosure is to provide a semiconductor package having improved reliability.

[0005] Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood from the following description by those skilled in the art.

[0006] According to some embodiments of the present disclosure, a semiconductor package includes a packaging substrate, a chip structure on the packaging substrate, a peripheral structure arranged on the packaging substrate and around the chip structure, and a reinforcement structure arranged at an edge of the packaging substrate and surrounding the peripheral structure and the chip structure, wherein the reinforcement structure includes a first reinforcement and a second reinforcement stacked in sequence, the second reinforcement includes a material different from that of the first reinforcement, and the second reinforcement has a second width wider than the first width of the first reinforcement and is vertically stacked with the peripheral structure.

[0007] According to some embodiments of the present disclosure, a semiconductor package includes a packaging substrate, a built-in substrate on the packaging substrate, a dedicated semiconductor chip arranged on the center of the built-in substrate, a first memory chip and a second memory chip arranged on one side of the dedicated semiconductor chip, a third memory chip and a fourth memory chip arranged on the other side of the dedicated semiconductor chip, a molding layer covering the dedicated semiconductor chip, the first memory chip to the fourth memory chip and the built-in substrate, and a reinforcement structure arranged at the edge of the packaging substrate and surrounding the built-in substrate, wherein the reinforcement structure includes a first reinforcement and a second reinforcement stacked in sequence, the second reinforcement includes a material different from that of the first reinforcement, the second reinforcement has a second width wider than the first width of the first reinforcement, and the thermal expansion coefficient of the first reinforcement is smaller than the thermal expansion coefficient of the second reinforcement.

[0008] According to some embodiments of the present disclosure, a semiconductor package includes a packaging substrate, a chip structure on the packaging substrate, and a reinforcement structure arranged at an edge of the packaging substrate and surrounding the chip structure, wherein the reinforcement structure includes a first reinforcement and a second reinforcement formed of different materials, and when viewed in a plan view, the first reinforcement and the second reinforcement surround the chip structure, and the second reinforcement is adjacent to an inner wall of the first reinforcement. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which illustrate non-limiting example embodiments as described herein.

[0010] Figure 1 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

[0011] Figure 2 is taken along line AA' according to an embodiment of the present disclosure Figure 1 sectional view of .

[0012] Figure 3 According to the embodiment of the present disclosure Figure 2 An enlarged view of portion “P1”.

[0013] Figure 4 is taken along line AA' according to an embodiment of the present disclosure Figure 1 sectional view of .

[0014] Figure 5 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0015] Figure 6 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0016] Figure 7is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0017] Figure 8 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0018] Fig. 9 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

[0019] Fig.10 is taken along line AA' according to an embodiment of the present disclosure Fig. 9 sectional view of .

[0020] Fig.11 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0021] Fig.12 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

[0022] Fig.13 is taken along line AA' according to an embodiment of the present disclosure Fig.12 sectional view of .

[0023] Fig.14 is taken along line AA' according to an embodiment of the present disclosure Fig.12 sectional view of .

[0024] Fig.15 is taken along line AA' according to an embodiment of the present disclosure Fig.12 sectional view of .

[0025] Fig.16A is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0026] Fig. 16B is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0027] Fig.17 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0028] Fig.18 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0029] Fig.19 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0030] Fig. 20 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0031] Fig.21is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0032] Fig. 22 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0033] Fig.23 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

[0034] Fig.24 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

[0035] Fig.25 is a plan view of a semiconductor package according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Hereinafter, in order to explain the present disclosure in detail, embodiments according to the present disclosure will be described with reference to the accompanying drawings.

[0037] Figure 1 is a plan view of a semiconductor package according to an embodiment of the present disclosure. Figure 2 is taken along line AA' according to an embodiment of the present disclosure Figure 1 sectional view of .

[0038] Reference Figure 1 and Figure 2 , the semiconductor package 1000 according to the embodiment may include a first substrate PB. The first substrate PB may also be referred to as a "package substrate". The first substrate PB may be, for example, a double-sided or multi-layer printed circuit board. The first substrate PB may be referred to as a package substrate. The first substrate PB may include a first main body layer, a first substrate upper conductive pattern UP1 disposed on its upper surface, and a first substrate lower conductive pattern BP1 disposed on its lower surface. A thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide), or a resin impregnated with a reinforcing material (such as glass fiber and / or an inorganic filler (e.g., a prepreg)) and / or a photocurable resin, etc. may be used as the first main body layer, but is not specifically limited thereto. The first substrate upper conductive pattern UP1 and the first substrate lower conductive pattern BP1 may include at least one of copper, aluminum, and gold. A via may be provided in the first main body layer, and the first substrate upper conductive pattern UP1 may be electrically connected to the first substrate lower conductive pattern BP1. The upper and lower surfaces of the first main body layer may be covered by an insulating layer. The insulating layer may be a photo solder resist (PSR).

[0039] The external connection terminals OC may be attached to the first under substrate conductive pattern BP1 under the first substrate PB. The external connection terminals OC may be solder balls. The external connection terminals OC may include or may be formed of at least one of tin and lead.

[0040] The chip structure CS and the first peripheral structure PD are arranged on the first substrate PB. The chip structure CS may be at least one selected from a system large-scale integration (LSI) chip, a logic circuit chip, an image sensor chip (such as a CMOS imaging sensor (CIS)), a memory element chip (such as a flash memory chip, a DRAM chip, an SRAM chip, an EEPROM chip, a PRAM chip, an MRAM chip, a ReRAM chip, a high bandwidth memory (HBM) chip, a hybrid memory cube (HMC) chip, and a micro-electromechanical system (MEMS) element chip) and an application-specific integrated circuit (ASIC) chip (such as a dedicated semiconductor chip). In this example, one chip structure CS is provided, but a plurality or more chip structures CS may be provided.

[0041] In detail, in the present embodiment, the chip structure CS includes a second substrate IB. That is, the second substrate IB can be mounted on the first substrate PB. The second substrate IB can also be referred to as a "built-in substrate". The second substrate IB may include a second main body layer, a second substrate upper conductive pattern UP2 arranged on its upper surface, and a second substrate lower conductive pattern BP2 arranged on its lower surface. The interlayer insulating layer and the wiring may be arranged on the lower surface and / or upper surface of the second main body layer. The second main layer may include, for example, silicon or may be formed of, for example, silicon. Vias may be arranged in the second main body layer. The second substrate upper conductive pattern UP2 and the second substrate lower conductive pattern BP2 may include at least one of copper, aluminum and gold, or may be formed of at least one of copper, aluminum and gold. The second substrate upper conductive pattern UP2 may be electrically connected to the second substrate lower conductive pattern BP2.

[0042] The first substrate PB and the second substrate IB may be electrically connected to each other through the first internal connection terminal IC1. The first internal connection terminal IC1 may electrically connect the first substrate upper conductive pattern UP1 and the second substrate lower conductive pattern BP2. The first internal connection terminal IC1 may be at least one of a solder ball, a conductive bump, and a conductive column. The first internal connection terminal IC1 may include at least one of copper, tin, and lead or may be formed of at least one of copper, tin, and lead. The first underfill layer UF1 may be placed between the first substrate PB and the second substrate IB.

[0043] The chip structure CS may include a central semiconductor chip AP and first to fourth peripheral semiconductor chips HM1 to HM4 mounted on a second substrate IB. The central semiconductor chip AP may be, for example, a logic chip, a processor chip, or an application-specific integrated circuit (ASIC) chip. The first peripheral semiconductor chip HM1 and the second peripheral semiconductor chip HM2 may be adjacent to one side of the central semiconductor chip AP and may be spaced apart from each other in the second direction Y. The third peripheral semiconductor chip HM3 and the fourth peripheral semiconductor chip HM4 are adjacent to the other side of the central semiconductor chip AP and may be spaced apart from each other in the second direction Y. Each of the first to fourth peripheral semiconductor chips HM1 to HM4 may be a memory chip or a high bandwidth memory (HBM) chip. Wiring may be provided on the second substrate IB to electrically connect the central semiconductor chip AP and the first to fourth peripheral semiconductor chips HM1 to HM4. As a result, the central semiconductor chip AP and the first to fourth peripheral semiconductor chips HM1 to HM4 can be connected through the second substrate IB without passing through the first substrate PB, and the electrical connection length between the central semiconductor chip AP and the first to fourth peripheral semiconductor chips HM1 to HM4 can be short, so the signal transmission speed can be improved, thereby improving the operating speed of the semiconductor package 1000.

[0044] The first chip conductive pad (pad, or referred to as "pad or pad") CP1 can be disposed on the lower surface of the central semiconductor chip AP. The first chip conductive pad CP1 may include a metal such as aluminum or copper or may be formed of a metal such as aluminum or copper. The second chip conductive pad CP2 may be disposed on the lower surfaces of the first peripheral semiconductor chip HM1 to the fourth peripheral semiconductor chip HM4. The first chip conductive pad CP1 and the second chip conductive pad CP2 may be electrically connected to a portion of the conductive pattern UP2 on the second substrate through the second internal connection terminal IC2. The second internal connection terminal IC2 may be at least one of a solder ball, a conductive bump, and a conductive column. The second internal connection terminal IC2 may include at least one of copper, tin, and lead or may be formed of at least one of copper, tin, and lead.

[0045] The chip structure CS may further include a second bottom filling layer UF2 and a molding layer MD. The second bottom filling layer UF2 may be placed between the central semiconductor chip AP and the second substrate IB and between the first peripheral semiconductor chip HM1 to the fourth peripheral semiconductor chip HM4 and the second substrate IB. The first bottom filling layer UF1 and the second bottom filling layer UF2 may include a thermosetting resin or a photocurable resin or may be formed by a thermosetting resin or a photocurable resin. In addition, the first bottom filling layer UF1 and the second bottom filling layer UF2 may also include an organic filler or an inorganic filler. The molding layer MD may cover the side walls of the central semiconductor chip AP and the first peripheral semiconductor chip HM1 to the fourth peripheral semiconductor chip HM4 and the upper surface of the second substrate IB. The upper surface of the molding layer MD may be coplanar with the upper surfaces of the central semiconductor chip AP and the first peripheral semiconductor chip HM1 to the fourth peripheral semiconductor chip HM4. The molding layer MD may include, for example, an insulating resin (such as an epoxy molding compound (EMC)) or may be formed by, for example, an insulating resin (such as an epoxy molding compound (EMC)). The mold layer MD may further include a filler, and the filler may be dispersed in the insulating resin. The filler may include, for example, silicon oxide (SiO 2 ) or can be made of, for example, silicon oxide (SiO 2 ) is formed. The side surface of the molded layer MD may be coplanar with the side surface of the second substrate 1B. Terms such as "same", "equal", "planar" or "coplanar" as used herein encompass identity or near identity including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0046] The first peripheral structures PD may be spaced apart from each other. The first peripheral structures PD may be passive elements such as capacitors or resistors. The first peripheral structures PD are provided in plurality and may be arranged in a row to surround the chip structure CS. The level of the upper surface of the first peripheral structure PD is lower than the level of the upper surface of the chip structure CS.

[0047] Figure 3 According to the embodiment of the present disclosure Figure 2 An enlarged view of portion “P1”.

[0048] Reference Figures 1 to 3, the reinforcement structure STS is arranged on the edge of the first substrate PB. The reinforcement structure STS may surround the chip structure CS and the first peripheral structure PD. The reinforcement structure STS may have a closed curve shape having a cavity CV, which is an empty space in which the chip structure CS and the first peripheral structure PD are inserted when viewed in a plan view. The reinforcement structure STS may be attached to the upper surface of the first substrate PB by a first adhesive layer AD1. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2 stacked in sequence. The first reinforcement ST1 and the second reinforcement ST2 may surround the chip structure CS and the first peripheral structure PD, respectively. Ordinals such as "first", "second", "third", etc. may simply be used as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, terms cited with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0049] The first reinforcement member ST1 and the second reinforcement member ST2 include different materials. At least one of the first reinforcement member ST1 and the second reinforcement member ST2 may include a metal (such as Cu, SUS, Ti, or Al), a ceramic (such as silicon dioxide, titanium dioxide, or aluminum oxide), SiN, or a polymer layer, or may be formed of a metal (such as Cu, SUS, Ti, or Al), a ceramic (such as silicon dioxide, titanium dioxide, or aluminum oxide), SiN, or a polymer layer. The first reinforcement member ST1 and the second reinforcement member ST2 have different thermal expansion coefficients. For example, the first thermal expansion coefficient of the first reinforcement member ST1 is less than the second thermal expansion coefficient of the second reinforcement member ST2. The first thermal expansion coefficient of the first reinforcement member ST1 is similar to / same as the thermal expansion coefficient of the first substrate PB. The first thermal expansion coefficient of the first reinforcement member ST1 may be about 9 ppm / °C to about 13 ppm / °C. The second thermal expansion coefficient of the second reinforcement member ST2 may be about 14 ppm / °C to about 25 ppm / °C. The first reinforcement member ST1 may include or may be formed of, for example, at least one of stainless steel (SUS), platinum, MgO, iron, cobalt, and nickel, and the second reinforcement member ST2 may be formed of, for example, at least one of gold, copper, silicon, and aluminum. As described above, the reinforcement member structure STS of the present disclosure may include a plurality of reinforcement members ST1 and ST2 having different thermal expansion coefficients, and thus the warpage of the semiconductor package 1000 may be more effectively suppressed and controlled.

[0050] The reinforcement structure STS further includes a second adhesive layer AD2 disposed between the first reinforcement ST1 and the second reinforcement ST2. That is, the second reinforcement ST2 may be attached to the first reinforcement ST1 through the second adhesive layer AD2. The second adhesive layer AD2 may be used to relieve physical stress.

[0051] An outer wall ST1_S1 of the first reinforcement ST1 may be aligned with an outer wall ST2_S1 of the second reinforcement ST2. An end surface of the first reinforcement ST1 may have a first width WT1 and a first thickness TH1. An end surface of the second reinforcement ST2 may have a second width WT2 and a second thickness TH2. The first thickness TH1 is different from the second thickness TH2. For example, the first thickness TH1 is greater than the height of the upper surface of the first peripheral structure PD. The second width WT2 is different from the first width WT1. In this example, the second width WT2 is greater than the first width WT1. A portion of the second reinforcement ST2 may protrude from one side of the first reinforcement ST1 and may be vertically overlapped with the first peripheral structure PD. The width WT3 of the portion of the second reinforcement ST2 protruding from one side of the first reinforcement ST1 may be, for example, 1 mm to 19 mm.

[0052] The structure of the stiffener structure STS of the present disclosure may maximize the bonding area with the first substrate PB and may effectively suppress warping when the chip structure CS and the first peripheral structure PD are mounted.

[0053] The upper surface of the reinforcement structure STS has a first height HE1 from the upper surface of the first substrate PB. The upper surface of the chip structure CS has a second height HE2 from the upper surface of the first substrate PB. The first height HE1 may be higher (i.e., greater) than the second height HE2. For example, the first height HE1 may be 1.1 to 3 times the second height HE2.

[0054] In another example, having Figures 1 to 3 The semiconductor package 1000 having a structure of may not include the first peripheral structure PD. In this case, since there is no first peripheral structure PD, a portion of the second reinforcement member ST2 may not overlap with the first peripheral structure PD. Figures 1 to 3 In the semiconductor package 1000 having the structure of FIG. 1 , even when the first peripheral structure PD exists, a portion of the second reinforcement member ST2 may not overlap the first peripheral structure PD.

[0055] Figure 4 is taken along line AA' according to an embodiment of the present disclosure Figure 1 sectional view of .

[0056] Reference Figure 4In the semiconductor package 1001 according to this example, in the reinforcement structure STS, the second adhesive layer AD2 is not disposed between the first reinforcement ST1 and the second reinforcement ST2. The first reinforcement ST1 and the second reinforcement ST2 may contact each other. The first reinforcement ST1 and the second reinforcement ST2 may be integrally connected. Other structures may be the same as those described in reference Figures 1 to 3 The structures described are the same / similar. It will be understood that when an element is referred to as being "connected" or "coupled" to another element or being "on" another element, it can be directly connected or coupled to the other element or directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as being "in contact with" or "in contact with" another element, there are no intervening elements at the point of contact.

[0057] Figure 5 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0058] Reference Figure 5 In the semiconductor package 1002 according to the present example, the first peripheral structure PD may be arranged in a plurality of rows between the reinforcement structure STS and the chip structure CS. The first peripheral structure PD may be, for example, a passive element such as a capacitor or a resistor. The first peripheral structure PD may be arranged to surround the chip structure CS. The reinforcement structure STS may include a first reinforcement ST1 and a second reinforcement ST2 stacked sequentially. The second reinforcement ST2 may overlap with the plurality of first peripheral structures PD. Other structures may be similar to those of reference 1. Figures 1 to 3 The structures described are the same / similar.

[0059] Figure 6 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0060] Reference Figure 6 In the semiconductor package 1003 according to the present example, the reinforcement structure STS includes a first reinforcement ST1, a second reinforcement ST2, and a third reinforcement ST3 stacked in sequence. The first reinforcement ST1, the second reinforcement ST2, and the third reinforcement ST3 may surround the chip structure CS and the first peripheral structure PD. An outer wall of the first reinforcement ST1, an outer wall of the second reinforcement ST2, and an outer wall of the third reinforcement ST3 may all be aligned with each other. A portion of the second reinforcement ST2 may protrude from one side of the first reinforcement ST1. A portion of the third reinforcement ST3 may protrude from one side of the second reinforcement ST2. The third reinforcement ST3 may overlap with the first peripheral structure PD. The third reinforcement ST3 may overlap vertically with the chip structure CS.

[0061] The first reinforcement member ST1, the second reinforcement member ST2, and the third reinforcement member ST3 include different materials. At least one of the first reinforcement member ST1, the second reinforcement member ST2, and the third reinforcement member ST3 may include a metal (such as Cu, SUS, Ti, or Al), a ceramic (such as silicon dioxide, titanium dioxide, or aluminum oxide), SiN, or a polymer layer, or may be formed of a metal (such as Cu, SUS, Ti, or Al), a ceramic (such as silicon dioxide, titanium dioxide, or aluminum oxide), SiN, or a polymer layer. The first reinforcement member ST1, the second reinforcement member ST2, and the third reinforcement member ST3 have different thermal expansion coefficients. For example, the first thermal expansion coefficient of the first reinforcement member ST1 is less than the second thermal expansion coefficient of the second reinforcement member ST2. The second thermal expansion coefficient of the second reinforcement member ST2 is less than the third thermal expansion coefficient of the third reinforcement member ST3. The first thermal expansion coefficient of the first reinforcement member ST1 is similar to / same as the thermal expansion coefficient of the first substrate PB. The first thermal expansion coefficient of the first reinforcement member ST1 may be about 9 ppm / °C to about 13 ppm / °C. The second thermal expansion coefficient of the second reinforcement member ST2 may be about 14 ppm / °C to about 25 ppm / °C. The third thermal expansion coefficient of the third reinforcement ST3 may be about 25.1 ppm / °C to 30 ppm / °C.

[0062] The first reinforcement member ST1 may include, for example, at least one of stainless steel (SUS), platinum, MgO, iron, cobalt, and nickel, or may be formed of, for example, at least one of stainless steel (SUS), platinum, MgO, iron, cobalt, and nickel, and the second reinforcement member ST2 may include, for example, at least one of gold, copper, silicon, and aluminum, or may be formed of, for example, at least one of gold, copper, silicon, and aluminum. The third reinforcement member ST3 may include, for example, at least one of magnesium, zinc, tin, cadmium, and lead, or may be formed of, for example, at least one of magnesium, zinc, tin, cadmium, and lead. As described above, the reinforcement member structure STS of the present disclosure includes a plurality of reinforcement members ST1, ST2, and ST3 having different thermal expansion coefficients to more effectively suppress and control the warpage of the semiconductor package 1003.

[0063] The reinforcement structure STS further includes a second adhesive layer AD2 disposed between the first reinforcement ST1 and the second reinforcement ST2. The reinforcement structure STS further includes a third adhesive layer AD3 disposed between the second reinforcement ST2 and the third reinforcement ST3. The second adhesive layer AD2 and the third adhesive layer AD3 can be used to relieve physical stress. Other structures can be similar to those of reference Figures 1 to 3 The structures described are the same / similar.

[0064] When the chip structure CS and the first peripheral structure PD are mounted, the structure of the stiffener structure STS of the present disclosure may maximize the bonding area with the first substrate PB and may effectively suppress warping.

[0065] Figure 7is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0066] Reference Figure 7 In the semiconductor package 1004 according to the present example, the second peripheral structure DM may be disposed between the chip structure CS and the reinforcement structure STS. The second peripheral structure DM may be a dam that prevents the first bottom filling layer UF1 from flowing to an undesired area. When viewed in a plan view, the second peripheral structure DM may have a closed curve shape having a cavity that is an empty space, or the second peripheral structure DM may have a bar shape that is extended in one direction. The second peripheral structure DM may surround the chip structure CS. The second reinforcement ST2 of the reinforcement structure STS may be vertically overlapped with the second peripheral structure DM. Other structures may be similar to those of reference 1. Figures 1 to 3 The structures described are the same / similar.

[0067] Figure 8 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0068] Reference Figure 8 , the semiconductor package 1005 according to this example may not include (or exclude) Figures 1 to 7 The first peripheral structure PD or the second peripheral structure DM. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2 stacked in sequence. The outer wall of the first reinforcement ST1 may not be aligned with the outer wall of the second reinforcement ST2, and may be offset from each other. In the cross-section of the first reinforcement ST1 and the second reinforcement ST2, the center ST1_C of the first reinforcement ST1 may be aligned with the center ST2_C of the second reinforcement ST2. Other structures may be similar to those of reference Figures 1 to 3 The structures described are the same / similar.

[0069] Fig. 9 is a plan view of a semiconductor package according to an embodiment of the present disclosure. Fig.10 is taken along line AA' according to an embodiment of the present disclosure Fig. 9 sectional view of .

[0070] Reference Fig. 9 and Fig.10 , the semiconductor package 1006 according to this example may not include (or exclude) Figures 1 to 7The first peripheral structure PD or the second peripheral structure DM of the present invention. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2 stacked in sequence. An outer wall ST1_S1 of the first reinforcement ST1 may be aligned with an outer wall ST2_S1 of the second reinforcement ST2. The first reinforcement ST1 may have a first width WT1. The second reinforcement ST2 may have a second width WT2 less than the first width WT1. A portion of the upper surface of the first reinforcement ST1 may be exposed without being covered by the second reinforcement ST2. Other structures may be the same as those of reference Figures 1 to 3 The structures described are the same / similar.

[0071] Fig.11 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0072] Reference Fig.11 In the semiconductor package 1007 according to the present example, the reinforcement structure STS includes a first reinforcement member ST1 and a second reinforcement member ST2 stacked in sequence. The outer wall of the first reinforcement member ST1 and the outer wall of the second reinforcement member ST2 may not be aligned and may be offset from each other. In the cross-section of the first reinforcement member ST1 and the second reinforcement member ST2, the center ST1_C of the first reinforcement member ST1 may be aligned with the center ST2_C of the second reinforcement member ST2. Other structures may be similar to those of reference 1. Fig.10 The structures described are the same / similar.

[0073] Fig.12 is a plan view of a semiconductor package according to an embodiment of the present disclosure. Fig.13 is taken along line AA' according to an embodiment of the present disclosure Fig.12 sectional view of .

[0074] Reference Fig.12 and Fig.13 According to this example, the semiconductor package 1008 may not include (or exclude) Figures 1 to 7 The first peripheral structure PD or the second peripheral structure DM. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2, and when viewed in a plan view, the first reinforcement ST1 and the second reinforcement ST2 each have a closed curve shape, and the closed curve shape has an empty space inside. The first reinforcement ST1 and the second reinforcement ST2 surround the chip structure CS respectively. The first reinforcement ST1 has an outer wall ST1_S1 and an inner wall ST1_S2. The second reinforcement ST2 can be attached to the inner wall ST1_S2 of the first reinforcement ST1 through a second adhesive layer AD2. That is, the second adhesive layer AD2 is placed between the first reinforcement ST1 and the second reinforcement ST2. The first reinforcement ST1 surrounds the second reinforcement ST2.

[0075] The first reinforcement member ST1 is attached to the upper surface of the first substrate PB through the first adhesive layer AD1. The second reinforcement member ST2 is attached to the upper surface of the first substrate PB through the third adhesive layer AD3. Each of the first reinforcement member ST1 and the second reinforcement member ST2 may have a first thickness TH1. The upper surfaces of the first reinforcement member ST1 and the second reinforcement member ST2 may be coplanar with each other. The first reinforcement member ST1 may have a first width WT1. The second reinforcement member ST2 may have a second width WT2 different from the first width WT1. For example, the second width WT2 may be greater than the first width WT1. Other structures may be similar to those of reference 1. Figures 1 to 3 The structures described are the same / similar.

[0076] Fig.14 is taken along line AA' according to an embodiment of the present disclosure Fig.12 sectional view of .

[0077] Reference Fig.14 According to this example, the semiconductor package 1009 may not include (or exclude) Figures 1 to 7 The first peripheral structure PD or the second peripheral structure DM. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2, and when viewed in a plan view, the first reinforcement ST1 and the second reinforcement ST2 each have a closed curve shape having an empty space inside. The first reinforcement ST1 and the second reinforcement ST2 respectively surround the chip structure CS. The first reinforcement ST1 surrounds the second reinforcement ST2. The first reinforcement ST1 may have a first thickness TH1. The second reinforcement ST2 may have a second thickness TH2 that is less than the first thickness TH1. The upper side surface of the first reinforcement ST1 may be exposed without being covered by the second reinforcement ST2. Other structures may be the same as those of reference Fig.12 and Fig.13 The structures described are the same / similar.

[0078] Fig.15 is taken along line AA' according to an embodiment of the present disclosure Fig.12 sectional view of .

[0079] Reference Fig.15 , the semiconductor package 1010 according to this example may not include (or exclude) Figures 1 to 7The first peripheral structure PD or the second peripheral structure DM. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2, and when viewed in a plan view, the first reinforcement ST1 and the second reinforcement ST2 each have a closed curve shape having an empty space inside. The first reinforcement ST1 and the second reinforcement ST2 respectively surround the chip structure CS. The first reinforcement ST1 surrounds the second reinforcement ST2. The first reinforcement ST1 may have a first thickness TH1. The second reinforcement ST2 may have a second thickness TH2 greater than the first thickness TH1. The upper portion of the outer wall ST2_S1 of the second reinforcement ST2 may be exposed without being covered by the first reinforcement ST1. Other structures may be the same as those described with reference to Fig.12 and Fig.13 The structures described are the same / similar.

[0080] Fig.16A is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0081] Reference Fig.16A According to this example, the semiconductor package 1011a may not include (or exclude) Figures 1 to 7 The first peripheral structure PD or the second peripheral structure DM. The reinforcement structure STS includes first to third reinforcements ST1, ST2 and ST3. The structures of the first reinforcement ST1 and the second reinforcement ST2 are Fig.15 The structures of the first reinforcement member ST1 and the second reinforcement member ST2 disclosed in the embodiment are the same. The third reinforcement member ST3 may be disposed on the first reinforcement member ST1 and may surround the second reinforcement member ST2. The third reinforcement member ST3 may be attached to the upper portion of the outer wall ST2_S1 of the second reinforcement member ST2 by the second adhesive layer AD2. The fourth adhesive layer AD4 may be disposed between the third reinforcement member ST3 and the first reinforcement member ST1. The upper surfaces of the third reinforcement member ST3 and the second reinforcement member ST2 may be coplanar with each other. Other structures may be the same as those of the reference Fig.12 and Fig.13 The structures described are the same / similar.

[0082] Fig. 16B is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0083] Reference Fig. 16B , the semiconductor package 1011b according to this example may not include (exclude) Figures 1 to 7The first peripheral structure PD or the second peripheral structure DM of the present invention. The reinforcement structure STS includes first to third reinforcement members ST1, ST2 and ST3. When viewed in a plan view, each of the first to third reinforcement members ST1, ST2 and ST3 may have a closed curve shape having a cavity that is an empty space inside. The structures of the first reinforcement member ST1 and the second reinforcement member ST2 are similar to Fig.10 The structures of the first reinforcement member ST1 and the second reinforcement member ST2 disclosed in the invention are the same. The second reinforcement member ST2 and the third reinforcement member ST3 are disposed on the first reinforcement member ST1. The second reinforcement member ST2 and the third reinforcement member ST3 are attached to the upper surface of the first reinforcement member ST1 through the second adhesive layer AD2. The third adhesive layer AD3 is disposed between the second reinforcement member ST2 and the third reinforcement member ST3. The upper surfaces of the second reinforcement member ST2 and the third reinforcement member ST3 may be coplanar with each other. The width of the first reinforcement member ST1 may be substantially equal to the sum of the widths of the second reinforcement member ST2 and the third reinforcement member ST3. Other structures may be the same as those of the reference Fig.10 The structures described are the same / similar.

[0084] Fig.17 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0085] Reference Fig.17 , the semiconductor package 1012 according to this example may not include (or exclude) Figures 1 to 7 The first peripheral structure PD or the second peripheral structure DM. The reinforcement structure STS includes first to third reinforcements ST1, ST2 and ST3. The second reinforcement ST2 is attached to the inner wall of the first reinforcement ST1 by a second adhesive layer AD2. The first reinforcement ST1 and the second reinforcement ST2 may have the same thickness, and their upper surfaces may be coplanar with each other. The third reinforcement ST3 may be disposed on the first reinforcement ST1 and the second reinforcement ST2. The third reinforcement ST3 may be attached to the first reinforcement ST1 and the second reinforcement ST2 by a fourth adhesive layer AD4. The width of the third reinforcement ST3 may be greater than the sum of the widths of the first reinforcement ST1 and the second reinforcement ST2. The side walls of the third reinforcement ST3 are not aligned with the side walls of the first reinforcement ST1 and the second reinforcement ST2. The center of the lower structure including the first reinforcement ST1 and the second reinforcement ST2 may be aligned with the center of the third reinforcement ST3. Other structures may be the same as those of reference Figures 1 to 3 The structures described are the same / similar.

[0086] Fig.18 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0087] Reference Fig.18, the semiconductor package 1013 according to this example includes a first peripheral structure PD disposed between a reinforcement structure STS and a chip structure CS. The reinforcement structure STS includes first to third reinforcements ST1, ST2, and ST3. The second reinforcement ST2 is attached to the inner wall of the first reinforcement ST1 by a second adhesive layer AD2. The first reinforcement ST1 and the second reinforcement ST2 may have the same thickness, and their upper surfaces may be coplanar with each other. The third reinforcement ST3 may be disposed on the first reinforcement ST1 and the second reinforcement ST2. The outer wall ST3_S1 of the third reinforcement ST3 may be aligned with the outer wall ST1_S1 of the first reinforcement ST1. The width of the third reinforcement ST3 may be greater than the sum of the widths of the first reinforcement ST1 and the second reinforcement ST2. A portion of the third reinforcement ST3 vertically overlaps the first peripheral structure PD. Other structures may be the same as those described with reference to FIG. Figures 1 to 3 and Fig.17 The structures described are the same / similar.

[0088] Fig.19 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0089] Reference Fig.19, the semiconductor package 1014 according to this example includes a first peripheral structure PD disposed between a reinforcement structure STS and a chip structure CS. The reinforcement structure STS includes a first reinforcement ST1, a second reinforcement ST2, and a third reinforcement ST3 stacked in sequence. The first reinforcement ST1 is attached to the upper surface of the first substrate PB through a first adhesive layer AD1. The second reinforcement ST2 is attached to the first reinforcement ST1 through a second adhesive layer AD2. The third reinforcement ST3 is attached to the second reinforcement ST2 through a third adhesive layer AD3. The first reinforcement ST1 and the second reinforcement ST2 may surround the chip structure CS and the first peripheral structure PD, respectively. The third reinforcement ST3 may completely cover the chip structure CS. The first reinforcement ST1 and the second reinforcement ST2 have the same width, and their side walls may be aligned with each other. The third reinforcement ST3 may also be referred to as a "heat sink", "heat sink", or "heat dissipation member". The thermal conductivity of the third reinforcement ST3 may be greater than the thermal conductivity of the first reinforcement ST1 and the second reinforcement ST2. The thermal expansion coefficient of the third reinforcement ST3 may be greater than the thermal expansion coefficient of the first reinforcement ST1 and the second reinforcement ST2. The thermal boundary material layer TI may be disposed between the third reinforcement member ST3 and the chip structure CS. The thermal boundary material layer TI may include a thermally curable resin layer. The thermal boundary material layer TI may also include filler particles dispersed in the thermally curable resin layer. The filler particles may include or may be formed of at least one of silicon dioxide, aluminum oxide, zinc oxide, and boron nitrogen. In the present disclosure, at least one of the first to third adhesive layers AD1 to AD3 may include the same material as the thermal boundary material layer TI. Other structures may be similar to Figure 6 The structures are the same / similar.

[0090] Fig. 20 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0091] Reference Fig. 20 , according to the present example, the semiconductor package 1015 includes a first peripheral structure PD disposed between a reinforcement structure STS and a chip structure CS. The reinforcement structure STS includes a first reinforcement ST1, a second reinforcement ST2, and a third reinforcement ST3 stacked in sequence. The first reinforcement ST1 and the second reinforcement ST2 may surround the chip structure CS and the first peripheral structure PD, respectively. The third reinforcement ST3 may completely cover the chip structure CS. The outer wall of the first reinforcement ST1 and the outer wall of the second reinforcement ST2 may be aligned with each other. The width of the second reinforcement ST2 may be greater than the width of the first reinforcement ST1. A portion of the second reinforcement ST2 may protrude from one side of the first reinforcement ST1 and vertically overlap with the first peripheral structure PD. Other structures may be connected to the chip structure CS. Fig.19 The structures are the same / similar.

[0092] Fig.21 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0093] Reference Fig.21 , the semiconductor package 1016 according to the present example includes a first peripheral structure PD disposed between a reinforcement structure STS and a chip structure CS. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2 stacked in sequence. The first reinforcement ST1 may surround the chip structure CS and the first peripheral structure PD. The second reinforcement ST2 may completely cover the chip structure CS. The second reinforcement ST2 may also be referred to as a "heat sink", "heat sink" or "heat dissipation member". The thermal conductivity of the second reinforcement ST2 may be greater than the thermal conductivity of the first reinforcement ST1. The thermal expansion coefficient of the second reinforcement ST2 may be greater than the thermal expansion coefficient of the first reinforcement ST1. An edge portion ST2_E of the second reinforcement ST2 may protrude downward and may be adjacent to the first reinforcement ST1 (e.g., the upper surface of the first reinforcement ST1). The first reinforcement ST1 may have a first width WT1. An edge portion ST2_E of the second reinforcement ST2 disposed on the first reinforcement ST1 may have a second width WT2 greater than the first width WT1. The lower surface of the edge portion ST2_E of the second reinforcement ST2 may be partially exposed. For example, a portion of the edge portion ST2_E of the second reinforcement member ST2 may be vertically overlapped with the first peripheral structure PD. The second adhesive layer AD2 may be disposed between the first reinforcement member ST1 and the second reinforcement member ST2. However, according to other aspects of the inventive concept, the first reinforcement member ST1 may be in contact with the second reinforcement member ST2 without the second adhesive layer AD2 disposed therebetween. The first reinforcement member ST1 and the second reinforcement member ST2 may be integrally formed. Other structures may be similar to Fig. 20 The structures are the same / similar.

[0094] Fig. 22 is a cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0095] Reference Fig. 22 , the semiconductor package 1017 according to this example may not include (or exclude) Figures 1 to 7 The first peripheral structure PD or the second peripheral structure DM of the present invention. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2 stacked in sequence. The first reinforcement ST1 may surround the chip structure CS. The second reinforcement ST2 may completely cover the chip structure CS. The edge portion ST2_E of the second reinforcement ST2 may have the same width as the first reinforcement ST1. Other structures may be similar to Fig.21 The structures are the same / similar.

[0096] Fig.23 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

[0097] Reference Fig.23 In the semiconductor package 1018 according to the present example, the reinforcement structure STS may surround the chip structure CS. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2. When viewed in a plan view, the first reinforcement ST1 and the second reinforcement ST2 may each have an "L" shape. The chip structure CS includes a first corner CN1 to a fourth corner CN4 arranged in a clockwise direction. The second reinforcement ST2 may be adjacent to the first corner CN1 and the third corner CN3, and may cover the first corner CN1 and the third corner CN3. The first reinforcement ST1 may be adjacent to the second corner CN2 and the fourth corner CN4, and may cover the second corner CN2 and the fourth corner CN4. The second adhesive layer AD2 may be placed between the first reinforcement ST1 and the second reinforcement ST2. The first reinforcement ST1 may have a thermal expansion coefficient different from that of the second reinforcement ST2. Other structures may be similar to those of reference Fig. 9 and Fig.10 The structures described are the same / similar.

[0098] Fig.24 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

[0099] Reference Fig.24 In the semiconductor package 1019 according to the present example, the reinforcement structure STS may surround the chip structure CS. The reinforcement structure STS includes a first reinforcement ST1 and a second reinforcement ST2. When viewed in a plan view, the first reinforcement ST1 may have an "I" shape. When viewed in a plan view, the second reinforcement ST2 may have a "U" shape. The chip structure CS includes a first corner CN1 to a fourth corner CN4 and a first side wall SW1 to a fourth side wall SW4 arranged in a clockwise direction. The second reinforcement ST2 may be adjacent to the first corner CN1 to the fourth corner CN4 and cover the first corner CN1 to the fourth corner CN4. The second reinforcement ST2 may be adjacent to the first side wall SW1 and the third side wall SW3 of the chip structure CS. The first reinforcement ST1 may be adjacent to the second side wall SW2 and the fourth side wall SW4 of the chip structure CS. The second adhesive layer AD2 may be placed between the first reinforcement ST1 and the second reinforcement ST2. Other structures may be the same as those described with reference to FIG. Fig.23 The structures described are the same / similar.

[0100] Fig.25 is a plan view of a semiconductor package according to an embodiment of the present disclosure.

[0101] Reference Fig.25In the semiconductor package 1020 according to the present example, the reinforcement structure STS may surround the chip structure CS. The reinforcement structure STS includes first to third reinforcements ST1, ST2, and ST3. When viewed in a plan view, the first reinforcement ST1 and the third reinforcement ST3 may have an "I" shape. When viewed in a plan view, the second reinforcement ST2 may have a "U" shape. The chip structure CS includes a first corner CN1 to a fourth corner CN4 and a first side wall SW1 to a fourth side wall SW4 arranged in a clockwise direction. The second reinforcement ST2 may be adjacent to the first corner CN1 to the fourth corner CN4 and cover the first corner CN1 to the fourth corner CN4. The second reinforcement ST2 may be adjacent to the first side wall SW1 and the third side wall SW3 of the chip structure CS. The first reinforcement ST1 and the third reinforcement ST3 may be adjacent to the second side wall SW2 and the fourth side wall SW4 of the chip structure CS. The third reinforcement ST3 may be attached to the inner wall of the first reinforcement ST1 by a third adhesive layer AD3. Other structures may be the same as those described with reference to FIG. Fig.24 The structures described are the same / similar.

[0102] In the semiconductor package according to the present disclosure, the structure of the stiffener structure may be changed, the stiffener structure may include a plurality of stiffeners having different materials, and thus warpage of the semiconductor package may be effectively suppressed or controlled in a minimum area.

[0103] Although the embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. Therefore, the exemplary embodiments of the present disclosure should be considered in all aspects to be illustrative and not restrictive, and the spirit and scope of the present disclosure are indicated by the appended claims. Figures 1 to 25 Aspects of the embodiments may be combined with each other.

Claims

1. A semiconductor package, the semiconductor package include: Package substrate; Chip structure, on the package substrate; A peripheral structure, disposed on the package substrate and around the chip structure; as well as A reinforcement structure is disposed at the edge of the package substrate and surrounds the peripheral structure and the chip structure, The reinforcement structure includes a first reinforcement and a second reinforcement stacked in sequence. wherein the second reinforcement member comprises a material different from that of the first reinforcement member, and The second reinforcement has a second width that is wider than the first width of the first reinforcement and is vertically overlapped with the peripheral structure.

2. The semiconductor package according to claim 1, in, The peripheral structure is at least one of a capacitor, a resistor, and a dam.

3. The semiconductor package according to claim 1, in, The first reinforcement member has a smaller thermal expansion coefficient than the second reinforcement member.

4. The semiconductor package according to claim 1, in, The reinforcement structure further includes a third reinforcement stacked on the second reinforcement, wherein the third reinforcement member comprises a material different from a material of at least one of the first reinforcement member and the second reinforcement member, and Wherein, the third reinforcement member is overlapped with the chip structure.

5. The semiconductor package according to claim 1, in, A first height between the upper surface of the stiffener structure and the upper surface of the package substrate is higher than a second height between the upper surface of the chip structure and the upper surface of the package substrate, and The first height is 1.1 to 3 times the second height.

6. The semiconductor package according to claim 1, in, The reinforcement structure also includes an adhesive layer disposed between the first reinforcement and the second reinforcement.

7. The semiconductor package according to claim 1, in, A side wall of the first reinforcement member is aligned with a side wall of the second reinforcement member, or The center of the first reinforcement member vertically overlaps the center of the second reinforcement member.

8. The semiconductor package according to claim 1, in, The reinforcement structure further includes a third reinforcement adjacent to a side surface of the second reinforcement or a side surface of the first reinforcement, the reinforcement structure surrounding both the chip structure and the peripheral structure, and The third reinforcement member includes a material different from a material of at least one of the first reinforcement member and the second reinforcement member.

9. The semiconductor package according to claim 1, in, When viewed in plan view, the first stiffener surrounds both the chip structure and the peripheral structure, and The second reinforcement member extends to cover the chip structure. 10 . The semiconductor package of claim 1 , further comprising a thermal boundary material layer disposed between the second stiffener and the chip structure.

11. A semiconductor package, the semiconductor package include: Package substrate; Built-in substrate, on the package substrate; A dedicated semiconductor chip is disposed at the center of the built-in substrate; A first memory chip and a second memory chip are arranged on one side of the dedicated semiconductor chip; A third memory chip and a fourth memory chip are arranged on the other side of the dedicated semiconductor chip; a molding layer covering the sidewalls of the dedicated semiconductor chip, the sidewalls of the first to fourth memory chips, and the upper surface of the built-in substrate; as well as A reinforcement structure is disposed at an edge of the package substrate and surrounds the built-in substrate, The reinforcement structure includes a first reinforcement and a second reinforcement stacked in sequence. wherein the second reinforcement member comprises a material different from that of the first reinforcement member, wherein the second reinforcement has a second width that is wider than the first width of the first reinforcement, and The thermal expansion coefficient of the first reinforcement is smaller than the thermal expansion coefficient of the second reinforcement.

12. The semiconductor package according to claim 11, in, The semiconductor package further includes a passive element disposed on the package substrate and between the built-in substrate and the first reinforcement member. wherein the second reinforcement member is vertically stacked with the passive element, and The passive element is at least one of a capacitor and a resistor.

13. The semiconductor package according to claim 11, in, The reinforcement structure further includes a third reinforcement stacked on the second reinforcement, wherein the third reinforcement member comprises a material different from a material of at least one of the first reinforcement member and the second reinforcement member, and The third reinforcing member is stacked with the dedicated semiconductor chip, the first memory chip to the fourth memory chip and the built-in substrate.

14. The semiconductor package according to claim 11, in, A first height of an upper surface of the stiffener structure from an upper surface of the package substrate is higher than a second height of an upper surface of the dedicated semiconductor chip from an upper surface of the package substrate, and The first height is 1.1 to 3 times the second height.

15. The semiconductor package according to claim 11, in, The reinforcement structure also includes an adhesive layer disposed between the first reinforcement and the second reinforcement.

16. The semiconductor package according to claim 11, in, A side wall of the first reinforcement member is aligned with a side wall of the second reinforcement member, or The center of the first reinforcement member vertically overlaps the center of the second reinforcement member.

17. The semiconductor package according to claim 11, in, The reinforcement structure further includes a third reinforcement adjacent to a side surface of the second reinforcement or a side surface of the first reinforcement, the reinforcement structure surrounding the built-in base, and The third reinforcement member includes a material different from a material of at least one of the first reinforcement member and the second reinforcement member.

18. A semiconductor package, the semiconductor package include: Package substrate; Chip structure, on the package substrate; as well as A reinforcement structure is disposed at the edge of the package substrate and surrounds the chip structure, wherein the reinforcement structure comprises a first reinforcement and a second reinforcement formed of different materials, and Wherein, when viewed in a plan view, the first reinforcement member and the second reinforcement member surround the chip structure, and the second reinforcement member is adjacent to an inner wall of the first reinforcement member.

19. The semiconductor package according to claim 18, in, A height of an upper surface of the first stiffener from an upper surface of the package substrate is different from a height of an upper surface of the second stiffener from an upper surface of the package substrate.

20. The semiconductor package according to claim 18, in, The reinforcement structure further includes a third reinforcement member disposed on at least one of the first reinforcement member and the second reinforcement member, and The third reinforcement member includes a material different from a material of at least one of the first reinforcement member and the second reinforcement member.

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