Power optimizer dedicated chip and application circuit thereof

Abstract

The application discloses a power optimizer special chip and an application circuit thereof, and belongs to the technical field of power optimizer special chip and application circuit thereof.The power optimizer special chip comprises a package body, an MCU chip, a driving chip and a power device which are packaged in the package body, the MCU chip is connected with at least one driving chip through at least one PWM pin, each driving chip drives two power devices, and the function pins of the power devices are used as the power node pins, the power ground pins and the drain pins of the special chip and are directly led out of the package body; the MCU chip is integrated with an MMPT algorithm module and a power loop control algorithm module, so that the development process is simplified, the development period is shortened, and the product is put into the market quickly; the application integrates digital control, PWM driving and power devices, and provides a low-cost, small-size and high-efficiency solution for the power optimizer of a photovoltaic module and other power generation components, and has great popularization value.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor and electronic circuit, and particularly relates to a power optimizer special chip and an application circuit thereof. BACKGROUND

[0002] Taking photovoltaic power generation as an example, the output of a single photovoltaic module is often insufficient to meet the actual power demand, and therefore photovoltaic module arrays must be formed in a series-parallel manner to meet design requirements. When selecting photovoltaic modules to form arrays, the following situations are often encountered: due to inconsistent electrical parameters of the series-parallel photovoltaic modules or factors such as partial or intermittent shading or aging of the module strings, the output after series-parallel connection is less than the sum of the outputs of the individual modules. This situation is referred to as "mismatch loss" in the professional field, and it will affect the actual power generation of the entire power station to varying degrees as the operation time of the photovoltaic power station increases.

[0003] In order to eliminate the effects of the above situations and improve photovoltaic power generation, the commonly used solution in the industry at present is to increase photovoltaic power optimizers. That is, in a photovoltaic module array containing multiple series-parallel modules, each photovoltaic module is connected to a power optimizer with independent maximum power point tracking function, and the output of each photovoltaic module is connected to the input of the power optimizer module. In this way, each photovoltaic module is an independent whole relative to the photovoltaic array, and its output power will not be affected by any other module, and it will always output the maximum power value under the current environmental conditions.

[0004] However, the key devices such as power devices, drive chips and controllers used in the photovoltaic optimizers on the market at present are usually built using discrete devices, which have low integration, large size, long development cycle, high cost and are inconvenient to install and use. SUMMARY

[0005] The application is proposed to solve the above technical problems, and provides a power optimizer special chip and an application circuit thereof. The application is implemented through the following technical scheme:

[0006] The application provides a power optimizer special chip, characterized by comprising a package body and an MCU chip, a first driving chip, a first power device and a second power device packaged in the package body; the MCU chip is integrated with an MMPT algorithm module and a power loop control algorithm module; the MCU chip has a first PWM output pin, and the first PWM output pin is connected with a PWM input pin of the first driving chip in the package body; a first driving output end and a second driving output end of the first driving chip are respectively connected with a gate of the first power device and a gate of the second power device in the package body; a drain of the first power device is taken as a first drain pin of the special chip and led out of the package body, a source of the second power device is taken as a power ground pin of the special chip and led out of the package body, and a source of the first power device and a drain of the second power device are taken as a first power node pin of the special chip and led out of the package body.

[0007] As a preferred technical scheme, the first driving chip has a group of high-side driving power supply pins and a group of low-side driving power supply pins led out of the special chip and respectively led out of the package body.

[0008] As a preferred technical scheme, the power optimizer special chip further comprises a second driving chip, a third power device and a fourth power device; the MCU chip has a second PWM output pin, and the second PWM output pin is connected with a PWM input pin of the second driving chip in the package body; a first driving output end and a second driving output end of the second driving chip are respectively connected with a gate of the third power device and a gate of the fourth power device in the package body; a drain of the fourth power device is taken as a second drain pin of the special chip and led out of the package body, a source of the third power device is connected with the power ground pin, and a drain of the third power device and a source of the fourth power device are taken as a second power node pin of the special chip and led out of the package body.

[0009] As a preferred technical scheme, the second driving chip has a group of high-side driving power supply pins and a group of low-side driving power supply pins led out of the special chip and respectively led out of the package body.

[0010] As a preferred technical scheme, the first power device, the second power device, the third power device and the fourth power device are GAN power devices.

[0011] As a preferred technical scheme, the MCU chip has a sampling signal processing module and a sampling signal input pin led out of the package body.

[0012] As a preferred technical scheme, the MCU chip has a signal comparison module and a comparison signal input pin led out of the package body.

[0013] As a preferred technical solution, the MCU chip has an HRPWM signal processing module and an HRPWM signal pin directly led out of the package.

[0014] As a preferred technical solution, the MCU chip has an I / O module and an I / O pin directly led out of the package.

[0015] As a preferred technical solution, the MCU chip has a data storage control module and a data storage pin directly led out of the package.

[0016] As a preferred technical solution, the MCU chip has a communication control module and a communication control pin directly led out of the package.

[0017] In the second aspect of the application, a power optimizer special chip application circuit is provided, which comprises the power optimizer special chip with double driving chips described above, and further comprises a capacitor C1, a capacitor C2, a resistor RCS1, a resistor RCS2 and an inductor L1; the positive electrode of the capacitor C1 is connected to the first drain pin and simultaneously connected to the positive output end of a power generation assembly; the negative electrode of the capacitor C1 is connected to the power ground pin and simultaneously connected to the negative output end of the power generation assembly through the resistor RCS1; the positive electrode of the capacitor C2 is connected to the second drain pin and simultaneously serves as the positive output end of the application circuit; the negative electrode of the capacitor C2 is connected to the power ground pin and simultaneously serves as the negative output end of the application circuit after the resistor RCS1; and the inductor L1 is connected in series between the first power node pin and the second power node pin.

[0018] In the third aspect of the application, another power optimizer special chip application circuit is provided, which comprises the power optimizer special chip with double driving chips described above, and further comprises a capacitor C1, a capacitor C2, a resistor RCS1, a resistor RCS2, an inductor L1 and an inductor L2; the positive electrode of the capacitor C1 is connected to a voltage bus VBUS and the first drain pin, and the negative electrode is connected to the power ground pin; the positive electrode of the capacitor C2 is connected to the voltage bus VBUS and the second drain pin, and the negative electrode is connected to the power ground pin; the power ground pin is connected to the negative output end of the power generation assembly and the negative output end of the application circuit through the resistor RCS1 and the resistor RCS2 respectively; and the first power node pin and the second power node pin are connected to the positive output end of the power generation assembly and the positive output end of the application circuit respectively.

[0019] The power optimizer special chip provided by the above technical solution integrates digital control, PWM driving and power devices, provides a low-cost, small-size and high-efficiency solution for the power optimizer of a photovoltaic assembly and other power generation assemblies, and can shorten the research and development cycle and the production and assembly time of the entire power optimizer. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The internal structure diagram of the first power optimizer dedicated chip is provided for the specific embodiment of the present application.

[0021] Figure 2 The application scenario example diagram of the first power optimizer dedicated chip is provided for the specific embodiment of the present application.

[0022] Figure 3 The internal structure diagram of the second power optimizer dedicated chip is provided for the specific embodiment of the present application.

[0023] Figure 4 The pin function diagram of the second power optimizer dedicated chip is provided for the specific embodiment of the present application.

[0024] Figure 5 The application circuit schematic diagram of the second power optimizer dedicated chip is provided for the specific embodiment of the present application.

[0025] Figure 6 The other application circuit schematic diagram of the second power optimizer dedicated chip is provided for the specific embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solutions of the embodiments of the present application are explained and described below in combination with the drawings of the embodiments of the present application. The following embodiments are only preferred embodiments of the present application, and are not all. Based on the embodiments in the embodiments, other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0027] As shown in Figure 1 The first power optimizer dedicated chip provided by the embodiments of the present application can be applied to photovoltaic power optimizer or other similar power optimizer of power generation component. The power optimizer dedicated chip includes a package body, and MCU chip, first driving chip Driver1, first power device GAN_H1 and second power device GAN_L1 packaged in the package body.

[0028] The MCU chip integrates an MMPT algorithm module and a power loop control algorithm module, and is used for realizing power optimization control; the MCU chip has a first PWM output pin, which is connected with a PWM input pin of a first driving chip Driver1 in the package; a first driving output end and a second driving output end of the first driving chip Driver1 are respectively connected with a gate (G terminal) of a first power device GAN_H1 and a gate (G terminal) of a second power device GAN_L1 in the package; a drain (D terminal) of the first power device GAN_H1 is taken as a first drain pin D1 of the special chip and led out of the package; a source (S terminal) of the second power device GAN_L1 is taken as a power ground pin PGND of the special chip and led out of the package; a source (S terminal) of the first power device GAN_H1 and a drain (D terminal) of the second power device GAN_L1 are taken as a first power node pin SW1 of the special chip and led out of the package.

[0029] The first driving chip Driver1 has a group of high-side driving power supply pins HB1 and HS1 led out of the special chip, and also has a group of low-side driving power supply pins COM1 and VDD1, and the high-side driving power supply pins HB1 and HS1 and the low-side driving power supply pins COM1 and VDD1 are respectively led out of the package.

[0030] The power optimizer special chip adopts a structure of a single driving chip and double power devices, and in a specific application, the first drain pin D1 and the first power node pin SW1 can be used to connect the power optimizer 100 adopting the special chip in a string group of a power generation assembly, and the MCU chip can be connected with a power generation component through the first driving chip Driver1 and the second driving chip Driver2. Figure 2

[0031] As shown in Figure 3 and Figure 4 , the second power optimizer special chip provided by the embodiment of the present application is used for realizing power optimization control. Figure 1 ​The second driving chip Driver2, the third power device GAN_H2 and the fourth power device GAN_L2 are further included on the basis of the special chip; the MCU chip further has a second PWM output pin, the second PWM output pin is connected with a PWM input pin of the second driving chip Driver2 in the package; a first driving output end and a second driving output end of the second driving chip Driver2 are respectively connected with a gate (G) of the third power device GAN_H2 and a gate (G) of the fourth power device GAN_L2 in the package; a drain (D) of the fourth power device GAN_L2 is taken out of the package as a second drain pin D2 of the special chip, a source (S) of the third power device GAN_H2 is connected with the power ground pin PGND, and a drain (D) of the third power device GAN_H2 and a source (S) of the fourth power device GAN_L2 are taken out of the package as a second power node pin SW2 of the special chip.

[0032] Similarly, the second driving chip Driver2 has a group of high-side driving power supply pins HB2 and HS2 taken out of the special chip, and further has a group of low-side driving power supply pins COM2 and VDD2, the high-side driving power supply pins HB2 and HS2 and the low-side driving power supply pins COM2 and VDD2 are taken out of the package.

[0033] In the second power optimizer special chip provided by the above embodiment, the MCU chip provides functions of external communication, signal sampling, power control, IO control and the like for realizing the photovoltaic optimizer; the two integrated isolated or non-isolated half-bridge driving chips Driver1 and Driver2 play a role of connecting the upper and lower links; the driving chips Driver1 and Driver2 are controlled by the MCU chip and directly control the on-off of the corresponding power devices; the four integrated power devices are all GAN power devices, GAN_H1 and GAN_L1 form an upper-lower tube power circuit node SW1, and GAN_H2 and GAN_L2 form an upper-lower tube power circuit node SW2; due to the small parasitic parameters of the GAN power devices, the photovoltaic power optimizer can provide higher working efficiency and switching frequency, and the volume and cost of the photovoltaic power optimizer can be reduced.

[0034] In addition, the driving chips Driver1 and Driver2 are directly connected with the MCU chip and the gates of the power devices in the package, so that the parasitic parameters of the lines are reduced; meanwhile, the two driving chips respectively take out a lower tube driving power supply pin VDD, a COM pin, an upper tube driving power supply pin HB and an HS pin, and the upper tube driving power supply can use a power supply independent of the lower tube or a bootstrap driving power supply.

[0035] Continuing to refer to Figure 3 and Figure 4In the special-purpose chip provided by the above embodiment, the MCU chip has a sampling signal processing module and a sampling signal input pin directly led out of the package, and the MCU chip also has a signal comparison module and a comparison signal input pin directly led out of the package; for example, the MCU chip leads out ADC1 / COMP1-ADC6 / COMP6 to provide the photovoltaic power optimizer with signal sampling and internal comparator protection functions. The MCU chip has an HRPWM signal processing module and an HRPWM signal pin directly led out of the package; for example, the MCU chip leads out HRPWM1 and HRPWM2 pins to reserve PWM control requirements of the photovoltaic power optimizer. The MCU chip has an I / O module and an I / O pin directly led out of the package; for example, the MCU chip leads out PA1-PA6 to provide the photovoltaic power optimizer with I / O control requirements. The MCU chip has a data storage control module and a data storage pin directly led out of the package; for example, the MCU chip leads out SDA and SCL pins to provide the photovoltaic power optimizer with a connection of an external storage. The MCU chip also has a communication control module and a communication control pin directly led out of the package; for example, the MCU chip leads out UART0_RX / GAN_RX and UART0_TX / GAN_TX to provide the photovoltaic power optimizer with a link for communication with the outside.

[0036] In the special-purpose chip provided by the above embodiment, the names and functions of the pins are as shown in the following table:

[0037]

[0038]

[0039] In each of the above embodiments, the MCU chip can be an existing MCU chip having PWM control and capable of integrating and MMPT algorithm and power loop control algorithm, for example, the MCU chip of TAE32F5300 and TAE32G5800 of Zhuhai Taiwei Electronics Co., Ltd. The first driving chip Driver1 and the second driving chip Driver2 can be an existing power device driving chip, for example, the NSD2621X series driving chip of Nanxin Microelectronics. In addition, all the power devices are GAN (gallium nitride) power devices, which can provide higher power generation efficiency and switching frequency, and can further reduce the volume and cost of the product.

[0040] The special chip provided by the above embodiment integrates digital control, PWM drive and GAN power device; since the three key devices are combined together, the volume is smaller, and the use and assembly are more convenient. Meanwhile, the integrated GAN power device can provide higher power generation efficiency and switching frequency, which can further reduce the volume and cost of the product; in addition, the special chip of the application solidifies the MMPT algorithm and power loop control algorithm, which can be directly called by the development engineer during the development process, simplifies the development process, and shortens the development cycle to speed up the product to market. Therefore, the application provides a low-cost, small-volume, high-efficiency and short-development-cycle solution for photovoltaic optimizers, which has great popularization value and economic benefits.

[0041] As shown in Figure 5 The application also provides another power optimizer special chip application circuit, which comprises the power optimizer special chip with double drive chips; further comprising a capacitor C1, a capacitor C2, a resistor RCS1, a resistor RCS2, an inductor L1 and an inductor L2; the positive electrode of the capacitor C1 is connected to the voltage bus VBUS and the first drain pin, and the negative electrode is connected to the power ground pin; the positive electrode of the capacitor C2 is connected to the voltage bus VBUS and the second drain pin, and the negative electrode is connected to the power ground pin; the power ground pin is connected to the negative output end of the power generation assembly and the negative output end of the application circuit through the resistor RCS1 and the resistor RCS2 respectively; and the first power node pin and the second power node pin are connected to the positive output end of the power generation assembly and the positive output end of the application circuit respectively.

[0042] As shown in Figure 6 The application also provides another power optimizer special chip application circuit, which comprises the power optimizer special chip with double drive chips; further comprising a capacitor C1, a capacitor C2, a resistor RCS1, a resistor RCS2, an inductor L1 and an inductor L2; the positive electrode of the capacitor C1 is connected to the voltage bus VBUS and the first drain pin, and the negative electrode is connected to the power ground pin; the positive electrode of the capacitor C2 is connected to the voltage bus VBUS and the second drain pin, and the negative electrode is connected to the power ground pin; the power ground pin is connected to the negative output end of the power generation assembly and the negative output end of the application circuit through the resistor RCS1 and the resistor RCS2 respectively; and the first power node pin and the second power node pin are connected to the positive output end of the power generation assembly and the positive output end of the application circuit respectively.

[0043] The above embodiments are only the preferred embodiments for fully disclosing the present application, but not for limiting the present application. Any equivalent technical features based on the creative spirit of the present application without creative labor should be considered as the scope of the present application. For example, the function, name, number, order, etc. of the pin are not limited to the figures of the present application, and other applications based on the idea and structure of the present application are within the protection scope of the present application. The present application is not limited to the photovoltaic power optimizer application proposed in the present application, but can also be applied to other application scenarios based on the present application, such as the application scenario of battery charging and discharging.

Claims

1. A power optimizer dedicated chip, characterized in that: It includes a package body and an MCU chip, a first driver chip, a first power device, and a second power device encapsulated in the package body; the MCU chip integrates an MMPT algorithm module and a power loop control algorithm module; the MCU chip has a first PWM output pin, and the first PWM output pin is connected to the PWM input pin of the first driver chip in the package body; the first driver output end and the second driver output end of the first driver chip are respectively connected to the gate of the first power device and the gate of the second power device in the package body; the drain of the first power device serves as the first drain pin of the dedicated chip and is led out of the package body, the source of the second power device serves as the power ground pin of the dedicated chip and is led out of the package body, and the source of the first power device and the drain of the second power device together serve as the first power node pin of the dedicated chip and are led out of the package body.

2. The power optimizer dedicated chip according to claim 1, characterized in that: The first driver chip has a group of high-side driver power supply pins and a group of low-side driver power supply pins that are led out of the dedicated chip and are respectively led out of the package body.

3. The power optimizer dedicated chip according to claim 2, characterized in that: The power optimizer dedicated chip also includes a second driver chip, a third power device and a fourth power device; the MCU chip has a second PWM output pin, and the second PWM output pin is connected to the PWM input pin of the second driver chip in the package; the first driver output end and the second driver output end of the second driver chip are respectively connected to the gate of the third power device and the gate of the fourth power device in the package; the drain of the fourth power device serves as the second drain pin of the dedicated chip and is led out of the package, the source of the third power device is connected to the power ground pin, and the drain of the third power device and the source of the fourth power device together serve as the second power node pin of the dedicated chip and are led out of the package.

4. The power optimizer dedicated chip according to claim 3, characterized in that: The second driver chip has a group of high-side driver power supply pins and a group of low-side driver power supply pins that are led out of the dedicated chip and are respectively led out of the package body.

5. The power optimizer dedicated chip according to any one of claims 3-4, characterized in that: The first power device, the second power device, the third power device and the fourth power device are GAN power devices.

6. The power optimizer dedicated chip according to any one of claims 3-4, characterized in that: The MCU chip has a sampling signal processing module and a sampling signal input pin directly led out of the package body.

7. The power optimizer dedicated chip according to any one of claims 3-4, characterized in that: The MCU chip has a signal comparison module and a comparison signal input pin directly led out of the package body.

8. The power optimizer dedicated chip according to any one of claims 3-4, characterized in that: The MCU chip has an HRPWM signal processing module and an HRPWM signal pin directly led out of the package body.

9. The power optimizer dedicated chip according to any one of claims 3-4, characterized in that: The MCU chip has an I / O module and I / O pins directly led out of the package body.

10. The power optimizer dedicated chip according to any one of claims 3-4, characterized in that: The MCU chip has a data storage control module and data storage pins directly led out of the package body.

11. The power optimizer dedicated chip according to any one of claims 3-4, characterized in that: The MCU chip has a communication control module and communication control pins directly led out of the package body.

12. A power optimizer dedicated chip application circuit, characterized in that: include: The power optimizer dedicated chip as described in any one of claims 3-11; also includes a capacitor C1, a capacitor C2, a resistor RCS1, a resistor RCS2, and an inductor L1; the positive electrode of the capacitor C1 is connected to the first drain pin and is also connected to the positive output end of the power generation component; the negative electrode of the capacitor C1 is connected to the power ground pin and is also connected to the negative output end of the power generation component through the resistor RCS1; the positive electrode of the capacitor C2 is connected to the second drain pin and serves as the positive output end of the application circuit; the negative electrode of the capacitor C2 is connected to the power ground pin and serves as the negative output end of the application circuit after passing through the resistor RCS1; the inductor L1 is connected in series between the first power node pin and the second power node pin.

13. A power optimizer dedicated chip application circuit, characterized in that: include: The power optimizer dedicated chip as described in any one of claims 3-11; also including capacitor C1, capacitor C2, resistor RCS1, resistor RCS2, inductor L1, and inductor L2; the positive pole of capacitor C1 is connected to the voltage bus VBUS and the first drain pin, and the negative pole is connected to the power ground pin; the positive pole of capacitor C2 is connected to the voltage bus VBUS and the second drain pin, and the negative pole is connected to the power ground pin; the power ground pin is connected to the negative output end of the power generation component and the negative output end of the application circuit through resistors RCS1 and RCS2 respectively; the first power node pin and the second power node pin are respectively connected to the positive output end of the power generation component and the positive output end of the application circuit.

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