Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device. The array substrate has an array region and a peripheral region surrounding the array region. The array substrate comprises a substrate, a driving circuit layer and a light shielding layer. The driving circuit layer is arranged on one side of the substrate and comprises a plurality of signal traces arranged in the array region. The light shielding layer is arranged between the substrate and the driving circuit layer, comprises at least two conductive layers arranged in a stack, and comprises a plurality of connection lines in the peripheral region, wherein the plurality of connection lines are connected to the plurality of signal traces respectively.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] At present, the performance improvement of display panel is urgently needed for the display product application end such as notebook computer, tablet computer and vehicle display, and the display product application end puts forward higher challenge for narrow frame.

[0003] Therefore, how to realize the narrow frame of the product application end is a technical problem to be solved. SUMMARY

[0004] The present application provides an array substrate, a display panel and a display device to reduce the size of the peripheral area of the array substrate, thereby reducing the size of the frame of the display panel.

[0005] In a first aspect, the present application provides an array substrate, the array substrate has an array area and a peripheral area arranged around the array area, and the array substrate comprises:

[0006] a substrate;

[0007] a driving circuit layer arranged on one side of the substrate and comprising a plurality of signal traces arranged in the array area; and

[0008] a light shielding layer arranged between the substrate and the driving circuit layer, comprising at least two layers of stacked conductive layers, and comprising a plurality of connection lines in the peripheral area, and the plurality of connection lines are respectively connected to the plurality of signal traces.

[0009] In a second aspect, the present application further provides a display panel, which comprises the array substrate of any of the above embodiments.

[0010] In a third aspect, the present application further provides a display device, which comprises the display panel of any of the above embodiments.

[0011] In the array substrate, the display panel and the display device of some embodiments of the present application, the light shielding layer comprises at least two layers of stacked conductive layers and a plurality of connection lines in the peripheral area. The plurality of connection lines are respectively connected to the plurality of signal traces in the array area. In this way, the plurality of connection lines comprise at least two layers of stacked conductive layers, the impedance of the plurality of connection lines is small, the speed of transmitting signals from the connection lines to the signal traces is fast, and the performance of the display panel is improved. Moreover, the signal traces can be routed by the connection lines of the light shielding layer in the peripheral area, which facilitates the multi-layer routing of the signal traces in the peripheral area, thereby reducing the space occupied by the signal traces in the peripheral area, and the display panel can realize narrow frame. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 A plan view schematic of an array substrate for some embodiments of the present application;

[0013] Figure 2 A plan view schematic of an array substrate for some other embodiments of the present application;

[0014] Figure 3 A plan view schematic of an array substrate for yet other embodiments of the present application;

[0015] Figure 4 A cross-sectional structure schematic taken along the line Figure 1 A cross-sectional structure schematic taken along the line

[0016] Figure 5 A cross-sectional structure schematic taken along the line Figure 1 A cross-sectional structure schematic taken along the line

[0017] Figure 6 A cross-sectional structure schematic taken along the line Figure 1 A cross-sectional structure schematic taken along the line

[0018] Figure 7 A cross-sectional structure schematic taken along the line Figure 1 A cross-sectional structure schematic taken along the line

[0019] Figure 8 A partial plan view schematic of an array substrate for some embodiments of the present application;

[0020] Figure 9 A partial plan view schematic of an array substrate for some other embodiments of the present application;

[0021] Figure 10 A partial plan view schematic of an array substrate for yet other embodiments of the present application;

[0022] Figure 11 A partial plan view schematic of an array substrate for yet other embodiments of the present application;

[0023] Figure 12 A partial plan view schematic of an array substrate for yet other embodiments of the present application;

[0024] Figure 13 A partial plan view schematic of an array substrate for yet other embodiments of the present application;

[0025] Figure 14 A partial plan view schematic of an array substrate for yet other embodiments of the present application;

[0026] Figure 15 A partial plan view schematic of an array substrate for yet other embodiments of the present application;

[0027] Figure 16 A schematic view of a display panel of some embodiments of the present application;

[0028] Figure 17 A schematic view of a display device of some embodiments of the present application.

[0029] Reference signs are as follows:

[0030] 300, display panel; 400, backlight module; 500, display device;

[0031] 100, array substrate; 100a, array region; 100b, peripheral region;

[0032] 200, counter substrate;

[0033] 1, substrate;

[0034] 2, drive circuit layer;

[0035] 21, first conductive layer; 211, scan line;

[0036] 22, second conductive layer;

[0037] 23, third conductive layer;

[0038] 24, first transparent conductive layer; 241, pixel electrode;

[0039] 25, second transparent conductive layer; 251, common electrode block; 252, touch electrode;

[0040] 26, semiconductor layer; 261, active layer; 2611, channel portion; 2612, lightly doped portion; 2613, heavily doped portion;

[0041] 27, black matrix;

[0042] 281, first insulating layer; 282, second insulating layer; 283, third insulating layer; 284, fourth insulating layer; 285, fifth insulating layer; 286, sixth insulating layer;

[0043] 3, light shielding layer;

[0044] 31, first metal layer; 32, second metal layer; 33, third metal layer; 34, fourth metal layer;

[0045] 35, connection line; 351, first connection line; 352, second connection line; 36, light shielding portion; 36A, light shielding portion group; 37, light shielding connection portion; 371, hollow portion; 3711, first hollow portion; 3712, second hollow portion;

[0046] 4, signal trace; 41, data line; 42, touch line;

[0047] 5, driving unit;

[0048] H1, first via hole; H2, second via hole; H3, third via hole;

[0049] 61, bridge line;

[0050] x, first direction; y, second direction; w, third direction. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative labor fall within the scope of protection of the present application.

[0052] As shown in Figures 1 to 7 , the present application provides an array substrate 100. The array substrate 100 is applied to a display panel 300, and the display panel 300 includes at least one of a liquid crystal display panel, an organic light-emitting diode display panel, a micro light-emitting diode display panel, and a sub-millimeter light-emitting diode display panel. The array substrate 100 has an array region 100a and a peripheral region 100b arranged around the array region 100a. The array region 100a overlaps with a display region of the display panel 300. The peripheral region 100b overlaps with a non-display region of the display panel 300.

[0053] The array substrate 100 includes a substrate 1, a driving circuit layer 2, and a light shielding layer 3.

[0054] The substrate 1 can include a hard substrate such as a glass substrate. The substrate 1 can also include a flexible substrate such as a polymer substrate.

[0055] The driving circuit layer 2 includes a plurality of driving circuits. As shown in Figures 1 to 3 , Figure 5 and Figure 7 , the driving circuit layer 2 is arranged on one side of the substrate 1 and includes a plurality of signal lines 4 arranged in the array region 100a. The plurality of signal lines 4 are used to transmit signals.

[0056] As shown in Figures 4 to 7 , the light shielding layer 3 is arranged between the substrate 1 and the driving circuit layer 2. The light shielding layer 3 includes at least two layers of conductive layers arranged in a stack. In this way, the light shielding layer 3 not only has a light shielding effect, but also has a low impedance.

[0057] As shown in Figures 1 to 3 , Figure 5 and Figure 7As shown, the light-shielding layer 3 includes multiple connecting lines 35 located in the peripheral area 100b. These connecting lines 35 are respectively connected to multiple signal traces 4. Thus, each connecting line 35 includes at least two stacked conductive layers. The connecting lines 35 with lower impedance transmit signals to the signal traces 4 in the array area 100a faster, improving the performance of the display panel 300. Furthermore, the signal traces 4 can be routed in the peripheral area 100b not only using the film layer containing the signal traces 4, but also using the connecting lines 35 of the light-shielding layer 3. This facilitates multi-layer routing of the signal traces 4 in the peripheral area 100b, thereby reducing the space occupied by the signal traces 4 in the peripheral area 100b and enabling a narrow bezel design for the display panel 300. In addition, since the light-shielding layer 3 is located below the driving circuit layer 2, it is less prone to damage, reducing the risk of damage to the connecting lines 35 connected to the signal traces 4 and improving the performance stability of the display panel 300.

[0058] It should be noted that in related technologies, in order to reduce the thickness of the light-shielding layer and thus reduce the risk of breakage of the film layer above the light-shielding layer due to slope climbing, the light-shielding layer is usually designed as a single-layer metal layer. In some embodiments of this application, in order to reduce the impedance when the light-shielding layer is applied to the wiring in the peripheral area 100b, the light-shielding layer 3 is adjusted to include at least two conductive layers.

[0059] In some embodiments, multiple connection lines 35 are also connected to the drive unit 5. Thus, the drive unit 5 is connected to the signal trace 4 via multiple connection lines 35.

[0060] In some embodiments, such as Figures 1 to 3 As shown, the multiple signal traces 4 include at least one of data lines 41 and touch lines 42. It is understood that the multiple signal traces 4 can also be other signal traces.

[0061] Data lines 41 are used to transmit data signals. Multiple data lines 41 extend along the second direction y and are spaced apart along the first direction x. The first direction x intersects the second direction y.

[0062] Touch lines 42 are used to transmit touch signals. Multiple touch lines 42 are insulated from multiple data lines 41. The multiple touch lines 42 extend along the second direction y and are spaced apart along the first direction x.

[0063] In some embodiments, the first direction x is perpendicular to the second direction y, but this is not a limitation. The angle between the first direction x and the second direction y can be an acute angle or an obtuse angle.

[0064] like Figures 1 to 3 As shown, the array substrate 100 may further include multiple touch electrodes 252, and a touch line 42 is connected to one touch electrode 252. Wherein, Figures 1 to 3The black dot P1 in the diagram indicates the connection point between the touch line 42 and the touch electrode 252.

[0065] In some embodiments, multiple data lines 41 and multiple touch lines 42 can be located in a single conductive layer. This allows multiple data lines 41 and multiple touch lines 42 to be formed simultaneously, simplifying the fabrication process of the multiple data lines 41 and multiple touch lines 42.

[0066] In other embodiments, the data line 41 and the touch line 42 may be located in different conductive layers to increase the layout space for the data line 41 and the touch line 42.

[0067] In some embodiments, such as Figure 1 As shown, multiple connecting lines 35 are connected to multiple data lines 41, and the connection position between the connecting lines 35 and the data lines 41 is indicated by a black dot P2. Multiple touch lines 42 extend from the array area 100a to the peripheral area 100b and connect to the driving unit 5. In this way, while achieving a narrow bezel in the display panel 300, the impedance of the data signal transmission traces is reduced, and the refresh rate of the display panel 300 is improved.

[0068] In other embodiments, such as Figure 2 As shown, multiple connecting lines 35 are connected to multiple touch lines 42, and the connection positions between the connecting lines 35 and the touch lines 42 are indicated by black dots P2. Multiple data lines 41 extend from the array area 100a to the peripheral area 100b and are connected to the driving unit 5. In this way, while achieving a narrow bezel for the display panel 300, the impedance of the traces transmitting touch signals is reduced, and the touch sensitivity of the display panel 300 is improved.

[0069] In some other embodiments, such as Figure 3 As shown, the multiple connection lines 35 include multiple first connection lines 351 and multiple second connection lines 352 spaced apart from each other. The multiple first connection lines 351 are connected to multiple data lines 41 respectively. The multiple second connection lines 352 are connected to multiple touch lines 42 respectively. The connection positions between the first connection lines 351 and the data lines 41, and the connection positions between the second connection lines 352 and the touch lines 42, are indicated by black dots P2. In this way, while achieving a narrow bezel for the display panel 300, the impedance of the traces transmitting data signals and touch signals is reduced, thereby improving the refresh rate and touch sensitivity of the display panel 300.

[0070] In some embodiments, such as Figure 5 As shown, the connection line 35 of the peripheral area 100b and the signal trace 4 of the array area 100a can be connected through the first via H1.

[0071] In other embodiments, such as Figure 7As shown, the connecting line 35 of the peripheral region 100b and the signal trace 4 of the array region 100a can be bridged by a bridge line 61. The bridge line 61 is connected with the connecting line 35 through a second via hole H2, and the bridge line 61 is connected with the signal trace 4 through a third via hole H3.

[0072] As shown in FIG. 1, the array substrate 100 includes a peripheral region 100b and an array region 100a. The peripheral region 100b is located around the array region 100a. The array region 100a includes a plurality of pixel units 10 arranged in an array. Each of the pixel units 10 includes a pixel electrode 2 and a signal trace 4. The signal trace 4 is connected with the pixel electrode 2. The peripheral region 100b includes a connecting line 35 and a bridge line 61. The connecting line 35 is connected with the bridge line 61. The bridge line 61 is connected with the signal trace 4. Figure 4 Figure 5 As shown in FIG. 1, the array substrate 100 includes a peripheral region 100b and an array region 100a. The peripheral region 100b is located around the array region 100a. The array region 100a includes a plurality of pixel units 10 arranged in an array. Each of the pixel units 10 includes a pixel electrode 2 and a signal trace 4. The signal trace 4 is connected with the pixel electrode 2. The peripheral region 100b includes a connecting line 35 and a bridge line 61. The connecting line 35 is connected with the bridge line 61. The bridge line 61 is connected with the signal trace 4.

[0073] In some embodiments, the material of the first metal layer 31 is selected from at least one of aluminum, an aluminum alloy, copper, and a copper alloy. The material of the second metal layer 32 is selected from at least one of molybdenum, a molybdenum alloy, titanium, and a titanium alloy. In this way, the light-shielding layer 3 has low impedance, and the reflectivity of the first metal layer 31 to light is greater than that of the second metal layer 32. In addition, the second metal layer 32 protects the first metal layer 31, reducing the risk of corrosion of the first metal layer 31.

[0074] For example, the first metal layer 31 includes aluminum, and the second metal layer 32 includes molybdenum. In this way, the first metal layer 31 has high reflectivity and low impedance to light, and the second metal layer 32 protects the first metal layer 31. In addition, the second metal layer 32 has high temperature resistance.

[0075] In some embodiments, the thickness of the first metal layer 31 can be greater than the thickness of the second metal layer 32. In this way, the reflection effect of the first metal layer 31 to the backlight is improved, and the utilization rate of the backlight is improved.

[0076] In other embodiments, the thickness of the first metal layer 31 can be less than or equal to the thickness of the second metal layer 32. In this way, the utilization rate of the backlight is improved, the impedance of the light-shielding layer 3 is reduced, and the risk of disconnection of other film layers due to excessive thickness of the light-shielding layer 3 is reduced.

[0077] As shown in FIG. 1, the array substrate 100 includes a peripheral region 100b and an array region 100a. The peripheral region 100b is located around the array region 100a. The array region 100a includes a plurality of pixel units 10 arranged in an array. Each of the pixel units 10 includes a pixel electrode 2 and a signal trace 4. The signal trace 4 is connected with the pixel electrode 2. The peripheral region 100b includes a connecting line 35 and a bridge line 61. The connecting line 35 is connected with the bridge line 61. The bridge line 61 is connected with the signal trace 4. Figure 6 Figure 7 ​​As shown, in some embodiments, the at least two conductive layers arranged in a stack includes two third metal layers 33 and a fourth metal layer 34, the fourth metal layer 34 is located between the two third metal layers 33, and the material of the fourth metal layer 34 has a higher electrical conductivity than the material of the third metal layer 33. In this way, the impedance of the light shielding layer 3 is reduced.

[0078] In some embodiments, the material of the third metal layer 33 is selected from at least one of molybdenum, molybdenum alloy, titanium and titanium alloy, and the material of the fourth metal layer 34 is selected from at least one of aluminum, aluminum alloy, copper and copper alloy. In this way, the light shielding layer 3 has low impedance, and the two third metal layers 33 protect the fourth metal layer 34, reducing the risk of corrosion of the fourth metal layer 34.

[0079] For example, the light shielding layer 3 can include, but is not limited to, any one of the following three-layer stacked metals: MoAlMo, TiAlTi, MoCuMo, TiCuTi, etc. In this way, the light shielding layer 3 has low impedance, and the two third metal layers 33 protect the fourth metal layer 34, reducing the risk of corrosion of the fourth metal layer 34.

[0080] In some embodiments, the thickness of the fourth metal layer 34 is greater than the thickness of the third metal layer 33. In this way, the impedance of the light shielding layer 3 is further reduced.

[0081] In some embodiments, the thickness of the fourth metal layer 34 is 1500 angstroms to 5000 angstroms, and the thickness of the third metal layer 33 is 200 angstroms to 1000 angstroms.

[0082] As shown in Figure 1 , Figure 4 and Figure 6 , the drive circuit layer 2 includes a plurality of thin film transistors T arranged in an array along the first direction x and the second direction y.

[0083] In some embodiments, the thin film transistor T can be selected from any one of a metal oxide transistor, a low-temperature polysilicon transistor, and an amorphous silicon transistor. For example, the thin film transistor T is a low-temperature polysilicon transistor, which improves the stability of the thin film transistor T under high temperature and high humidity conditions.

[0084] It should be noted that in the case of the thin film transistor T being a low-temperature polysilicon transistor, the light shielding layer 3 adopts the design of the first metal layer 31 and the second metal layer 32 or the two third metal layers 33 and the fourth metal layer 34 described above, which can improve the high temperature resistance of the light shielding layer 3 during the formation of the low-temperature polysilicon transistor.

[0085] In some embodiments, the thin film transistor T can include at least one of a drive transistor and a switching transistor. The drive transistor can be turned on to drive the light emitting device to emit light. The switching transistor can be turned on to transmit a data signal transmitted by the data line 41 to the drive transistor. Exemplarily, the plurality of thin film transistors T can be drive transistors.

[0086] In some embodiments, as shown in FIG. 1, the plurality of thin film transistors T arranged along the second direction y are connected to the data line 41. Figure 1

[0087] As shown in FIG. 1, the drive circuit layer 2 further includes a semiconductor layer 26. The semiconductor layer 26 includes a plurality of active layers 261 arranged in an array along the first direction x and the second direction y, and the plurality of active layers 261 are located in the array region 100a. The plurality of thin film transistors T include the plurality of active layers 261. The active layer 261 includes a channel portion 2611. Figure 4 Figure 6 Figures 8 to 12 As shown in FIG. 1, the drive circuit layer 2 further includes a semiconductor layer 26. The semiconductor layer 26 includes a plurality of active layers 261 arranged in an array along the first direction x and the second direction y, and the plurality of active layers 261 are located in the array region 100a. The plurality of thin film transistors T include the plurality of active layers 261. The active layer 261 includes a channel portion 2611.

[0088] In some embodiments, the active layer 261 can include at least one of a low-temperature polysilicon active layer, an amorphous silicon active layer, and a metal oxide active layer, but is not limited thereto. Exemplarily, the active layer 261 is a low-temperature polysilicon active layer. In this way, the high-temperature resistance and other properties of the active layer 261 are improved.

[0089] In some embodiments, as shown in FIG. 1, when the active layer 261 is a low-temperature polysilicon active layer, the active layer 261 further includes a doped portion located on both sides of the channel portion 2611, and the channel portion 2611 is connected between the two doped portions. One doped portion includes a lightly doped portion 2612 and a heavily doped portion 2613, and the lightly doped portion 2612 is connected between the channel portion 2611 and the heavily doped portion 2613. Figure 4 Figure 6 In some embodiments, as shown in FIG. 1, when the active layer 261 is a low-temperature polysilicon active layer, the active layer 261 further includes a doped portion located on both sides of the channel portion 2611, and the channel portion 2611 is connected between the two doped portions. One doped portion includes a lightly doped portion 2612 and a heavily doped portion 2613, and the lightly doped portion 2612 is connected between the channel portion 2611 and the heavily doped portion 2613.

[0090] In some embodiments, as shown in FIG. 1, when the active layer 261 is a low-temperature polysilicon active layer, the active layer 261 further includes a doped portion located on both sides of the channel portion 2611, and the channel portion 2611 is connected between the two doped portions. One doped portion includes a lightly doped portion 2612 and a heavily doped portion 2613, and the lightly doped portion 2612 is connected between the channel portion 2611 and the heavily doped portion 2613. Figures 8 to 12 In some embodiments, as shown in FIG. 1, when the active layer 261 is a low-temperature polysilicon active layer, the active layer 261 further includes a doped portion located on both sides of the channel portion 2611, and the channel portion 2611 is connected between the two doped portions. One doped portion includes a lightly doped portion 2612 and a heavily doped portion 2613, and the lightly doped portion 2612 is connected between the channel portion 2611 and the heavily doped portion 2613.

[0091] Figure 4 Figure 6 Figures 8 to 12 ​​​​​​​As shown, the light-shielding layer 3 also includes a plurality of light-shielding portions 36 arranged in an array along the first direction x and the second direction y in the array region 100a. The plurality of orthographic projections of the plurality of channel portions 2611 on the substrate are respectively located within the orthographic projections of the plurality of light-shielding portions 36 on the substrate. Thus, the plurality of light-shielding portions 36 block incident light, mitigating the problem of incident light entering the channel portions 2611 and causing photogenerated carriers to be generated in the active layer 261. Furthermore, by increasing the area of ​​the light-shielding portions 36 based on the fact that the light-shielding layer 3 includes at least two conductive layers, the problem of line breakage in the active layer 261 due to the increased thickness of the light-shielding layer 3 is reduced.

[0092] like Figure 8 As shown, in some embodiments, the orthographic projection of the channel portion 2611 of an active layer 261 onto the substrate 1 lies within the orthographic projection of the light-shielding portion 36 onto the substrate 1, and the orthographic projections of the other portions of the active layer 261, excluding the channel portion 2611, onto the substrate 1 do not overlap with the orthographic projection of the light-shielding portion 36 onto the substrate 1. Thus, the light-shielding portion 36 partially blocks the active layer 261, reducing the generation of photogenerated carriers by the channel portion 2611 of the active layer 261.

[0093] like Figures 9 to 12 As shown, in some embodiments, the orthographic projection of an active layer 261 on the substrate 1 lies within the orthographic projection of a light-shielding portion 36 on the substrate 1. Thus, each light-shielding portion 36 covers an active layer 261, enabling multiple light-shielding portions 36 to better block incident light while also reducing the risk of the active layer 261 breaking due to the increased thickness of the light-shielding layer 3.

[0094] In some embodiments, such as Figures 8 to 15 As shown, the light-shielding layer 3 also includes a light-shielding connecting portion 37, and at least two light-shielding portions 36 are connected through at least one light-shielding connecting portion 37. Thus, when the area of ​​the light-shielding portion 36 increases, the coupling effect between at least two signal lines and at least two interconnected light-shielding portions 36 cancels each other out, thereby improving the signal crosstalk problem.

[0095] In some embodiments, such as Figures 8 to 15 As shown, the light-shielding layer 3 includes at least two light-shielding part groups 36A, which are insulated from each other. Each light-shielding part group 36A includes at least two light-shielding parts 36 interconnected by at least one light-shielding part connecting part 37. Thus, the coupling between the at least two interconnected light-shielding parts 36 in a light-shielding part group 36A and the signal line cancels each other out, improving signal crosstalk. The connection between any two light-shielding parts 36 in any two light-shielding part groups 36A is broken.

[0096] In some embodiments, such as Figures 8 to 12As shown, in the first direction x, any two adjacent light shielding parts 36 of the even number of adjacent light shielding parts 36 are connected by one light shielding connecting part 37. In this way, the signal crosstalk problem caused by the coupling effect between the light shielding part 36 and the data line 41 transmitting the opposite polarity data is improved when the area of the light shielding part 36 is increased.

[0097] In some embodiments, in the first direction x, any two adjacent light shielding parts 36 of the 2n adjacent light shielding parts 36 are connected by one light shielding connecting part 37, n is an integer greater than or equal to 2 and less than or equal to 5. In this way, while improving the crosstalk problem caused by the coupling effect between the light shielding part 36 and the data line 41, the risk of the light shielding connecting part 37 breaking due to process reasons and thus causing the connection between adjacent light shielding parts 36 to fail is reduced, and the controllability of improving the crosstalk problem is also improved.

[0098] In some embodiments, in the first direction x, two adjacent light shielding parts 36 are connected by a light shielding connecting part 37; and / or, any two adjacent light shielding parts 36 of the four adjacent light shielding parts 36 are connected by a light shielding connecting part 37; and / or, any two adjacent light shielding parts 36 of the six adjacent light shielding parts 36 are connected by a light shielding connecting part 37.

[0099] Exemplarily, as shown in FIG. 1A, in the first direction x, any two adjacent light shielding parts 36 of the four adjacent light shielding parts 36 are connected by one light shielding connecting part 37. Figures 8 to 12

[0100] It should be noted that when the array substrate 100 is applied to a liquid crystal display panel, the liquid crystal display panel will adopt column inversion technology or dot inversion technology to reduce damage to liquid crystal molecules. When the column inversion technology or the dot inversion technology is adopted, adjacent data lines 41 will transmit data signals of opposite polarity. Specifically, when the data voltage transmitted by one of the two adjacent data lines 41 is greater than the common voltage, the data voltage transmitted by the data line 41 is a positive data voltage, represented by “+”; when the data voltage transmitted by the other of the two adjacent data lines 41 is less than the common voltage, the data voltage transmitted by the data line 41 is a negative data voltage, represented by “-”.

[0101] As shown in FIG. 1A and FIG. 1B, Figure 13 and Figure 14 As shown in FIG. 1A and FIG. 1B, when the liquid crystal display panel 300 adopts the column inversion technology or the dot inversion technology, the light shielding part 36 coupled to the data line 41 transmitting the positive data voltage is marked with “+”, and the light shielding part 36 coupled to the data line 41 transmitting the negative data voltage is marked with “-”.

[0102] For example, Figures 8 to 13 ​The design shown, that is, any two adjacent light shielding parts 36 in the even number of adjacent light shielding parts 36 in the first direction x are connected by a light shielding connecting part 37, so that the coupling effects between the even number of adjacent light shielding parts 36 in the first direction x and the data lines 41 transmitting opposite polarities are offset to each other, and the signal crosstalk problem caused by the coupling effect between the light shielding part 36 and the data line 41 is improved.

[0103] For Figure 14 The design shown, in the third direction w, any two adjacent light shielding parts 36 in the even number of adjacent light shielding parts 36 are connected by a light shielding connecting part 37, and the third direction w intersects the first direction x and the second direction y. In this way, the coupling effects between the even number of adjacent light shielding parts 36 in the third direction w and the data lines 41 transmitting opposite polarities are offset to each other, and the crosstalk problem caused by the coupling effect between the light shielding part 36 and the data line 41 is improved.

[0104] Exemplarily, the included angle between the third direction w and one of the first direction x and the second direction y is 45 degrees, but is not limited thereto.

[0105] In some embodiments, as Figures 8 to 12 The design shown, the driving circuit layer 2 further includes a plurality of scan lines 211. The plurality of scan lines 211 are insulated from the plurality of data lines 41 and the plurality of touch lines 42. The plurality of scan lines 211 extend along the first direction x and are arranged at intervals along the second direction y.

[0106] In some embodiments, as Figure 14 The design shown, in the second direction y, at least two light shielding parts 36 are connected by at least one light shielding connecting part 37. In this way, the signal crosstalk problem caused by the coupling effect between the light shielding part 36 and the plurality of scan lines 211 is improved when the area of the light shielding part 36 is increased.

[0107] In some embodiments, in the second direction y, any two adjacent light shielding parts 36 in the m adjacent light shielding parts 36 are connected by a light shielding connecting part 37, and m is an integer greater than or equal to 2 and less than or equal to 10. In this way, while the signal crosstalk problem caused by the coupling effect between the light shielding part 36 and the data line 41 is improved, the risk of the light shielding connecting part 37 breaking due to process reasons and thus causing the connection between the adjacent light shielding parts 36 to fail is reduced, and the controllability of improving the crosstalk problem is also improved. Exemplarily, m can be 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0108] In some embodiments, the orthogonal projection of the light shielding connecting part 37 on the substrate is staggered with the orthogonal projection of at least one of the signal traces 4 and the scan lines 211 on the substrate. In this way, the overlapping area between the light shielding connecting part 37 and at least one of the signal traces 4 and the scan lines 211 is reduced, the coupling capacitance generated by the overlapping area is reduced, and the risk of signal crosstalk caused by the coupling capacitance is reduced.

[0109] In one example embodiment, as shown in FIG. 3, the light-shielding connecting portion 37 extends along the first direction x and connects two adjacent light-shielding portions 36 in the first direction x. The orthogonal projection of the light-shielding connecting portion 37 on the substrate 1 is offset from the orthogonal projection of the scan line 211 on the substrate 1. In this way, the light-shielding connecting portion 37 does not overlap with the scan line 211, and the coupling capacitance formed between the light-shielding connecting portion 37 and the scan line 211 is reduced, further improving the signal crosstalk problem. Figure 9

[0110] In another example embodiment, the light-shielding connecting portion 37 extends along the second direction y and connects two adjacent light-shielding portions 36 in the second direction y. The orthogonal projection of the light-shielding connecting portion 37 on the substrate 1 is offset from the orthogonal projection of the data line 41 and the touch control line 42 on the substrate 1. In this way, the light-shielding connecting portion 37 does not overlap with the data line 41 and the touch control line 42, and the coupling capacitance formed between the light-shielding connecting portion 37 and the data line 41 and the touch control line 42 is reduced, further improving the signal crosstalk problem.

[0111] In some embodiments, as shown in FIG. 3 and FIG. 4, the area of the light-shielding connecting portion 37 is smaller than the area of the light-shielding portion 36. In this way, the area of the light-shielding connecting portion 37 is small, which improves the signal crosstalk problem caused by the coupling between the light-shielding connecting portion 37 and other signal lines, and improves the light transmittance of the array substrate 100. Figure 8 Figure 9 As shown in FIG. 5, the light-shielding connecting portion 37 includes a hollow portion 371 that penetrates the light-shielding connecting portion 37 along the thickness direction of the light-shielding layer 3. In this way, light can pass through the hollow portion 371, and more light can be incident into the array substrate 100, improving the display brightness of the display panel.

[0112] As shown in FIG. 6, the hollow portions 371 are arranged at intervals. In this way, the light incident into the array substrate 100 can pass through the hollow portions 371. Figures 10 to 12 In some embodiments, as shown in FIG. 7, the hollow portions 371 can be the same. In this way, the manufacturing process of the hollow portions 371 is simplified.

[0113] Figures 10 to 12 In some embodiments, the shapes of the hollow portions 371 can be the same to simplify the forming process of the hollow portions 371. In other embodiments, the shapes of at least two hollow portions 371 can be different.

[0114] As shown in FIG. 8, the hollow portions 371 can be arranged in a staggered manner. In this way, the light incident into the array substrate 100 can pass through the hollow portions 371. Figure 10 In some embodiments, the shapes of the hollow portions 371 can be the same to simplify the forming process of the hollow portions 371. In other embodiments, the shapes of at least two hollow portions 371 can be different.

[0115] As shown in FIG. 9, the hollow portions 371 can be arranged in a staggered manner. In this way, the light incident into the array substrate 100 can pass through the hollow portions 371.

[0116] Figures 10 to 12 ​​​​As shown, the orthographic projection of the hollow part 371 on the substrate overlaps with the orthographic projection of at least one of the scan line 211 and the signal line 4 on the substrate. In this way, on the basis of improving the light transmittance of the array substrate 100, the overlapping area between the light-shielding connecting part 37 and at least one of the signal line 4 and the scan line 211 is reduced, the coupling capacitance caused by the overlapping area is reduced, and the risk of signal crosstalk caused by the coupling capacitance is reduced.

[0117] In some embodiments, as shown in Figure 11 and Figure 12 , the plurality of hollow parts 371 includes a first hollow part 3711 and a second hollow part 3712, and the area of the first hollow part 3711 is greater than the area of the second hollow part 3712. The first hollow part 3711 overlaps with the data line 41 and the scan line 211, and the second hollow part 3712 overlaps with one of the data line 41 and the scan line 211. In this way, the first hollow part 3711 with a larger area overlaps with the data line 41 and the scan line 211 at the same time, reducing the overlapping area between the light-shielding connecting part 37 and the data line 41 and the scan line 211, and the second hollow part 3712 with a smaller area overlaps with one of the data line 41 and the scan line 211.

[0118] In some embodiments, the number of second hollow parts 3712 is greater than the number of first hollow parts 3711. In this way, the coupling capacitance between one of the data line 41 and the scan line 211 and the light-shielding connecting part 37 is more flexibly reduced.

[0119] In some embodiments, the plurality of light-shielding parts 36 can not be connected to a voltage. In other embodiments, the plurality of light-shielding parts 36 can also be connected to a constant voltage.

[0120] As shown in Figure 12 , the array substrate 100 further includes a black matrix 27. The black matrix 27 plays a shielding role for light. The black matrix 27 is located on the side of the light-shielding layer 3 away from the substrate 1. The orthographic projection of the black matrix 27 on the substrate overlaps with the orthographic projection of the light-shielding connecting part 37 on the substrate. In this way, the black matrix 27 plays a shielding role for the light-shielding connecting part 37. The orthographic projection of the black matrix 27 on the substrate can also cover the orthographic projection of the scan line 211 and the data line 41 on the substrate.

[0121] In some embodiments, as shown in Figure 4 and Figure 6 , the array substrate 100 further includes a first insulating layer 281, and the first insulating layer 281 is located between the driving circuit layer 2 and the light-shielding layer 3.

[0122] In some embodiments, as shown in Figure 4 and Figure 6 , the driving circuit layer 2 includes a first conductive layer 21. The first conductive layer 21 is located on the side of the light-shielding layer 3 away from the substrate.

[0123] like Figure 4 As shown, the first conductive layer 21 may include scan lines 211 and the gate of the thin-film transistor T. For example... Figure 7 As shown, the first conductive layer 21 may also include signal traces 4.

[0124] like Figure 4 and Figure 6 As shown, in some embodiments, the first conductive layer 21 may be located on the side of the semiconductor layer 26 opposite to the light-shielding layer 3, and the corresponding thin-film transistor T includes a top gate. In other embodiments, the first conductive layer 21 may be located between the semiconductor layer 26 and the light-shielding layer 3, and the corresponding thin-film transistor T includes a bottom gate.

[0125] In some embodiments, a second insulating layer 282 is disposed between the first conductive layer 21 and the semiconductor layer 26.

[0126] In some embodiments, such as Figure 4 and Figure 6 As shown, the driving circuit layer 2 includes a second conductive layer 22. The second conductive layer 22 is located on the side of the first conductive layer 21 that faces away from the substrate. Figure 4 and Figure 5 As shown, in some embodiments, the second conductive layer 22 may include signal traces 4 such as data lines 41 and touch lines 42, as well as the source of the thin-film transistor T. For example... Figure 6 As shown, in some other embodiments, the second conductive layer 22 includes a data line 41, a touch line 42, and the source and drain of a thin-film transistor T.

[0127] In some embodiments, a third insulating layer 283 is provided between the second conductive layer 22 and the first conductive layer 21.

[0128] like Figure 4 As shown, in some embodiments, the driving circuit layer 2 further includes a third conductive layer 23. The third conductive layer 23 is located on the side of the second conductive layer 22 facing away from the substrate 1. The third conductive layer 23 may include the touch line 42 and the drain of the thin-film transistor T.

[0129] In some embodiments, a fourth insulating layer 284 is provided between the third conductive layer 23 and the second conductive layer 22.

[0130] In some embodiments, the array substrate 100 further includes a first transparent conductive layer 24 and a second transparent conductive layer 25. The first transparent conductive layer 24 is located on the side of the driving circuit layer 2 that is away from the substrate. The second transparent conductive layer 25 is located on the side of the first transparent conductive layer 24 that is away from the substrate.

[0131] One of the first transparent conductive layer 24 and the second transparent conductive layer 25 includes a pixel electrode 241 connected with the drain of the thin film transistor T. The other of the first transparent conductive layer 24 and the second transparent conductive layer 25 includes a plurality of common electrode blocks 251. Exemplarily, the first transparent conductive layer 24 includes the pixel electrode 241, and the second transparent conductive layer 25 includes the common electrode blocks 251.

[0132] In some embodiments, the plurality of common electrode blocks 251 are connected with the touch lines 42 through vias, so that the common electrode blocks 251 are multiplexed as the touch electrodes 252.

[0133] As shown in FIG. 1, in some embodiments, the first transparent conductive layer 24 is provided with a fifth insulating layer 285 between the first transparent conductive layer 24 and the second conductive layer 22 or the third conductive layer 23. The first transparent conductive layer 24 is provided with a sixth insulating layer 286 between the first transparent conductive layer 24 and the second transparent conductive layer 25. Figure 4 Figure 6 As shown in FIG. 1, in some embodiments, the first transparent conductive layer 24 is provided with a fifth insulating layer 285 between the first transparent conductive layer 24 and the second conductive layer 22 or the third conductive layer 23. The first transparent conductive layer 24 is provided with a sixth insulating layer 286 between the first transparent conductive layer 24 and the second transparent conductive layer 25.

[0134] In some embodiments, the first insulating layer 281 to the fourth insulating layer 284 and the sixth insulating layer 286 can all be inorganic insulating layers. The inorganic insulating layer can include at least one of silicon oxide, silicon nitride and silicon oxynitride. The fifth insulating layer 285 can be an organic insulating layer. The organic insulating layer can include at least one of polyimide and polyacrylate.

[0135] Based on the same inventive concept, as shown in FIG. 1, the present application further provides a display panel 300. The display panel 300 includes the array substrate 100 described above. Figure 16 In some embodiments, the display panel 300 further includes an opposite substrate 200, which is arranged opposite to the array substrate 100. The opposite substrate 200 can be any one of a color film substrate and an encapsulation substrate.

[0136] In some embodiments, in the case that the display panel 300 is a liquid crystal display panel, the opposite substrate 200 is provided with a black matrix 27 on a surface facing the array substrate 100. In the case that the light shielding layer 3 of the array substrate 100 includes a light shielding connection portion 37, the black matrix 27 covers the light shielding connection portion 37 in orthographic projection on the array substrate 100.

[0137] As shown in FIG. 1, based on the same inventive concept, the present application further provides a display device 500. The display device 500 includes the display panel 300 described above.

[0138] Figure 17 In some embodiments, in the case that the display device 500 is a liquid crystal display device, the display device 500 further includes a backlight module 400, which is located at the light-incident side of the display panel 300.

[0139] In some embodiments, in the case that the display device 500 is a liquid crystal display device, the display device 500 further includes a backlight module 400, which is located at the light-incident side of the display panel 300. ​​

[0140] The above descriptions of the embodiments are only used to help understand the technical solutions of the present application and the core ideas thereof; it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized by, The array substrate has an array region and a peripheral region surrounding the array region, and comprises: a substrate; a drive circuit layer disposed on one side of the substrate and comprising a plurality of signal lines disposed in the array region, a semiconductor layer, and a plurality of scan lines; the semiconductor layer comprises a plurality of active layers disposed at intervals, and each active layer comprises a channel portion; and a light shielding layer disposed between the substrate and the drive circuit layer, comprising at least two conductive layers disposed in layers, and comprising a plurality of connection lines in the peripheral region; each of the plurality of connection lines is connected to a corresponding one of the plurality of signal lines; the light shielding layer further comprises a plurality of light shielding portions and a light shielding connection portion, and the plurality of channel portions are located within the plurality of light shielding portions in the substrate. At least two of the light shielding portions are connected by at least one light shielding connection portion, and the light shielding connection portion is offset from at least one of the signal lines and the scan lines in the substrate.

2. The array substrate of claim 1, wherein, The area of one light shielding connection portion is smaller than that of one light shielding portion; or The light shielding portion is connected to a constant voltage.

3. The array substrate of claim 1, wherein, The projection of one active layer on the substrate is located within the projection of one light shielding portion on the substrate.

4. The array substrate of claim 1, wherein, The light shielding portion is not connected to a voltage.

5. The array substrate of claim 1, wherein, The drive circuit layer further comprises a plurality of data lines disposed at intervals, and the plurality of data lines are arranged in a first direction and extend in a second direction. In the first direction, any two adjacent light shielding portions among the even-numbered adjacent light shielding portions are connected by one light shielding connection portion; and / or In a third direction, any two adjacent light shielding portions among the even-numbered adjacent light shielding portions are connected by one light shielding connection portion, and the third direction intersects the first direction and the second direction.

6. The array substrate of claim 1, wherein, The plurality of scan lines extend in a first direction and are arranged in a second direction. In the second direction, at least two light shielding portions are connected by the light shielding connection portion.

7. The array substrate of claim 1, wherein, The signal lines comprise at least one of a data line and a touch control line.

8. The array substrate of claim 1, wherein, The light shielding connection portion is provided with a hollow portion, and the hollow portion penetrates the light shielding connection portion in the thickness direction of the light shielding layer.

9. The array substrate of claim 8, wherein, The signal lines comprise at least one of a data line and a touch control line, and the drive circuit layer further comprises a scan line. The projection of the hollow portion on the substrate overlaps the projection of at least one of the scan line and the signal line on the substrate.

10. The array substrate of claim 1, wherein, The light shielding layer comprises at least two light shielding portion groups, any two of which are insulated from each other, and one light shielding portion group comprises at least two light shielding portions connected to each other by at least one light shielding connection portion.

11. The array substrate according to any one of claims 1 to 10, wherein, The at least two conductive layers disposed in layers comprise a first metal layer and a second metal layer, the first metal layer is located between the substrate and the second metal layer, and the reflectivity of the first metal layer to light is greater than that of the second metal layer.

12. The array substrate of claim 11, wherein, The material of the first metal layer is selected from at least one of aluminum, an aluminum alloy, copper, and a copper alloy, and the material of the second metal layer is selected from at least one of molybdenum, a molybdenum alloy, titanium, and a titanium alloy.

13. The array substrate according to any one of claims 1 to 10, wherein, The at least two electrically conductive layers arranged in a stack include two third metal layers and a fourth metal layer between the two third metal layers, and the fourth metal layer has a material with a higher electrical conductivity than the material of the third metal layers.

14. The array substrate of claim 13, wherein, The material of the third metal layers is selected from at least one of molybdenum, molybdenum alloy, titanium and titanium alloy, and the material of the fourth metal layer is selected from at least one of aluminum, aluminum alloy, copper and copper alloy; and / or the thickness of the fourth metal layer is greater than the thickness of the third metal layer.

15. The array substrate of claim 1, wherein, The array substrate further comprises: A black matrix is located on the side of the light-shielding layer away from the substrate, and the orthographic projection of the black matrix on the substrate overlaps with the orthographic projection of the light-shielding connecting portion on the substrate.

16. A display panel, characterized by The display device comprises the display panel of claim 16.

17. A display device comprising: The display device comprises the display panel of claim 16.

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