Silicon carbide super junction umos with high-k gate dielectric and blocking junctions

Abstract

The application discloses a silicon carbide super-junction UMOS with a high-K dielectric layer and a blocking junction, and belongs to the technical field of semiconductors. The silicon carbide super-junction UMOS comprises a drain, an N-type substrate layer, a first N-type auxiliary region, a P-type auxiliary region, a second N-type auxiliary region, an N-column region, a first P-column region, a second P-column region, an N-type current guide layer, a P-type base region, a P-type source region, an N-type source region, a high-K gate insulating dielectric layer, a thermal buffer layer, a polysilicon gate, a source and a P-type shielding layer. The high-K gate insulating dielectric layer is used to modulate the internal electric field of the UMOS, increase the reverse breakdown voltage of the device, reduce the on-resistance, and improve the static characteristics of the device. The P-type auxiliary region and the second N-type auxiliary region are used to form an auxiliary layer with the properties of a blocking junction and the characteristics of N-type variable doping, thereby enhancing the soft reverse recovery characteristics and the high breakdown voltage capability. The N-type current guide layer and the P-type base region are used to form a secondary blocking junction, thereby enhancing the reverse recovery, improving the current distribution in the N-column, and reducing the specific on-resistance.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a silicon carbide super-junction UMOS structure with a high-K dielectric layer and a blocking junction. BACKGROUND

[0002] With the increasing frequency of power device applications, the requirements for the dynamic performance of devices such as switching speed and reverse recovery characteristics of contemporary power systems are also increasing, which puts forward new requirements for the dynamic performance optimization design of devices. As a representative of new power MOSFET devices, the super-junction power MOSFET device realizes ultra-low specific on-resistance through a unique charge compensation technology, and the device efficiency is significantly improved, and the power loss of the system is greatly reduced.

[0003] The super-junction structure realizes high withstand voltage while maintaining a thin drift region by alternately arranging P / N columns in the drift region, and significantly reduces the specific on-resistance of the device, thereby breaking through the theoretical limit of traditional unipolar devices, and thus attracting widespread attention in the industry and gradually being applied to the development of SiC power devices. However, the super-junction structure needs to solve the problem of charge imbalance. Once charge imbalance occurs, the breakdown voltage may be greatly reduced. Due to the field modulation of high-K dielectric material, the influence of charge imbalance is minimized, and it has become a popular research direction.

[0004] Meanwhile, in the super-junction UMOSFET, the staggered structure of P columns and N columns can cause JFET (junction field effect transistor) effect in some cases, that is, the narrow channel formed between the P columns and the N columns restricts the flow of current. This effect usually increases the on-resistance of the device and reduces the efficiency. SUMMARY

[0005] In view of the above problems in the prior art, the application provides a silicon carbide super-junction UMOS with a high-K dielectric layer and a blocking junction, which solves the problems of charge imbalance and JFET effect of the super-junction structure.

[0006] In order to achieve the above-mentioned application purposes, the application adopts the following technical scheme: a silicon carbide super-junction UMOS with a high-K dielectric layer and a blocking junction, comprising: a drain, an N-type substrate layer, a first N-type auxiliary region, a P-type auxiliary region, a second N-type auxiliary region, an N-column region, a first P-column region, a second P-column region, an N-type current guide layer, a P-type base region, a P-type source region, an N-type source region, a high-K gate insulating dielectric layer, a thermal buffer layer, a polysilicon gate, a source, and a P-type shielding layer.

[0007] The N-type substrate layer is located above the drain, the first N-type auxiliary region is located above the N-type substrate layer, the P-type auxiliary region is located above the first N-type auxiliary region, the second N-type auxiliary region is located above the P-type auxiliary region, the N-column region is located above the second N-type auxiliary region and in the middle of the N-column region, the first P-column region is located above the second N-type auxiliary region and on both sides of the N-column region, the second P-column region is located above the first P-column region, the N-type current guide layer is located above the second P-column region, the P-type base region is located above the N-type current guide layer, the P-type source region and the N-type source region are adjacent and are both located above the P-type base region, the P-type shielding layer is located in the trench above the N-column region, the thermal buffer layer is located above the P-type shielding layer and is in contact with the N-type current guide layer, the P-type base region and the N-type source region, the high-K gate insulating medium layer is located above the thermal buffer layer, the polysilicon gate is embedded in the high-K gate insulating medium layer, and the source electrode is located above the P-type source region, the N-type source region, the high-K gate insulating medium layer and the thermal buffer layer and directly contacts;

[0008] The drain, the N-type substrate layer, the first N-type auxiliary region, the P-type auxiliary region, the second N-type auxiliary region, the N-column region, the P-type base region, the N-type source region and the source electrode form an electron flow area.

[0009] The present application has the following beneficial effects: the present application replaces the conventional gate medium insulating layer with a high-K medium, and forms a MIS metal-insulating layer-semiconductor structure with the high-K gate insulating medium layer, the thermal buffer layer, the polysilicon gate and the N-column region, modulates the internal electric field of the UMOS device with the high-K medium, increases the reverse breakdown voltage of the device, reduces the on-resistance, and improves the static characteristics of the device; at the same time, the P-type auxiliary region and the second N-type auxiliary region form an auxiliary layer with blocking junction properties and N-type variable doping characteristics, which enhances the soft reverse recovery characteristics and high breakdown voltage capability of the device; the N-column region, the first P-column region and the second P-column region form a super-junction structure, and the N-type current guide layer with high doping concentration is deposited again, which can reduce the non-uniform current flow and reduce the specific on-resistance.

[0010] Further, the doping concentrations in the first N-type auxiliary region and the second N-type auxiliary region are different and both show a continuous downward decreasing trend;

[0011] The P-type auxiliary region and the second N-type auxiliary region form an auxiliary layer and form a blocking junction.

[0012] The thickness of the P-type auxiliary region is set to 0.65-0.8 μm and is set to high doping concentration.

[0013] The beneficial effect of the further scheme is that the doping concentration in the first N-type auxiliary region and the second N-type auxiliary region is different, which can make the electric field change more gently and improve the breakdown voltage of the UMOS device; the P-type auxiliary region and the second N-type auxiliary region form an auxiliary layer, which has the properties of blocking junction and N-type variable doping, can reduce the flow of carriers, has high blocking voltage capability, and makes the UMOS device have higher breakdown voltage; the thickness of the P-type auxiliary region is set to 0.65-0.8 μm, which can reduce the JFET effect and prevent the current from being hindered.

[0014] Further, the N-column region, the first P-column region and the second P-column region form a super-junction structure.

[0015] The first P-column region and the second P-column region form a P-column region, which is used to assist the N-column region in depletion and form a potential barrier in the N-column region to isolate the high electric field generated by the current flow in the gate and the N-column region.

[0016] The doping concentration in the first P-column region and the second P-column region is different and shows a continuous downward trend from bottom to top.

[0017] The beneficial effect of the further scheme is that the N-column region, the first P-column region and the second P-column region form a super-junction structure, which can improve the voltage resistance of the UMOS device and reduce the specific on-resistance.

[0018] Further, the N-type current guide layer and the P-type base region form a secondary blocking junction.

[0019] The N-type current guide layer is set to high doping concentration to form a low resistance path.

[0020] The N-type current guide layer is located above the super-junction structure formed by the N-column region, the first P-column region and the second P-column region and below the P-type base region.

[0021] The beneficial effect of the further scheme is that the formation of the secondary blocking junction can improve the breakdown voltage of the UMOS device, and the N-type current guide layer set to high doping concentration can reduce the non-uniform current flow of the P-column and the N-column, thereby reducing the specific on-resistance.

[0022] Further, the P-type source region and the adjacent N-type source region form a body diode.

[0023] The N-type source region is set to high doping concentration.

[0024] The beneficial effect of the further scheme is that the P-type source region and the adjacent N-type source region form a body diode, which makes the gate more effectively control the electron flow in the channel region and improves the switching characteristics of the UMOS device.

[0025] Further, the high-K gate insulating medium layer, the thermal buffer layer, the polysilicon gate and the N column region form a MIS metal-insulating layer-semiconductor structure.

[0026] The high-K gate insulating medium layer sets a high dielectric constant.

[0027] The above further scheme has the beneficial effect that the high-K gate insulating medium layer, the thermal buffer layer, the polysilicon gate and the N column region form a MIS metal-insulating layer-semiconductor structure, the high-K medium is used to modulate the electric field inside the device, the reverse breakdown voltage of the UMOS device can be increased, the on-resistance can be reduced, and the static characteristics of the device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A silicon carbide super-junction UMOS structure with a high-K medium layer and a blocking junction is provided for the present application;

[0029] Figure 2 A longitudinal electric field distribution diagram of a UMOS device, a conventional SiC UMOS device and a common super-junction SiC UMOS device is provided for the present application;

[0030] Figure 3 A longitudinal current density distribution diagram of a UMOS device, a conventional SiC UMOS device and a common super-junction SiC UMOS device is provided for the present application;

[0031] Figure 4 A breakdown voltage distribution curve diagram of a UMOS device, a conventional SiC UMOS device and a common super-junction SiC UMOS device is provided for the present application;

[0032] Figure 5 An output characteristic curve diagram of a UMOS device, a conventional SiC UMOS device and a common super-junction SiC UMOS device is provided for the present application;

[0033] Figure 6 A reverse recovery characteristic curve diagram of a UMOS device, a conventional SiC UMOS device and a common super-junction SiC UMOS device is provided for the present application;

[0034] Wherein: 1-drain; 2-N-type substrate layer; 3-first N-type auxiliary region; 4-P-type auxiliary region; 5-second N-type auxiliary region; 6-N column region; 7-first P column region; 8-second P column region; 9-N-type current guide layer; 10-P-type base region; 11-P-type source region; 12-N-type source region; 13-high-K gate insulating medium layer; 14-thermal buffer layer; 15-polysilicon gate; 16-source; 17-P-type shielding layer. DETAILED DESCRIPTION

[0035] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0036] Example 1

[0037] like Figure 1 As shown, a silicon carbide superjunction UMOS structure with a high-K dielectric layer and a blocking junction includes: a drain 1, an N-type substrate layer 2, a first N-type auxiliary region 3, a P-type auxiliary region 4, a second N-type auxiliary region 5, an N-pillar region 6, a first P-pillar region 7, a second P-pillar region 8, an N-type drain layer 9, a P-type base region 10, a P-type source region 11, an N-type source region 12, a high-K gate insulating dielectric layer 13, a thermal buffer layer 14, a polysilicon gate 15, a source 16, and a P-type shielding layer 17;

[0038] The N-type substrate layer 2 is located above the drain 1, the first N-type auxiliary region 3 is located above the N-type substrate layer 2, the P-type auxiliary region 4 is located above the first N-type auxiliary region 3, the second N-type auxiliary region 5 is located above the P-type auxiliary region 4, the N-column region 6 is located in the middle above the second N-type auxiliary region 5, the first P-column region 7 is located above the second N-type auxiliary region 5 and on both sides of the N-column region 6, the second P-column region 8 is located above the first P-column region 7, the N-type drain layer 9 is located above the second P-column region 8, the P-type base region 10 is located above the N-type drain layer 9, and the P-type The source region 11 and the N-type source region 12 are both located above the P-type base region 10, the P-type shield layer 17 is located in the trench above the N-column region 6, the thermal buffer layer 14 is located above the P-type shield layer 17 and is in contact with the N-type drain layer 9, the P-type base region 10 and the N-type source region 12, the high-K gate insulating dielectric layer 13 is located above the thermal buffer layer 14, the polysilicon gate 15 is embedded in the high-K gate insulating dielectric layer 13, and the source 16 is located above the P-type source region 11, the N-type source region 12, the high-K gate insulating dielectric layer 13 and the thermal buffer layer 14, and is in direct contact with them.

[0039] In one embodiment of the present invention, the drain 1, the N-type substrate layer 2, the first N-type auxiliary region 3, the P-type auxiliary region 4, the second N-type auxiliary region 5, the N-column region 6, the P-type base region 10, the N-type source region 12 and the source 16 constitute an electron flow region for conduction.

[0040] In a UMOS (Ultra-thin Oxide MOSFET) device, the PN junction between the source and drain electrodes forms a body diode within the UMOS. The body diode has reverse recovery characteristics. When the UMOS device is in the switching state, the body diode also experiences a reverse recovery time. In high-frequency and high-performance applications, the reverse recovery process of the body diode increases switching losses and reduces the overall switching performance of the device. By introducing a P-type auxiliary region 4 and adding artificial holes in the second N-type auxiliary region 5, the UMOS device has a soft reverse recovery characteristic. The number of stored minority carriers in the body diode when switching from the forward conduction state to the reverse blocking state is reduced, the charge recombination process is accelerated, the current is smoothed, and the peak electric field caused by the current spike generated by the reverse recovery is reduced.

[0041] In one embodiment of the present invention, the doping concentrations in the first N-type auxiliary region 3 and the second N-type auxiliary region 5 are different, and both show a trend of continuously decreasing from bottom to top, so that the potential change has a trapezoidal effect, making the electric field change more gentle, increasing the breakdown voltage of the UMOS device, and improving performance. The P-type auxiliary region 4 and the second N-type auxiliary region 5 form an auxiliary layer with blocking junction properties and N-type variable doping characteristics, which is used to reduce the flow of carriers; in the forward bias state, current can pass freely. In the reverse bias state, the P-type auxiliary region 4 and the second N-type auxiliary region 5 form a depletion region with a high blocking voltage capability, so that the UMOS device has a higher breakdown voltage.

[0042] At the same time, the first N-type auxiliary region 3 and the P-type auxiliary region 4 will form a blocking PN junction, and the resulting depletion region will hinder the conduction of current and produce a JFET effect. In order to reduce the JFET effect, the P-type auxiliary region 4 needs to be very thin and highly doped. In this embodiment, the thickness of the P-type auxiliary region 4 is set to 0.65-0.8μm.

[0043] In one embodiment of the present invention, a lower doping concentration is used in the second N-type auxiliary region 5, so that the depletion region of the UMOS device can be expanded wider when reverse biased, which facilitates the dispersion of the electric field, reduces the electric field strength, and further improves the breakdown voltage of the UMOS device; and a higher doping concentration is used in the P-type auxiliary region 4, which can further reduce the forward on-resistance and improve the conduction characteristics of the UMOS device when forward biased.

[0044] In one embodiment of the present invention, the N column region 6, the first P column region 7 and the second P column region 8 form a super junction structure, which work together to improve the voltage withstand capability of the UMOS device and reduce the characteristic on-resistance;

[0045] The N-column region 6 is the main electron conduction path when the UMOS device is turned on. When the gate voltage exceeds the threshold voltage, the electrons in the N-column region 6 are enriched into a conductive channel due to the super-junction structure, allowing current to flow from the drain to the source.

[0046] The first P-column region 7 and the second P-column region 8 together form a P-column region, which does not participate in conduction in the super-junction structure and is arranged alternately with the N-column region to form a charge-neutral structure, assisting the N-column region 6 in depletion and achieving charge balance. Meanwhile, the P-column region can form a potential barrier in the N-column region 6, isolating the high electric field generated by the current flow between the gate and the N-column region 6, and helping to guide the flow of electrons when the UMOS device is turned on.

[0047] The first P-column region 7 and the second P-column region 8 are doped with different doping concentrations. By implementing layered and varied doping, the potential change presents a trapezoidal effect, avoiding the formation of a local peak electric field at the bottom of the trench, improving the breakdown voltage of the device, and improving the overall performance.

[0048] In an embodiment of the present application, the N-type current guide layer 9 and the P-type base region 10 form a secondary blocking junction, which improves the uniform distribution of current in the N-column, plays a rectifying role, and reduces the specific on-resistance; in the forward bias state, the current can pass freely, and in the reverse bias state, it has high blocking voltage capability, making the UMOS device have higher breakdown voltage.

[0049] Meanwhile, the super-junction structure formed by the interlaced P-column and N-column has a small discontinuous or unevenly doped region between the columns, allowing the current to flow non-uniformly. The N-type current guide layer 9 is provided above, and the N-type current guide layer 9 is set to a high doping concentration, which can increase the carrier concentration and form a low-resistance path, allowing the current to be more effectively distributed to the N-column region, reducing the increase in specific on-resistance caused by non-uniform current flow, and reducing the formation of local overload and hot spots, improving the on-state performance and thermal stability of the UMOS device.

[0050] It should be emphasized that the N-type current guide layer 9 should be above the P-column and the N-column, below the P-type base region 10, and between the two, so that when the device is turned on in the forward direction, the P-column region and the N-type current guide layer 9 are in the blocking state of the body diode, allowing the flow of electrons to be fixed in the N-column region.

[0051] In an embodiment of the present application, the P-type source region 11 is located above the P-type base region 10 and below the source electrode 16; the P-type source region 11 and the adjacent N-type source region 12 form a body diode, which can adjust and control the threshold voltage of the gate when the UMOS device is in the on-state, and through the structural interaction of the N-type source region 12, the gate can more effectively control the flow of electrons in the channel region, thereby improving the switching characteristics of the device.

[0052] In one embodiment of the present application, the N-type source region 12 is located above the P-type base region 10 and below the source electrode 16, the N-type source region 12 is in direct contact with the source electrode 16, and the N-type source region 12 is arranged to have a high doping concentration, which can reduce the contact resistance between the source electrode 16 metal and the SiC material; at the same time, when the device is turned on, the N-type source region 12 improves the electron injection capability, speeds up the formation of the conduction channel, further reduces the specific on-resistance, and optimizes the conduction performance of the UMOS device.

[0053] In one embodiment of the present application, the high-K gate insulating medium layer 13, the thermal buffer layer 14, the polysilicon gate 15, and the N-column region 6 form a MIS structure, i.e., a metal-insulator-semiconductor structure, the high-K gate insulating medium layer 13 has a high dielectric constant, which can modulate the electric field at the bottom of the trench, reduce the peak electric field at the bottom of the trench, and improve the breakdown voltage of the device; at the same time, when the device is turned on, the high-K gate insulating medium layer 13 can increase the charge amount on the surface of the N-column region 6, form a low-resistance path, and reduce the specific on-resistance; since the energy band gap of the high-K gate insulating medium layer 13 is very narrow, when the UMOS device is reversely blocked, the probability of carrier tunneling through the dielectric is greatly increased, which leads to an increase in the gate leakage current; at this time, a thin thermal buffer layer 14 is added between the high-K gate insulating medium layer 13 and the N-column region 6, which can reduce the thermal stress and reduce the carrier tunneling effect, and the thermal buffer layer 14 can use SiO2 as the material.

[0054] In one embodiment of the present application, the P-type shielding layer 17 is located at the bottom of the trench above the N-column region 6. The P-type shielding layer 17 can attract electrons in the trench region, increase the electron density when the channel is formed, improve the control ability of the gate, make the gate more effectively control the opening and closing of the channel, thereby reduce the threshold voltage of the device and improve the switching speed; at the same time, the P-type shielding layer 17 can optimize the electric field distribution, especially in the trench above the N-column region 6, which can effectively smooth the electric field gradient, reduce the formation of sharp peak electric field, and improve the breakdown voltage of the UMOS device.

[0055] The present application has the following advantages: the present application replaces the conventional gate medium insulating layer with a high-K medium, and forms a MIS metal-insulator-semiconductor structure with the high-K gate insulating medium layer, the thermal buffer layer, the polysilicon gate, and the N-column region, modulates the internal electric field of the UMOS device by using the high-K medium, increases the reverse breakdown voltage of the device, reduces the on-resistance, and improves the static characteristics of the device; at the same time, the P-type auxiliary region and the second N-type auxiliary region form an auxiliary layer with a blocking junction property and an N-type variable doping feature, which enhances the soft reverse recovery characteristics and high breakdown voltage capability of the device; the N-column region, the first P-column region, and the second P-column region form a super-junction structure, and a high-doping-concentration N-type drainage layer is further deposited, which can reduce the non-uniform current flow and reduce the specific on-resistance.

[0056] Embodiment 2

[0057] The present invention proposes a silicon carbide superjunction UMOS device with a high-K dielectric layer and a blocking junction, comprising: a drain 1, an N-type substrate layer 2, a first N-type auxiliary region 3, a P-type auxiliary region 4, a second N-type auxiliary region 5, an N-column region 6, a first P-column region 7, a second P-column region 8, an N-type drain layer 9, a P-type base region 10, a P-type source region 11, an N-type source region 12, a high-K gate insulating dielectric layer 13, a thermal buffer layer 14, a polysilicon gate 15, a source 16, and a P-type shielding layer 17;

[0058] In one embodiment of the present invention, various structural parameters and doping concentrations of the UMOS device are shown in Table 1.

[0059] Table 1

[0060] Structure Parameter Unit First N-type auxiliary region length 1.5 μm N-type buffer 1 region concentration 2.5 x 10 15 ]]> cm -3 ]] P-type auxiliary region length 0.8 μm P-type auxiliary region concentration 2.8 x 10 16 ]]> cm -3 ]]> Second N-type auxiliary region length 1.5 μm Second N-type auxiliary region concentration 8 x 10 14 ]] cm -3 ]] N-type drift layer length 0.65 μm N-type drift layer concentration 5 x 10 16 ]] cm -3 ]] High-K gate insulating medium layer thickness 0.1 μm

[0061] like Figure 2 The figure shows the longitudinal electric field distribution of the UMOS device provided by the present invention, the conventional SiC UMOS device and the conventional superjunction SiC UMOS device; wherein, Conv SiC UMOS is a conventional SiC UMOS device, SiC SJ UMOS is a conventional superjunction SiC UMOS device, and Hk SiC BJSJ UMOS is a UMOS device provided by the present invention. The horizontal axis is the vertical length in μm, and the vertical axis is the electric field distribution in MV·cm -1 As can be seen from the figure, conventional SiC UMOS devices have a relatively sharp electric field intensity in the drift region; conventional superjunction SiC UMOS devices exhibit a reduced electric field intensity, which alleviates the peak electric field, indicating that the superjunction structure can effectively disperse and evenly distribute the electric field, reducing electric field concentration; while the UMOS device provided by the present invention has the smoothest electric field intensity distribution. While combining the advantages of the superjunction structure, the high-K gate insulating dielectric provides better electric field regulation, further reducing the electric field spike in the drift region, and exhibiting optimal electric field distribution performance. At the same time, when the drift region thickness is the substrate position, the electric field intensity distribution of the UMOS device provided by the present invention is also the lowest of the three structures. By adding a blocking junction and a variable doping structure, the potential change can be made to have a trapezoidal effect, smoothing the electric field change and improving the withstand voltage performance of the UMOS device.

[0062] like Figure 3It is shown that the longitudinal current density distribution diagram of the UMOS device provided by the application, the conventional SiC UMOS device and the general super-junction SiC UMOS device; wherein, Conv SiC UMOS is the conventional SiC UMOS device, SiC SJ UMOS is the general super-junction SiC UMOS device, Hk SiC BJSJ UMOS is the UMOS device provided by the application, the abscissa is the vertical direction length, the unit is μm, and the ordinate is the electric field distribution, the unit is A·cm -2 It can be seen from the figure that the conventional SiC UMOS device shows a lower current density in the entire drift region; the general super-junction SiC UMOS device FET shows a higher current density, especially in the trench region, the super-junction structure improves the uniformity of the electric field distribution through the staggered P columns and N columns, allowing a higher current density to flow; and the UMOS device provided by the application shows the highest current density in the entire drift region, and also shows the highest current density in the trench region, the application combines the advantages of the super-junction structure, and also uses the high-K gate insulating medium to modulate the electric field, further increases the current density, and improves the conductivity and efficiency of the device.

[0063] It can also be seen from the figure that the current density of the UMOS structure provided by the application is the highest at the substrate position and the P-type base region of the drift region thickness, which shows that the addition of the blocking junction structure and the use of high doping concentration in the application can significantly reduce the forward on-resistance, improve the current density, and improve the on-state characteristics.

[0064] It can be seen that the high-K gate medium of the structure of the application realizes the highest current density through more effective electric field modulation and current transmission control, which shows its advantages in optimizing current transmission and increasing power handling capacity; at the same time, the auxiliary layer with the blocking junction and the N-type variable doping characteristics can reduce the forward on-resistance, improve the current density, and improve the on-state characteristics.

[0065] As Figure 4As shown, a breakdown voltage distribution curve of the UMOS device provided by the present invention, a conventional SiC UMOS device and a conventional super junction SiC UMOS device is shown; wherein, Conv SiC UMOS is a conventional SiC UMOS device, SiC SJ UMOS is a conventional super junction SiC UMOS device, and Hk SiC BJSJ UMOS is a UMOS device provided by the present invention. The abscissa is Drain Voltage, in V, and the ordinate is Drain Current, in A. As can be seen from the figure, the conventional SiC UMOS device has the lowest breakdown voltage, and the breakdown voltages of the other two structures are improved. Specifically, it can be seen that the breakdown voltage of the UMOS device provided by the present invention is improved by 23.4% compared with the conventional SiC UMOS device and by 27.8% compared with the conventional super junction SiC UMOS device.

[0066] like Figure 5 As shown in the figure, the output characteristic curves of the UMOS device provided by the present invention, the conventional SiC UMOS device and the conventional super junction SiC UMOS device are shown; wherein, Conv SiC UMOS is a conventional SiC UMOS device, SiC SJ UMOS is a conventional super junction SiC UMOS device, and Hk SiC BJSJ UMOS is a UMOS device provided by the present invention. The horizontal axis is the Drain Voltage, in V, and the vertical axis is the Drain Current, in A, V g is the gate voltage; as can be seen from the figure, the drain current increases with increasing gate voltage; for the same gate voltage, the UMOS device provided by the present invention has a maximum drain current, so the structure designed in this article can reduce the device characteristic on-resistance while maintaining a high breakdown voltage. A specific comparison shows that the UMOS device provided by the present invention is reduced by 31.1% and 14.6% compared with conventional SiC UMOS devices and ordinary superjunction SiC UMOS devices, respectively.

[0067] like Figure 6 As shown in the figure, the reverse recovery characteristic curves of the UMOS device provided by the present invention, the conventional SiC UMOS device and the conventional super junction SiC UMOS device are shown; wherein, Conv SiC UMOS is the conventional SiC UMOS device, SiC SJ UMOS is the conventional super junction SiC UMOS device, Hk SiC BJSJ UMOS is the UMOS device provided by the present invention, the horizontal axis is Time, the unit is S, and the vertical axis is Current current density, the unit is A / cm 2 As can be seen from the figure, the conventional SiC UMOS device and the ordinary super junction SiC UMOS device have different The value is larger, and the voltage fluctuation is more intense; and the UMOS device provided by the application has The value is significantly reduced, and the voltage fluctuation is obviously slowed down; the soft coefficient S of the conventional SiC UMOS device is 0.35, the soft coefficient S of the ordinary super-junction SiC UMOS device is 0.5, and the soft coefficient S of the UMOS device provided by the application is 0.74. Compared with the previous structure, the soft coefficient of the application is increased by 69% and 48%, respectively.

Claims

1. A silicon carbide superjunction UMOS with a high-K dielectric layer and a blocking junction, characterized in that: include: A drain (1), an N-type substrate layer (2), a first N-type auxiliary region (3), a P-type auxiliary region (4), a second N-type auxiliary region (5), an N-column region (6), a first P-column region (7), a second P-column region (8), an N-type drain layer (9), a P-type base region (10), a P-type source region (11), an N-type source region (12), a high-K gate insulating dielectric layer (13), a thermal buffer layer (14), a polysilicon gate (15), a source (16), and a P-type shielding layer (17); The N-type substrate layer (2) is located above the drain (1); the first N-type auxiliary region (3) is located above the N-type substrate layer (2); the P-type auxiliary region (4) is located above the first N-type auxiliary region (3); the second N-type auxiliary region (5) is located above the P-type auxiliary region (4); the N-column region (6) is located in the middle above the second N-type auxiliary region (5); the first P-column region (7) is located above the second N-type auxiliary region (5) and on both sides of the N-column region (6); the second P-column region (8) is located above the first P-column region (7); the N-type drain layer (9) is located above the second P-column region (8); the P-type base region (10) is located above the N-type drain layer (9); The P-type source region (11) and the N-type source region (12) are adjacent and both are located above the P-type base region (10); the P-type shielding layer (17) is located in a groove above the N-pillar region (6); the thermal buffer layer (14) is located above the P-type shielding layer (17) and is in contact with the N-type drain layer (9), the P-type base region (10) and the N-type source region (12); the high-K gate insulating dielectric layer (13) is located above the thermal buffer layer (14); the polysilicon gate (15) is embedded in the high-K gate insulating dielectric layer (13); and the source electrode (16) is located above the P-type source region (11), the N-type source region (12), the high-K gate insulating dielectric layer (13) and the thermal buffer layer (14), and is in direct contact with the N-type source region (11); The drain (1), N-type substrate layer (2), first N-type auxiliary region (3), P-type auxiliary region (4), second N-type auxiliary region (5), N-column region (6), P-type base region (10), N-type source region (12) and source (16) constitute an electron flow region.

2. The silicon carbide superjunction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, characterized in that: The doping concentrations in the first N-type auxiliary region (3) and the second N-type auxiliary region (5) are different, and both show a trend of continuously decreasing from bottom to top; The P-type auxiliary region (4) and the second N-type auxiliary region (5) form an auxiliary layer and form a blocking junction; The thickness of the P-type auxiliary region (4) is set to 0.65-0.8 μm, and is set to a high doping concentration.

3. The silicon carbide superjunction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, characterized in that: The N column region (6), the first P column region (7) and the second P column region (8) form a super junction structure; The first P column region (7) and the second P column region (8) form a P column region, which is used to assist the depletion of the N column region (6) and form a potential barrier in the N column region (6) to isolate the gate and the high electric field generated by the current flow in the N column region (6); The doping concentrations in the first P column region (7) and the second P column region (8) are different, and both show a trend of continuously decreasing from bottom to top.

4. The silicon carbide superjunction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, wherein: The N-type drain layer (9) and the P-type base region (10) form a secondary blocking junction; The N-type drain layer (9) is set to have a high doping concentration to form a low-resistance path; The N-type drain layer (9) is located above the super junction structure composed of the N-column region (6), the first P-column region (7) and the second P-column region (8), and below the P-type base region (10).

5. The silicon carbide superjunction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, wherein: The P-type source region (11) and the adjacent N-type source region (12) form a body diode; The N-type source region (12) is set to have a high doping concentration.

6. The silicon carbide superjunction UMOS with a high-K dielectric layer and a blocking junction according to claim 1, characterized in that: The high-K gate insulating dielectric layer (13), the thermal buffer layer (14), the polysilicon gate (15) and the N column region (6) form a MIS metal-insulating layer-semiconductor structure; The high-K gate insulating dielectric layer (13) is provided with a high dielectric constant.

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