High voltage semiconductor devices and their manufacturing methods

Abstract

This invention relates to the field of semiconductor technology, specifically to a high-voltage semiconductor device and its manufacturing method. The high-voltage semiconductor device includes: a semiconductor substrate; a channel region and a drain region formed within the semiconductor substrate, and a drain electrode, a source region, and a source electrode formed within the drain region; a gate formed on the semiconductor substrate and located above the channel region; a first isolation region formed in the drain region and located between the drain electrode and the gate; a gate electrode communicating with the gate for connecting the gate to an external control circuit; a dummy gate, one end of which is recessed into the first isolation region, and the other end of which is connected to the gate electrode, forming an independent MOS; and a work function layer formed on the surface of the dummy gate. The high-voltage semiconductor device provided by this invention can solve the problem of limited optimization of both source / drain breakdown voltage and on-resistance in existing high-voltage semiconductor devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a high-voltage semiconductor device and its manufacturing method. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOS) are the most basic devices in semiconductor manufacturing and are widely used in various integrated circuits. They are divided into NMOS transistors and PMOS transistors according to the different charge carriers and doping types during manufacturing.

[0003] In the fabrication of high-voltage semiconductor devices, a shallow trench isolation structure (STI) is added between the gate and drain to increase the length between the drain and source, thereby improving the source-drain breakdown voltage (BVD). While this configuration increases the BVD, the presence of the STI structure also increases the carrier motion trajectory, leading to a higher on-resistance R when the high-voltage semiconductor device is turned on. on This increases the risk of reduced device performance. Summary of the Invention

[0004] The purpose of this invention is to provide a high-voltage semiconductor device and its manufacturing method, which addresses the problem of limited optimization of both source-drain breakdown voltage and on-resistance in existing high-voltage semiconductor devices.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a high-voltage semiconductor device comprising:

[0007] Semiconductor substrate;

[0008] A channel region and a drain region are formed in the semiconductor substrate, and a drain electrode, a source region, and a source electrode are formed in the drain region, wherein the drain region and the source region are of a first conductivity type, and the semiconductor substrate and the channel region are of a second conductivity type.

[0009] A gate is formed on the semiconductor substrate and located above the channel region;

[0010] A first isolation region is formed in the drain region and located between the drain and the gate;

[0011] A gate electrode, connected to the gate, is used to connect the gate to an external control circuit.

[0012] A virtual gate is recessed into the first isolation region at one end and connected to the gate electrode at the other end to form an independent MOS, and the gate is connected to the virtual gate to form a closed-loop structure.

[0013] A work function layer is formed on the surface of the virtual gate.

[0014] Preferably, the virtual gate is formed by extending the material forming the gate electrode into the first isolation region and sinking into the first isolation region, and is an integral structure with the gate electrode.

[0015] Preferably, a protective layer covering the source, the gate, and the drain is formed on the surface of the semiconductor substrate, and an interlayer dielectric layer is formed on the protective layer. The gate electrode includes a main segment formed on the upper part of the interlayer dielectric layer and an extension segment penetrating the interlayer dielectric layer and the protective layer. The upper end of the extension segment is connected to the main segment, and the lower end of the extension segment is connected to a virtual gate recessed into a first isolation region. The gate electrode is electrically connected to the gate through a first conductive plug.

[0016] Preferably, the work function layer extends from the virtual gate surface to the gate electrode surface along the overall structure.

[0017] Preferably, it further includes a lightly doped region formed in the semiconductor substrate and a heavily doped region formed on top of the lightly doped region, wherein the lightly doped region and the heavily doped region are of a second conductivity type; the lightly doped region is arranged around the outside of the drain region and the source region, and the heavily doped region is connected to the outlet electrode through a second conductive plug.

[0018] Secondly, the present invention provides a method for manufacturing a high-voltage semiconductor device, comprising:

[0019] An intermediate semiconductor structure is provided, the intermediate semiconductor structure including a semiconductor substrate, in which a channel region, a drain region, a drain electrode formed in the drain region, a source region formed in the source region, and a source electrode formed in the source region are formed; a gate is formed on the surface of the channel region; the source region and the drain region are of a first conductivity type, and the semiconductor substrate and the channel region are of a second conductivity type; a first isolation region is formed in the drain region, the first isolation region being located between the drain electrode and the gate.

[0020] A protective layer covering the source, the gate, and the drain is formed on the intermediate semiconductor structure. An interlayer dielectric layer is formed on the protective layer. The interlayer dielectric layer is etched to form a first trench to accommodate the gate electrode. An electrode material is deposited in the first trench to form the gate electrode. The gate electrode is connected to the gate and is used to connect the gate to an external control circuit.

[0021] The interlayer dielectric layer is etched and extended into the first isolation region to form a receiving trench. A power function layer is formed on the trench wall. An electrode material is deposited on the power function layer to form a virtual gate. The virtual gate is connected to the gate electrode to form an independent MOS. The gate and the virtual gate are connected to form a closed-loop structure.

[0022] Preferably, the gate electrode and the virtual gate are integrally deposited, that is, firstly, a first trench for accommodating the gate electrode and a receiving trench for accommodating the virtual gate are simultaneously formed by etching. The first trench includes a main body and an extension extending into the receiving trench to communicate with each other. The main body is formed on the upper part of the interlayer dielectric layer by etching. The extension is etched through the interlayer dielectric layer and the protective layer to the first isolation region. The receiving trench is etched down into the first isolation region. Then, a work function layer is simultaneously deposited on the inner walls of the main body, the extension, and the receiving trench. Finally, electrode material is simultaneously deposited on the work function layer to form the gate electrode and the virtual gate.

[0023] Preferably, the method further includes: forming a first conductive plug in the interlayer dielectric layer and the protective layer, wherein the lower end of the first conductive plug is connected to the gate electrode and the upper end of the first conductive plug is electrically connected to the gate electrode.

[0024] Preferably, the method further includes: performing ion implantation on the outside of the drain region and the source region in the semiconductor substrate to form a lightly doped region, and forming a heavily doped region on the upper surface of the lightly doped region by ion implantation, wherein the lightly doped region and the heavily doped region are of a second conductivity type;

[0025] A second conductive plug is formed in the interlayer dielectric layer and the protective layer. The lower end of the second conductive plug is connected to the heavily doped region, and the upper end of the second conductive plug is electrically connected to the outlet electrode.

[0026] Preferably, the fabrication of the intermediate semiconductor structure includes:

[0027] Provide a semiconductor substrate;

[0028] A well region is formed on the semiconductor substrate, and the well region is of a second conductivity type;

[0029] The well region is etched to form a shallow trench, and the shallow trench is filled to obtain a first isolation region;

[0030] Ion implantation is performed into the well region to form a source region and a drain region. A channel region that has not been implanted with ions is retained between the source region and the drain region. The source region and the drain region are of a first conductivity type, and the channel region is of a second conductivity type.

[0031] A gate electrode is formed in the channel region, a source electrode is formed in the source region, and a drain electrode is formed in the drain region.

[0032] The unexpected beneficial effects of this invention are as follows:

[0033] The high-voltage semiconductor device of this invention features a unique virtual gate structure. One end of the virtual gate is recessed into the first isolation region, while the other end is connected to the gate electrode, forming an independent MOS, i.e., a MOS independent of the gate (i.e., the main gate). Simultaneously, a work function layer is disposed on the outer surface of the virtual gate, ensuring that the gate (i.e., the main gate) and the virtual gate can operate synchronously under the same voltage conditions. This simultaneous placement of the virtual gate and the work function layer allows the virtual gate, connected to the gate, to rapidly draw electrons from the drain region below the drain electrode to the interface between the first isolation region and the drain region when a turn-on voltage is applied. This shortens the electron trajectory, reduces the electron transport time in the drain region, and thus lowers the on-resistance of the device. Furthermore, the presence of the first isolation region enhances the source-drain breakdown voltage.

[0034] Based on the unique structure of the high-voltage semiconductor device of this invention, it can be fabricated with both NMOS and PMOS metal work function layers through a simple process flow. Furthermore, the main gate structure is connected to the metal virtual gate sunk into the STI, without adding additional photomasks for the NMOS and PMOS metal work function layers. Moreover, the manufacturing process can be achieved entirely based on existing conditions, saving process costs.

[0035] In summary, the high-voltage semiconductor device provided by this invention can solve the problem of limited optimization of source-drain breakdown voltage and on-resistance in existing high-voltage semiconductor devices. Attached Figure Description

[0036] Figure 1 A schematic diagram of the high-voltage semiconductor device described in this invention is shown.

[0037] Figure 2 A schematic diagram illustrating the working principle of the high-voltage semiconductor device described in this invention is shown.

[0038] Figure 3 A schematic diagram of the etching trap region forming shallow trenches according to the present invention is shown.

[0039] Figure 4 A schematic diagram of the isolation zone formed according to the present invention is shown.

[0040] Figure 5 A schematic diagram of the source and drain regions formed according to the present invention is shown.

[0041] Figure 6 A schematic diagram of the gate formed according to the present invention is shown.

[0042] Figure 7 A schematic diagram of the source and drain electrodes after the present invention is formed is shown.

[0043] Figure 8 A schematic diagram illustrating the etching process of the present invention to form conductive plug channels is shown.

[0044] Figure 9 A schematic diagram of the conductive plug formed according to the present invention is shown.

[0045] Figure 10 A schematic diagram of the etching groove formed by the present invention is shown.

[0046] Figure 11 A schematic diagram of the groove formed according to the present invention is shown.

[0047] Figure 12 A schematic diagram of the etching process for forming the receiving groove according to the present invention is shown.

[0048] Figure 13 A schematic diagram of the receiving groove formed according to the present invention is shown.

[0049] Figure 14 A schematic diagram of the electrode after the present invention has been formed is shown.

[0050] In the figure, 1—semiconductor substrate, 2—channel region, 3—drain region, 4—drain electrode, 5—gate, 6—first isolation region, 61—receiving trench, 7—gate electrode, 71—body segment, 72—extension segment, 8—virtual gate, 9—work function layer, 10—interlayer dielectric layer, 11—first conductive plug, 12—first trench, 121—body portion, 122—extension portion, 13—source region, 14—source electrode, 15—shallow trench, 16—protective layer, 17—well region, 18—first sacrificial layer, 19—second sacrificial layer, 20—photoresist layer, 21—gate dielectric layer, 22—sidewall structure, 221— 222—First silicon oxide layer, 223—Second silicon oxide layer, 224—Second silicon nitride layer, 23—Self-aligned metal silicide, 24—Drain electrode, 25—Source electrode, 26—Third sacrificial layer, 27—Conductive plug channel, 28—First barrier layer, 29—Second barrier layer, 30—Fourth sacrificial layer, 31—Fifth sacrificial layer, 32—Lightly doped region, 33—Heavily doped region, 34—Outlet electrode, 35—Second conductive plug, 36—Third conductive plug, 37—Fourth conductive plug, 38—Second isolation region, 39—Second tank, 40—Third tank. Detailed Implementation

[0051] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0052] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] In this invention, it should be noted that terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, terms such as "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0054] In one embodiment, please refer to Figure 1 As shown, a high-voltage semiconductor device is provided, comprising:

[0055] Semiconductor substrate 1 serves as the carrier substrate for high-voltage semiconductor devices;

[0056] A channel region 2 and a drain region 3 are formed in the semiconductor substrate 1, and a drain electrode 4, a source region 13, and a source electrode 14 are formed in the drain region 3. The drain region 3 and the source region 13 are of a first conductivity type, and the semiconductor substrate 1 and the channel region 2 are of a second conductivity type.

[0057] Gate 5 is formed on the semiconductor substrate 1 and located above the channel region 2;

[0058] The first isolation region 6 is formed in the drain region 3 and is located between the drain electrode 4 and the gate electrode 5;

[0059] Gate electrode 7 is connected to the gate 5 and is used to connect the gate 5 to an external control circuit.

[0060] The virtual gate 8 is recessed into the first isolation region 6 at one end and connected to the gate electrode 7 at the other end to form an independent MOS, and the gate 5 is connected to the virtual gate 8 to form a closed-loop structure.

[0061] The work function layer 9 is formed on the surface of the virtual gate 8.

[0062] Since one end of the virtual gate 8 is recessed into the first isolation region 6, and the other end is connected to the gate electrode 7, forming an independent MOS, it actually uses the insulating material of the first isolation region 6 below the virtual gate 8 as a dielectric layer, and the drain region 3 below this dielectric layer as a channel region, thus forming an independent MOS. Simultaneously, this invention incorporates a work function layer 9 on the outer surface of the virtual gate 8, ensuring that the gate 5 and the virtual gate 8 can operate synchronously under the same voltage conditions. See also Figure 2 As shown, due to the coordinated arrangement of the virtual gate 8 and the work function layer 9, when an on-state voltage is applied to the gate 5, the virtual gate 8, connected to the gate 5, can simultaneously and rapidly draw electrons from the drain region 3 below the drain 4 to the interface between the first isolation region 6 and the drain region 3, thus shortening the electron trajectory and reducing the electron transport time in the drain region 3, thereby reducing the on-resistance of the device. Furthermore, the presence of the first isolation region 6 between the drain 4 and the gate 5 enhances the source-drain breakdown voltage. Therefore, the high-voltage semiconductor device provided by this invention can solve the problem of limited optimization of both source-drain breakdown voltage and on-resistance in existing high-voltage semiconductor devices.

[0063] It should be noted that the connection between the gate 5 and the virtual gate 8 to form a closed-loop structure refers to: See [link to relevant documentation]. Figure 1 As shown, when a turn-on voltage is applied to the gate 5, the channel region 2 in the semiconductor substrate 1 at the lower end of the gate 5 is turned on, and the channel region 2 is turned on and the drain region 3 below the virtual gate 8 is turned on. The upper end of the gate 5 and the upper end of the virtual gate 8 are connected through the gate electrode 7, thereby forming a closed-loop structure.

[0064] In one embodiment, the semiconductor substrate 1 is a single-crystal silicon doped with impurities, and the type of impurities in the semiconductor substrate 1 can be set according to the type of semiconductor device. By doping the semiconductor substrate 1, the resistance of the semiconductor substrate 1 is reduced, and latch-up effect is prevented. Specifically, boron (B) or gallium (Ga) can be doped into the semiconductor substrate 1 to form a P-type doped substrate, or phosphorus (P) or arsenic (As) can be doped into the semiconductor substrate 1 to form an N-type doped substrate. N-type semiconductor devices can choose to use a P-type semiconductor substrate, while P-type semiconductor devices can choose to use an N-type semiconductor substrate. In other embodiments, depending on the semiconductor device, the semiconductor substrate 1 can be selected from semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, or other III / V compounds, and also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator.

[0065] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type. That is, the high-voltage semiconductor device described in this embodiment is an N-type semiconductor device, and the semiconductor substrate 1 uses a P-type semiconductor substrate.

[0066] As a preferred embodiment, see [link to preferred embodiment]. Figure 1 As shown, the virtual gate 8 is formed by the material forming the gate electrode 7 extending into and sinking into the first isolation region 6. That is, the virtual gate 8 is connected to the gate 5 through the gate electrode 7, forming a closed-loop structure with series conduction. This closed-loop structure not only regulates the device R on and I DS This design also prevents electron loss and reduces voltage division. Firstly, the closed-loop structure connects the gate 5 and the virtual gate 8 of the semiconductor device together. Combined with the work function layer 9, this ensures that the devices controlled by the gate 5 and the virtual gate 8 operate synchronously without delay. When a startup voltage is applied to the gate 5, the virtual gate 8 attracts a large number of electrons to the bottom region of the first isolation region 6 between the drain 4 and the gate 5. This effectively shortens the conduction channel of the gate 5, i.e., the main gate device, making it easier for the high-voltage device to turn on, effectively lowering the threshold voltage V. th The saturation current I of the device DS and threshold voltage V th They are inversely proportional, therefore when the threshold voltage V th When the current decreases, the saturation current I DS It will increase. Synchronously, the on-resistance R of the device... on =V drain / I DS V drainThe drain voltage is the voltage at which the device's saturation current I... DS When increasing, according to the physical formula R on This will decrease accordingly. Therefore, this structure and design not only ensures a high breakdown voltage of the device, but also increases the saturation current and reduces the on-resistance, achieving a win-win effect.

[0067] As a preferred embodiment, see [link to preferred embodiment]. Figure 2 As shown, a protective layer 16 covering the source 14, gate 5, and drain 4 is formed on the surface of the semiconductor substrate 1, and an interlayer dielectric layer 10 is formed on the protective layer 16. The gate electrode 7 includes a main segment 71 formed on the upper part of the interlayer dielectric layer 10 and an extension segment 72 penetrating the interlayer dielectric layer 10 and the protective layer 16. The upper end of the extension segment 72 is connected to the main segment 71, and the lower end of the extension segment 72 is connected to the virtual gate 8 recessed into the first isolation region 6. The gate electrode 7 is electrically connected to the gate 5 through a first conductive plug 11.

[0068] The main function of the interlayer dielectric layer 10 is to provide isolation, allowing different circuit components (such as gate 5, source 14, drain 4, etc.) to operate independently on the semiconductor substrate 1 without interfering with each other. The interlayer dielectric layer 10 is typically made of insulating materials, such as silicon dioxide (SiO2) or other dielectric materials.

[0069] In one embodiment, see Figure 2 As shown, the first conductive plug 11 is a vertical conductive channel used to establish electrical connections between different layers of the device. Here, the first conductive plug 11 passes through the interlayer dielectric layer 10 and the protective layer 16 to connect the body segment 71 of the gate electrode 7 to the gate 5, ensuring the electrical connection between the two.

[0070] As a preferred embodiment, see [link to preferred embodiment]. Figure 1 As shown, the work function layer 9 extends from the surface of the virtual gate 8 along the overall structure to the surface of the gate electrode 7, that is, the work function layer 9 extends along the overall structure to the surface of the gate electrode 7 in contact with the surrounding material, and is used to adjust the work function of the gate electrode 7, thereby ensuring that the gate 5 and the virtual gate 8 can work synchronously under the same voltage conditions.

[0071] As a preferred embodiment, see [link to preferred embodiment]. Figure 14 As shown, the high-voltage semiconductor device further includes a lightly doped region 32 formed in the semiconductor substrate 1 and a heavily doped region 33 formed on the upper part of the lightly doped region 32. The lightly doped region 32 and the heavily doped region 33 are of a second conductivity type. The lightly doped region 32 is arranged around the outside of the drain region 3 and the source region 13, and the heavily doped region 33 is connected to the outlet electrode 34 through a second conductive plug 35.

[0072] As a preferred embodiment, see [link to preferred embodiment]. Figure 1 As shown, the first isolation region 6 is a shallow trench isolation structure. Its formation process is as follows: a shallow trench 15 is formed using silicon etching technology, and then an insulating material, such as oxide, is filled into the shallow trench 15 to achieve isolation. By forming the first isolation region 6 between the drain 4 and the gate 5, the length between the drain 4 and the source 14 is increased, thereby improving the source-drain breakdown voltage (BVD) of the high-voltage semiconductor device, and thus improving the overall performance and reliability of the high-voltage semiconductor device.

[0073] In a preferred embodiment, the work function layer 9 is made of at least one of TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TiBN, TaN, TaSiN, and TiSiN. The gate electrode 7 and the dummy gate 8 are made of at least one of Cu, W, Co, Al, Ag, Au, Pt, and Ni.

[0074] For example, the work function layer 9 is made of TiAlN, and the gate electrode 7 and the virtual gate 8 are both made of Cu.

[0075] In another embodiment, a method for manufacturing a high-voltage semiconductor device is provided, comprising:

[0076] An intermediate semiconductor structure is provided, the intermediate semiconductor structure including a semiconductor substrate 1, in which a channel region 2, a drain region 3, a drain electrode 4, a source region 13, and a source electrode 14 are formed in the drain region 3. A gate electrode 5 is formed on the surface of the channel region 2; a first isolation region 6 is formed in the drain region 3, the first isolation region 6 being located between the drain electrode 4 and the gate electrode 5; the source region 13 and the drain region 3 are of a first conductivity type, and the semiconductor substrate 1 and the channel region 2 are of a second conductivity type.

[0077] A protective layer 16 is formed on the intermediate semiconductor structure, covering the source 14, the gate 5 and the drain 4. An interlayer dielectric layer 10 is formed on the protective layer 16. The interlayer dielectric layer 10 is etched to a set depth to form a first trench 12 to accommodate the gate electrode 7. An electrode material is deposited in the first trench 12 to form the gate electrode 7. The gate electrode 7 is connected to the gate 5 and is used to connect the gate 5 to an external control circuit.

[0078] The interlayer dielectric layer 10 is etched and extends to a set depth within the first isolation region 6 to form a receiving trench 61. A power function layer 9 is formed on the trench wall of the receiving trench 61. Electrode material is deposited on the power function layer 9 to form a virtual gate 8, and the virtual gate 8 is connected to the gate electrode 7 to form an independent MOS. The gate 5 is connected to the virtual gate 8 to form a closed-loop structure.

[0079] Specific manufacturing examples are as follows:

[0080] Manufacturing intermediate semiconductor structures includes:

[0081] Please see Figure 3 As shown, a semiconductor substrate 1 is provided. In this embodiment, the semiconductor substrate 1 is a doped silicon wafer, and the doping type is P-type.

[0082] Please see Figure 3 As shown, a well region 17 is formed on the semiconductor substrate 1, and the well region 17 is of the second conductivity type, namely P-type.

[0083] Please see Figure 3 As shown, the well region 17 is etched to form a shallow trench 15. Please refer to [link / reference]. Figure 4 As shown, an insulating material, such as silicon oxide, is filled into the shallow trench 15 to form a first isolation region 6. A first sacrificial layer 18 is grown on the surface of the well region 17. In this embodiment, the semiconductor substrate 1 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced into the furnace tube. The upper surface of the well region 17 reacts with the oxygen at a high temperature to form a dense first sacrificial layer 18. After the formation of the first sacrificial layer 18, a second sacrificial layer 19 is formed on the upper surface of the first sacrificial layer 18. The second sacrificial layer 19 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. In this embodiment, the second sacrificial layer 19 is, for example, silicon nitride. The first sacrificial layer 18, acting as a buffer layer, can improve the stress between the base well region 17 and the second sacrificial layer 19. In this invention, for example, the second sacrificial layer 19 can be formed on the first sacrificial layer 18 by methods such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0084] A photoresist layer 20 is formed on the second sacrificial layer 19. Multiple openings are formed on the photoresist layer 20 through processes such as exposure and development. These openings are used to locate the shallow trench isolation structure. Using the photoresist layer 20 as a mask, the second sacrificial layer 19 located beneath the photoresist layer 20 is quantitatively removed using etching methods such as dry etching, wet etching, or a combination of both. Then, using the second sacrificial layer 19 as a mask, the first sacrificial layer 18 and part of the semiconductor substrate 1 are removed in situ, resulting in a shallow trench 15 with a depth D1 of 330 nm. The shallow trench 15 has an inverted trapezoidal cross-section. In this embodiment, for example, dry etching is used to form the shallow trench 15, and the etching gas is, for example, one or a combination of several of chlorine, difluoromethane, trifluoromethane, nitrogen trifluoride, sulfur hexafluoride, or hydrogen bromide, or a mixture of these and oxygen. After etching, the photoresist layer 20 is removed, for example, by oxygen plasma removal or wet removal.

[0085] Please see Figure 4 As shown, after the shallow trench 15 is formed, an insulating material is deposited within the shallow trench 15, for example, by high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio process chemical vapor deposition (HARP-CVD), and the insulating material is, for example, silicon oxide. After the insulating material deposition is completed, a planarization process, for example, chemical mechanical polishing (CMP) is used to align the tops of the insulating material and the second sacrificial layer 19 to the same plane, forming multiple shallow trench isolation structures, namely the first isolation region 6 and the second isolation region 38.

[0086] After forming the shallow trench isolation structure, the second sacrificial layer 19 is removed. For example, the second sacrificial layer 19 is removed by a wet etching process using hot phosphoric acid as the etching solution. By setting multiple shallow trench isolation structures, wherein the second isolation region 38 is arranged between adjacent semiconductor devices to isolate different semiconductor devices and reduce mutual interference between them. A first isolation region 6 is also formed in the drain region 3 between the gate 5 and the drain 4, increasing the length between the drain 4 and the source 14, thereby improving the source-drain breakdown voltage (BVD) of the high-voltage semiconductor device.

[0087] In one embodiment, the first isolation region 6 and the second isolation region 38 are made of the same material as the first sacrificial layer 15, which is silicon oxide.

[0088] Before depositing the insulating material, a lining oxide layer is formed on the inner wall of the shallow trench 15. This lining oxide layer provides additional isolation, ensuring good electrical isolation between the filling insulating material (typically silicon oxide or other dielectric) in the shallow trench 15 and the surrounding silicon substrate. Furthermore, the lining oxide layer improves the interface quality between the sidewalls of the shallow trench 15 and the insulating material, thereby enhancing the overall structural reliability. Simultaneously, the lining oxide layer reduces stress caused by the mismatch in thermal expansion coefficients between the filling insulating material of the shallow trench 15 and the silicon substrate.

[0089] Please see Figure 5 As shown, after the first isolation region 6 is formed, ion implantation is performed into the well region 17 to form the source region 13 and the drain region 3, respectively. A channel region 2, which has not undergone ion implantation, is retained between the source region 13 and the drain region 3. The source region 13 and the drain region 3 are of the first conductivity type, i.e., N-type, while the channel region 2 remains of the second conductivity type, i.e., P-type. Specifically, after forming the shallow trench isolation structure, i.e., the first isolation region 6 and the second isolation region 38, a photoresist layer 20 is coated onto the upper surface of the first sacrificial layer 18 of the semiconductor substrate 1. Through processes such as exposure and development, openings are formed in the photoresist layer 20, and the positions of the source region 13 and the drain region 3 are located using these openings. Then, using the photoresist layer 20 as a mask, ion implantation is performed, with the implanted ion type being the opposite of the ion type in the well region 17. In this embodiment, the doped ions in the source region 13 and the drain region 3 are N-type impurities such as phosphorus (P) or arsenic (As).

[0090] Please see Figure 6 As shown, after the source region 13 and drain region 3 are formed, the photoresist layer 20 is removed, and a gate 5 is formed on the channel region 2. A gate dielectric layer 21 is disposed between the gate 5 and the well region 17. The gate dielectric layer 21 is, for example, silicon dioxide, a high dielectric constant dielectric layer, a low dielectric constant dielectric layer, or a combination of multiple dielectric layers. The gate 5 is, for example, a polysilicon gate or a metal gate. In this embodiment, the gate dielectric layer 21 is a first sacrificial layer 18 located below the gate 5. That is, the gate dielectric layer 21 is formed by etching away part of the first sacrificial layer 18, so that the upper surfaces of part of the drain region 3, the source region 13, the first isolation region 6, and the second isolation region 38 are flush with the upper surface of the semiconductor device 1. The remaining first sacrificial layer 18 is used as the gate dielectric layer 21, and a gate and a sidewall structure 22 located on the side of the gate 5 are formed on the gate dielectric layer 21.

[0091] A sidewall structure 22 is provided on the side of the gate 5 structure, and the sidewall structure 22 is, for example, a silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride. In this embodiment, the sidewall structure 22 is, for example, a stacked structure of silicon oxide and silicon nitride. Specifically, the stacked structure includes a first silicon oxide layer 221, a first silicon nitride layer 222, a second silicon oxide layer 223, and a second silicon nitride layer 224 arranged sequentially from the inside to the outside.

[0092] Please see Figure 7 As shown, after the gate 5 is formed, a source 14 is formed on the source region 13, and a drain 4 is formed on the drain region 3. Specifically, the source 14 and drain 4 are formed using an ion implantation process, and the surfaces of the source region 13 and drain region 3 are heavily doped to obtain heavily doped regions. The heavy doping types of the source region 13 and drain region 3 are the same, with doping ions being N-type impurities such as phosphorus (P) or arsenic (As). The edge of the heavily doped region at the location of the source region 13 is aligned with the edge of the sidewall structure 22 away from the gate 5. The heavily doped region at the location of the source region 13 serves as the source 14 of the high-voltage semiconductor device, and the heavily doped region at the location of the drain region 3 serves as the drain 4 of the high-voltage semiconductor device.

[0093] Please see Figure 7 As shown, after the source 14 and drain 4 are formed, a self-aligned metal silicide 23 is formed on the source 14, drain 4, and gate 5 of the semiconductor device. The self-aligned metal silicide 23 is, for example, a low-resistance nickel silicide (NiSi), cobalt silicide (CoSi2), or titanium silicide (TiSi2). By forming the self-aligned metal silicide 23, the contact resistance between the subsequently formed metal connection structure and the semiconductor device is reduced, improving the performance of the semiconductor device. Simultaneously, it prevents the source 14 or drain 4 from being broken down or leaking current, thereby improving the stability of the semiconductor device. Furthermore, the self-aligned metal silicide 23 can also serve as a contact structure for the semiconductor device, leading out the source 14, drain 4, and gate 5.

[0094] Please see Figure 8 As shown, after the formation of the self-aligned metal silicide 23, a protective layer 16 is formed on the semiconductor substrate 1. This protective layer 16 covers the source 14, drain 4, gate 5, and sidewall structure 22, and is, for example, a silicon nitride layer. Exemplarily, the protective layer 16 is prepared by a low-temperature deposition method such as plasma-enhanced chemical vapor deposition (PECVD), and the deposition source includes a nitrogen source and a silicon source. The nitrogen source is selected from one or a combination of nitrogen (N2) or ammonia (NH3), and the silicon source is selected from one or a combination of silane (SiH4), silane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), tetrachlorosilane (SiCl4), or hexachlorosilane (Si2Cl6).

[0095] Please see Figure 8As shown, after the protective layer 16 is formed, an interlayer dielectric layer 10 is formed on the protective layer 16. The interlayer dielectric layer 10 is prepared, for example, using silicon dioxide or a low-k dielectric material to improve the reliability of the semiconductor structure. Furthermore, the interlayer dielectric layer 10 is deposited, for example, using a high aspect ratio process to improve its filling capability. Specifically, a silicon-containing precursor and an oxygen-containing precursor are used for deposition within a temperature range of 400°C to 500°C and a pressure of 30 torr to 760 torr. The silicon-containing precursor includes, for example, one of silane or tetraethyl orthosilicate (TEOS), and the oxygen-containing precursor includes, for example, one of O2 or O3. In this embodiment, the silicon-containing precursor is, for example, TEOS, and the oxygen-containing precursor is, for example, O3. The interlayer dielectric layer 10 is deposited at a temperature of 430°C and a pressure of 500 torr for a deposition time of 100s to 150s. After the interlayer dielectric layer 10 is formed, a planarization process is performed on the interlayer dielectric layer 10, such as by chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 10, so as to ensure that the upper surface of the interlayer dielectric layer 10 is flat and improve the convenience of metal connection structure.

[0096] Please see Figure 8 As shown, after the interlayer dielectric layer 10 is formed, a third sacrificial layer 26 is formed on the interlayer dielectric layer 10, and a photoresist layer 20 is formed on the third sacrificial layer 26. Through processes such as exposure and development, three openings are formed on the photoresist layer 20. These three openings are used to locate the positions of the first conductive plug 11, the third conductive plug 36, and the fourth conductive plug 37, respectively. Using the photoresist layer 20 as a mask, the third sacrificial layer 26, the protective layer 16, and part of the self-aligned metal silicide 23 located under the photoresist layer 20 are quantitatively removed using etching methods such as dry etching, wet etching, or a combination of dry and wet etching, forming three conductive plug channels 27 for depositing the first conductive plug 11, the third conductive plug 36, and the fourth conductive plug 37.

[0097] Please see Figure 9As shown, after the conductive plug channels 27 are formed, a first barrier layer 28 is deposited on the inner walls of the three conductive plug channels 27 to contact the self-aligned silicide 23 on the source 14, drain 4, and gate 5. Examples of materials for the first barrier layer 28 include, but are not limited to, Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. Exemplarily, the deposition process is physical vapor deposition (PVD), electrochemical electroplating (ECP), or chemical vapor deposition (CVD). Finally, a first conductive plug 11, a third conductive plug 36, and a fourth conductive plug 37 are deposited within the first barrier layer 28. Exemplarily, the materials for the first conductive plug 11, the third conductive plug 36, and the fourth conductive plug 37 are copper (Cu) or tungsten (W). In this embodiment, metallic tungsten is selected as the deposition material for the first conductive plug 11, the third conductive plug 36, and the fourth conductive plug 37. After removing the photoresist layer 20 and the third sacrificial layer 26, a planarization process is performed on the first conductive plug 11, the third conductive plug 36 and the fourth conductive plug 37 to ensure that the upper surfaces of the first conductive plug 11, the third conductive plug 36 and the fourth conductive plug 37 are on the same plane as the upper surface of the interlayer dielectric layer 10, thus obtaining the intermediate semiconductor structure.

[0098] After obtaining the intermediate semiconductor structure, the gate electrode 7 and the dummy gate 8 are integrally deposited and formed. Specifically, a first trench 12 for accommodating the gate electrode 7 and a receiving trench 61 for accommodating the dummy gate 8 are simultaneously formed by etching. The first trench 12 includes a main body 121 and an extension 122 extending into and communicating with the receiving trench 61. The main body 121 is formed on the upper part of the interlayer dielectric layer 10 by etching. The extension 122 is etched through the interlayer dielectric layer 10 and the protective layer 16 to the first isolation region 6. The receiving trench 61 is etched down into the first isolation region 6. Then, a work function layer 9 is simultaneously deposited on the inner walls of the main body 121, the extension 122, and the receiving trench 61. Electrode material is then simultaneously deposited on the work function layer 9 to form the gate electrode 7 and the dummy gate 8.

[0099] Specifically, please refer to Figure 10As shown, after the first conductive plug 11, the third conductive plug 36, and the fourth conductive plug 37 are formed, a fourth sacrificial layer 30 is formed on the upper surface of the interlayer dielectric layer 10. Exemplarily, the fourth sacrificial layer 30 comprises silicon carbon nitride (SiCN), silicon carbon oxygen (SiCO), tetraethoxysilane (TEOS), titanium nitride (TiN), silicon oxynitride (SiON), oxide (OX), and an anti-reflective coating (BARC) deposited sequentially from bottom to top. A photoresist layer 20 is coated on the upper surface of the fourth sacrificial layer 30. Through processes such as exposure and development, openings perpendicular to the source 14, drain 4, and gate 5 are formed on the photoresist layer 20, with the openings positioning the first trench 12, the second trench 39, and the third trench 40.

[0100] Please see Figure 11 As shown, using the photoresist layer 20 as a mask, a portion of the fourth sacrificial layer 30 located under the photoresist layer 20 is quantitatively removed by etching methods such as dry etching, wet etching, or a combination of dry etching and wet etching, to form the main body 121 of the first trench 12 corresponding to the gate 5, the second trench 39 corresponding to the source 14, and the third trench 40 corresponding to the drain 4.

[0101] Please see Figure 12 As shown, after forming the first trench 12, the second trench 39, and the third trench 40, a fifth sacrificial layer 31 is formed on the product surface. The fifth sacrificial layer 31 includes an ODL layer and an SHB layer coated from bottom to top. The ODL layer is a high-carbon-content polymer organic structure layer, mainly serving a planarization function; the SHB layer is a silicon-oxygen hard mask intermediate layer structure, mainly serving an anti-reflection function. Then, a photoresist layer 20 is coated on the upper surface of the fifth sacrificial layer 31. Through processes such as exposure and development, an opening perpendicular to the first isolation region 6 between the gate 5 and the drain 4 is formed on the photoresist layer 20, with the opening positioning the extension 122 of the first trench 12.

[0102] Please see Figure 13 As shown, using photoresist layer 20 as a mask, the fifth sacrificial layer 31 located under photoresist layer 20 is quantitatively removed using etching methods such as dry etching, wet etching, or a combination of dry and wet etching. Then, using the fifth sacrificial layer 31 as a mask, the fourth sacrificial layer 30 and part of the interlayer dielectric layer 10 are removed in situ, forming a receiving trench 61 in the first isolation region 6 between drain 4 and gate 5, and a first trench 12, a second trench 39, and a third trench 40 that are respectively connected to the first conductive plug 11, the third conductive plug 36, and the fourth conductive plug 37. The cross-sections of the second trench 39 corresponding to the source 14 and the third trench 40 corresponding to the drain 4 are both U-shaped, and the cross-section of the first trench 12 corresponding to the gate 5 is an inverted L-shaped.

[0103] The first tank 12 includes a horizontally arranged main body 121 and an extension 122 connected to the lower right side of the main body 121. The extension 122 extends vertically, and its lower end communicates with the upper opening of the receiving tank 61. That is, the receiving tank 61 and the tank 12 corresponding to the gate 5 are integrally formed into an inverted L-shaped deposition tank. In this embodiment, the extension 122 is a through hole, the upper end of which communicates with the right end of the main body 121, and the lower end of which communicates with the upper opening of the receiving tank 61. A preset distance is maintained between the inner wall of the receiving tank 61 and the inner wall of the shallow trench 15, and the two do not directly contact each other. For example, see [link to relevant documentation]. Figure 13 As shown, the distance D2 between the bottom of the receiving groove 61 and the bottom of the shallow groove 15 is 3nm.

[0104] Please see Figure 2 As shown, after the extension of the first trench 12 and the receiving trench 61 are formed, a work function layer 9 is simultaneously deposited in the first trench 12, the second trench 39, and the third trench 40 corresponding to the positions of the gate 5, the source 14, and the drain 4, and in the receiving trench 61 located within the first isolation region 6. Exemplarily, the material of the work function layer 9 is TiAlN, and its formation process includes: sequentially depositing a 1nm thick titanium nitride layer and a 4.8nm thick titanium chloride layer on the inner wall of the trench 12 or the receiving trench 61; after deposition, performing diffusion annealing; the annealing temperature is set to 400℃, and the annealing time is set to 20~40s, allowing aluminum in the titanium chloride layer to diffuse into the titanium nitride layer to form TiAlN, i.e., the work function layer 9. Because the work function layer 9 is formed by simultaneous deposition, no additional photomasks for NMOS and PMOS metal work function layers are added, and the manufacturing process can be achieved entirely based on existing conditions, saving process costs.

[0105] Please see Figure 2 As shown, after the work function layer 9 is formed, a second barrier layer 29 is deposited on the inner wall of the work function layer 9. The second barrier layer 29 includes a TaN layer with a thickness of 6 nm and a Ta layer with a thickness of 5 nm. Finally, copper is deposited simultaneously on the inner wall of the second barrier layer 29 to form a source electrode 25 electrically connected to the source electrode 14 through a third conductive plug 36, a drain electrode 24 electrically connected to the drain electrode 4 through a fourth conductive plug 37, and a gate electrode 7 electrically connected to the gate electrode 5 through a first conductive plug 11. The copper layer deposition thickness in the main body 121 of the first trench 12, the second trench 39, and the third trench 40 is 12.5 nm.

[0106] The gate electrode 7 is inverted "L" shape, including a main segment 71 formed in the main body portion 121 of the first trench 1 on the upper part of the interlayer dielectric layer 10, and an extension segment 72 that penetrates the interlayer dielectric layer 10 and the protective layer 16 and is formed in the extension portion 122 of the first trench 1. The upper end of the extension segment 72 is connected to the main body segment 71, and the lower end of the extension segment 72 is connected to the virtual gate 8 that is sunk into the first isolation region 6.

[0107] In this design, the source electrode 25 is electrically connected to the self-aligned silicide 23 on the lower source electrode 14 via a third conductive plug 36, and the drain electrode 24 is electrically connected to the self-aligned silicide 23 on the lower drain electrode 4 via a fourth conductive plug 37. The left end of the main body segment 71 of the gate electrode 7 is electrically connected to the self-aligned silicide 23 on the lower gate electrode 5 via a first conductive plug 11. When the gate electrode 7 is under operating voltage conditions, the presence of the special work function layer 9 ensures that the gate electrode 5 and the virtual gate 8 can work synchronously under the same voltage conditions. This rapidly draws electrons from the drain region 3 below the drain electrode 4 to the interface between the first isolation region 6 and the drain region 3, concentrating them and shortening the electron trajectory. This reduces the electron transmission time in the drain region 3, thereby lowering the on-resistance of the device. Furthermore, the presence of the first isolation region 6 increases the source-drain breakdown voltage. In summary, the high-voltage semiconductor device provided by this invention can solve the problem of limited optimization of both source-drain breakdown voltage and on-resistance in existing high-voltage semiconductor devices.

[0108] In one embodiment, please refer to Figure 14 As shown, a lightly doped P-type region 32 is formed around the outer periphery of the active region (source region 13) and the drain region 3 by ion implantation. Then, a heavily doped P-type region 33 is formed on the surface of the lightly doped P-type region 32 by ion implantation. A self-aligned metal silicide 23 is formed on the upper surface of the heavily doped P-type region 33. A contact electrode 34 is deposited on the upper part of the interlayer dielectric layer 10. This contact electrode 34 is connected to the self-aligned metal silicide 23 on the upper surface of the heavily doped P-type region 33 via a second conductive plug 35 formed in the interlayer dielectric layer 10 and the protective layer 16, facilitating grounding of the semiconductor substrate 1.

[0109] This invention offers the following unexpected technical advantages: The high-voltage semiconductor device of this invention features a unique virtual gate structure. One end of the virtual gate 8 is recessed into the first isolation region 6, while the other end is connected to the gate electrode 7, forming an independent MOS, i.e., a MOS independent of the gate 5 (i.e., the main gate). Simultaneously, a work function layer 9 is disposed on the outer surface of the virtual gate 8, ensuring that the gate 5 (i.e., the main gate) and the virtual gate 8 can operate synchronously under the same voltage conditions. This simultaneous placement of the virtual gate 8 and the work function layer 9 allows the virtual gate 8, connected to the gate 5, to rapidly draw electrons from the drain region 3 below the drain electrode 4 to the interface between the first isolation region 6 and the drain region 3, thus shortening the electron trajectory and reducing the electron transmission time in the drain region 3, thereby lowering the on-resistance of the device. Furthermore, the presence of the first isolation region 6 enhances the source-drain breakdown voltage.

[0110] Based on the unique structure of the high-voltage semiconductor device of this invention, it can be fabricated with both NMOS and PMOS metal work function layers through a simple process flow. Furthermore, the main gate structure is connected to the metal virtual gate sunk into the STI, without adding additional photomasks for the NMOS and PMOS metal work function layers. Moreover, the manufacturing process can be achieved entirely based on existing conditions, saving process costs.

[0111] The above embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention.

Claims

1. A high-voltage semiconductor device, comprising: Semiconductor substrate (1); A channel region (2), a drain region (3), a drain electrode (4), a source region (13), and a source electrode (14) are formed in the drain region (3) and the source region (13), respectively. The drain region (3) and the source region (13) are of a first conductivity type, and the semiconductor substrate (1) and the channel region (2) are of a second conductivity type. A gate (5) is formed on the semiconductor substrate (1) and located above the channel region (2); Its characteristic is that it further includes: A first isolation region (6) is formed in the drain region (3) and located between the drain electrode (4) and the gate electrode (5); The gate electrode (7) is connected to the gate (5) and is used to connect the gate (5) to an external control circuit. The virtual gate (8) is recessed into the first isolation region (6) at one end and connected to the gate electrode (7) at the other end to form an independent MOS, and the gate (5) is connected to the virtual gate (8) to form a closed-loop structure; A work function layer (9) is formed on the surface of the virtual gate (8).

2. The high-voltage semiconductor device according to claim 1, characterized in that: The virtual gate (8) is formed by the material forming the gate electrode (7) extending into and sinking into the first isolation region (6), and is an integral structure with the gate electrode (7).

3. The high-voltage semiconductor device according to claim 2, characterized in that: The semiconductor substrate (1) has a protective layer (16) formed on its surface covering the source (14), the gate (5) and the drain (4). An interlayer dielectric layer (10) is formed on the protective layer (16). The gate electrode (7) includes a main body segment (71) formed on the upper part of the interlayer dielectric layer (10) and an extension segment (72) penetrating the interlayer dielectric layer (10) and the protective layer (16). The upper end of the extension section (72) is connected to the main body section (71), and the lower end of the extension section (72) is connected to the virtual fence (8) that has sunk into the first isolation zone (6); The gate electrode (7) is electrically connected to the gate (5) through the first conductive plug (11).

4. The high-voltage semiconductor device according to claim 2, characterized in that: The work function layer (9) extends from the surface of the virtual gate (8) along the overall structure to the surface of the gate electrode (7).

5. The high-voltage semiconductor device according to claim 1, characterized in that: It also includes a lightly doped region (32) formed in the semiconductor substrate (1) and a heavily doped region (33) formed on the upper part of the lightly doped region (32), wherein the lightly doped region (32) and the heavily doped region (33) are of a second conductivity type; The lightly doped region (32) is arranged around the outside of the drain region (3) and the source region (13), and the heavily doped region (33) is connected to the outlet electrode (34) through the second conductive plug (35).

6. A method for manufacturing a high-voltage semiconductor device, characterized in that, include: An intermediate semiconductor structure is provided, the intermediate semiconductor structure including a semiconductor substrate (1), in which a channel region (2), a drain region (3), a drain electrode (4), a source region (13), and a source electrode (14) are formed in the drain region (3); a gate electrode (5) is formed on the surface of the channel region (2); the source region (13) and the drain region (3) are of a first conductivity type, and the semiconductor substrate (1) and the channel region (2) are of a second conductivity type; a first isolation region (6) is formed in the drain region (3), the first isolation region (6) being located between the drain electrode (4) and the gate electrode (5); A protective layer (16) is formed on the intermediate semiconductor structure, covering the source (14), the gate (5) and the drain (4). An interlayer dielectric layer (10) is formed on the protective layer (16). The interlayer dielectric layer (10) is etched to form a first trench (12) to accommodate the gate electrode (7). Electrode material is deposited in the first trench (12) to form the gate electrode (7). The gate electrode (7) is connected to the gate (5) to connect the gate (5) to an external control circuit. The interlayer dielectric layer (10) is etched and extended into the first isolation region (6) to form a receiving trench (61). A power function layer (9) is formed on the trench wall of the receiving trench (61). An electrode material is deposited on the power function layer (9) to form a virtual gate (8). The virtual gate (8) is connected to the gate electrode (7) to form an independent MOS. The gate (5) is connected to the virtual gate (8) to form a closed-loop structure.

7. The method for manufacturing a high-voltage semiconductor device according to claim 6, characterized in that, The gate electrode (7) and the virtual gate (8) are integrally deposited. First, a first trench (12) for accommodating the gate electrode (7) and a receiving trench (61) for accommodating the virtual gate (8) are simultaneously formed by etching. The first trench (12) includes a main body (121) and an extension (122) extending into the receiving trench (61) to communicate with each other. The main body (121) is formed on the upper part of the interlayer dielectric layer (10) by etching. The extension (122) is etched through the interlayer dielectric layer (10) and the protective layer (16) to the first isolation region (6). The receiving trench (61) is etched down into the first isolation region (6). Then, a work function layer (9) is simultaneously deposited on the inner wall of the main body (121), the extension (122) and the receiving trench (61). Then, electrode material is simultaneously deposited on the work function layer (9) to form the gate electrode (7) and the virtual gate (8).

8. The method for manufacturing a high-voltage semiconductor device according to claim 6, characterized in that, Also includes: A first conductive plug (11) is formed in the interlayer dielectric layer (10) and the protective layer (16). The lower end of the first conductive plug (11) is connected to the gate (5), and the upper end of the first conductive plug (11) is electrically connected to the gate electrode (7).

9. The method for manufacturing a high-voltage semiconductor device according to claim 6, characterized in that, Also includes: Ion implantation is performed on the outside of the drain region (3) and the source region (13) in the semiconductor substrate (1) to form a lightly doped region (32), and a heavily doped region (33) is formed on the upper surface of the lightly doped region (32) by ion implantation. The lightly doped region (32) and the heavily doped region (33) are of the second conductivity type. A second conductive plug (35) is formed in the interlayer dielectric layer (10) and the protective layer (16). The lower end of the second conductive plug (35) is connected to the heavily doped region (33), and the upper end of the second conductive plug (35) is electrically connected to the outlet electrode (34).

10. The method for manufacturing a high-voltage semiconductor device according to claim 6, characterized in that, The fabrication of the intermediate semiconductor structure includes: A semiconductor substrate is provided (1); A well region (17) is formed on the semiconductor substrate (1), and the well region (17) is of a second conductivity type; The well region (17) is etched to form a shallow trench (15), and the shallow trench (15) is filled to obtain a first isolation region (6); Ion implantation is performed into the well region (17) to form a source region (13) and a drain region (3). A channel region (2) that has not been implanted with ions is retained between the source region (13) and the drain region (3). The source region (13) and the drain region (3) are of the first conductivity type, and the channel region (2) is of the second conductivity type. A gate (5) is formed in the channel region (2), a source (14) is formed in the source region (13), and a drain (4) is formed in the drain region (3).

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