A CAN mailbox access device and method based on DSRAM

Abstract

A CAN mailbox access device and method based on DSRAM, relating to the field of integrated circuit design, comprising: a DSRAM storage module, used for storing sent mails and received mails, comprising an A terminal and a B terminal, wherein a chip internal bus reads and writes the DSRAM storage module through the A terminal, and a CAN bus reads and writes the DSRAM storage module through the B terminal; an address arbitration module, used for determining an access method according to an address accessed by the chip internal bus; a mapping address access module, used for converting a pointer into an internal address of the DSRAM storage module; a physical address access module, used for converting a physical address into an internal address of the DSRAM storage module for direct read and write operations when accessing through a physical address; the present invention stores a sending mailbox and a receiving mailbox separately through different storage spaces, thereby reducing conflicts in data processing, and sending and receiving operations can be performed in parallel without interfering with each other, thereby improving overall data processing efficiency.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a CAN mailbox access device and method based on DSRAM. Background Art

[0002] In the existing technical solution, the mailbox access mechanism of CAN uses FIFO cache to cache and read mails through pointers, but each receiving FIFO usually has limited cache space. For example, a common configuration is that each FIFO can cache 3 messages. When a large number of messages are received, if the number of received messages exceeds the capacity of the FIFO, the new message may overwrite the old message, which may cause cache overflow and data loss. Frequent read and write pointer operations may cause cache misses, increase access delays, and frequent allocation and release may cause memory fragmentation, affecting system performance.

[0003] DSRAM (Dual-Port SRAM) is a special type of static random access memory (SRAM) that has two independent ports, A and B, allowing the memory to be accessed from two different addresses at the same time. The two ports can read and write at the same time without interfering with each other, which provides higher bandwidth than single-port SRAM. Each port has its own address line, data line, and control signal, so it can operate independently, and because SRAM is a static memory, it does not need to be refreshed, so the access speed is fast.

[0004] Currently, there is no good solution for how to utilize the DSRAM-based CAN mailbox and use a more efficient and flexible mailbox access method to improve the utilization rate of the CAN mailbox based on CAN communication and increase the throughput rate of email information inside the chip.

[0005] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims of this application and are not admitted to be prior art by inclusion in this section. Summary of the invention

[0006] In order to overcome the deficiencies in the background technology, the present invention discloses a DSRAM-based CAN mailbox access device and method.

[0007] In order to achieve the above-mentioned invention object, the present invention adopts the following technical scheme:

[0008] A CAN mailbox access device based on DSRAM, the device comprises a DSRAM storage module, an address arbitration module, a mapping address access module and a physical address access module, wherein:

[0009] A DSRAM storage module is used to store sent mails and received mails; the DSRAM storage module includes a first storage space TBUF and a second storage space RBUF; the first storage space TBUF is used to store sent mails; the second storage space RBUF is used to store received mails; the DSRAM storage module includes an A terminal and a B terminal, and both the A terminal and the B terminal can read and write to the first storage space and the second storage space; the chip internal bus reads and writes the DSRAM storage module through the A terminal, and the CAN bus reads and writes the DSRAM storage module through the B terminal;

[0010] An address arbitration module, used to determine an access method according to the address of the chip internal bus access; the access method includes mapped address access and physical address access;

[0011] A mapping address access module, used to access the address area of ​​the first storage space TBUF and the second storage space RBUF in the DSRAM storage module through a pointer when using a mapping address method, and convert the pointer into an internal address area of ​​the DSRAM storage module;

[0012] The physical address access module is used to access the physical addresses of the first storage space TBUF and the second storage space RBUF of the DSRAM storage module through the chip internal bus when accessing through the physical address, and convert it into direct read and write operations on the internal address space of the DSRAM storage module.

[0013] Specifically, the first storage space is a sending slot; the second storage space is a receiving slot;

[0014] Specifically, the mapping address access module also includes a mapping address sending module and a mapping address receiving module:

[0015] The mapping address sending module is used to process the access operation of the chip internal bus to the mapping address TBUF0, and supports FIFO mode and external trigger mode; in FIFO mode, the address space of the first storage space TBUF is accessed by incrementing the first read pointer tbuf_rptr and the first write pointer tbuf_wptr; in external trigger mode, the third write pointer tt_wptr is used to point to the address space of the first storage space TBUF, and then the mail information in the first storage space TBUF is sent through the third read pointer tt_rptr;

[0016] The mapped address receiving module is used to process the access operation of the chip internal bus to the mapped address RBUF0 and supports FIFO mode. In FIFO mode, the DSRAM address space in the range of RBUF0~RBUFN is accessed by incrementing the second read pointer rbuf_rptr and the second write pointer rbuf_wptr. The mails received in the second storage space RBUF can only be read but not written.

[0017] Specifically, the physical address access module also includes a physical address sending module and a physical address receiving module:

[0018] The physical address sending module is used to convert the access of the chip internal bus to the physical address TBUF0~TBUFM into the access to the first storage space TBUF storage area, and realize the sending operation of the mail information in the first storage space TBUF through the pointer fourth read pointer t_rptr.

[0019] The physical address receiving module is used to convert the access of the chip internal bus to the physical address RBUF0~RBUFN into the access to the second storage space RBUF storage area.

[0020] Specifically, the device further includes:

[0021] The A-end access control module is used to manage the A-end read and write operations of the DSRAM storage module, determine the current access method through the address arbitration module, convert the address sent by the chip internal bus into the internal address area of ​​the DSRAM storage module, and realize the read and write operations of the DSRAM storage space according to the read and write data information and data strobe control information;

[0022] The B-side access control module is used to manage the B-side read and write operations of the DSRAM storage module, write to the CAN bus through the pointer, send mail to the DSRAM storage space, and convert the DSRAM data into mail information when reading and send it to the CAN bus.

[0023] The DSRAM-based CAN mailbox access device provided by the present invention introduces a DSRAM storage module as a CAN sending mailbox and a receiving mailbox, and stores the sending mailbox and the receiving mailbox separately through different storage spaces, thereby reducing data processing conflicts and improving access speed. The sending and receiving operations can be performed in parallel without interfering with each other, thereby improving the overall data processing efficiency.

[0024] Furthermore, the DSRAM storage module provides a larger storage space, which can be configured with more sending and receiving mailboxes, providing greater help for network applications that need to process a large number of messages.

[0025] In a second aspect, the present invention provides an access method based on the above-mentioned DSRAM-based CAN mailbox access device, wherein the mapping address access is specifically:

[0026] The CAN bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module through fixed access, and accesses other email addresses through pointers;

[0027] The fixed address of the chip internal bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module, and the addresses of TBUF0 / RBUF0 are offset in sequence through the FIFO pointer, so as to access the mail information in the first storage space TBUF and the second storage space RBUF. The FIFO pointer includes a first write pointer tbuf_wptr, a first read pointer tbuf_rptr, a second write pointer rbuf_wptr and a second read pointer rbuf_rptr:

[0028] When end A writes to the first storage space TBUF, the first write pointer tbuf_wptr is incremented;

[0029] When the A end reads the first storage space TBUF, the first read pointer tbuf_rptr does not change. When reading the second storage space RBUF, the slot corresponding to the first read pointer rbuf_rptr is manually released, and the first read pointer rbuf_rptr increases.

[0030] When the B end writes RBUF0~RBUFN, the second write pointer rbuf_wptr increases;

[0031] When TBUF is not empty, when TBUF0~TBUFM is read through the B terminal, the receiving slot starts sending mails in sequence according to the FIFO pointer. The first read pointer tbuf_rptr increases, and the second read pointer rbuf_rptr does not change;

[0032] The filling status of TBUF / RBUF is marked according to the difference between the read and write pointers of FIFO.

[0033] Specifically, the mapping address access also includes:

[0034] The fixed address of the chip internal bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module. The email information pointed to by the FIFO pointer is effectively sent through polling to send the cache ID information. The email corresponding to the second write pointer with a smaller ID is sent first:

[0035] When the A terminal writes TBUF0~TBUFM, the first write pointer tbuf_wptr increases;

[0036] When the A terminal reads TBUF0~TBUFM, the first read pointer tbuf_rptr does not change. When reading RBUF0~RBUFN, RBUF is manually released and the first read pointer rbuf_rptr increases.

[0037] When the B end writes RBUF0~RBUFN, the second write pointer rbuf_wptr increases;

[0038] When TBUF is not empty, when TBUF0~TBUFM is read through the B terminal, the receiving slot starts sending mail according to the ID priority, the first read pointer tbuf_rptr increases, and the second read pointer rbuf_rptr does not change;

[0039] The filling status of TBUF / RBUF is based on the TBUF slot sent, and the corresponding slot is unfilled.

[0040] Specifically, the mapping address access also includes:

[0041] The fixed address of the chip internal bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module, and directly offsets by selecting the configuration method of the third write pointer tt_wptr and the third read pointer tt_rptr to realize the sending and receiving of any email information of TBUF0~TBUFM and RBUF0~RBUFN of the DSRAM storage module;

[0042] Use external trigger as the condition for CAN to send emails; the external trigger includes: timing trigger, interrupt trigger and software trigger;

[0043] End A configures the third write pointer tt_wptr to write the email information to the TBUF0~TBUFM slots, and the slots written are in the filled state;

[0044] When the A terminal reads TBUF0~TBUFM, the first read pointer tbuf_rptr does not change. When reading RBUF0~RBUFN, RBUF is manually released and the first read pointer rbuf_rptr increases.

[0045] When the B end writes RBUF0~RBUFN, the second write pointer rbuf_wptr increases;

[0046] When the TBUF slot pointed to by the third read pointer tt_rptr is not empty, the B end reads and starts sending the mail in TBUF0~TBUFM through the third read pointer tt_rptr, and the first read pointer tbuf_rptr does not change. After the mail is sent, the TBUF slot pointed to by the third read pointer tt_rptr is unfilled.

[0047] In a third aspect, the present invention further provides an access method based on the above-mentioned DSRAM-based CAN mailbox access device, wherein the physical address access is specifically:

[0048] The chip is divided into a section of TBUF0~TBUFM and RBUF0~RBUFN address space. The chip internal bus can arbitrarily access the address space of TBUF0~TBUFM and arbitrarily read the address space of RBUF0~RBUFN.

[0049] When the A terminal writes any physical address of TBUF0~TBUFM, the first write pointer tbuf_wptr does not change, and the TBUF0~TBUFM slot filling status, according to the chip internal bus address range, the corresponding slot is filled;

[0050] When the A terminal reads the physical addresses of TBUF0~TBUFM and RBUF0~RBUFN through the chip internal bus, the read pointers tbuf_rptr and rbuf_rptr do not change;

[0051] When the B terminal writes RBUF0~RBUFN, the second write pointer rbuf_wptr does not change;

[0052] When the TBUF slot pointed to by the fourth read pointer t_rptr is not empty, the B end reads and sends the corresponding TBUF0~TBUFM slot information through the fourth read pointer t_rptr, the first read pointer tbuf_rptr and the second read pointer rbuf_rptr do not change, and the TBUF slot pointed to by the fourth read pointer t_rptr is unfilled.

[0053] Specifically, the physical address access also includes: the TBUF0~TBUFM slots can be directly accessed multiple times through the chip internal bus, the corresponding slots are in a filled state, and the CAN sending mailbox starts the sending of the corresponding TBUF0~TBUFM slots through the fourth read pointer t_rptr, and the content of the mapping address TBUF internal sending mailbox can also be directly modified through the chip internal bus.

[0054] The DSRAM-based CAN mailbox access method proposed in the present invention can meet the processing requirements of different users for CAN email information, and can flexibly modify the configuration and use the mapped address or physical address to process the CAN mailbox, thereby improving the use efficiency and flexibility of the CAN mailbox inside the chip and further improving the throughput rate of the email information inside the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0056] Figure 1 Schematic diagram of a DSRAM-based CAN mailbox access device provided according to an embodiment of the present invention;

[0057] Figure 2 Schematic diagram of a DSRAM storage module access method provided in an embodiment of the present invention;

[0058] Figure 3 is a schematic diagram of a DSRAM storage module access method provided in an embodiment of the present invention;

[0059] Figure 4 It is a schematic diagram of FIFO access of a DSRAM-based CAN mailbox mapping address access method according to an embodiment of the present invention;

[0060] Figure 5 A pointer pointing access schematic diagram of a DSRAM-based CAN mailbox mapping address access method provided according to an embodiment of the present invention;

[0061] Figure 6 It is a schematic diagram of a DSRAM-based CAN mailbox physical address access method provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The present invention can be explained in detail through the following embodiments. The purpose of disclosing the present invention is to protect all technical improvements within the scope of the present invention. In the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "front", "back", "left", "right", etc. indicating directions or positional relationships, they only correspond to the drawings of the present application for the convenience of describing the present invention, and do not indicate or imply that the device or element referred to must have a specific direction.

[0063] The following explains some terms involved in this embodiment:

[0064] (1) DSRAM: dual-port SRAM storage module,

[0065] (2) Mailbox: an address space for storing email information.

[0066] (3) Slot: The amount of storage space required for an email message.

[0067] (4) Frame: The transmission method of CAN communication.

[0068] (5) Receive slot (RBUF0~N): RBUF0~N represents the storage space that can receive 0~N email messages.

[0069] (6) Sending slot (TBUF0~M): TBUF0~M represents the storage space that can receive 0~M email messages.

[0070] (7) Mapping address: Only TBUF0 and RBUF0 addresses are mapped. Other mail addresses are accessed through FIFO pointers.

[0071] (8) Physical address: The address that can be directly accessed by the chip's internal bus.

[0072] Embodiment 1.

[0073] refer to Figure 1 , this embodiment provides a DSRAM-based CAN mailbox access device, including a DSRAM storage module, an address arbitration module, a mapping address access module and a physical address access module, wherein:

[0074] A DSRAM storage module, used for storing sent mails and received mails; the DSRAM storage module comprises a first storage space TBUF and a second storage space RBUF;

[0075] The first storage space TBUF is used to store sent mails, and its storage address range is TBUF0~TBUFM; TBUF0~TBUFM represents a storage space that can store 0~M mail information;

[0076] The second storage space RBUF is used to store received mails, and its storage address range is RBUF0~RBUFN; RBUF0~RBUFN represents a storage space that can store 0~N mail information;

[0077] The DSRAM storage module includes an A terminal and a B terminal, and both the A terminal and the B terminal can read and write to the first storage space and the second storage space;

[0078] The first storage space is a sending slot; the second storage space is a receiving slot;

[0079] The CAN external access dual-port DSRAM storage module access method is as follows Figure 2 As shown, the chip internal bus is written to the DSRAM through the A end of the DSRAM, and the chip internal bus reads the contents of the DSRAM through the A end of the DSRAM; the CAN bus receive frame is written through the B end of the DSRAM, and the CAN bus send frame information is obtained by reading the B end of the DSRAM.

[0080] Both the A and B ends of the DSRAM access the mailbox of the DSRAM. The address space of the DSRAM can be accessed sequentially through the read-write pointer (wptr / rptr), or any storage space inside the DSRAM can be accessed through the pointing (brackets) of the sending slot (TBUF0~TBUFM) and the receiving slot (RBUF0~RBUFN), such as Figure 3 shown.

[0081] An address arbitration module, used to determine an access method according to the address of the chip internal bus access; the access method includes mapped address access and physical address access;

[0082] The chip's internal bus accesses the address space of the DSRAM storage module, and the arbitration module determines the address space area to be accessed based on the accessed address range:

[0083] If the accessed address is TBUF0 or RBUF0, it means that the mapped address is currently being accessed and the mapped address access method is used; if the accessed address is within the range of physical addresses TBUF0~TBUFM, RBUF0~RBUFN, it means that the physical address access method is currently being used.

[0084] The TBUF0 / RBUF0 address here is the virtual memory address corresponding to the starting address of the sending slot / receiving slot, which is different from the address range of the physical addresses TBUF0~TBUFM and RBUF0~RBUFN.

[0085] A mapping address access module, used to access the address area of ​​the first storage space TBUF and the second storage space RBUF in the DSRAM storage module through a pointer when using a mapping address method, and convert the pointer into an internal address area of ​​the DSRAM storage module;

[0086] The address area of ​​TBUF and RBUF in the DSRAM storage module is accessed through a pointer, and the mapped address access converts the pointer (tbuf_rptr, tbuf_wptr, rbuf_rptr, rbuf_wptr, tt_wptr, tt_rptr) into the address area of ​​the DSRAM storage module.

[0087] It can be understood that mapped address access is a method of converting a logical address (pointer) into a physical address. In embedded systems, logical addresses are usually used by software, while physical addresses are the addresses of actual hardware components.

[0088] The conversion formula is: TBUF0 base address in DSRAM + pointer * email length = mapping address mode to access the address area of ​​DSRAM.

[0089] For example: the base address of TBUF0 in DSRAM is 0x1000, and the length of the message is 72 bytes.

[0090] It can be understood that the CAN mailbox data information has 64 bytes and the control information has 8 bytes, a total of 72 bytes.

[0091] If tbuf_wptr is 2, it means the write pointer points to the third message (because pointers usually start at 0).

[0092] Calculate the physical address using the formula: 0x1000 + 2 * 72 = 0x1090.

[0093] Therefore, to write the third message, write the data to DSRAM address 0x1090.

[0094] Specifically, the mapping address access module also includes a mapping address sending module and a mapping address receiving module:

[0095] The mapping address sending module is used to process the access operation of the chip internal bus to the mapping address TBUF0, and supports FIFO mode and external trigger mode; in FIFO mode, the address space of the first storage space TBUF is accessed by incrementing the first read pointer tbuf_rptr and the first write pointer tbuf_wptr; in external trigger mode, the third write pointer tt_wptr is used to point to the address space of the first storage space TBUF, and then the mail information in the first storage space TBUF is sent through the third read pointer tt_rptr;

[0096] The chip internal bus accesses the mapped address TBUF0 address and is judged as the mapped address mode in the address arbitration module. The chip internal bus selects the FIFO mode each time the mapped address TBUF0 is accessed, and the pointer (tbuf_rptr, tbuf_wptr) is incremented. The pointer points to the corresponding DSRAM address space of TBUF0~TBUFM. It can also select the external trigger mode. Based on the mapped address TBUF0, tt_wptr is used to point to the address of the DSRAM corresponding to TBUF0~TBUFM, and tt_rptr is used to send the email information of the specified TBUF0~TBUFM slot.

[0097] The mapped address receiving module is used to process the access operation of the chip internal bus to the mapped address RBUF0 and supports FIFO mode. In FIFO mode, the DSRAM address space in the range of RBUF0~RBUFN is accessed by incrementing the second read pointer rbuf_rptr and the second write pointer rbuf_wptr. The mails received in the second storage space RBUF can only be read but not written.

[0098] The address RBUF0 of the internal bus of the chip is judged as the mapping address mode in the address arbitration module. The internal bus of the chip reads the mapping address TBUF0 each time. In the FIFO mode, the pointer (rbuf_rptr, rbuf_wptr) increases, and the pointer points to the corresponding DSRAM address space of RBUF0~RBUFM. RBUF0~RBUFM is the slot for receiving mail. The received mail can only be read but not written, that is, the internal bus of the chip can only read RBUF0~RBUFM.

[0099] The physical address access module is used to access the physical addresses of the first storage space TBUF and the second storage space RBUF of the DSRAM storage module through the chip internal bus when accessing through the physical address, and convert it into direct read and write operations on the internal address space of the DSRAM storage module.

[0100] Specifically, the physical address access module also includes a physical address sending module and a physical address receiving module:

[0101] The physical address sending module is used to convert the access of the chip internal bus to the physical address TBUF0~TBUFM into the access to the storage area of ​​the first storage space TBUF, and realize the sending operation of the mail information in the first storage space TBUF through the fourth read pointer t_rptr.

[0102] The internal bus of the chip accesses the physical address TBUF0~TBUFM. This address is at a different address from the mapped address TBUF0, but both are mapped to the TBUF0 storage area of ​​DSRAM. The physical address TBUF0~TBUFM is judged as a physical address access in the address arbitration. The TBUF0~TBUFM storage area of ​​DSRAM is accessed according to the specific address of TBUF0~TBUFM, and the email information of the specified TBUF0~TBUFM slot is sent through the fourth read pointer t_rptr.

[0103] The fourth read pointer t_rptr is used to indicate which slot's mail information should be sent;

[0104] For example: The starting physical address of the TBUF0 storage area of ​​DSRAM is 0x2000.

[0105] The size of each mail slot is 72 bytes.

[0106] There are M slots from TBUF0 to TBUFM, so the physical address range is 0x2000 to (0x2000 + M * 72- 1).

[0107] The mapping address TBUF0 is 0x1000, but this address is not used directly to access DSRAM. Instead, it is converted into a physical address through some mapping mechanism.

[0108] Now, suppose we want to send an email message to slot A. Here are the steps:

[0109] When the chip's internal bus receives an access request with the requested address being 0x2000 + (A-1) * 72, the address arbitration module determines that this is a physical address access.

[0110] Based on the requested slot number A, calculate the physical address. For example, if N is 3, the physical address will be 0x2000 + (3-1) * 72 = 0x20C8.

[0111] Assume that the pointer t_rptr is set to 3, which means we need to send the email message of the 3rd slot.

[0112] Sending email information: According to the value of t_rptr, the system will read 72 bytes of data starting from the physical address 0x2090 of DSRAM and send it out through the bus.

[0113] A physical address receiving module, used for converting the access of the chip internal bus to the physical address RBUF0~RBUFN into the access to the second storage space RBUF storage area;

[0114] The internal bus of the chip accesses the physical address RBUF0~RBUFM. This address is at a different address from the mapped address RBUF0, but both are mapped to the RBUF0 storage area of ​​DSRAM. The physical address RBUF0~RBUFM is judged as a physical address access in the address arbitration, and the RBUF0~RBUFM storage area of ​​DSRAM is accessed according to the specific address of RBUF0~RBUFM.

[0115] In a possible implementation manner, an A-end access control module and a B-end access module may be added to the device to control the DSRAM storage module.

[0116] The A-end access control module is used to manage the A-end read and write operations of the DSRAM storage module. The address arbitration module determines the current access method, converts the address sent by the chip internal bus into the internal address area of ​​the DSRAM storage module, and implements the read and write operations of the DSRAM storage space according to the read and write data information and data strobe control information;

[0117] The A end accesses the DSRAM control and data information, the address information, read-write data information, and read-write data selection control information of the A end of the DSRAM, the address, read-write data, and data selection control information sent by the internal bus of the chip, and determines whether it is a mapped address or a physical address through the address, and converts the address into the address information for accessing the DSRAM. For the read-write data and data selection information sent by the internal bus of the chip, the storage space of the DSRAM is accessed by accessing the address pointing to the DSRAM.

[0118] The B-side access control module is used to manage the B-side read and write operations of the DSRAM storage module, write the CAN bus through the pointer to send the email to the DSRAM storage space, and convert the DSRAM data into email information when reading and send it to the CAN bus;

[0119] The B-side accesses DSRAM control and data information, control information: the B-side write address of DSRAM, corresponding to the first write pointer rbuf_wptr of RBUF, the CAN bus sends mail to CAN, and writes to the storage space of CAN internal mailbox DSRAM in sequence through the first write pointer rbuf_wptr; the B-side read address of DSRAM, corresponding to the first read pointer tbuf_rptr (mapped address FIFO pointer), the third read pointer tt_rptr (mapped address external trigger pointer) or the fourth read pointer t_rptr (physical address mode pointer) of TBUF points to the slot of TBUF0~M, which is sent as a sending mailbox. Data information: The B-side write operation converts the mail sent from the CAN bus into the data stream of DSRAM, and the B-side read operation converts the data of DSRAM into mail information and sends it to the CAN bus.

[0120] DSRAM stores data information, while CAN mail stores frame information. The conversion between the two is an existing technology and will not be described in detail here.

[0121] The A-end access control module and the B-end access control module are connected to the DSRAM storage module respectively, and the A-end access control module is connected to the address arbitration module through the mapping address access module / physical address access module.

[0122] The DSRAM-based CAN mailbox access device provided in this embodiment introduces DSRAM to store the CAN sending mailbox and receiving mailbox, and stores the sending mailbox and the receiving mailbox separately through different storage spaces, thereby effectively reducing data processing conflicts and improving access speed. Moreover, the sending and receiving operations can be performed in parallel without interfering with each other, further improving the overall data processing efficiency.

[0123] Furthermore, the DSRAM storage module provides a larger storage space, which can be configured with more sending and receiving mailboxes, providing greater help for network applications that need to process a large number of messages.

[0124] Embodiment 2.

[0125] refer to Figure 4 This embodiment provides an access method for the DSRAM-based CAN mailbox access device according to the first embodiment, wherein the mapping address access is specifically as follows:

[0126] The CAN bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module through fixed access, and accesses other email addresses through pointers;

[0127] The fixed address of the chip internal bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module, and the addresses of TBUF0 / RBUF0 are offset in sequence through the FIFO pointer, thereby accessing the mail information in the first storage space TBUF and the second storage space RBUF.

[0128] Described here is the working principle of the buffers (TBUF and RBUF) used for sending and receiving messages in the CAN bus controller, which is similar to the behavior of a FIFO (First In First Out) buffer.

[0129] The FIFO pointers include a first write pointer tbuf_wptr, a first read pointer tbuf_rptr, a second write pointer rbuf_wptr and a second read pointer rbuf_rptr:

[0130] When end A writes to the first storage space TBUF, the first write pointer tbuf_wptr is incremented;

[0131] When the A end reads the first storage space TBUF, the first read pointer tbuf_rptr does not change. When reading the second storage space RBUF, the slot corresponding to the first read pointer rbuf_rptr is manually released, and the first read pointer rbuf_rptr increases.

[0132] The A end reads the sending mailbox TBUF0~TBUFM, which is the mailbox accessed by the chip's internal bus. This email has not been sent. The email can only be sent through the B port. The pointer tbuf_rptr will change only when the email is sent. Otherwise, the chip's internal bus reads the sent email, and the read pointer tbuf_rptr changes, then the B end will not be able to locate or skip the email to be sent.

[0133] When the A terminal reads the mail from RBUF0 to RBUFN, it needs to release the mail manually to prove that the mail has been read. This ensures that the internal bus of the chip is not operated incorrectly. Since the RBUF pointer is in FIFO mode, if the user makes an error operation and reads the mail but does not parse the mail information, the next read operation can only be done in physical address mode. The A terminal reads the mail and releases it manually. The pointer points to the next RBUF mail and waits for reading. If it is not read, the RBUF mail is full, which will cause the mail to be overwritten or no new mail information will be received.

[0134] When the B end writes RBUF0~RBUFN, the second write pointer rbuf_wptr increases;

[0135] When TBUF is not empty, when TBUF0~TBUFM is read through the B terminal, the receiving slot starts sending mails in sequence according to the FIFO pointer. The first read pointer tbuf_rptr increases, and the second read pointer rbuf_rptr does not change;

[0136] The filling status of TBUF / RBUF is marked according to the difference between the read and write pointers of FIFO.

[0137] The read pointer wptr points to the location of the email to be written into the DSRAM, and the write pointer rptr points to the location of the email that has not been read into the DSRAM. When the two pointers point to the same location, it means it is empty. The TBUF / RBUF slot between the two means that there is already an email message in the operation, which is considered to be filled. Otherwise, it is an unfilled location.

[0138] Specifically, the mapping address access also includes:

[0139] The fixed address of the chip internal bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module. The email information pointed to by the FIFO pointer is effectively sent through polling to send the cache ID information. The email corresponding to the second write pointer with a smaller ID is sent first:

[0140] When the A terminal writes TBUF0~TBUFM, the first write pointer tbuf_wptr increases;

[0141] When the A terminal reads TBUF0~TBUFM, the first read pointer tbuf_rptr does not change. When reading RBUF0~RBUFN, RBUF is manually released and the first read pointer rbuf_rptr increases.

[0142] When the B end writes RBUF0~RBUFN, the second write pointer rbuf_wptr increases;

[0143] When TBUF is not empty, when TBUF0~TBUFM is read through the B terminal, the receiving slot starts sending mail according to the ID priority, the first read pointer tbuf_rptr increases, and the second read pointer rbuf_rptr does not change;

[0144] The filling status of TBUF / RBUF is based on the TBUF slot sent, and the corresponding slot is unfilled.

[0145] Specifically, refer to Figure 5 , the mapped address access also includes:

[0146] The fixed address of the chip internal bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module, and directly offsets by selecting the configuration method of the third write pointer tt_wptr and the third read pointer tt_rptr to realize the sending and receiving of any email information of TBUF0~TBUFM and RBUF0~RBUFN of the DSRAM storage module;

[0147] The brackets in the figure indicate that the pointer can point to any one of the DSRAM slots, and is configured through the chip's internal bus configuration CAN internal external trigger pointer register; the arrow indicates that the pointer can only be automatically incremented based on the internal read and write status of the FIFO.

[0148] Use external trigger as the condition for CAN to send emails; the external trigger includes: timing trigger, interrupt trigger and software trigger;

[0149] End A configures the third write pointer tt_wptr to write the email information to the TBUF0~TBUFM slots, and the slots written are in the filled state;

[0150] When the A terminal reads TBUF0~TBUFM, the first read pointer tbuf_rptr does not change. When reading RBUF0~RBUFN, RBUF is manually released and the first read pointer rbuf_rptr increases.

[0151] When the B end writes RBUF0~RBUFN, the second write pointer rbuf_wptr increases;

[0152] When the TBUF slot pointed to by the third read pointer tt_rptr is not empty, the B end reads and starts sending the mail in TBUF0~TBUFM through the third read pointer tt_rptr, and the first read pointer tbuf_rptr does not change. After the mail is sent, the TBUF slot pointed to by the third read pointer tt_rptr is unfilled.

[0153] Embodiment three.

[0154] refer to Figure 6 This embodiment provides an access method for the DSRAM-based CAN mailbox access device according to the first embodiment, wherein the physical address access is specifically as follows:

[0155] The chip is divided into a section of TBUF0~TBUFM and RBUF0~RBUFN address space. The chip internal bus can arbitrarily access the address space of TBUF0~TBUFM and arbitrarily read the address space of RBUF0~RBUFN.

[0156] When the A terminal writes any physical address of TBUF0~TBUFM, the first write pointer tbuf_wptr does not change, and the TBUF0~TBUFM slot filling status, according to the chip internal bus address range, the corresponding slot is filled;

[0157] When the A terminal reads the physical addresses of TBUF0~TBUFM and RBUF0~RBUFN through the chip internal bus, the read pointers tbuf_rptr and rbuf_rptr do not change;

[0158] When the B terminal writes RBUF0~RBUFN, the second write pointer rbuf_wptr does not change;

[0159] When the TBUF slot pointed to by the fourth read pointer t_rptr is not empty, the B end reads and sends the corresponding TBUF0~TBUFM slot information through the fourth read pointer t_rptr, the first read pointer tbuf_rptr and the second read pointer rbuf_rptr do not change, and the TBUF slot pointed to by the fourth read pointer t_rptr is unfilled.

[0160] The physical address access also includes: the TBUF0~TBUFM slots can be directly accessed multiple times through the chip internal bus, the corresponding slots are in a filled state, and the CAN sending mailbox starts the sending of the corresponding TBUF0~TBUFM slots through the fourth read pointer t_rptr, and the content of the mapping address TBUF internal sending mailbox can also be directly modified through the chip internal bus.

[0161] The DSRAM-based CAN mailbox access method proposed in this embodiment can meet the processing requirements of different users for CAN email information, and can flexibly modify the configuration and use mapped addresses or physical addresses to process CAN mailboxes, thereby improving the efficiency and flexibility of using the CAN mailbox inside the chip and further improving the throughput rate of email information inside the chip.

[0162] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 Processes Multiple processes and / or boxes Figure 1 A device that has the functions specified in one or more boxes.

[0163] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0164] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0165] The parts of the present invention that are not described in detail are prior art. It is obvious to those skilled in the art that the present invention is not limited to the details of the above-mentioned exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention; therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive, and it is intended that all changes that fall within the meaning and scope of equivalent elements are included in the present invention.

Claims

1. A CAN mailbox access device based on DSRAM, characterized in that: The device comprises a DSRAM storage module, an address arbitration module, a mapping address access module and a physical address access module, wherein: A DSRAM storage module is used to store sent mails and received mails; the DSRAM storage module includes a first storage space TBUF and a second storage space RBUF; the first storage space TBUF is used to store sent mails; the second storage space RBUF is used to store received mails; the DSRAM storage module includes an A terminal and a B terminal, and both the A terminal and the B terminal can read and write to the first storage space and the second storage space; the chip internal bus reads and writes the DSRAM storage module through the A terminal, and the CAN bus reads and writes the DSRAM storage module through the B terminal; An address arbitration module, used to determine an access method according to the address of the chip internal bus access; the access method includes mapped address access and physical address access; A mapping address access module, used to access the address area of ​​the first storage space TBUF and the second storage space RBUF in the DSRAM storage module through a pointer when using a mapping address method, and convert the pointer into an internal address area of ​​the DSRAM storage module; A physical address access module, used to access the physical addresses of the first storage space TBUF and the second storage space RBUF of the DSRAM storage module through the chip internal bus when accessing through the physical address, and convert it into a direct read and write operation on the internal address space of the DSRAM storage module; The mapping address access module also includes a mapping address sending module and a mapping address receiving module: The mapping address sending module is used to process the access operation of the chip internal bus to the mapping address TBUF0, and supports FIFO mode and external trigger mode; in FIFO mode, the address space of the first storage space TBUF is accessed by incrementing the first read pointer tbuf_rptr and the first write pointer tbuf_wptr; in external trigger mode, the third write pointer tt_wptr is used to point to the address space of the first storage space TBUF, and then the mail information in the first storage space TBUF is sent through the third read pointer tt_rptr; The mapped address receiving module is used to process the access operation of the chip internal bus to the mapped address RBUF0 and supports FIFO mode. In FIFO mode, the DSRAM address space in the range of RBUF0~RBUFN is accessed by incrementing the second read pointer rbuf_rptr and the second write pointer rbuf_wptr. The mails received in the second storage space RBUF can only be read but not written.

2. The device according to claim 1, characterized in that The first storage space is a sending slot; the second storage space is a receiving slot.

3. The device according to claim 1, characterized in that The physical address access module also includes a physical address sending module and a physical address receiving module: A physical address sending module, used for converting the access of the chip internal bus to the physical address TBUF0~TBUFM into the access to the storage area of ​​the first storage space TBUF, and implementing the sending operation of the mail information in the first storage space TBUF through the pointer fourth read pointer t_rptr; The physical address receiving module is used to convert the access of the chip internal bus to the physical address RBUF0~RBUFN into the access to the second storage space RBUF storage area.

4. The device according to claim 1, characterized in that The device also includes: The A-end access control module is used to manage the A-end read and write operations of the DSRAM storage module, determine the current access method through the address arbitration module, convert the address sent by the chip internal bus into the internal address area of ​​the DSRAM storage module, and realize the read and write operations of the DSRAM storage space according to the read and write data information and data strobe control information; The B-side access control module is used to manage the B-side read and write operations of the DSRAM storage module, write the CAN bus through the pointer to send mail to the DSRAM storage space, and convert the DSRAM data into mail information when reading and send it to the CAN bus.

5. An access method for a CAN mailbox access device based on a DSRAM according to any one of claims 1 to 4, characterized in that: The mapping address access is specifically: The CAN bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module through fixed access, and accesses other email addresses through pointers; The fixed address of the chip internal bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module, and the addresses of TBUF0 / RBUF0 are offset in sequence through the FIFO pointer, so as to access the mail information in the first storage space TBUF and the second storage space RBUF. The FIFO pointer includes a first write pointer tbuf_wptr, a first read pointer tbuf_rptr, a second write pointer rbuf_wptr and a second read pointer rbuf_rptr: When end A writes to the first storage space TBUF, the first write pointer tbuf_wptr is incremented; When the A end reads the first storage space TBUF, the first read pointer tbuf_rptr does not change. When reading the second storage space RBUF, the slot corresponding to the first read pointer rbuf_rptr is manually released, and the first read pointer rbuf_rptr increases. When the B end writes RBUF0~RBUFN, the second write pointer rbuf_wptr increases; When TBUF is not empty, when TBUF0~TBUFM is read through the B terminal, the receiving slot starts sending mails in sequence according to the FIFO pointer. The first read pointer tbuf_rptr increases, and the second read pointer rbuf_rptr does not change; The filling status of TBUF / RBUF is marked according to the difference between the read and write pointers of FIFO.

6. The method according to claim 5, characterized in that The mapped address access also includes: The fixed address of the chip internal bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module. The email information pointed to by the FIFO pointer is effectively sent through polling to send the cache ID information. The email corresponding to the second write pointer with a smaller ID is sent first: When the A terminal writes TBUF0~TBUFM, the first write pointer tbuf_wptr increases; When the A terminal reads TBUF0~TBUFM, the first read pointer tbuf_rptr does not change. When reading RBUF0~RBUFN, RBUF is manually released and the first read pointer rbuf_rptr increases. When the B end writes RBUF0~RBUFN, the second write pointer rbuf_wptr increases; When TBUF is not empty, when TBUF0~TBUFM is read through the B terminal, the receiving slot starts sending mail according to the ID priority, the first read pointer tbuf_rptr increases, and the second read pointer rbuf_rptr does not change; The filling status of TBUF / RBUF is based on the TBUF slot sent, and the corresponding slot is unfilled.

7. The method according to claim 5, characterized in that The mapped address access also includes: The fixed address of the chip internal bus accesses the TBUF0 and RBUF0 addresses in the DSRAM storage module, and directly offsets by selecting the configuration method of the third write pointer tt_wptr and the third read pointer tt_rptr to realize the sending and receiving of any email information of TBUF0~TBUFM and RBUF0~RBUFN of the DSRAM storage module; Use external trigger as the condition for CAN to send emails; the external trigger includes: timing trigger, interrupt trigger and software trigger; End A configures the third write pointer tt_wptr to write the email information to the TBUF0~TBUFM slots, and the slots written are in the filled state; When the A terminal reads TBUF0~TBUFM, the first read pointer tbuf_rptr does not change. When reading RBUF0~RBUFN, RBUF is manually released and the first read pointer rbuf_rptr increases. When the B end writes RBUF0~RBUFN, the second write pointer rbuf_wptr increases; When the TBUF slot pointed to by the third read pointer tt_rptr is not empty, the B end reads and starts sending the mail in TBUF0~TBUFM through the third read pointer tt_rptr, and the first read pointer tbuf_rptr does not change. After the mail is sent, the TBUF slot pointed to by the third read pointer tt_rptr is unfilled.

8. An access method for a CAN mailbox access device based on a DSRAM according to any one of claims 1 to 4, characterized in that: The physical address access is specifically: The chip is divided into a section of TBUF0~TBUFM and RBUF0~RBUFN address space. The chip internal bus can arbitrarily access the address space of TBUF0~TBUFM and arbitrarily read the address space of RBUF0~RBUFN. When the A terminal writes any physical address of TBUF0~TBUFM, the first write pointer tbuf_wptr does not change, and the TBUF0~TBUFM slot filling status, according to the chip internal bus address range, the corresponding slot is filled; When the A terminal reads the physical addresses of TBUF0~TBUFM and RBUF0~RBUFN through the chip internal bus, the read pointers tbuf_rptr and rbuf_rptr do not change; When the B terminal writes RBUF0~RBUFN, the second write pointer rbuf_wptr does not change; When the TBUF slot pointed to by the fourth read pointer t_rptr is not empty, the B end reads and sends the corresponding TBUF0~TBUFM slot information through the fourth read pointer t_rptr, the first read pointer tbuf_rptr and the second read pointer rbuf_rptr do not change, and the TBUF slot pointed to by the fourth read pointer t_rptr is unfilled.

9. The method according to claim 8, characterized in that The physical address access also includes: the TBUF0~TBUFM slots can be directly accessed multiple times through the chip internal bus, the corresponding slots are in a filled state, and the CAN sending mailbox starts the sending of the corresponding TBUF0~TBUFM slots through the fourth read pointer t_rptr, and the content of the mapping address TBUF internal sending mailbox can also be directly modified through the chip internal bus.

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