semiconductor structure

Abstract

The present disclosure relates to a semiconductor structure. The semiconductor structure includes: a stacked storage layer, an interconnect layer, and a pad layer. The storage layer includes a plurality of bit lines and a plurality of word lines. The pad layer includes a plurality of first pads and a plurality of second pads. The interconnect layer includes a stacked first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer. The first wiring layer and the fourth wiring layer are respectively connected to the bit lines, and the plurality of first pads are respectively connected to the first wiring layer and the fourth wiring layer; the second wiring layer and the third wiring layer are respectively connected to the word lines, and the plurality of second pads are respectively connected to the second wiring layer and the third wiring layer. The semiconductor structure facilitates the connection of the bit lines and word lines to the external drive circuit, thereby further improving the storage density and storage capacity of the three-dimensional memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It is composed of a number of memory cells arranged in an array. For example, a memory cell generally includes a transistor and a capacitor, wherein the first electrode (e.g., the drain) of the transistor is electrically connected to the capacitor, the second electrode (e.g., the source) of the transistor is electrically connected to the bit line, and the control electrode (e.g., the gate) of the transistor is electrically connected to the word line. Furthermore, the control electrode of the transistor in a row / column of memory cells can be electrically connected to a word line, and the second electrode of the transistor in a column / row of memory cells can be electrically connected to a bit line.

[0003] As the demand for memory capacity continues to increase, memory cells are being arranged in three dimensions. For example, by continuously increasing the number of stacked layers of memory cells arranged in an array, a three-dimensional memory can be constructed, thereby increasing the storage density per unit area.

[0004] However, as the number of stacked memory cells increases, the number of bit lines, word lines, and supporting contact structures electrically connected to each memory cell also increases, which tends to occupy more area within the 3D memory and limit further increases in storage density and capacity. Therefore, designing the connections between the bit lines and word lines in the 3D memory and the external driver circuits to further enhance the storage density and capacity of the 3D memory is a pressing issue. Summary of the Invention

[0005] Based on this, the embodiments of the present disclosure provide a semiconductor structure that facilitates the connection of bit lines and word lines with external driving circuits, thereby further improving the storage density and storage capacity of a three-dimensional memory.

[0006] On the one hand, an embodiment of the present disclosure provides a semiconductor structure, comprising: a first substrate and a storage layer, an interconnect layer, and a pad layer stacked on the first substrate. The storage layer includes a plurality of bit lines and a plurality of word lines. The pad layer includes a plurality of first pads and a plurality of second pads. The interconnect layer includes a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer stacked. The first wiring layer and the fourth wiring layer are respectively connected to the bit lines, and the plurality of first pads are respectively connected to the first wiring layer and the fourth wiring layer. The second wiring layer and the third wiring layer are respectively connected to the word lines, and the plurality of second pads are respectively connected to the second wiring layer and the third wiring layer.

[0007] According to some embodiments, the plurality of bit lines include a plurality of first bit lines and a plurality of second bit lines. The plurality of word lines include a plurality of first word lines and a plurality of second word lines. The storage layer further includes a plurality of first active pillars and a plurality of second active pillars. The first active pillars are arranged corresponding to the first word lines and are connected to the first bit lines or the second bit lines. The second active pillars are arranged corresponding to the second word lines and are connected to the first bit lines or the second bit lines. The first wiring layer is connected to the plurality of first bit lines; the second wiring layer is connected to the plurality of first word lines; the third wiring layer is connected to the plurality of second word lines; and the fourth wiring layer is connected to the plurality of second bit lines.

[0008] According to some embodiments, the fourth wiring layer is connected to the corresponding second bit line through the first wiring layer.

[0009] According to some embodiments, the stacking direction of the storage layer, the interconnection layer and the pad layer is a first direction, the extension direction of the first bit line and the second bit line is a second direction, the axial direction of the first active column and the second active column is a third direction, and the first direction, the second direction and the third direction intersect with each other; wherein, the first bit line and the second bit line are alternately arranged in the third direction, and are respectively arranged in bit line columns in the first direction; the first active column and the second active column are respectively located on both sides of the corresponding bit line column in the third direction, and the first active column and the second active column located on both sides of the same bit line are staggered in the second direction.

[0010] According to some embodiments, the first active pillars are arranged in rows along the first direction on a first side of the bit line column along the third direction, and in rows along the second direction; the first word lines extend along the first direction and are disposed correspondingly to the first active pillars in a column; the second active pillars are arranged in rows along the first direction on a second side of the bit line column along the third direction, and in rows along the second direction; the second word lines extend along the first direction and are disposed correspondingly to the second active pillars in a column.

[0011] According to some embodiments, the pad layer has a central region and edge regions located on both sides of the central region. The edge regions include a first edge region and a second edge region sequentially arranged in a direction approaching or away from the central region. The plurality of second pads correspondingly connected to the second wiring layer and the third wiring layer are distributed in the central region. The plurality of first pads correspondingly connected to the first wiring layer are distributed in the first edge region. The plurality of first pads correspondingly connected to the fourth wiring layer are distributed in the second edge region.

[0012] According to some embodiments, the semiconductor structure further includes: a second substrate, and a logic circuit layer and a bonding layer sequentially arranged on the second substrate in a direction away from the second substrate. The bonding layer includes a plurality of first bonding pads and a plurality of second bonding pads; the first bonding pads are bonded to the first pads, and the second bonding pads are bonded to the second pads. The logic circuit layer includes: a word line driver amplifier circuit, a bit line sense amplifier circuit, and a peripheral circuit. The word line driver amplifier circuit is connected to the second pads via the second bonding pads. The bit line sense amplifier circuit is connected to the first pads via the first bonding pads. The peripheral circuit is arranged between the word line driver amplifier circuit and the bit line sense amplifier circuit.

[0013] According to some embodiments, a plurality of the second bonding pads are distributed in an array in a central area of ​​the bonding layer.

[0014] According to some other embodiments, the plurality of second bonding pads bonded to the second pads corresponding to the second wiring layer are a first bonding group, the plurality of second bonding pads bonded to the second pads corresponding to the third wiring layer are a second bonding group, and the first bonding group and the second bonding group are staggered in the central area of ​​the bonding layer.

[0015] According to some embodiments, a plurality of the first bonding pads are distributed in an array in an edge region of the bonding layer.

[0016] According to some other embodiments, the multiple first bonding pads bonded to the first pads corresponding to the first wiring layer are a first bonding group, and the multiple first bonding pads bonded to the first pads corresponding to the fourth wiring layer are a second bonding group, and the first bonding group and the second bonding group are staggered in the edge area of ​​the bonding layer.

[0017] According to some embodiments, the first bonding group and the second bonding group are staggered, including: the bonding pads in the first bonding group are arranged in a first bonding column along the second direction, and the bonding pads in the second bonding group are arranged in a second bonding column along the second direction; the first bonding column and the second bonding column are distributed in parallel and spaced apart in the third direction, and staggered in the second direction.

[0018] According to some other embodiments, the staggered distribution of the first bonding group and the second bonding group includes: the first bonding group and the bonding pads in the first bonding group are alternately distributed in a row in the second direction.

[0019] The embodiments of the present disclosure may or may have at least the following advantages:

[0020] The semiconductor structure provided by the disclosed embodiments can utilize interconnect layers and pad layers stacked above the storage layer, specifically using multiple wiring layers at different levels, to implement lead-out connections for corresponding bit lines and corresponding word lines, thereby effectively connecting the bit lines and word lines to external driver circuits and avoiding the need for step structures around the storage layer for connecting lead-out bit lines and / or word lines. Therefore, the disclosed embodiments can effectively improve the planar area utilization of the storage layer, thereby facilitating improvements in the storage density and storage capacity of three-dimensional memory.

[0021] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A schematic structural diagram of a semiconductor structure provided in some embodiments;

[0024] Figure 2 for Figure 1 A schematic structural diagram of a storage layer, an interconnection layer, and a pad layer in the semiconductor structure shown;

[0025] Figure 3 for Figure 2 A schematic structural diagram of an interconnection structure corresponding to a bit line in the semiconductor structure shown;

[0026] Figure 4 for Figure 2 A schematic structural diagram of another interconnection structure corresponding to a bit line in the semiconductor structure shown;

[0027] Figure 5 A schematic diagram of a bit line contact structure and corresponding bit line connections provided in some embodiments;

[0028] Figure 6 for Figure 2 A schematic structural diagram of an interconnection structure corresponding to a word line in the semiconductor structure shown;

[0029] Figure 7 for Figure 6 A schematic structural diagram of an interconnection structure corresponding to a first word line in the word line corresponding interconnection structure shown;

[0030] Figure 8 for Figure 6 A schematic structural diagram of an interconnection structure corresponding to a second word line in the word line corresponding interconnection structure shown;

[0031] Figure 9 A schematic structural diagram of another interconnection structure corresponding to word lines provided in some embodiments;

[0032] Figure 10 for Figure 9 A schematic structural diagram of an interconnection structure corresponding to a first word line in the word line corresponding interconnection structure shown;

[0033] Figure 11 for Figure 9 A schematic structural diagram of an interconnection structure corresponding to a second word line in the word line corresponding interconnection structure shown;

[0034] Figure 12 A schematic diagram of the distribution of bit lines and word lines provided in some embodiments;

[0035] Figure 13 A schematic diagram of another bit line and word line distribution provided in some embodiments;

[0036] Figure 14 A schematic structural diagram of a storage layer provided in some embodiments;

[0037] Figure 15 A schematic structural diagram of a logic circuit layer and a bonding layer provided in some embodiments;

[0038] Figure 16 A schematic diagram of the distribution of edge areas and central areas in a pad layer, a bonding layer, and a logic circuit layer provided in some embodiments;

[0039] Figure 17 Schematic diagram of the distribution of bonding pads in a first bonding group and a second bonding group provided in some embodiments.

[0040] Description of reference numerals:

[0041] 01-first substrate, 02-second substrate;

[0042] 1-storage layer, BL-bit line, BL1-first bit line, BL2-second bit line, WL-word line, WL1-first word line, WL2-second word line, 11-first active pillar, 12-second active pillar, 13-bit line contact structure, 14-isolation layer, C-storage capacitor;

[0043] 2-interconnection layer, M0-first wiring layer, M1-second wiring layer, M2-third wiring layer, M3-fourth wiring layer;

[0044] 3-pad layer, 31-first pad, 32-second pad;

[0045] 4-Logic circuit layer, 41-Word line drive amplifier circuit, 42-Bit line sense amplifier circuit, 43-Peripheral circuit;

[0046] 5-bonding layer, 51-first bonding pad, 52-second bonding pad; G1-first bonding group, G2-second bonding group;

[0047] R1-central region, R11-first central region, R12-second central region, R2-edge region, R21-first edge region, R22-second edge region. DETAILED DESCRIPTION

[0048] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0050] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0051] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0053] Some embodiments of the present disclosure provide a semiconductor structure for connecting bit lines and word lines to external driving circuits, so as to further improve the storage density and storage capacity of a three-dimensional memory.

[0054] See also Figure 1 and Figure 2 The semiconductor structure includes: a first substrate 01 and a storage layer 1, an interconnection layer 2, and a pad layer 3 stacked on the first substrate 01. The storage layer 1 includes a plurality of bit lines BL and a plurality of word lines WL. The pad layer 3 includes a plurality of first pads 31 and a plurality of second pads 32. The interconnection layer 2 includes a first wiring layer M0, a second wiring layer M1, a third wiring layer M2, and a fourth wiring layer M3 stacked. The first wiring layer M0 and the fourth wiring layer M3 are respectively connected to the bit lines BL, and the plurality of first pads 31 are respectively connected to the first wiring layer M0 and the fourth wiring layer M3. The second wiring layer M1 and the third wiring layer M2 are respectively connected to the word lines WL, and the plurality of second pads 32 are respectively connected to the second wiring layer M1 and the third wiring layer M2.

[0055] The disclosed embodiments utilize the interconnect layer 2 and pad layer 3 stacked above the memory layer 1. Specifically, multiple wiring layers at different levels are used to implement the corresponding bit lines BL and word lines WL, respectively, thereby effectively connecting the bit lines BL and word lines WL to external drive circuits. This avoids the need for step structures around the periphery of the memory layer 1 for connecting the lead-out bit lines and / or word lines. Therefore, the disclosed embodiments can effectively improve the planar area utilization of the memory layer 1, thereby facilitating the improvement of the storage density and storage capacity of the three-dimensional memory.

[0056] For example, the first substrate 01 can be composed of one or more layers of semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, the first substrate 01 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the first substrate 01 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. The disclosed embodiments do not limit the type, number of layers, etc. of the first substrate 1.

[0057] In some embodiments, see Figure 1 and Figure 2 , the first wiring layer M0 , the second wiring layer M1 , the third wiring layer M2 , and the fourth wiring layer M3 in the interconnection layer 2 are stacked in a direction away from the first substrate 01 .

[0058] Here, the wiring layer refers to a layer structure formed of a conductive material and having a plurality of conductive lines. In addition, an insulating layer may be provided between adjacent wiring layers. Figure 1 and Figure 2 The insulating layer between adjacent wiring layers is not illustrated in the figure, but it can be understood that the insulating layer is located between adjacent wiring layers and is used to insulate the conductive lines in the corresponding wiring layers.

[0059] In some examples, conductive lines in different wiring layers may penetrate corresponding insulating layers and be connected.

[0060] In some examples, different conductive lines in the same wiring layer can be isolated or connected in series, in parallel, etc. to match the circuit design.

[0061] In some examples, each wiring layer in the interconnection layer 2 is a metal wiring layer, such as a tungsten wiring layer or a copper wiring layer.

[0062] It should be noted that the interconnection layer 2 in the embodiment of the present disclosure includes but is not limited to a first wiring layer M0, a second wiring layer M1, a third wiring layer M2 and a fourth wiring layer M3; that is, when there are more connection requirements, the number of wiring layers in the interconnection layer 2 can be increased accordingly; or, it can also be understood that the above-mentioned wiring layers in the interconnection layer 2 can also be reasonably applied as multiple sub-layers arranged in a stacked manner.

[0063] It should be noted that the aforementioned storage layer 1 refers to a memory cell array region, i.e., the storage layer 1 also includes a plurality of memory cells arranged in an array and correspondingly connected to the bit lines BL and word lines WL. Furthermore, each memory cell matches the type and structural design of the memory, and various specific implementations are possible, such as a 1T1C (one transistor and one capacitor) architecture, a 2T1C (two transistors and one capacitor) architecture, a 2T0C (two transistors and zero capacitors) architecture, etc. This is not limited in the presently disclosed embodiments.

[0064] For ease of description, the following embodiments and drawings of the present disclosure illustrate only the example of a memory cell in memory layer 1 employing a 1T1C architecture. However, it is understood that in examples where the memory cell in memory layer 1 employs other architectures, the interconnection structure extending from the bit lines BL and word lines WL can be adaptively used in conjunction with the description of the interconnection structure extending from the bit lines BL and word lines WL in the embodiments of the present disclosure.

[0065] In some embodiments, please refer to Figure 1 and Figure 2 The plurality of bit lines BL include a plurality of first bit lines BL1 and a plurality of second bit lines BL2. The plurality of word lines WL include a plurality of first word lines WL1 and a plurality of second word lines WL2. The memory layer 1 further includes a plurality of first active pillars 11 and a plurality of second active pillars 12. The first active pillars 11 are arranged corresponding to the first word lines WL1 and are connected to the first bit lines BL1 or the second bit lines BL2. The second active pillars 12 are arranged corresponding to the second word lines WL2 and are connected to the first bit lines BL1 or the second bit lines BL2.

[0066] For example, the stacking direction of the memory layer 1, the interconnect layer 2, and the pad layer 3 is a first direction (e.g., the Z direction). The first bit line BL1 and the second bit line BL1 extend in a second direction (e.g., the Y direction). The axis direction of the first active pillar 11 and the second active pillar 12 is a third direction (e.g., the X direction). The first direction (e.g., the Z direction), the second direction (e.g., the Y direction), and the third direction (e.g., the X direction) intersect with each other.

[0067] Here, the intersection of two directions means that there is an angle between the two directions, and the angle can be a right angle of 90°, or an angle other than 90°.

[0068] For example, the first bit lines BL1 and the second bit lines BL2 are alternately arranged in the third direction (eg, the X direction), and are respectively arranged in bit line rows in the first direction (eg, the Z direction).

[0069] Here, the number of stacked layers of corresponding bit lines in the bit line column is related to the number of stacked layers of memory cells in the memory layer 1 .

[0070] In some examples, the number of layers corresponding to the first bit line BL1 or the second bit line BL2 in the bit line column includes, but is not limited to, 59 layers or 64 layers.

[0071] For example, the first active pillar 11 and the second active pillar 12 are both semiconductor pillars, for example, they can be formed of a metal oxide semiconductor material. Furthermore, the first active pillar 11 and the first word line WL1 are arranged in correspondence, which can be manifested as: the first word line WL1 covers the sidewalls of the first active pillar 11, and a gate oxide layer is provided between the first word line WL1 and the first active pillar 11; thus, the area of ​​the first active pillar 11 covered by the first word line WL1 can serve as the channel region of the corresponding transistor. Similarly, the second active pillar 12 and the second word line WL2 are arranged in correspondence, which can be manifested as: the second word line WL2 covers the sidewalls of the second active pillar 12, and a gate oxide layer is provided between the second word line WL2 and the second active pillar 12; thus, the area of ​​the second active pillar 12 covered by the second word line WL2 can serve as the channel region of the corresponding transistor.

[0072] For example, Figure 1 and Figure 2 As shown in FIG, the first active pillar 11 and the second active pillar 12 are respectively located on both sides of the corresponding bit line column in the third direction (e.g., the X direction). The bit line column can be a bit line column consisting of the first bit line BL1 or a bit line column consisting of the second bit line BL2. Based on this, the first active pillar 11 and the second active pillar 12 located on both sides of the same bit line (the first bit line BL1 or the second bit line BL2) along the third direction (e.g., the X direction) can share the same bit line, for example, be in contact with the bit line.

[0073] For example, storage capacitors C may be respectively provided at ends of the first active pillar 11 and the second active pillar 12 away from the corresponding bit lines.

[0074] In some examples, ends of the first active pillar 11 and the second active pillar 12 away from the corresponding bit lines can serve as storage contact structures to sequentially form a first electrode, a dielectric layer, and a second electrode of the storage capacitor C on the surface of the storage contact structure.

[0075] In other examples, the ends of the first active pillar 11 and the second active pillar 12 away from the corresponding bit line can directly serve as the first electrode of the storage capacitor C, and a dielectric layer and a second electrode are sequentially formed on the surface of the first electrode to obtain the storage capacitor C.

[0076] In some embodiments, please refer to Figure 1 and Figure 2 The first wiring layer M0 is connected to a plurality of first bit lines BL1. The second wiring layer M1 is connected to a plurality of first word lines WL1. The third wiring layer M2 is connected to a plurality of second word lines WL2. The fourth wiring layer M3 is connected to a plurality of second bit lines BL2.

[0077] For example, see Figures 3 to 5 The semiconductor structure further includes a plurality of bit line contact structures 13. The bit line contact structures 13 extend along a first direction (eg, Z direction), and the first bit line BL1 and the second bit line BL2 are each connected to the first wiring layer M0 via at least one bit line contact structure 13.

[0078] In some examples, such as Figure 3 and Figure 4 As shown in FIG, a plurality of first bit lines BL1 are arranged in a bit line column along a first direction (e.g., the Z direction), and each first bit line BL1 in the same bit line column is connected to a corresponding first wiring layer M0 via a bit line contact structure 13. A plurality of second bit lines BL2 are arranged in a bit line column along the first direction (e.g., the Z direction), and each second bit line BL2 in the same bit line column is connected to a corresponding first wiring layer M0 via a bit line contact structure 13.

[0079] In other examples, such as Figure 5 As shown in FIG, the same bit line BL is connected via two bit line contact structures 13 .

[0080] Here, the bit line contact structure 13 may extend along a first direction (e.g., Z direction) and be disposed in a through hole of other bit lines above the corresponding connected bit line, and be insulated from other bit lines. For example, the bottom surface of the bit line contact structure 13 contacts the surface of the corresponding connected bit line, and an isolation layer 14 is disposed between the sidewall of the bit line contact structure 13 and the hole wall of other bit lines above the corresponding connected bit line (please refer to FIG. Figure 3 and Figure 4 understand).

[0081] It is understood that an insulating layer is generally provided between adjacent bit lines in any bit line column, and between adjacent bit line columns in a third direction (eg, the X direction).

[0082] For some examples, see Figure 3 The first wiring layer M0 may include a plurality of conductive lines extending at least along a third direction (X direction); wherein a portion of the conductive lines is connected to each first bit line BL1 through a corresponding bit line contact structure 13, and another portion of the conductive lines is connected to each second bit line BL2 through a corresponding bit line contact structure 13.

[0083] In some examples, a plurality of conductive lines for connecting to the first bit line BL1 and a plurality of conductive lines for connecting to the second bit line BL2 in the first wiring layer M0 are alternately arranged in a second direction (eg, the Y direction).

[0084] In some embodiments, please refer to Figure 3, a plurality of bit line contact structures 13 respectively connected to each first bit line BL1 and each second bit line BL2 are arranged in an array; wherein, the conductive line connected to the first bit line BL1 in the first wiring layer M0 can first extend along the second direction (for example, the Y direction) to be staggered with the conductive line connected to the second bit line BL2 in the first wiring layer M0 in the second direction (for example, the Y direction), and then extend along the third direction (for example, the X direction), and finally extend along the first direction (for example, the Z direction), so as to be directly connected to the corresponding first pad 31.

[0085] In some embodiments, please refer to Figure 3 The fourth wiring layer M3 is connected to the corresponding second bit line BL2 through the first wiring layer M0. That is, the conductive line in the first wiring layer M0 connected to the second bit line BL2 may first extend along the first direction (e.g., the Z direction) and connect to the conductive line in the fourth wiring layer M3 accordingly, and then extend along the first direction (e.g., the Z direction) through the conductive line in the fourth wiring layer M3 to connect to the corresponding first pad 31.

[0086] Here, each conductive line in the fourth wiring layer M3 may also extend along the third direction (X direction), for example.

[0087] It is worth mentioning that the conductive lines in the first wiring layer M0 may also have other implementations.

[0088] In other embodiments, see Figure 4 The multiple conductive lines in the first wiring layer M0, connected to each first bit line BL1 or each second bit line BL in the same bit line column, can be first extended in a third direction (e.g., the X direction) and then extended in a second direction (e.g., the Y direction). Accordingly, the arrangement of the corresponding first pads 31 can be adaptively configured to match the lead-out ends of the conductive lines in the first wiring layer M0.

[0089] In some embodiments, see Figure 1 and Figure 2 The first active pillars 11 are arranged in rows along a first direction (e.g., Z direction) and in a second direction (e.g., Y direction) on a first side of the bit line column along a third direction (e.g., X direction). The second active pillars 12 are arranged in rows along a first direction (e.g., Z direction) and in a second direction (e.g., Y direction) on a second side of the bit line column along the third direction (e.g., X direction).

[0090] Accordingly, see Figures 6 to 8The first word lines WL1 extend along a first direction (e.g., the Z direction) and are arranged corresponding to a row of first active pillars 11. The second word lines WL2 extend along the first direction (e.g., the Z direction) and are arranged corresponding to a row of second active pillars 12. Furthermore, a plurality of first word lines WL1 are arranged in rows along a third direction (e.g., the X direction) and in columns along a second direction (e.g., the Y direction). A plurality of second word lines WL2 are arranged in rows along the third direction (e.g., the X direction) and in columns along a second direction (e.g., the Y direction).

[0091] In some examples, such as Figure 7 As shown in the figure, the second wiring layer M1 may include multiple conductive lines extending along a third direction (for example, the X direction), wherein one conductive line corresponds to connecting a row of first word lines WL1, and each conductive line can also extend along the first direction (for example, the Z direction) to connect to the corresponding second pad 32. Figure 7 The second pads 32 are only used to illustrate the lead-out connection of the conductive wires in the second wiring layer M1, and the number of the second pads and the corresponding connection relationship with the first word line WL1 do not constitute a limitation to the present disclosure.

[0092] In some examples, such as Figure 8 As shown in the figure, the third wiring layer M2 may include a plurality of conductive lines extending along a third direction (for example, the X direction), wherein one conductive line corresponds to a second word line WL2 connected in a row, and each conductive line may also extend along the first direction (for example, the Z direction) to be connected to the corresponding second pad 32. Figure 8 The second pads 32 are only used to illustrate the lead-out connection of the conductive wires in the third wiring layer M2, and the number of the second pads and the corresponding connection relationship with the second word line WL2 do not constitute a limitation to the present disclosure.

[0093] Also, please combine Figure 6 、 Figure 7 and Figure 8 It is understood that, in some embodiments, the orthographic projections of the conductive lines in the second wiring layer M1 and the conductive lines in the third wiring layer M2 on the first substrate 01 may be alternately spaced.

[0094] In addition, in some of the above embodiments, multiple second pads 32 for connecting the conductive wires in the second wiring layer M1, and multiple second pads 32 for connecting the conductive wires in the third wiring layer M2 can be arranged above the second wiring layer M1 and the third wiring layer M2 along the first direction (for example, the Z direction).

[0095] Illustratively, multiple second pads 32 for connecting conductive lines in the second wiring layer M1 and multiple second pads 32 for connecting conductive lines in the third wiring layer M2 are located in the central areas above the second wiring layer M1 and the third wiring layer M2, respectively.

[0096] For example, the central area above the second wiring layer M1 and the third wiring layer M2 has edge areas on both sides of the third direction (e.g., X direction); wherein, the plurality of second pads 32 for connecting the conductive wires in the second wiring layer M1 can be set in one of the edge areas, and the plurality of second pads 32 for connecting the conductive wires in the third wiring layer M2 can be set in the other edge area. Figures 9 to 11 , each conductive line in the second wiring layer M1 and each conductive line in the third wiring layer M2 can be extended and led out in directions opposite to the third direction (eg, X direction).

[0097] In some embodiments, see Figure 12 The first active pillars 11 and the second active pillars 12 on both sides of the same bit line BL are staggered in the second direction (e.g., the Y direction). Accordingly, the first word line WL1 corresponding to the first active pillar 11 and the second word line WL2 corresponding to the second active pillar 12 are staggered in the second direction (e.g., the Y direction).

[0098] For example, please continue to see Figure 12 , the first active pillar 11 and the second active pillar 12 that is offset in the second direction (for example, the Y direction) and adjacent in the third direction (for example, the X direction) can share the same bit line BL. Based on this, according to the arrangement order of each word line and each bit line BL in the third direction (for example, the X direction), the first word line WL1 is, for example, an odd-bit word line, and the second word line WL2 is, for example, an even-bit word line. Among them, the even-bit bit line BL can be connected to the first wiring layer M0. The odd-bit bit line BL can be connected to the fourth wiring layer M3 through the first wiring layer M0, or directly connected to the fourth wiring layer M3. The odd-bit word line can be connected to the second wiring layer M1, and the even-bit word line can be connected to the third wiring layer M2. Alternatively, in other examples, the even-bit word line is connected to the second wiring layer M1, and the odd-bit word line is connected to the third wiring layer M2, which is also allowed.

[0099] In the embodiment of the present disclosure, the first active pillars 11 and the second active pillars 12 located on both sides of the same bit line BL are staggered in the second direction (for example, the Y direction) and share the same bit line BL, which is beneficial to increasing the spacing between adjacent word lines WL (i.e., corresponding to the first word line WL1 and the second word line WL2) to reduce the parasitic capacitance between adjacent word lines WL, thereby improving the electrical performance of the semiconductor structure.

[0100] It should be added that, in some embodiments, see Figure 13The bit line contact structure 13 connected to the bit line BL can be located between two corresponding adjacent word lines WL along the second direction (for example, the Y direction), so as to reduce the parasitic capacitance between the bit line contact structure 13 and the corresponding word line WL, thereby further improving the electrical performance of the semiconductor structure.

[0101] In other embodiments, see Figure 14 The first active pillars 11 and the second active pillars 12 located on both sides of the same bit line BL (including the first bit line BL1 or the second bit line BL2) are arranged linearly in the second direction (for example, the Y direction); that is, each first active pillar 11 and each second active pillar 12 can be arranged in an array in the intersection plane of the second direction (for example, the Y direction) and the third direction (for example, the X direction).

[0102] In some embodiments, please combine Figure 2 It is understood that the pad layer 3 has a central region R1 and edge regions R2 located on both sides of the central region R1. The edge region R2 includes a first edge region R21 and a second edge region R22 arranged in sequence in a direction close to or away from the central region R1. Among them, the plurality of second pads 32 correspondingly connected to the second wiring layer M1 and the third wiring layer M2 are distributed in the central region R1. The plurality of first pads 31 correspondingly connected to the first wiring layer M0 are distributed in the first edge region R21. The plurality of first pads 31 correspondingly connected to the fourth wiring layer M3 are distributed in the second edge region R22.

[0103] In some examples, a center-to-center distance between the second edge region R22 and the center region R1 is substantially equal to a center-to-center distance between the second edge region R22 and the first edge region R21 .

[0104] Here, substantially equal includes equal and within the range of ±5% of the equal value. Furthermore, the center distance refers to the distance between the geometric centers of the target areas.

[0105] In the embodiment of the present disclosure, based on the lead-out connection of the fourth wiring layer M3 to the second bit line BL2, the second edge region R22 can be expanded from the first edge region R11 to the center region R1, for example, expanding by one quarter of the size of the corresponding pad layer 3 in the third direction (for example, the X direction).

[0106] In some other examples, it is also permitted that the center distance between the second edge region R22 and the center region R1 is greater than the center distance between the second edge region R22 and the first edge region R21 .

[0107] In some embodiments, please refer to Figure 2The central region R1 of the pad layer 3 includes a first central region R11 and a second central region R12 arranged side by side along a third direction (e.g., the X direction). The plurality of second pads 32 corresponding to the second wiring layer M1 are distributed in the first central region R11. The plurality of second pads 32 corresponding to the third wiring layer M2 are distributed in the second central region R12.

[0108] In some examples, a center distance between the second edge region R22 and the adjacent first central region R11 or second central region R12 is substantially equal to a center distance between the second edge region R22 and the adjacent first edge region R21 .

[0109] Here, substantially equal includes equal and within the range of ±5% of the equal value. Furthermore, the center distance refers to the distance between the geometric centers of the target areas.

[0110] In some other examples, it is also permitted that the center distance between the second edge region R22 and the adjacent first central region R11 or the second central region R12 is greater than the center distance between the second edge region R22 and the adjacent first edge region R21 .

[0111] In the disclosed embodiment, the interconnection layer 2 adopts the aforementioned structure, which facilitates the design of the distribution position of each pad in the pad layer 3, that is, each pad in the pad layer 3 has a higher degree of freedom, which is conducive to reducing parasitic capacitance and thus weakening the influence of resistance and capacitance (RC).

[0112] In some embodiments, please combine Figure 1 and Figure 15 It is understood that the semiconductor structure further includes: a second substrate 02, and a logic circuit layer 4 and a bonding layer 5 sequentially disposed on the second substrate 02 in a direction away from the second substrate 02. The bonding layer 5 includes a plurality of first bonding pads 51 and a plurality of second bonding pads 52; wherein the first bonding pads 51 are bonded to the first pads 31, and the second bonding pads 52 are bonded to the second pads 32.

[0113] In the disclosed embodiment, the logic circuit layer 4 and the bonding layer 5 may have the same advantages as the aforementioned pad layer 3 , for example, they may have a higher degree of design freedom, which is beneficial for reducing parasitic capacitance to further reduce the resistance-capacitance (RC) effect.

[0114] For example, the material and structure of the second substrate 02 can be implemented with reference to the first substrate 01. The bonding layer 5 can be provided on the side of the logic circuit layer 4 facing away from the second substrate 02 to bond with the pad layer 3 on the first substrate 01. In addition, an insulating layer is provided between adjacent bonding pads of the bonding layer 5 and between adjacent pads of the pad layer 3 for insulation. Figure 1 and Figure 15In the figure, the insulating layers are omitted, but this does not mean that there is no need to set the insulating layers. The insulating layers can be set according to the electrical requirements of each component in the semiconductor structure.

[0115] For example, the bonding layer 5 and the pad layer 3 can be bonded using a hybrid bonding method, for example, including metal bonding between the bonding pad and the corresponding pad, and bonding of an insulating layer between the bonding layer 5 and the pad layer 3. This helps to further reduce the resistance-capacitance (RC) effect.

[0116] In some embodiments, see Figure 15 The logic circuit layer 4 includes a word line driver amplifier circuit (SWD) 41 and a bit line sense amplifier circuit (BLSA) 42. The word line driver amplifier circuit 41 is connected to the second pad 32 via the second bonding pad 52. The bit line sense amplifier circuit 42 is connected to the first pad 31 via the first bonding pad 51.

[0117] For example, please continue to see Figure 15 The logic circuit layer 4 further includes a peripheral circuit 43 located between the word line driving amplifier circuit 41 and the bit line sensing amplifier circuit 42 .

[0118] Here, the peripheral circuit 43 may be other auxiliary circuits and / or functional circuits other than the word line driving amplifier circuit 41 and the bit line sensing amplifier circuit 42. The embodiment of the present disclosure does not limit this.

[0119] In some embodiments, see Figure 15 The bonding layer 5 has a central region R1 and edge regions R2 located on either side of the central region R1. The orthographic projection of the word line driver amplifier circuit 41 on the bonding layer 5 is located within the central region R1 of the bonding layer 5. The orthographic projection of the bit line sense amplifier circuit 42 on the bonding layer 5 is located within the edge regions R2 of the bonding layer 5. Furthermore, the distribution of the central region R1 and edge regions R2 in the bonding layer 5 can be the same as or similar to the distribution of the edge regions R2 and central region R1 in the pad layer 3.

[0120] For some examples, see Figure 16 In Figure (a), the central region R1 and its two side edge regions R2 are both rectangular regions and are arranged side by side in a third direction (e.g., the X direction). Furthermore, the central region R1 includes a first central region R11 and a second central region R12 arranged side by side. The edge regions R2 include a first edge region R21 and a second edge region R22 arranged side by side, thereby more accurately demarcating the distribution locations of the corresponding pads or bonding pads.

[0121] For other examples, see Figure 16 In Figure (b), both the central area R1 and the edge area R2 can be circular areas. The edge areas R2 on both sides of the aforementioned central area R1 can be composed of different parts of the same edge area R2 located on both sides of the central area R1 in the same direction. In addition, the central area R1 may include a first central area R11 and a second central area R12 arranged side by side in a third direction (for example, the X direction); or, the central area R1 may also include a first central area R11 and a second central area R12 distributed from the inside to the outside or from the outside to the inside along its radial direction. Similarly, the edge area R2 may include a first edge area R21 and a second edge area R22 arranged side by side in a third direction (for example, the X direction); or, the edge area R2 may also include a first edge area R21 and a second edge area R22 distributed from the inside to the outside or from the outside to the inside along its radial direction. This facilitates a more accurate division of the distribution positions of the corresponding pads or bonding pads.

[0122] It can be understood that in the embodiment of the present disclosure, the distribution of the corresponding edge regions R2 and center regions R1 in the pad layer 3, bonding layer 5, and logic circuit layer 4 can be matched and arranged with reference to the above-mentioned relevant descriptions. In addition, the corresponding first pads 31 and first bonding pads 51 in the pad layer 3 and bonding layer 5 have the same position distribution, and the corresponding second pads 32 and second bonding pads 52 in the pad layer 3 and bonding layer 5 have the same position distribution. The connection bumps in the logic circuit layer 4 used to connect the corresponding bonding pads in the bonding layer 5 can have the same or similar position distribution as the corresponding bonding pads.

[0123] For ease of description, the following embodiments of the present disclosure are described using the position distribution of each bonding pad in the bonding layer 5 as an example. However, it is understood that the position distribution of each pad in the pad layer 3 (including the first pad 31 and the second pad 32), as well as the position distribution of each connection bump in the logic circuit layer 4, can be implemented to match the position distribution of each bonding pad in the bonding layer 5, and this will not be described in detail in the embodiments of the present disclosure.

[0124] In some embodiments, please combine Figure 16 and Figure 17 As can be understood from FIG. 5 (a), the plurality of second bonding pads 52 are distributed in an array in the central region R1 of the bonding layer 5; that is, they can be arranged in rows along the third direction (eg, X direction) and in columns along the second direction (eg, Y direction).

[0125] In other embodiments, please combine Figure 16 and Figure 17 Figure (b) in Figure 17As can be understood from Figure (c), the multiple second bonding pads 52 bonded to the second pads 32 corresponding to the second wiring layer M1 are the first bonding group G1, and the multiple second bonding pads 52 bonded to the second pads 32 corresponding to the third wiring layer M2 are the second bonding group G2. The first bonding group G1 and the second bonding group G2 are staggered in the central area R1 of the bonding layer 5.

[0126] By way of further example, the central region R1 of the bonding layer 5 includes a first central region R11 and a second central region R12; wherein, a plurality of second bonding pads 52 bonded to the second pads 32 corresponding to the second wiring layer M1 are distributed in the first central region R11; and a plurality of second bonding pads 52 bonded to the second pads 32 corresponding to the third wiring layer M2 are distributed in the second central region R12.

[0127] Similarly, in some embodiments, the plurality of first bonding pads 51 are distributed in an array in the edge region R2 of the bonding layer 5 .

[0128] In other embodiments, the multiple first bonding pads 31 bonded to the first solder pads 31 corresponding to the first wiring layer M0 are the first bonding group G1, and the multiple first bonding pads 51 bonded to the first solder pads 31 corresponding to the fourth wiring layer M3 are the second bonding group G2, and the first bonding group G1 and the second bonding group G2 are staggered in the edge area R2 of the bonding layer 5.

[0129] By way of further example, the edge region R2 includes a first edge region R21 and a second edge region R22. A plurality of first bonding pads 51 bonded to the first pads 31 corresponding to the first wiring layer M0 are distributed in the first edge region R21, and a plurality of first bonding pads 51 bonded to the first pads 31 corresponding to the fourth wiring layer M3 are distributed in the second edge region R22.

[0130] In some of the above embodiments, the staggered distribution of the first bonding group G1 and the second bonding group G2 may be specifically implemented in the following manner, but is not limited thereto.

[0131] For some examples, see Figure 17 In FIG. (b), the bond pads in the first bond group G1 (e.g., the first bond pad 51 or the second bond pad 52) are arranged in a first bond row along the second direction (e.g., the Y direction), and the bond pads in the second bond group G2 are arranged in a second bond row along the second direction (e.g., the Y direction). The first bond row and the second bond row are arranged parallel and spaced apart in a third direction (e.g., the X direction) and staggered in the second direction (e.g., the Y direction).

[0132] For other examples, see Figure 17In FIG. 5( c ), the bonding pads (eg, the first bonding pads 51 or the second bonding pads 52 ) in the first bonding group G1 and the second bonding group G2 are alternately arranged in a row in the second direction (eg, the Y direction).

[0133] In summary, please refer to Figure 1 In the semiconductor structure provided by the embodiments of the present disclosure, the first wiring layer M0 in the interconnect layer 2 can be used to lead the bit line contact structure 13 of the first bit line BL1 to the corresponding first edge region R21. Furthermore, the first wiring layer M0 in the interconnect layer 2 can also be used to lead the bit line contact structure 13 of the second bit line BL2 to a corresponding connection with the fourth wiring layer M4, and then to the corresponding second edge region R22 through the fourth wiring layer M4. In this way, the lead-out connection of the first bit line BL1 and the second bit line BL2 does not adversely interfere with the lead-out connection of the first word line WL1 and the second word line WL2.

[0134] Also, please continue reading Figure 1 In the semiconductor structure provided by the embodiment of the present disclosure, the second wiring layer M1 in the interconnect layer 2 can be used to lead each first word line WL1 (for example, an odd-bit word line) to the corresponding first central region R11. Furthermore, the third wiring layer M2 in the interconnect layer 2 can be used to lead each second word line WL2 (for example, an even-bit word line) to the corresponding second central region R12. In this way, the embodiment of the present disclosure uses different wiring layers to respectively implement the lead-out connection of each first word line WL1 and each second word line WL2. This not only helps reduce the process difficulty of patterning the second wiring layer M1 and the third wiring layer M2, thereby improving production efficiency and yield, but also helps reduce the coupling effect between adjacent word lines, thereby improving the accuracy of signal transmission.

[0135] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0136] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0137] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, and all such variations and improvements fall within the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A first substrate and a storage layer, an interconnect layer, and a pad layer stacked on the first substrate; the storage layer includes a plurality of bit lines, a plurality of word lines, and a plurality of active pillars; the storage layer, the interconnect layer, and the pad layer are stacked in a first direction, the plurality of bit lines extend in a second direction, and the axis direction of the plurality of active pillars is a third direction, and the first direction, the second direction, and the third direction intersect with each other; The pad layer includes a plurality of first pads and a plurality of second pads; the interconnect layer includes a first wiring layer, a second wiring layer, a third wiring layer and a fourth wiring layer arranged in a stacked manner; wherein, The first wiring layer and the fourth wiring layer are respectively connected to the bit lines, and the plurality of first pads are respectively connected to the first wiring layer and the fourth wiring layer; The second wiring layer and the third wiring layer are respectively connected to the word lines, and the plurality of second pads are respectively connected to the second wiring layer and the third wiring layer.

2. The semiconductor structure according to claim 1, wherein: The plurality of bit lines include a plurality of first bit lines and a plurality of second bit lines; the plurality of word lines include a plurality of first word lines and a plurality of second word lines; the plurality of active pillars include a plurality of first active pillars and a plurality of second active pillars; the first active pillars are correspondingly arranged with the first word lines and are correspondingly connected to the first bit lines or the second bit lines; the second active pillars are correspondingly arranged with the second word lines and are correspondingly connected to the first bit lines or the second bit lines; wherein, The first wiring layer is connected to a plurality of the first bit lines correspondingly; The second wiring layer is correspondingly connected to a plurality of the first word lines; The third wiring layer is correspondingly connected to a plurality of the second word lines; The fourth wiring layer is connected to a plurality of second bit lines correspondingly.

3. The semiconductor structure according to claim 2, wherein: The fourth wiring layer is connected to the corresponding second bit line through the first wiring layer.

4. The semiconductor structure according to claim 2 or 3, characterized in that: The first bit lines and the second bit lines are alternately arranged in the third direction and are respectively arranged in bit line rows in the first direction; The first active pillar and the second active pillar are respectively located on both sides of the corresponding bit line column in the third direction, and the first active pillar and the second active pillar located on both sides of the same bit line are staggered in the second direction.

5. The semiconductor structure according to claim 4, wherein: The first active pillars are arranged in columns along the first direction and in rows along the second direction on a first side of the bit line column along the third direction; the first word lines extend along the first direction and are arranged corresponding to the first active pillars in one column; The second active pillars are arranged in columns along the first direction and in rows along the second direction on the second side of the bit line column along the third direction; the second word lines extend along the first direction and are disposed corresponding to the second active pillars in one column.

6. The semiconductor structure according to any one of claims 1 to 3 and 5, characterized in that: The pad layer has a central area and edge areas located on both sides of the central area; the edge areas include a first edge area and a second edge area sequentially arranged in a direction close to or away from the central area; Among them, the multiple second pads correspondingly connected to the second wiring layer and the third wiring layer are distributed in the central area; the multiple first pads correspondingly connected to the first wiring layer are distributed in the first edge area; and the multiple first pads correspondingly connected to the fourth wiring layer are distributed in the second edge area.

7. The semiconductor structure according to any one of claims 1 to 3 and 5, characterized in that: Also includes: a second substrate, and a logic circuit layer and a bonding layer sequentially arranged on the second substrate in a direction away from the second substrate; Wherein, the bonding layer includes a plurality of first bonding pads and a plurality of second bonding pads; the first bonding pads are bonded to the first pads correspondingly, and the second bonding pads are bonded to the second pads correspondingly; The logic circuit layer includes: a word line drive amplifier circuit, a bit line sense amplifier circuit and a peripheral circuit; the word line drive amplifier circuit is correspondingly connected to the second pad through the second bonding pad; the bit line sense amplifier circuit is correspondingly connected to the first pad through the first bonding pad; the peripheral circuit is arranged between the word line drive amplifier circuit and the bit line sense amplifier circuit.

8. The semiconductor structure according to claim 7, wherein: A plurality of the second bonding pads are distributed in an array in the central area of ​​the bonding layer; or, The multiple second bonding pads bonded to the second pads corresponding to the second wiring layer are the first bonding group, and the multiple second bonding pads bonded to the second pads corresponding to the third wiring layer are the second bonding group. The first bonding group and the second bonding group are staggered in the central area of ​​the bonding layer.

9. The semiconductor structure according to claim 7, wherein: A plurality of the first bonding pads are distributed in an array in the edge area of ​​the bonding layer; or, The multiple first bonding pads bonded to the first pads corresponding to the first wiring layer are a first bonding group, and the multiple first bonding pads bonded to the first pads corresponding to the fourth wiring layer are a second bonding group. The first bonding group and the second bonding group are staggered in the edge area of ​​the bonding layer.

10. The semiconductor structure according to claim 8 or 9, characterized in that: The dislocation distribution of the first bonding group and the second bonding group comprises: The bonding pads in the first bonding group are arranged in a first bonding row along the second direction, and the bonding pads in the second bonding group are arranged in a second bonding row along the second direction; the first bonding row and the second bonding row are arranged in parallel and spaced apart in the third direction, and staggered in the second direction; Alternatively, the first bonding group and the bonding pads in the first bonding group are alternately distributed in a row in the second direction.

11. The semiconductor structure according to claim 4, wherein: The pad layer has a central area and edge areas located on both sides of the central area; the edge areas include a first edge area and a second edge area sequentially arranged in a direction close to or away from the central area; Among them, the multiple second pads correspondingly connected to the second wiring layer and the third wiring layer are distributed in the central area; the multiple first pads correspondingly connected to the first wiring layer are distributed in the first edge area; and the multiple first pads correspondingly connected to the fourth wiring layer are distributed in the second edge area.

12. The semiconductor structure according to claim 4, wherein: Also includes: a second substrate, and a logic circuit layer and a bonding layer sequentially arranged on the second substrate in a direction away from the second substrate; Wherein, the bonding layer includes a plurality of first bonding pads and a plurality of second bonding pads; the first bonding pads are bonded to the first pads correspondingly, and the second bonding pads are bonded to the second pads correspondingly; The logic circuit layer includes: a word line drive amplifier circuit, a bit line sense amplifier circuit and a peripheral circuit; the word line drive amplifier circuit is correspondingly connected to the second pad through the second bonding pad; the bit line sense amplifier circuit is correspondingly connected to the first pad through the first bonding pad; the peripheral circuit is arranged between the word line drive amplifier circuit and the bit line sense amplifier circuit.

13. The semiconductor structure according to claim 11, wherein: Also includes: a second substrate, and a logic circuit layer and a bonding layer sequentially arranged on the second substrate in a direction away from the second substrate; Wherein, the bonding layer includes a plurality of first bonding pads and a plurality of second bonding pads; the first bonding pads are bonded to the first pads correspondingly, and the second bonding pads are bonded to the second pads correspondingly; The logic circuit layer includes: a word line drive amplifier circuit, a bit line sense amplifier circuit and a peripheral circuit; the word line drive amplifier circuit is correspondingly connected to the second pad through the second bonding pad; the bit line sense amplifier circuit is correspondingly connected to the first pad through the first bonding pad; the peripheral circuit is arranged between the word line drive amplifier circuit and the bit line sense amplifier circuit.

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