Semiconductor structure and manufacturing method thereof

Abstract

The disclosed embodiments relate to the field of semiconductors and provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a first transistor, comprising: a first gate and a first source and a first drain located on opposite sides of the first gate along a first direction; the first transistor also includes: a first channel layer, the first channel layer surrounding the first gate and being in contact and electrically connected to the first source and the first drain; and a second transistor, located above the first transistor, comprising: a second gate and a second source and a second drain located on opposite sides of the second gate along a second direction, the second drain being in contact and connected to the first gate; the second transistor also includes: a second channel layer surrounding the second gate and being in contact and electrically connected to the second source and the second drain. This can increase the channel length of the second transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Common dynamic random access memory (DRAM) is a 1T1C type, where a single transistor source or drain is electrically connected to a capacitor to form a single memory cell. This structure uses capacitors to store data, but reading data consumes the capacitor's charge, and the capacitor itself leaks electricity, requiring constant refreshing. This results in high DRAM power consumption and unstable electrical performance. Furthermore, the large area required to manufacture the capacitor makes scaling down the capacitor challenging.

[0003] To overcome the problem caused by capacitance, a 2T0C type memory cell structure is used, that is, the source or drain of a transistor is electrically connected to the gate of another transistor to form a memory cell structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can at least increase the channel length of the second transistor.

[0005] According to some embodiments of the present disclosure, on one hand, the embodiments of the present disclosure provide a semiconductor structure, including: a first transistor, the first transistor including: a first gate and a first source and a first drain located on opposite sides of the first gate along a first direction, the first transistor also including: a first channel layer, the first channel layer surrounds the sidewalls and bottom surface of the first gate, and is in contact and electrically connected with the first source and the first drain; a second transistor, the second transistor is located above the first transistor, the second transistor including: a second gate and a second source and a second drain located on opposite sides of the second gate along a second direction, the second drain is in contact and connected with the first gate, the second transistor also including: a second channel layer, the second channel layer surrounds the bottom surface, the top surface and one of the two sidewalls arranged along the first direction of the second gate, and is in contact and electrically connected with the second source and the second drain.

[0006] In some embodiments, the first channel layer, the first source electrode, and the first drain electrode are integrally formed, and the second channel layer, the second source electrode, and the second drain electrode are integrally formed.

[0007] In some embodiments, the first transistor further includes: a first dielectric layer, the first dielectric layer covering the bottom surface of the first gate arranged along the second direction and surrounding the sidewall in contact with the bottom surface arranged along the second direction, and the first dielectric layer is located between the first gate and the first channel layer.

[0008] In some embodiments, a material of the first channel layer and a material of the second channel layer are the same.

[0009] In some embodiments, the second transistor includes a conductive plug, the conductive plug being in contact with a sidewall of the second gate arranged along the first direction and spaced apart from the first gate.

[0010] In some embodiments, the conductive plug covers the entire sidewall of the second gate arranged along the first direction.

[0011] In some embodiments, the second transistor further includes a first insulating layer located between the conductive plug and the first gate.

[0012] In some embodiments, the second transistor further includes a second insulating layer, wherein the second insulating layer is located between the conductive plug and the second source, and the second insulating layer is also located between the first insulating layer and the second drain.

[0013] In some embodiments, the second transistor further includes: a second dielectric layer, the second dielectric layer covering the sidewalls of the second gate arranged along the first direction and surrounding the bottom surface and top surface in contact with the sidewalls arranged along the first direction, and the second dielectric layer is located between the second gate and the second channel layer.

[0014] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, including: forming a first transistor, the first transistor including: a first gate and a first source and a first drain located on opposite sides of the first gate along a first direction, the first transistor also including: a first channel layer, the first channel layer surrounds the sidewalls and bottom surface of the first gate, and is in contact and electrically connected with the first source and the first drain; forming a second transistor, the second transistor being located above the first transistor, the second transistor including: a second gate and a second source and a second drain located on opposite sides of the second gate along a second direction, the second drain is in contact and connected with the first gate, the second transistor also including: a second channel layer, the second channel layer surrounds the bottom surface, the top surface and one of the two sidewalls arranged along the first direction of the second gate, and is in contact and electrically connected with the second source and the second drain.

[0015] In some embodiments, the method of forming the first transistor includes: forming a stack structure, the stack structure including a first base layer, a first sacrificial layer, a second base layer, a second sacrificial layer and a third base layer stacked in sequence; etching the stack structure to form a first groove passing through the stack structure along the second direction; etching the first sacrificial layer exposed along the first groove to form a second groove passing through the stack structure in the first direction; forming the first transistor, the first source and the first drain fill the second groove, the first channel layer covers the inner wall of the first groove, the first gate is located in the first groove, and the top surface of the first gate arranged along the second direction is flush with the bottom surface of the second base layer arranged along the second direction.

[0016] In some embodiments, the first transistor further includes a first dielectric layer, and after forming the second groove, the following steps are further performed: forming a first initial channel layer, wherein the first initial channel layer covers the inner wall of the first groove; forming a first initial dielectric layer, wherein the first initial dielectric layer covers the surface of the first initial channel layer; forming a first initial gate, wherein the first initial gate fills the first groove; etching the first initial channel layer, the first initial dielectric layer, and the first initial gate, with the remaining first initial channel layer serving as the first channel layer, the remaining first initial dielectric layer serving as the first dielectric layer, and the remaining first initial gate serving as the first gate.

[0017] In some embodiments, the method of forming the second transistor includes: after forming the first transistor, epitaxially growing the second base layer, the second sacrificial layer and the third base layer exposed along the first groove to fill the first groove; etching the second base layer, the second sacrificial layer and the third base layer that fill the first groove to form a third groove; etching the second sacrificial layer on one side of the third groove to form a fourth groove; forming the second transistor, part of the second gate is located in the fourth groove, part of the second gate is located in the third groove, the second source and the second drain are located in the third groove, and cover the side walls of the second base layer and the third base layer exposed in the third groove and on the same side as the third groove, and the second channel layer covers the inner wall of the fourth groove and is in contact with the second source and the second drain.

[0018] In some embodiments, the second transistor further includes a second dielectric layer, and after forming the fourth groove, the following steps are further included: forming a second initial channel layer, wherein the second initial channel layer covers the inner wall of the fourth groove, the second initial channel layer also covers the surface of the second base layer and the third base layer facing the third groove, and the second initial channel layer also covers the inner wall of the third groove; etching the second initial channel layer, and the remaining second initial channel layer serves as the second channel layer; forming a second initial dielectric layer, and the second initial dielectric layer covers the surface of the second channel layer; forming a second initial gate, and the second initial gate fills the third groove and the fourth groove; etching the second initial dielectric layer and the second initial gate, and the remaining second initial dielectric layer serves as the second dielectric layer, and the remaining second initial gate serves as the second gate.

[0019] In some embodiments, after forming the second gate, the following steps are further included: forming a first insulating layer, wherein the first insulating layer is located in the third groove and is located on the surface of the first gate; forming a conductive plug, wherein the conductive plug is located on the top surface of the first insulating layer, fills the third groove, and is in contact with the second gate.

[0020] In some embodiments, before etching the second initial gate, the method further includes: etching a portion of the second initial dielectric layer to form a second insulating layer, where the second insulating layer is located between the second initial gate and the second initial channel layer.

[0021] In some embodiments, the method of forming the first transistor and the second transistor includes: forming a first base layer and a first sacrificial layer arranged in a stacked manner; etching the first base layer and the first sacrificial layer to form a fifth groove; forming the first transistor, wherein the first gate is located in the fifth groove, the first source and the first drain are located on the top surface of the first base layer, the top surface of the first gate is flush with the top surfaces of the first source and the first drain, and the first channel layer covers the inner wall of the fifth groove; forming a second base layer, a second sacrificial layer and a third base layer arranged in a stacked manner, wherein the second base layer is located on the top surface of the first transistor; etching the second base layer, the second sacrificial layer and the third base layer to form a sixth groove, wherein the sixth groove exposes the top surface of the first gate; etching the second sacrificial layer along the sixth groove to form a seventh groove; forming the second transistor, wherein part of the second gate is located in the seventh groove, part of the second gate is located in the sixth groove, the second source is located on the surface of the third base layer exposed by the sixth groove, the second drain is located on the surface of the second base layer exposed by the sixth groove, and the second channel layer covers the inner wall of the seventh groove.

[0022] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by setting the first transistor to include a first gate and a first source and a first drain arranged along a first direction, the first transistor is used as a read transistor, and the first gate is equivalent to a capacitor; by setting the second transistor to include a second gate and a second source and a second drain arranged along a second direction, the second transistor is used as a write transistor, and the second drain is contacted and connected to the first gate, thereby providing charge to the first gate, and by surrounding the second gate with a second channel layer and electrically connecting the second source and the second drain, the carrier transmission path of the second channel layer can be extended along the second direction, thereby increasing the channel length of the second transistor, reducing the short channel effect, and improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic structural diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0025] Figures 2 to 17 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figures 18 to 24 A schematic structural diagram corresponding to each step of a method for manufacturing another semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, the current 2T0C structure is generally two transistors stacked along the second direction. However, with the miniaturization of semiconductor structures and the increase in integration, the size of the transistors in the 2T0C is miniaturized, resulting in a shortening of the channel lengths of the two transistors, resulting in the existence of a short channel effect in the current 2T0C structure.

[0028] The present disclosure provides a semiconductor structure. A first transistor is provided, including a first gate and a first source and a first drain arranged along a first direction. The first transistor is used as a read transistor, and the first gate is equivalent to a capacitor. A second transistor is provided, including a second gate and a second source and a second drain arranged along a second direction. The second transistor is used as a write transistor, and the second drain is contacted and connected to the first gate, thereby providing charge to the first gate. A second channel layer is formed around the second gate and is electrically connected to the second source and the second drain, so that the carrier transmission path of the second channel layer can be extended along the second direction, thereby increasing the channel length of the second transistor, reducing the short channel effect, and improving the reliability of the semiconductor structure.

[0029] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0030] refer to Figure 1 , Figure 1 A schematic structural diagram of a semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0031] In some embodiments, the semiconductor structure provided by the embodiments of the present disclosure may include: a first transistor 100, the first transistor 100 includes: a first gate 101 and a first source 102 and a first drain 103 located on opposite sides of the first gate 101 along the first direction X, the first transistor 100 also includes: a first channel layer 104, the first channel layer 104 surrounds the sidewalls and bottom surface of the first gate 101, and is in contact and electrically connected to the first source 102 and the first drain 103.

[0032] In some embodiments, the semiconductor structure provided by the embodiments of the present disclosure may further include: a second transistor 110, the second transistor 110 is located above the first transistor 100, the second transistor 110 includes: a second gate 111 and a second source 112 and a second drain 113 located on opposite sides of the second gate 111 along the second direction Y, the second drain 113 is in contact with the first gate 101, the second transistor 110 also includes: a second channel layer 114, the second channel layer 114 surrounds the bottom surface, the top surface and one of the two side walls arranged along the first direction of the second gate 111, and is in contact and electrically connected with the second source 112 and the second drain 113.

[0033] By setting the first transistor 100 to include a first gate 101 and a first source 102 and a first drain 103 arranged along the first direction X, the first transistor 100 is used as a read transistor, and the first gate 101 is equivalent to a capacitor; by setting the second transistor 110 to include a second gate 111 and a second source 112 and a second drain 113 arranged along the second direction Y, the second transistor 110 is used as a write transistor, and the second drain 113 is in contact with the first gate 101 to provide charge to the first gate 101. By surrounding the second gate 111 and being in contact and electrically connected to the second source 112 and the second drain 113, the carrier transmission path of the second channel layer 114 can be extended along the second direction Y, thereby increasing the channel length of the second transistor 110, reducing the short channel effect, and improving the reliability of the semiconductor structure.

[0034] In some embodiments, the semiconductor structure may further include a first base layer 120, with the first source 102 and the first drain 103 covering the top surface of the first base layer 120. In other words, a first groove may be formed in the first base layer 120, and the first gate 101 and the first channel layer 104 of the first transistor 100 are located in the first groove, and the first source 102 and the first drain 103 cover the surface of the first base layer 120 around the first groove.

[0035] In some embodiments, the material of the first base layer 120 may include a semiconductor material, such as, but not limited to, silicon. In some embodiments, the first base layer 120 may include a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, a basic semiconductor may include germanium; a compound semiconductor may include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and an alloy semiconductor may include silicon germanium, silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, the first base layer 120 may also be a silicon-on-insulator (SOI) structure, a silicon-germanium-on-insulator (SGI) structure, a germanium-on-insulator (GOI) structure, or a combination thereof.

[0036] In addition, the first base layer 120 can be doped according to design requirements (e.g., a P-type substrate or an N-type substrate). In some embodiments, the first base layer 120 can be doped with P-type dopant ions (e.g., boron ions, aluminum ions) or N-type dopant ions (e.g., phosphorus ions, arsenic ions).

[0037] In some embodiments, the first channel layer 104 can be an integral structure with the first source electrode 102 and the first drain electrode 103. In other words, the first source electrode 102 and the first drain electrode 103 are formed simultaneously during the process of forming the first channel layer 104. Providing the first channel layer 104, the first source electrode 102, and the first drain electrode 103 as an integral structure can facilitate the transmission of carriers among the first source electrode 102, the first channel layer 104, and the first drain electrode 103.

[0038] In some embodiments, the material of the first channel layer 104 may be IGZO (Indium Gallium Zinc Oxide). IGZO material has high mobility. By setting the material of the first channel layer 104 to IGZO, it can facilitate the transmission of carriers in the first channel layer 104 and facilitate high-speed transmission of carriers.

[0039] In some embodiments, in the first direction X, the sidewall of the first source 102 is flush with one of the opposite sidewalls of the first base layer 120, that is, the first base layer 120 exposes the sidewall of the first source 102, thereby facilitating the connection of the first source 102 to the read word line or the read bit line.

[0040] In some embodiments, in the first direction X, the sidewall of the first drain 103 is flush with the other of the opposite sidewalls of the first base layer 120, that is, the first base layer 120 exposes the sidewall of the first drain 103, thereby facilitating the connection of the first drain 103 to the read word line or the read bit line.

[0041] In some embodiments, the first transistor 100 may further include a first dielectric layer 105. The first dielectric layer 105 covers the bottom surface of the first gate 101 arranged along the second direction Y and surrounds the sidewalls in contact with the bottom surface arranged along the second direction Y. The first dielectric layer 105 is located between the first gate 101 and the first channel layer 104. The provision of the first dielectric layer 105 can prevent direct contact between the first gate 101 and the first channel layer 104, thereby preventing carriers from flowing directly to the first gate 101.

[0042] In some embodiments, the material of the first dielectric layer 105 may be hafnium oxide or silicon oxide.

[0043] It can be understood that the specific material of the first dielectric layer 105 can be set according to the material of the first gate 101. For example, the material of the first gate 101 is a metal material, such as tungsten, etc., and the material of the first dielectric layer 105 can be hafnium oxide. When the material of the first gate 101 is a metal material, the gate dielectric layer will generate a large leakage current. Therefore, the material of the first dielectric layer 105 is set to hafnium oxide. Hafnium oxide has a higher dielectric constant, which can reduce the leakage current of the first dielectric layer 105; when the material of the first gate 101 is polycrystalline silicon, the material of the first dielectric layer 105 can be silicon oxide. When the material of the first gate 101 is polycrystalline silicon, the gate dielectric layer will not generate a large leakage current. Therefore, even if the material of the first dielectric layer 105 is set to silicon oxide, the gate dielectric layer will not generate a large leakage current.

[0044] It should be noted that the dielectric constant here refers to: relative dielectric constant, with the value of the absolute dielectric constant of free space or vacuum being considered as the standard. The relative dielectric constant refers to the ratio of the absolute dielectric constant of any material to the absolute dielectric constant of free space or vacuum.

[0045] In some embodiments, the semiconductor structure may further include a second base layer 130 and a third base layer 140 , and the second gate 111 of the second transistor 110 is located between the second base layer 130 and the third base layer 140 .

[0046] In some embodiments, the semiconductor structure may further include a second sacrificial layer 150. In the second direction Y, the top surface of the second sacrificial layer 150 is in contact with the bottom surface of the third base layer 140, and the bottom surface of the second sacrificial layer 150 is in contact with the top surface of the second base layer 130. The second sacrificial layer 150 can support the second base layer 130 and the third base layer 140, thereby providing support for forming the second transistor 110 and preventing the second base layer 130 and the third base layer 140 from collapsing or deforming.

[0047] In some embodiments, the materials of the second base layer 130 and the third base layer 140 may be the same. In some embodiments, the materials of the second base layer 130 and the third base layer 140 may be the same as those of the first base layer 120 .

[0048] In some embodiments, the second channel layer 114 can be an integral structure with the second source electrode 112 and the second drain electrode 113. In other words, the second source electrode 112 and the second drain electrode 113 are formed simultaneously during the formation of the second channel layer 114. Providing the second channel layer 114, the second source electrode 112, and the second drain electrode 113 as an integral structure can facilitate the transmission of carriers among the second source electrode 112, the second channel layer 114, and the second drain electrode 113.

[0049] In some embodiments, the material of the second channel layer 114 may also be the same as that of the first channel layer 104 , for example, IGZO material.

[0050] It can be understood that the second channel layer 114 of the second transistor 110 surrounds the second gate 111 and also covers the side walls of the second base layer 130 and the third base layer 140 arranged along the first direction X. The transmission path of the carriers in the second transistor 110 is from the second base layer 130 into the second channel layer 114 connected to the second base layer 130, then surrounds the second gate 111, and finally flows to the second channel layer 114 connected to the third base layer 140. The channel length of the second transistor 110 can be adjusted by adjusting the thickness of the semiconductor structure on the top surface of the first transistor 100, thereby improving the short channel effect of the second transistor 110.

[0051] In some embodiments, the channel length of the second transistor 110 may be greater than the channel length of the first transistor 100 .

[0052] It should be noted that, taking the second gate 111 formed as a cylinder as an example, the channel length of the second transistor 110 here can be the width of the side wall of the second base layer 130 along the first direction X in the second direction Y plus the side perimeter of the second gate 111 divided by 2 plus the width of the side wall of the third base layer 140 along the first direction X in the second direction Y.

[0053] Taking the cylindrical first gate 101 as an example, the channel length of the first transistor 100 here can be: the width of the sidewall of the first base layer 120 in the second direction Y in the first direction X plus the side perimeter of the first gate 101 divided by two.

[0054] In some embodiments, in the second direction Y, the top surface of the second source electrode 112 is flush with the top surface of the third base layer 140, and the second drain electrode 113 is in contact with the first gate electrode 101. By setting the top surface of the second source electrode 112 flush with the top surface of the third base layer 140, it is convenient to connect to the write bit line, and further facilitate the input of the data signal to the second transistor 110 through the write word line.

[0055] In some embodiments, the second transistor 110 may further include a second dielectric layer 115. The second dielectric layer 115 covers the sidewalls of the second gate 111 arranged along the first direction X and surrounds the bottom and top surfaces in contact with the sidewalls arranged along the first direction X. The second dielectric layer 115 is located between the second gate 111 and the second channel layer 114. The provision of the second dielectric layer 115 can prevent carriers from flowing directly to the second gate 111.

[0056] In some embodiments, the material of the second dielectric layer 115 can be the same as that of the first dielectric layer 105. For example, if the second gate 111 is made of a metal material, the material of the second dielectric layer 115 can be hafnium oxide; if the second gate 111 is made of polysilicon, the material of the second dielectric layer 115 can be silicon oxide.

[0057] In some embodiments, the second transistor 110 may include a conductive plug 160 , which is in contact with a sidewall of the second gate 111 arranged along the first direction X and is spaced apart from the first gate 101 . The conductive plug 160 may be provided to lead out the second gate 111 , thereby providing a data signal to the second gate 111 through the conductive plug 160 .

[0058] In some embodiments, the conductive plug 160 and the second gate 111 may be integrally formed, or the material of the conductive plug 160 may be the same as that of the second gate 111. By providing the conductive plug 160 and the second gate 111 as an integrally formed structure, or by providing the conductive plug 160 and the second gate 111 with the same material, the difference between the conductive plug 160 and the second gate 111 can be reduced, thereby reducing abnormalities in data transmission between the conductive plug 160 and the second gate 111 and improving the reliability of data transmission between the conductive plug 160 and the second gate 111.

[0059] In some embodiments, the conductive plug 160 can cover the entire side wall of the second gate 111 arranged along the first direction X. By setting the conductive plug 160 to cover the entire side wall of the second gate 111 arranged along the first direction X, the contact area between the conductive plug 160 and the second gate 111 can be increased, and the contact resistance between the conductive plug 160 and the second gate 111 can be reduced.

[0060] In some embodiments, the conductive plug 160 may also only cover a portion of the sidewall of the second gate 111 arranged along the first direction X. The area of ​​the portion of the sidewall of the second gate 111 arranged along the first direction X can be adjusted according to actual needs and actual process steps.

[0061] In some embodiments, the conductive plug 160 may also serve as a portion of the second gate 111 , thereby directly connecting the write bit line to the second gate 111 .

[0062] In some embodiments, the second transistor 110 may further include a first insulating layer 170, which is located between the conductive plug 160 and the first gate 101. The first insulating layer 170 can be provided to isolate the first conductive plug 160 from the first gate 101, thereby preventing electrical connection between the first gate 101 and the second gate 111, thereby improving the reliability of the semiconductor structure.

[0063] In some embodiments, the semiconductor structure may further include: a fourth base layer 180, which may also serve as a support layer for the second base layer 130 and the third base layer 140, thereby avoiding deformation between the second base layer 130 and the third base layer 140, thereby improving the reliability of the semiconductor structure.

[0064] In some embodiments, the second transistor 110 may further include a second insulating layer 190. The second insulating layer 190 is located between the conductive plug 160 and the second source 112, and is also located between the first insulating layer 170 and the second drain 113. The second insulating layer 190 can be provided to isolate the conductive plug 160 from the second source 112 and the second drain 113, thereby improving the insulation between the conductive plug 160 and the second source 112 and the second drain 113.

[0065] In some embodiments, the material of the second insulating layer 190 may be silicon nitride.

[0066] In some embodiments, the top surface of the second insulating layer 190 can be flush with the top surface of the third base layer 140 and cover the side wall of the second dielectric layer 115 in the first direction X. By setting the second insulating layer 190, the second dielectric layer 115 can be covered in the semiconductor structure, which can prevent the second dielectric layer 115 from being exposed to the air and prevent the oxygen in the air from affecting the second dielectric layer 115.

[0067] In the embodiment of the present disclosure, a first transistor 100 is provided to include a first gate 101 and a first source 102 and a first drain 103 arranged along a first direction X, and the first transistor 100 is used as a read transistor, and the first gate 101 is equivalent to a capacitor. A second transistor 110 is provided to include a second gate 111 and a second source 112 and a second drain 113 arranged along a second direction Y, and the second transistor 110 is used as a write transistor. The second drain 113 is in contact with and connected to the first gate 101, thereby providing charge to the first gate 101. By surrounding the second gate 111 and being in contact and electrically connected to the second source 112 and the second drain 113, the carrier transmission path of the second channel layer 114 can be extended along the second direction Y, thereby increasing the channel length of the second transistor 110, reducing the short channel effect, and improving the reliability of the semiconductor structure.

[0068] Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above-mentioned embodiments can refer to the corresponding description of the above-mentioned embodiments and will not be repeated below.

[0069] In some embodiments, the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure may include: forming a first transistor 100, the first transistor 100 including: a first gate 101 and a first source 102 and a first drain 103 located on opposite sides of the first gate 101 along the first direction X, the first transistor 100 also including: a first channel layer 104, the first channel layer 104 surrounds the sidewalls and bottom surface of the first gate 101, and is in contact and electrically connected to the first source 102 and the first drain 103.

[0070] In some embodiments, the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure may include: forming a second transistor 110, the second transistor 110 being located above the first transistor 100, the second transistor 110 including: a second gate 111 and a second source 112 and a second drain 113 located on opposite sides of the second gate 111 along the second direction Y, the second drain 113 being in contact with and connected to the first gate 101, the second transistor 110 also including: a second channel layer 114, the second channel layer 114 surrounding the bottom surface, the top surface, and one of the two sidewalls arranged along the first direction X of the second gate 111, and being in contact and electrically connected to the second source 112 and the second drain 113.

[0071] By forming a first transistor 100 having a first source 102 and a first drain 103 arranged along a first direction X, the first transistor 100 can be used as a read transistor, and the first gate 101 can be equivalent to a capacitor. By forming a second transistor 110 having a second source 112 and a second drain 113 arranged along a second direction Y, the second transistor 110 can be used as a write transistor. The second drain 113 is in contact with and connected to the first gate 101, thereby providing charge to the first gate 101. By surrounding the second gate 111 with a second channel layer 114 and being in contact and electrically connected to the second source 112 and the second drain 113, the carrier transmission path of the second channel layer 114 can be extended along the second direction Y, thereby increasing the channel length of the second transistor 110, reducing the short channel effect, and improving the reliability of the semiconductor structure.

[0072] In some embodiments, reference Figures 2 to 7The method for forming the first transistor 100 may include: forming a stack structure 200, the stack structure 200 including a first base layer 120, a first sacrificial layer 210, a second base layer 130, a second sacrificial layer 150 and a third base layer 140 stacked in sequence; etching the stack structure 200 to form a first groove 230 penetrating the stack structure 200 along the second direction Y; etching the first sacrificial layer 210 exposed along the first groove 230 to form a second groove 240 penetrating the stack structure 200 in the first direction X; forming the first transistor 100, the first source 102 and the first drain 103 filling the second groove 240, the first channel layer 104 covering the inner wall of the first groove 230, the first gate 101 being located in the first groove 230, and the top surface of the first gate 101 arranged along the second direction Y being flush with the bottom surface of the second base layer 130 arranged along the second direction Y.

[0073] By etching the stacked structure 200, space is provided for forming the first gate 101 and the first channel layer 104 of the first transistor 100, and by etching the first sacrificial layer 210, space is provided for forming the first source 102 and the first drain 103 of the first transistor 100, thereby forming the first transistor 100 having the first source 102 and the first drain 103 arranged along the first direction X.

[0074] refer to Figure 2 , forming a stacked structure 200 .

[0075] In some embodiments, the materials of the first base layer 120 , the second base layer 130 , and the third base layer 140 may be the same.

[0076] In some embodiments, the first sacrificial layer 210 and the second sacrificial layer 150 may be made of the same material, for example, both may be insulating materials, such as silicon oxide, silicon nitride, etc.

[0077] refer to Figure 3 , forming a mask layer 250 , the mask layer 250 covers the top surfaces of the stack structure 200 on two opposite sides in the second direction, thereby providing a process basis for subsequently etching the stack structure 200 to form the first groove 230 .

[0078] In some embodiments, the mask layer 250 can be a photoresist, and the photoresist can be a positive photoresist and a negative photoresist. Positive photoresist means that under the irradiation of an exposure source such as ultraviolet rays, the illuminated part is decomposed and the unexposed part is retained. Negative photoresist means that under the irradiation of an exposure source such as ultraviolet rays, the illuminated part is retained and the unexposed part is decomposed. The resolution of positive photoresist is better than that of negative photoresist, and negative photoresist has strong heat resistance. The corresponding material can be selected according to actual needs.

[0079] refer to Figure 4The stack structure 200 is etched using the mask layer 250 as a mask to form a first groove 230 . After the first groove 230 is formed, the mask layer 250 can be removed.

[0080] refer to Figure 5 The first sacrificial layer 210 is etched along the sidewalls of the first sacrificial layer 210 exposed in the first groove 230 and arranged along the first direction X, thereby removing the first sacrificial layer 210 to form a second groove 240. The second groove 240 is located between the first base layer 120 and the second base layer 130. The formation of the second groove 240 provides a process foundation for forming the first source 102 and the first drain 103.

[0081] refer to Figure 6 and Figure 7 The first transistor 100 may further include: a first dielectric layer 105. After forming the second groove 240, the following steps may be performed: forming a first initial channel layer 260, the first initial channel layer 260 covering the inner wall of the first groove 230; forming a first initial dielectric layer 270, the first initial dielectric layer 270 covering the surface of the first initial channel layer 260; forming a first initial gate 280, the first initial gate 280 filling the first groove 230; etching the first initial channel layer 260, the first initial dielectric layer 270, and the first initial gate 280, leaving the remaining first initial channel layer 260 as the first channel layer 104, the remaining first initial dielectric layer 270 as the first dielectric layer 105, and the remaining first initial gate 280 as the first gate 101. By first depositing and then etching back, the quality of the formed first channel layer 104, the first dielectric layer 105, and the first gate 101 can be improved.

[0082] refer to Figure 6 , forming a first initial channel layer 260, the first initial channel layer 260 fills the second groove 240 and also covers the inner wall of the first groove 230, the formed first initial dielectric layer 270 covers the surface of the first initial channel layer 260, and the formed first initial gate 280 fills the first groove 230 and also covers the surface of the first initial dielectric layer 270.

[0083] refer to Figure 7 , the first initial channel layer 260, the first initial dielectric layer 270 and the first initial gate 280 are etched back, and the top surface of the remaining first channel layer 104 is flush with the bottom surface of the second base layer 130, the top surface of the remaining first dielectric layer 105 is flush with the top surface of the first channel layer 104, and the top surface of the remaining first gate 101 is flush with the top surface of the first dielectric layer 105.

[0084] It should be noted that the term "flush" here may refer to being completely flush, or the height difference between the film layers being within an allowable error range.

[0085] It can be understood that the first channel layer 104 formed here includes the first source 102 and the first drain 103 , that is, the first source 102 , the first drain 103 and the first channel layer 104 are an integrated structure.

[0086] refer to Figures 8 to 16 and Figure 1 The method for forming the second transistor 110 includes: after forming the first transistor 100, epitaxially growing the second base layer 130, the second sacrificial layer 150, and the third base layer 140 along the exposed first groove 230 to fill the first groove 230; etching the second base layer 130, the second sacrificial layer 150, and the third base layer 140 that fill the first groove 230 to form a third groove 290; etching the second sacrificial layer 150 on one side of the third groove 290 to form a fourth groove 300; forming the second transistor 110, wherein a portion of the second gate 111 is located in the fourth groove 300, a portion of the second gate 111 is located in the third groove 290, the second source 112 and the second drain 113 are located in the third groove 290 and cover the sidewalls of the second base layer 130 and the third base layer 140 exposed in the third groove 290 and on the same side as the third groove 290, and the second channel layer 114 covers the inner wall of the fourth groove 300 and is in contact with the second source 112 and the second drain 113.

[0087] By forming a second transistor 110 having a second source 112 and a second drain 113 arranged along the second direction Y, and the second source 112 and the second drain 113 formed here are an integrated structure with the second channel layer 114, the depth of the fourth groove 300 in the second direction Y can be controlled, and the size of the formed second channel layer 114 can be controlled, thereby increasing the channel length of the second transistor 110, reducing the short channel effect, and improving the reliability of the semiconductor structure.

[0088] refer to Figure 8 , epitaxial growth is performed on the second base layer 130 , the second sacrificial layer 150 and the third base layer 140 .

[0089] refer to Figure 9 , the second base layer 130 , the second sacrificial layer 150 and the third base layer 140 are etched to form a third groove 290 , where the third groove 290 exposes the surface of the first gate 101 .

[0090] In some embodiments, the width of the third groove 290 in the first direction X is smaller than the width of the first groove 230 in the first direction X. It is understood that by setting the width of the third groove 290 smaller than the width of the first groove 230, the surface of the first gate 101 exposed by the third groove 290 can be reduced, thereby preventing the subsequently formed second channel layer 114 from contacting and connecting with the first channel layer 104, thereby improving the reliability of the semiconductor structure.

[0091] refer to Figure 10 After forming the third groove 290, the second sacrificial layer 150 on one side of the third groove 290 can be etched to form a fourth base layer 180. By forming the fourth base layer 180, it is possible to avoid the fourth groove 300 being formed unexpectedly during the subsequent formation of the fourth groove 300.

[0092] In other words, if the second sacrificial layer 150 on one side of the third groove 290 is not etched and the fourth base layer 180 is not formed before forming the fourth groove 300 , then in the subsequent process of forming the fourth groove 300 , the fourth groove 300 will be formed on both opposite sides of the third groove 290 .

[0093] refer to Figure 11 , forming a fourth groove 300.

[0094] refer to Figures 12 to 16 The second transistor 110 may further include a second dielectric layer 115. After forming the fourth groove 300, the following steps may be performed: forming a second initial channel layer 310, wherein the second initial channel layer 310 covers the inner wall of the fourth groove 300, and the second initial channel layer 310 also covers the surfaces of the second base layer 130 and the third base layer 140 facing the third groove 290, and the second initial channel layer 310 also covers the inner wall of the third groove 290; etching the second initial channel layer 310, and the remaining second initial channel layer 310 serves as the second channel layer 114; forming a second initial dielectric layer 320, and the second initial dielectric layer 320 covers the surface of the second initial channel layer 310; forming a second initial gate 330, and the second initial gate 330 fills the third groove 290 and the fourth groove 300; etching the second initial dielectric layer 320 and the second initial gate 330, and the remaining second initial dielectric layer 320 serves as the second dielectric layer 115, and the remaining second initial gate 330 serves as the second gate 111.

[0095] The second dielectric layer 115 can be provided to isolate the second gate 111 from the second source 112, and can also isolate the second gate 111 from the second drain 113. By first forming the second initial channel layer 310, the second initial dielectric layer 320, and the second initial gate 330, and then etching back to form the second channel layer 114, the second dielectric layer 115, and the second gate 111, the reliability of the formed second channel layer 114, the second dielectric layer 115, and the second gate 111 can be improved.

[0096] refer to Figure 12 , a second preliminary channel layer 310 is formed, and the second preliminary channel layer 310 covers the inner walls of the third groove 290 and the fourth groove 300 .

[0097] refer to Figure 13, the second preliminary channel layer 310 is etched, and the remaining second preliminary channel layer 310 serves as the second channel layer 114 .

[0098] refer to Figure 14 , forming a second initial dielectric layer 320 and a second initial gate 330.

[0099] refer to Figure 15 Before etching the second initial gate 330, the process further includes etching a portion of the second initial dielectric layer 320 and forming a second insulating layer 190. The second insulating layer 190 is located between the second initial gate 330 and the second initial channel layer 310. The formation of the second insulating layer 190 can enhance the insulation between the second gate 111 and the second source 112, and between the second gate 111 and the second drain 113, which will be formed subsequently.

[0100] refer to Figure 16 , the second preliminary gate 330 is etched to form the second gate 111 .

[0101] refer to Figure 17 and Figure 1 After forming the second gate 111, the following steps may be performed: forming a first insulating layer 170, the first insulating layer 170 being located in the third groove 290 and on the surface of the first gate 101; and forming a conductive plug 160, the conductive plug 160 being located on the top surface of the first insulating layer 170, filling the third groove 290, and being in contact with the second gate 111. The formation of the first insulating layer 170 can isolate the subsequently formed conductive plug 160 from the first gate 101, thereby preventing the conductive plug 160 from making electrical contact with the first gate 101.

[0102] refer to Figures 18 to 24 and Figure 1The method for forming the first transistor 100 and the second transistor 110 may further include: forming a first base layer 120 and a first sacrificial layer 210 arranged in a stacked manner; etching the first base layer 120 and the first sacrificial layer 210 to form a fifth groove 340; forming the first transistor 100, the first gate 101 is located in the fifth groove 340, the first source 102 and the first drain 103 are located on the top surface of the first base layer 120, the top surface of the first gate 101 is flush with the top surfaces of the first source 102 and the first drain 103, and the first channel layer 104 covers the inner wall of the fifth groove 340; forming a second base layer 130, a second sacrificial layer 150 and a third base layer 140 arranged in a stacked manner, the second base layer 130 is located in the fifth groove 340, and the first source 102 and the first drain 103 are located on the top surface of the first base layer 120. On the top surface of the first transistor 100; etching the second base layer 130, the second sacrificial layer 150 and the third base layer 140 to form a sixth groove 350, the sixth groove 350 exposes the top surface of the first gate 101; etching the second sacrificial layer 150 along the sixth groove 350 to form a seventh groove 360; forming a second transistor 110, part of the second gate 111 is located in the seventh groove 360, part of the second gate 111 is located in the sixth groove 350, the second source 112 is located on the surface of the third base layer 140 exposed by the sixth groove 350, the second drain 113 is located on the surface of the second base layer 130 exposed by the sixth groove 350, and the second channel layer 114 covers the inner wall of the seventh groove 360.

[0103] refer to Figure 18 , forming a first base layer 120 and a first sacrificial layer 210 .

[0104] refer to Figure 19 , forming a fifth groove 340.

[0105] refer to Figure 20 , forming the first transistor 100 , and before forming the first transistor 100 , the first sacrificial layer 210 may be removed.

[0106] refer to Figure 21 , forming a second base layer 130 , a second sacrificial layer 150 and a third base layer 140 .

[0107] refer to Figure 22 , forming a sixth groove 350.

[0108] refer to Figure 23 , the second sacrificial layer 150 is etched along the sixth groove 350 to form a seventh groove 360 ​​.

[0109] In some embodiments, before forming the seventh groove 360 ​​, the method may further include etching the second sacrificial layer 150 on one side of the sixth groove 350 , and may also form a fourth base layer 180 .

[0110] refer to Figure 24, forming a second initial gate 330 and forming a second insulating layer 190 , wherein the second insulating layer 190 is located between the second initial gate 330 and the second source 112 , and the second insulating layer 190 is also located between the second initial gate 330 and the second drain 113 .

[0111] By forming a first transistor 100 having a first source 102 and a first drain 103 arranged along a first direction X, the first transistor 100 can be used as a read transistor, and the first gate 101 can be equivalent to a capacitor. By forming a second transistor 110 having a second source 112 and a second drain 113 arranged along a second direction Y, the second transistor 110 can be used as a write transistor. The second drain 113 is in contact with and connected to the first gate 101, thereby providing charge to the first gate 101. By surrounding the second gate 111 with a second channel layer 114 and being in contact and electrically connected to the second source 112 and the second drain 113, the carrier transmission path of the second channel layer 114 can be extended along the second direction Y, thereby increasing the channel length of the second transistor 110, reducing the short channel effect, and improving the reliability of the semiconductor structure.

[0112] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: A first transistor is located in the first groove, the first groove extending along the second direction, the first transistor comprising: a first gate and a first source and a first drain located on opposite sides of the first gate along the first direction, the first transistor further comprising: a first channel layer, the first channel layer surrounding the sidewalls and bottom surface of the first gate and being in electrical contact with the first source and the first drain, the first direction being perpendicular to the second direction; The second transistor is located in the fourth groove, which extends along the first direction. The second transistor is located above the first transistor. The second transistor includes: a second gate and a second source and a second drain located on opposite sides of the second gate along the second direction. The second drain is in contact with the first gate. The second transistor also includes: a second channel layer, which surrounds the bottom surface, the top surface and one of the two sidewalls arranged along the first direction of the second gate, and is in contact and electrically connected with the second source and the second drain.

2. The semiconductor structure according to claim 1, wherein: The first channel layer, the first source electrode, and the first drain electrode are an integrated structure, and the second channel layer, the second source electrode, and the second drain electrode are an integrated structure.

3. The semiconductor structure according to claim 1, wherein: The first transistor further includes: A first dielectric layer covers the bottom surface of the first gate arranged along the second direction and surrounds the sidewall in contact with the bottom surface arranged along the second direction, and the first dielectric layer is located between the first gate and the first channel layer.

4. The semiconductor structure according to claim 1, wherein: The material of the first channel layer is the same as that of the second channel layer.

5. The semiconductor structure according to claim 1, wherein: The second transistor includes a conductive plug, which is in contact with a sidewall of the second gate arranged along the first direction and is spaced apart from the first gate.

6. The semiconductor structure according to claim 5, wherein: The conductive plug covers the entire sidewall of the second gate arranged along the first direction.

7. The semiconductor structure according to claim 5, wherein: The second transistor further includes a first insulating layer located between the conductive plug and the first gate.

8. The semiconductor structure according to claim 7, wherein: The second transistor further includes a second insulating layer, wherein the second insulating layer is located between the conductive plug and the second source, and the second insulating layer is also located between the first insulating layer and the second drain.

9. The semiconductor structure according to claim 1, wherein: The second transistor further includes: A second dielectric layer covers the sidewalls of the second gate arranged along the first direction and surrounds the bottom surface and the top surface contacting the sidewalls arranged along the first direction, and the second dielectric layer is located between the second gate and the second channel layer.

10. A method for manufacturing a semiconductor structure, characterized in that: include: A first transistor is formed in the first groove, the first groove extending along the second direction, the first transistor comprising: a first gate and a first source and a first drain located on opposite sides of the first gate along the first direction, the first transistor further comprising: a first channel layer, the first channel layer surrounding the sidewalls and bottom surface of the first gate and being in contact and electrically connected to the first source and the first drain, the first direction being perpendicular to the second direction; A second transistor is formed in the fourth groove, the fourth groove extending along the first direction, the second transistor is located above the first transistor, the second transistor includes: a second gate and a second source and a second drain located on opposite sides of the second gate along the second direction, the second drain is in contact with the first gate, and the second transistor also includes: a second channel layer, the second channel layer surrounds the bottom surface, the top surface and one of the two sidewalls arranged along the first direction of the second gate, and is in contact and electrically connected with the second source and the second drain.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The method of forming the first transistor includes: forming a stacked structure, the stacked structure comprising a first base layer, a first sacrificial layer, a second base layer, a second sacrificial layer, and a third base layer stacked in sequence; Etching the stack structure to form the first groove penetrating the stack structure along the second direction; Etching the first sacrificial layer along the first groove exposed by the first groove to form a second groove penetrating the stack structure in the first direction; The first transistor is formed, the first source and the first drain fill the second groove, the first channel layer covers the inner wall of the first groove, the first gate is located in the first groove, and the top surface of the first gate arranged along the second direction is flush with the bottom surface of the second base layer arranged along the second direction.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The first transistor further includes a first dielectric layer, and after forming the second groove, further includes: forming a first initial channel layer, wherein the first initial channel layer covers an inner wall of the first groove; forming a first initial dielectric layer, wherein the first initial dielectric layer covers a surface of the first initial channel layer; forming a first initial gate, wherein the first initial gate completely fills the first groove; The first initial channel layer, the first initial dielectric layer, and the first initial gate are etched, and the remaining first initial channel layer serves as the first channel layer, the remaining first initial dielectric layer serves as the first dielectric layer, and the remaining first initial gate serves as the first gate.

13. The method for manufacturing a semiconductor structure according to claim 11, wherein: The method of forming the second transistor includes: After forming the first transistor, epitaxially growing the second base layer, the second sacrificial layer, and the third base layer along the exposed portions of the first groove to completely fill the first groove; Etching the second base layer, the second sacrificial layer, and the third base layer that fill the first groove to form a third groove; Etching the second sacrificial layer on one side of the third groove to form the fourth groove; The second transistor is formed, part of the second gate is located in the fourth groove, part of the second gate is located in the third groove, the second source and the second drain are located in the third groove, and cover the sidewalls of the second base layer and the third base layer exposed by the third groove and on the same side as the third groove, and the second channel layer covers the inner wall of the fourth groove and is in contact with the second source and the second drain.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: The second transistor further includes a second dielectric layer, and after forming the fourth groove, the following steps are further included: forming a second initial channel layer, wherein the second initial channel layer covers the inner wall of the fourth groove, the second initial channel layer further covers the surfaces of the second base layer and the third base layer facing the third groove, and the second initial channel layer further covers the inner wall of the third groove; etching the second initial channel layer to leave the second initial channel layer as the second channel layer; forming a second initial dielectric layer, wherein the second initial dielectric layer covers a surface of the second channel layer; forming a second initial gate, wherein the second initial gate completely fills the third groove and the fourth groove; The second initial dielectric layer and the second initial gate are etched, and the remaining second initial dielectric layer serves as the second dielectric layer, and the remaining second initial gate serves as the second gate.

15. The method for manufacturing a semiconductor structure according to claim 14, wherein: After forming the second gate, the method further includes: forming a first insulating layer, wherein the first insulating layer is located in the third groove and on a surface of the first gate; A conductive plug is formed, where the conductive plug is located on a top surface of the first insulating layer, fills the third groove, and is in contact with and connected to the second gate.

16. The method for manufacturing a semiconductor structure according to claim 14, wherein: Before etching the second initial gate, the method further includes etching a portion of the second initial dielectric layer to form a second insulating layer, where the second insulating layer is located between the second initial gate and the second initial channel layer.

17. The method for manufacturing a semiconductor structure according to claim 10, wherein: The method of forming the first transistor and the second transistor includes: forming a first base layer and a first sacrificial layer that are stacked; Etching the first base layer and the first sacrificial layer to form a fifth groove; forming the first transistor, wherein the first gate is located in the fifth groove, the first source and the first drain are located on a top surface of the first base layer, the top surface of the first gate is flush with the top surfaces of the first source and the first drain, and the first channel layer covers an inner wall of the fifth groove; forming a second base layer, a second sacrificial layer, and a third base layer in a stacked arrangement, wherein the second base layer is located on a top surface of the first transistor; Etching the second base layer, the second sacrificial layer, and the third base layer to form a sixth groove, wherein the sixth groove exposes a top surface of the first gate; etching the second sacrificial layer along the sixth groove to form a seventh groove; The second transistor is formed, part of the second gate is located in the seventh groove, part of the second gate is located in the sixth groove, the second source is located on the surface of the third base layer exposed by the sixth groove, the second drain is located on the surface of the second base layer exposed by the sixth groove, and the second channel layer covers the inner wall of the seventh groove.

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