Memory cell array layout structure applied to non-volatile memory

Abstract

The invention discloses a memory cell array layout structure applied to a non-volatile memory. A memory cell array of the non-volatile memory includes a plurality of memory cells. Each storage unit comprises a capacitor, an erase gate element, a selection transistor, a floating gate transistor and a switching transistor. Furthermore, a plurality of well regions are formed on the semiconductor substrate, and a floating gate transistor is formed on the semiconductor substrate. The position of the well region and the shape of the floating gate are specially designed. Furthermore, at least two kinds of memory units with different shapes are designed and configured on the semiconductor plate. Therefore, the layout area (layout area) of the memory cell array layout structure can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to a storage unit of a non-volatile memory, and more particularly to a storage unit array layout structure used in the non-volatile memory to reduce the size of the non-volatile memory. Background Art

[0002] Please refer to Figure 1A and Figure 1B , which shows a memory cell of a conventional non-volatile memory and its equivalent circuit. The memory cell is disclosed in US Pat. No. US11,164,880B2.

[0003] like Figure 1A As shown, the semiconductor substrate includes a P-type well region PW, a first N-type well region NW1 and a second N-type well region NW2. The first N-type well region NW1 and the second N-type well region NW2 are formed on two sides of the P-type well region PW. Furthermore, the first gate G1 and the second gate G2 cover the P-type well region PW. In addition, the gate FG is a floating gate, and the floating gate FG covers the P-type well region PW, the first N-type well region NW1 and the second N-type well region NW2. The material of the floating gate FG, the first gate G1 and the second gate G2 is polysilicon.

[0004] Next, after the p-type ion implantation, a first p-type doping region 17 and a second p-type doping region 18 are formed in the second N-type well region NW2. In addition, after the n-type ion implantation, a first n-type doping region 11, a second n-type doping region 12, a third n-type doping region 13 and a fourth n-type doping region 14 are formed in the P-type well region PW.

[0005] Furthermore, the wire (source line) SL is connected to the first n-type doping region 11; the wire (bit line) BL is connected to the fourth n-type doping region 14; the wire (erase line) EL is connected to the first p-type doping region 17 and the second p-type doping region 18; the wire (coupling line) CL is connected to the first N-type well region NW1; the wire (select line) SGL is connected to the first gate G1; and the wire (word line) WL is connected to the second gate G2.

[0006] like Figure 1A As shown, the floating gate FG extends to the first N-type well region NW1, and the floating gate FG and the first N-type well region form a capacitor C1. That is, one end of the capacitor C1 is connected to the floating gate FG, and the other end of the capacitor C1 is connected to the coupling line CL.

[0007] Furthermore, the floating gate FG extends to the second N-type well region NW2, and the floating gate FG, the second N-type well region NW2, the first p-type doping region 17, and the second p-type doping region 18 form a p-type transistor Mp. That is, the gate of the p-type transistor Mp is connected to the floating gate FG, and the drain and source of the p-type transistor Mp are connected to the erase line EL. Furthermore, the p-type transistor Mp can also be called an erase gate element, and the floating gate FG, the second N-type well region NW2, the first p-type doping region 17, and the second p-type doping region 18 are used as an exit path for electrons.

[0008] In addition, the P-type well region PW includes a first n-type doping region 11, a second n-type doping region 12, a third n-type doping region 13, and a fourth n-type doping region 14. A first gate G1 is formed on the surface between the first n-type doping region 11 and the second n-type doping region 12. A floating gate FG is formed on the surface between the second n-type doping region 12 and the third n-type doping region 13. A gate G2 is formed on the surface between the third n-type doping region 13 and the fourth n-type doping region 14. That is, the P-type well region PW includes a first n-type transistor Ms, a second n-type transistor Mf, and a third n-type transistor Msw.

[0009] The first n-type transistor Ms is a select transistor, and its first gate G1 is connected to the select line SGL. In addition, the first n-type doping region 11 is connected to the source line SL. Furthermore, the second n-type doping region 12 is shared by the first n-type transistor Ms and the second n-type transistor Mf, and can be regarded as the n-type doping region of the first n-type transistor Ms and the n-type doping region of the second n-type transistor Mf are connected to each other.

[0010] The second n-type transistor Mf is a floating gate transistor, and its gate FG is a floating gate. Furthermore, the third n-type doping region 13 is shared by the second n-type transistor Mf and the third n-type transistor Msw.

[0011] The third n-type transistor Msw is a switch transistor, a second gate G2 of which is connected to the word line WL, and a fourth n-type doping region 14 is connected to the bit line BL.

[0012] like Figure 1BThe memory cell 100 shown. The gate of the select transistor Ms is connected to the select line SGL, and the first source / drain terminal is connected to the source line SL. The first source / drain terminal of the floating gate transistor Mf is connected to the second source / drain terminal of the select transistor Ms. The gate of the switch transistor Msw is connected to the word line WL, the first source / drain terminal is connected to the second source / drain terminal of the floating gate transistor Mf, and the second source / drain terminal is connected to the bit line BL. The capacitor C1 is connected between the floating gate FG and the coupling line CL. The gate of the p-type transistor Mp is connected to the floating gate FG, and the first source / drain terminal and the second source / drain terminal of the p-type transistor Mp are connected to the erase line EL.

[0013] Basically, a non-volatile memory is composed of a plurality of memory cells forming a memory cell array. That is, the main purpose of the present invention is to design a plurality of memory cells on a semiconductor substrate through an appropriate layout structure and to reduce the layout area of ​​the non-volatile memory. Summary of the invention

[0014] The present invention relates to a memory cell array layout structure of a non-volatile memory, comprising: a first first-type well region, a second first-type well region, a first second-type well region and a second second-type well region; wherein the second first-type well region is located between the first second-type well region and the second second-type well region, and the first second-type well region is located between the first first-type well region and the second first-type well region; a first gate, a second gate and a first floating gate are formed on the surface of the second second-type well region; wherein the first floating gate extends from the second second-type well region through the second first-type well region and the first second-type well region to the first first-type well region; a first first-type doping region, a second first-type doping region, a third first-type doping region and a fourth first-type doping region formed on the surface of the second second-type well region; wherein the first gate is located on the surface between the first first-type doping region and the second first-type doping region, the first floating gate is located on the surface between the second first-type doping region and the third first-type doping region, and the second gate is located on the surface between the third first-type doping region and the fourth first-type doping region; a first second-type doping region is formed in the first first-type well region, and the first second-type doping region is adjacent to the first floating gate; a first contact terminal is formed in the first second-type doping region, and the first contact terminal is connected to an erase line; and a second contact terminal is formed in the second first-type well region, and the second contact terminal is connected to a coupling line.

[0015] The present invention relates to a memory cell array layout structure of a non-volatile memory, comprising: a first first-type well region, a second first-type well region, a first second-type well region, a second second-type well region and a third second-type well region; wherein the second first-type well region is located between the first second-type well region and the second second-type well region, the first second-type well region is located between the first first-type well region and the second first-type well region, and the first first-type well region is located between the first second-type well region and the third second-type well region; a first gate, a second gate and a first floating gate are formed on the surface of the third second-type well region; wherein the first floating gate extends from the third second-type well region through the first first-type well region and the first second-type well region to the second first-type well region; a first first-type doping region , a second first-type doping region, a third first-type doping region and a fourth first-type doping region are formed on the surface of the third second-type well region; wherein the first gate is located on the surface between the first first-type doping region and the second first-type doping region, the first floating gate is located on the surface between the second first-type doping region and the third first-type doping region, and the second gate is located on the surface between the third first-type doping region and the fourth first-type doping region; a first second-type doping region is formed in the first first-type well region, and the first second-type doping region is adjacent to the first floating gate; a first contact terminal is formed in the first second-type doping region, and the first contact terminal is connected to an erase line; and a second contact terminal is formed in the second first-type well region, and the second contact terminal is connected to a coupling line.

[0016] In order to better understand the above and other aspects of the present invention, preferred embodiments are specifically described below in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A and Figure 1B A storage unit of an existing non-volatile memory and its equivalent circuit diagram;

[0018] Figure 2A and Figure 2B A schematic diagram of a first embodiment of the layout structure of a memory cell array of the present invention;

[0019] Figure 3A and Figure 3B is a schematic diagram of a second embodiment of the layout structure of the memory cell array of the present invention;

[0020] Figure 4A and Figure 4B is a schematic diagram of a third embodiment of the layout structure of the memory cell array of the present invention;

[0021] Figure 5 A modified layout diagram of the second embodiment; and

[0022] Figure 6 This is a modified layout structure diagram of the third embodiment.

[0023] Explanation of symbols

[0024] 11,12,13,14,21,22,23,24,31,32,33,34,41,42,43,44,47,51,52,53,54,61,62,63,64,66,68: n-type doping region

[0025] 17,18,28,38,48,58,67: p-type doped regions

[0026] 100: Storage unit DETAILED DESCRIPTION

[0027] Please refer to Figure 2A and Figure 2B , which illustrates the first embodiment of the layout structure of the memory cell array of the present invention.

[0028] like Figure 2A As shown, staggered P-type well regions PW1, PW2 and N-type well regions NW1, NW2, NW3 are formed below the surface of the semiconductor substrate. Furthermore, 12 memory cells are designed on the P-type well regions PW1, PW2 and N-type well regions NW1, NW2, NW3. 1 ~cell 12 Among them, odd storage cells 1 、cell 3 、cell 5 、cell 7 、cell 9 、cell 11 Designed on N-type well regions NW1, NW2 and P-type well region PW1, even-numbered storage cells 2 、cell 4 、cell 6 、cell 8 、cell 10 、cell 12 Designed on N-type well regions NW2, NW3 and P-type well region PW2. All memory cells 1 ~cell 12 Shared N-type well region NW2. Furthermore, all memory cells 1 ~cell 12 The structure is similar to that of 1 , the rest will not be elaborated.

[0029] like Figure 2AAs shown, in the storage unit cell 1 In the embodiment, N-type well regions NW1 and NW2 are formed on both sides of the P-type well region PW1. The first gate G1 and the second gate G2 cover the P-type well region PW1. In addition, the gate FG is a floating gate, and the floating gate FG covers the P-type well region PW1 and the N-type well regions NW1 and NW2. Among them, the gate FG, the first gate G1 and the second gate G2 include a gate dielectric layer and a polysilicon layer. The gate dielectric layer is formed on the surface of the semiconductor substrate, and the polysilicon layer covers the gate dielectric layer.

[0030] Next, a p-type doping region 28 is formed in the N-type well region NW1. In addition, n-type doping regions 21 to 24 are formed in the P-type well region PW1. Furthermore, a contact terminal is formed on the n-type doping region 21 to connect to the source line SL; a contact terminal is formed on the n-type doping region 24 to connect to the bit line BL; a contact terminal is formed on the p-type doping region 28 to connect to the erase line EL; a contact terminal is formed on the N-type well region NW2 to connect to the coupling line CL; a contact terminal is formed on the first gate G1 to connect to the selection line SGL; and a contact terminal is formed on the second gate G2 to connect to the word line WL.

[0031] like Figure 2A As shown, the floating gate FG extends to the N-type well region NW2, and the floating gate FG and the N-type well region NW2 form a capacitor. That is, one end of the capacitor is connected to the floating gate FG, and the other end of the capacitor is connected to the coupling line CL.

[0032] Furthermore, the floating gate FG extends to the N-type well region NW1, and the floating gate FG, the N-type well region NW1, and the p-type doping region 28 form a p-type transistor. That is, the gate of the p-type transistor is connected to the floating gate FG, and the drain and source of the p-type transistor are connected to the erase line EL. Furthermore, the p-type transistor can also be called an erase gate element, and the floating gate FG, the N-type well region NW1, and the p-type doping region 28 are used as an exit path for electrons.

[0033] In addition, the first gate G1 is located above the surface between the n-type doping region 21 and the n-type doping region 22. The floating gate FG is located above the surface between the n-type doping region 22 and the n-type doping region 23. The second gate G2 is located above the surface between the n-type doping region 23 and the n-type doping region 24. That is, the P-type well region PW1 includes a first n-type transistor, a second n-type transistor, and a third n-type transistor. Among them, the first n-type transistor includes the first gate G1, the n-type doping region 21, and the n-type doping region 22. The second n-type transistor includes the floating gate FG, the n-type doping region 22, and the n-type doping region 23. The third n-type transistor includes the second gate G2, the n-type doping region 23, and the n-type doping region 24.

[0034] The first n-type transistor is a select transistor, a first gate G1 of which is connected to a select line SGL, and an n-type doping region 21 of which is connected to a source line SL.

[0035] The second n-type transistor is a floating gate transistor, and its gate FG is a floating gate.

[0036] The third n-type transistor is a switch transistor, a second gate G2 of which is connected to the word line WL, and an n-type doping region 24 of which is connected to the bit line BL.

[0037] By properly connecting the word lines WL, the bit lines BL, the select lines SGL, the coupling lines CL and the erase lines EL, a memory cell array can be formed. 1 The equivalent circuit is the same as Figure 1B , I will not go into details here.

[0038] like Figure 2B As shown, it is a schematic diagram of a zoomed out layout structure. The non-volatile memory includes a plurality of pages, each of which includes a plurality of memory cells. Among them, the semiconductor substrate includes staggered P-type well regions PW1 to PW5 and N-type well regions NW1 to NW6. Furthermore, the plurality of memory cells of the first page page1 will be designed on the N-type well regions NW1 to NW3 and the P-type well regions PW1 and PW2. The plurality of memory cells of the second page page2 will be designed on the N-type well regions NW4 to NW6 and the P-type well regions PW4 and PW5. In addition, a spacing P-type well region PW3 (spacing PW3) needs to be designed between the N-type well region NW3 of the first page page1 and the N-type well region NW4 of the second page page2.

[0039] In the layout structure of the memory cell array of the first embodiment, each page includes three N-type well regions and two P-type well regions, and a spacing P-type well region needs to be designed between pages. Therefore, in the non-volatile memory, the layout structure of the memory cell array will have a larger layout area.

[0040] In other embodiments of the present invention, the position of the well region and the shape of the floating gate are specially designed so that the layout area occupied by the layout structure of the memory cell array can be effectively reduced.

[0041] Please refer to Figure 3A and Figure 3B , which illustrates the second embodiment of the layout structure of the memory cell array of the present invention. Figure 3A As shown, staggered P-type well regions PW1, PW2 and N-type well regions NW1, NW2 are formed below the surface of the semiconductor substrate. The N-type well region NW2 is located between the P-type well region PW1 and the P-type well region PW2, and the P-type well region PW1 is located between the N-type well region NW1 and the N-type well region NW2. Furthermore, 6 memory cells are designed on the P-type well regions PW1, PW2 and the N-type well regions NW1, NW2. 1 ~cell 6 Among them, the storage unit cell 1 、cell 4 、cell 5 The structure is similar to that of the storage unit cell 2 、cell 3 、cell 6 The following only introduces the storage unit cell 1 、cell 2 , the rest will not be elaborated.

[0042] like Figure 3A As shown, in the storage unit cell 1 In the first gate G 1 With the second gate G 2 Covering the P-type well region PW2. In addition, the first floating gate FG 1 Covering the P-type well regions PW1, PW2 and the N-type well regions NW1, NW2.

[0043] In the storage cell 2 In the third gate G 3 With the fourth gate G 4 Covering the P-type well region PW1. In addition, the second floating gate FG 2 The first floating gate FG covers the P-type well regions PW1, PW2 and the N-type well regions NW1, NW2.1 , the second floating gate FG 2 , the first gate G 1 The second gate G 2 , the third gate G 3 With the fourth gate G 4 Both include a gate dielectric layer and a polysilicon layer. The gate dielectric layer is formed on the surface of the semiconductor substrate, and the polysilicon layer covers the gate dielectric layer.

[0044] Next, a p-type doping region 38 is formed in the N-type well region NW1. In addition, n-type doping regions 31-34 are formed in the P-type well region PW2, and n-type doping regions 41-44 are formed in the P-type well region PW1. Furthermore, a contact terminal is formed on the n-type doping region 31 to connect to the source line SL. 1 ; A contact terminal is formed on the n-type doped region 34 and connected to the line BL 1 ; A contact terminal is formed on the n-type doped region 41 and connected to the source line SL 2 ; A contact terminal is formed on the n-type doped region 44 and connected to the line BL 2 ; A contact terminal is formed on the p-type doped region 38 and connected to the erase line EL; a contact terminal is formed on the N-type well region NW2 and connected to the coupling line CL; a first gate G 1 The contact terminal is connected to the selection line SGL 1 ; The second gate G 2 The contact terminal is formed on the word line WL 1 ; The third gate G 3 The contact terminal is connected to the selection line SGL 2 ; The fourth gate G 4 The contact terminal is formed on the word line WL 2 .

[0045] like Figure 3A As shown, the first floating gate FG 1 The first floating gate FG extends from the P-type well region PW2 to the N-type well region NW2, the P-type well region PW1 to the N-type well region NW1, and the first floating gate FG 1 A capacitor is formed with the N-type well region NW2. That is, one end of the capacitor is connected to the first floating gate FG 1 , the other end of the capacitor is connected to the coupling line CL. Furthermore, the first floating gate FG 1 It further extends to the N-type well region NW1 and is adjacent to the p-type doping region 38. The first floating gate FG 1 , N-type well region NW1, and p-type doping region 38 form a p-type transistor. That is, the gate of the p-type transistor is connected to the first floating gate FG 1The drain and source of the p-type transistor are connected to the erase line EL. Furthermore, the p-type transistor can also be called an erase gate element, and the first floating gate FG 1 , N-type well region NW1, and p-type doped region 38 are used as storage cells Cell 1 The exit path of electrons. That is, the storage cell 1 The electrons can be transferred from the floating gate FG 1 Exit to the erase line EL.

[0046] The second floating gate FG 2 Includes two branches, a second floating gate FG 2 The first branch of the second floating gate FG extends from the P-type well region PW1 to the N-type well region NW2 and the P-type well region PW2; 2 The second branch of the second floating gate FG extends from the P-type well region PW1 to the N-type well region NW1, and the second branch is adjacent to the p-type doping region 38. 2 A capacitor is formed with the N-type well region NW2. That is, one end of the capacitor is connected to the second floating gate FG 2 , the other end of the capacitor is connected to the coupling line CL. Furthermore, the second floating gate FG 2 , N-type well region NW1, and p-type doping region 38 form a p-type transistor. That is, the gate of the p-type transistor is connected to the second floating gate FG 2 The drain and source of the p-type transistor are connected to the erase line EL. Furthermore, the second floating gate FG 2 , N-type well region NW1, and p-type doped region 38 are used as storage cells Cell 2 The exit path of electrons. That is, the storage cell 2 The electrons can be transmitted by the second floating gate FG 2 Exit to the erase line EL.

[0047] In the storage cell 1 In the first gate G 1 The first floating gate FG is located on the surface between the n-type doping region 31 and the n-type doping region 32. 1 The second gate G is located above the surface between the n-type doping region 32 and the n-type doping region 33. 2 The P-type well region PW2 includes a first n-type transistor, a second n-type transistor, and a third n-type transistor. The first n-type transistor includes a first gate G 1 , n-type doping region 31 and n-type doping region 32. The second n-type transistor includes a first floating gate FG 1, n-type doping region 32 and n-type doping region 33. The third n-type transistor includes a second gate G 2 , n-type doping region 33 and n-type doping region 34 .

[0048] The first n-type transistor is a select transistor, and its first gate G 1 Connect to the select line SGL 1 , the n-type doping region 31 is connected to the source line SL 1 The second n-type transistor is a floating gate transistor. The third n-type transistor is a switch transistor, and its second gate G 2 Connected to word line WL 1 , the n-type doping region 34 is connected to the bit line BL 1 .

[0049] In the storage cell 2 In the third gate G 3 The second floating gate FG is located on the surface between the n-type doping region 41 and the n-type doping region 42. 2 The fourth gate G is located above the surface between the n-type doping region 42 and the n-type doping region 43. 4 The P-type well region PW1 includes a fourth n-type transistor, a fifth n-type transistor, and a sixth n-type transistor. The fourth n-type transistor includes a third gate G 3 , n-type doping region 41 and n-type doping region 42. The fifth n-type transistor includes a second floating gate FG 2 , n-type doping region 42 and n-type doping region 43. The sixth n-type transistor includes a fourth gate G 4 , n-type doping region 43 and n-type doping region 44 .

[0050] The fourth n-type transistor is a selection transistor, and its third gate G 3 Connect to the select line SGL 2 , the n-type doping region 41 is connected to the source line SL 2 The fifth n-type transistor is a floating gate transistor. The sixth n-type transistor is a switch transistor, and its fourth gate G 4 Connected to word line WL 2 , n-type doping region 44 is connected to the bit line BL 2 .

[0051] By appropriately connecting the word line WL 1 ~WL2 , bit line BL 1 ~BL 2 , select line SGL 1 ~SGL 2 , coupling lines CL and erase lines EL, a memory cell array can be formed.

[0052] Furthermore, in the second embodiment, the storage unit cell 1 With storage cell 2 The equivalent circuit is the same as Figure 1B , I will not go into details here.

[0053] like Figure 3B As shown, it is a schematic diagram of a zoomed out layout structure. The non-volatile memory includes a plurality of pages, each of which includes a plurality of memory cells. The semiconductor substrate includes staggered P-type well regions PW1 to PW4 and N-type well regions NW1 to NW4. Furthermore, the plurality of memory cells of the first page page1 will be designed on the N-type well regions NW1, NW2 and the P-type well regions PW1, PW2. The plurality of memory cells of the second page page2 will be designed on the N-type well regions NW3, NW4 and the P-type well regions PW3, PW4.

[0054] Compared to the layout structure of the memory cell array of the first embodiment, in the layout structure of the second embodiment, each page includes two N-type well regions and two P-type well regions, and there is no need to design a spacing well region between pages. Therefore, in the non-volatile memory, the layout structure of the memory cell array of the second embodiment has a smaller layout area.

[0055] Please refer to Figure 4A and Figure 4B , which illustrates the third embodiment of the layout structure of the memory cell array of the present invention. Figure 4A As shown, staggered P-type well regions PW1, PW2, PW3 and N-type well regions NW1, NW2 are formed below the surface of the semiconductor substrate. N-type well region NW2 is located between P-type well region PW1 and P-type well region PW2, P-type well region PW1 is located between N-type well region NW1 and N-type well region NW2, and N-type well region NW1 is located between P-type well region PW1 and P-type well region PW3. Furthermore, 6 memory cells are designed on P-type well regions PW1, PW2, PW3 and N-type well regions NW1, NW2. 1 ~cell 6 Among them, the storage unit cell 1 、cell 4 、cell5 The structure is similar to that of the storage unit cell 2 、cell 3 、cell 6 The following only introduces the storage unit cell 1 、cell 2 , the rest will not be elaborated.

[0056] like Figure 4A As shown, in the storage unit cell 1 In the first gate G 1 With the second gate G 2 Covering the P-type well region PW2. In addition, the first floating gate FG 1 Covering the P-type well regions PW1, PW2, PW3 and the N-type well regions NW1, NW2.

[0057] In the storage cell 2 In the third gate G 3 With the fourth gate G 4 Covering the P-type well region PW3. In addition, the second floating gate FG 2 The first floating gate FG covers the P-type well regions PW1, PW2, PW3 and the N-type well regions NW1, NW2. 1 , the second floating gate FG 2 , the first gate G 1 The second gate G 2 , the third gate G 3 With the fourth gate G 4 Both include a gate dielectric layer and a polysilicon layer. The gate dielectric layer is formed on the surface of the semiconductor substrate, and the polysilicon layer covers the gate dielectric layer.

[0058] Next, a p-type doping region 58 is formed in the N-type well region NW1. In addition, n-type doping regions 51-54 are formed in the P-type well region PW2, and n-type doping regions 61-64 are formed in the P-type well region PW3. Furthermore, a contact terminal is formed on the n-type doping region 51 to connect to the source line SL. 1 ; A contact terminal is formed on the n-type doped region 54 and connected to the line BL 1 ; A contact terminal is formed on the n-type doped region 61 and connected to the source line SL 2 ; A contact terminal is formed on the n-type doped region 64 and connected to the line BL 2 ; A contact terminal is formed on the p-type doped region 58 and connected to the erase line EL; a contact terminal is formed on the N-type well region NW2 and connected to the coupling line CL; a first gate G 1 The contact terminal is connected to the selection line SGL1 ; The second gate G 2 The contact terminal is formed on the word line WL 1 ; The third gate G 3 The contact terminal is connected to the selection line SGL 2 ; The fourth gate G 4 The contact terminal is formed on the word line WL 2 .

[0059] like Figure 4A As shown, the first floating gate FG 1 The first floating gate FG extends from the P-type well region PW2 to the N-type well region NW2, the P-type well region PW1, the N-type well region NW1 to the P-type well region PW3, and the first floating gate FG 1 A capacitor is formed with the N-type well region NW2. That is, one end of the capacitor is connected to the first floating gate FG 1 , the other end of the capacitor is connected to the coupling line CL. Furthermore, the first floating gate FG 1 It further extends to the N-type well region NW1 and is adjacent to the p-type doped region 58. The first floating gate FG 1 , N-type well region NW1, and p-type doping region 58 form a p-type transistor. That is, the gate of the p-type transistor is connected to the first floating gate FG 1 The drain and source of the p-type transistor are connected to the erase line EL. Furthermore, the p-type transistor can also be called an erase gate element, and the first floating gate FG 1 , N-type well region NW1, and p-type doped region 58 are used as storage cells Cell 1 The exit path of electrons. That is, the storage cell 1 The electrons can be transferred from the floating gate FG 1 Exit to the erase line EL.

[0060] The second floating gate FG 2 The second floating gate FG extends from the P-type well region PW3 through the N-type well region NW1, the P-type well region PW1, and the N-type well region NW2 to the P-type well region PW2. 2 A capacitor is formed with the N-type well region NW2. That is, one end of the capacitor is connected to the second floating gate FG 2 , the other end of the capacitor is connected to the coupling line CL. Furthermore, the second floating gate FG 2 Adjacent to the p-type doped region 58. The second floating gate FG 2 , N-type well region NW1, and p-type doping region 58 form a p-type transistor. That is, the gate of the p-type transistor is connected to the second floating gate FG 2 The drain and source of the p-type transistor are connected to the erase line EL. Furthermore, the second floating gate FG2 , N-type well region NW1, and p-type doped region 58 are used as storage cells Cell 2 The exit path of electrons. That is, the storage cell 2 The electrons can be transmitted by the second floating gate FG 2 Exit to the erase line EL.

[0061] In the storage cell 1 In the first gate G 1 The first floating gate FG is located on the surface between the n-type doping region 51 and the n-type doping region 52. 1 The second gate G is located above the surface between the n-type doping region 52 and the n-type doping region 53. 2 The P-type well region PW2 includes a first n-type transistor, a second n-type transistor, and a third n-type transistor. The first n-type transistor includes a first gate G 1 , n-type doping region 51 and n-type doping region 52. The second n-type transistor includes a first floating gate FG 1 , n-type doping region 52 and n-type doping region 53. The third n-type transistor includes a second gate G 2 , n-type doping region 53 and n-type doping region 54 .

[0062] The first n-type transistor is a select transistor, and its first gate G 1 Connect to the select line SGL 1 , the n-type doping region 51 is connected to the source line SL 1 The second n-type transistor is a floating gate transistor. The third n-type transistor is a switch transistor, and its second gate G 2 Connected to word line WL 1 , n-type doping region 54 is connected to the bit line BL 1 .

[0063] In the storage cell 2 In the third gate G 3 The second floating gate FG is located on the surface between the n-type doping region 61 and the n-type doping region 62. 2 The fourth gate G is located above the surface between the n-type doping region 62 and the n-type doping region 63. 4 The P-type well region PW3 includes a fourth n-type transistor, a fifth n-type transistor, and a sixth n-type transistor. The fourth n-type transistor includes a third gate G3 , n-type doping region 61 and n-type doping region 62. The fifth n-type transistor includes a second floating gate FG 2 , n-type doping region 62 and n-type doping region 63. The sixth n-type transistor includes a fourth gate G 4 , n-type doping region 63 and n-type doping region 64 .

[0064] The fourth n-type transistor is a selection transistor, and its third gate G 3 Connect to the select line SGL 2 , the n-type doping region 61 is connected to the source line SL 2 The fifth n-type transistor is a floating gate transistor. The sixth n-type transistor is a switch transistor, and its fourth gate G 4 Connected to word line WL 2 , n-type doping region 64 is connected to bit line BL 2 .

[0065] By appropriately connecting the word line WL 1 ~WL 2 , bit line BL 1 ~BL 2 , select line SGL 1 ~SGL 2 , coupling lines CL and erase lines EL, a memory cell array can be formed.

[0066] Furthermore, in the third embodiment, the storage unit cell 1 With storage cell 2 The equivalent circuit is the same as Figure 1B , I will not go into details here.

[0067] like Figure 4B As shown, it is a schematic diagram of a zoomed out layout structure. The non-volatile memory includes a plurality of pages, each of which includes a plurality of memory cells. The semiconductor substrate includes staggered P-type well regions PW1 to PW5 and N-type well regions NW1 to NW4. Furthermore, the plurality of memory cells of the first page page1 will be designed on the N-type well regions NW1, NW2 and the P-type well regions PW1, PW2, and PW3. The plurality of memory cells of the second page page2 will be designed on the N-type well regions NW3, NW4 and the P-type well regions PW2, PW4, and PW5. The two pages share the P-type well region PW2.

[0068] Compared to the layout structure of the memory cell array of the first embodiment, in the layout structure of the third embodiment, each page includes two N-type well regions and three P-type well regions, and two pages share the P-type well region PW2. Therefore, in the non-volatile memory, the layout structure of the memory cell array of the third embodiment has a smaller layout area.

[0069] Furthermore, the layout structures of the second embodiment and the third embodiment can also be modified appropriately. Figure 5 , which shows a modified layout structure of the second embodiment. Compared with the second embodiment, the storage unit cell 2 、cell 3 、cell 6 The floating gate does not extend to the P-type well region PW2. Furthermore, at least one doped region is formed in the N-type well region NW2 and connected to the coupling line CL. Figure 5 As shown, an n-type doping region 47 and a p-type doping region 48 are formed in the N-type well region NW2, and the n-type doping region 47 and the p-type doping region 48 are adjacent to all floating gates. A contact terminal is formed on the n-type doping region 47 and connected to the coupling line CL, and a contact terminal is formed on the p-type doping region 48 and connected to the coupling line CL. In this way, the capacitor formed between the coupling line CL and the floating gate has a higher coupling efficiency (coupling ratio). Of course, only one n-type doping region or one p-type doping region can also be formed in the N-type well region NW2.

[0070] Please refer to Figure 6 , which shows a modified layout structure of the third embodiment. Compared with the third embodiment, the storage unit cell 2 、cell 3 、cell 6 The floating gate of the memory cell does not extend to the P-type well region PW2. 1 、cell 4 、cell 5 The floating gate does not extend to the P-type well region PW3. Similarly, at least one doped region connected to the coupling line CL is formed in the N-type well region NW2. Figure 6As shown, an n-type doping region 66, a p-type doping region 67 and an n-type doping region 68 are formed in the N-type well region NW2, and the n-type doping region 66, the p-type doping region 67 and the n-type doping region 68 are adjacent to all floating gates. Among them, a contact terminal is formed on the n-type doping region 66 and connected to the coupling line CL, a contact terminal is formed on the p-type doping region 67 and connected to the coupling line CL, and a contact terminal is formed on the n-type doping region 68 and connected to the coupling line CL. In this way, the capacitor formed between the coupling line CL and the floating gate has a higher coupling efficiency (coupling ratio). Of course, only one n-type doping region or one p-type doping region can also be formed in the N-type well region NW2.

[0071] Of course, in Figure 5 In the layout structure, the N-type well region NW2 can also form a similar Figure 6 The three doping regions 66 to 68 are shown. Figure 6 In the layout structure, the N-type well region NW2 can also form a similar Figure 5 Two doped regions 47, 48 are shown.

[0072] In the second embodiment and the third embodiment of the present invention, all the memory cells Cell 1 ~Cell 6 All are connected to the same coupling line CL and the same erase line EL. In addition, the present invention is not limited to the word line WL in the memory cell. 1 , WL 2 , bit line BL 1 BL 2 , source line SL 1 , SL 2 , select line SGL 1 , SGL 2 For example, in an embodiment of a memory cell array, the source line SL 1 , SL 2 interconnected, word line WL 1 , WL 2 Connect to each other, select line SGL 1 , SGL 2 interconnected, bit line BL 1 BL 2 In another embodiment of the memory cell array, the source line SL 1 , SL 2 interconnected, bit line BL 1 BL 2 interconnected, word line WL 1 , WL 2 Not connected to each other, select line SGL 1 , SGL2 Of course, in other embodiments of the memory cell array, the word line WL 1 , WL 2 , bit line BL 1 BL 2 , source line SL 1 , SL 2 , select line SGL 1 , SGL 2 There may also be other connection relationships.

[0073] In addition, in an embodiment of the present invention, the memory cell includes three n-type transistors, a capacitor and a p-type transistor. Of course, the present invention is not limited thereto. A person skilled in the art can also modify the memory cell according to the technology disclosed in the present invention, by exchanging the n-type doping region with the p-type doping region, and exchanging the N-type well region with the P-type well region, so that the modified memory cell includes three p-type transistors, a capacitor and an n-type transistor.

[0074] From the above description, it can be seen that the present invention proposes a memory cell array layout structure used in non-volatile memory. The arrangement positions of multiple well regions and the shape of floating gates are designed on a semiconductor substrate, and two memory cells with different shapes are designed to effectively reduce the layout area of ​​the memory cell array layout structure.

[0075] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the definition of the attached claims.

Claims

1. A storage cell array layout structure of a non-volatile memory, comprising: A first first-type well region, a second first-type well region, a first second-type well region and a second second-type well region; wherein the second first-type well region is located between the first second-type well region and the second second-type well region, and the first second-type well region is located between the first first-type well region and the second first-type well region; A first gate, a second gate and a first floating gate are formed on the surface of the second second-type well region; wherein the first floating gate extends from the second second-type well region through the second first-type well region and the first second-type well region to the first first-type well region; A first first-type doping region, a second first-type doping region, a third first-type doping region and a fourth first-type doping region are formed on the surface of the second second-type well region; wherein the first gate is located on the surface between the first first-type doping region and the second first-type doping region, the first floating gate is located on the surface between the second first-type doping region and the third first-type doping region, and the second gate is located on the surface between the third first-type doping region and the fourth first-type doping region; A first second-type doping region is formed in the first first-type well region, and the first second-type doping region is adjacent to the first floating gate; A first contact terminal is formed in the first second-type doping region, and the first contact terminal is connected to an erase line; and The second contact end is formed in the second first-type well region, and the second contact end is connected to the coupling line.

2. The memory cell array layout structure as described in claim 1, wherein the first floating gate and the second first-type well region form a first capacitor; the first floating gate, the first first-type well region, and the first second-type doped region form a first second-type transistor; the first gate, the first first-type doped region, and the second first-type doped region form a first selection transistor; the first floating gate, the second first-type doped region, and the third first-type doped region form a first floating gate transistor; the second gate, the third first-type doped region, and the fourth first-type doped region form a first switch transistor; and the first selection transistor, the first floating gate transistor, the first switch transistor, the first capacitor, and the first second-type transistor form a first memory cell.

3. The memory cell array layout structure according to claim 1, further comprising: A third gate, a fourth gate and a second floating gate are formed on the surface of the first second-type well region; wherein the second floating gate includes a first branch and a second branch, the first branch extends from the first second-type well region to the second first-type well region, the second branch extends from the first second-type well region to the first first-type well region, and the second branch is adjacent to the first second-type doped region; and The fifth first-type doping region, the sixth first-type doping region, the seventh first-type doping region and the eighth first-type doping region are formed on the surface of the first second-type well region; wherein the third gate is located on the surface between the fifth first-type doping region and the sixth first-type doping region, the second floating gate is located on the surface between the sixth first-type doping region and the seventh first-type doping region, and the fourth gate is located on the surface between the seventh first-type doping region and the eighth first-type doping region.

4. The memory cell array layout structure as described in claim 3, wherein the second floating gate and the second first-type well region form a second capacitor; the second floating gate, the first first-type well region, and the first second-type doping region form a second second-type transistor; the third gate, the fifth first-type doping region, and the sixth first-type doping region form a second selection transistor; the second floating gate, the sixth first-type doping region, and the seventh first-type doping region form a second floating gate transistor; the fourth gate, the seventh first-type doping region, and the eighth first-type doping region form a second switch transistor; and the second selection transistor, the second floating gate transistor, the second switch transistor, the second capacitor, and the second second-type transistor form a second memory cell.

5. The memory cell array layout structure according to claim 3, further comprising: a ninth first-type doping region formed in the second first-type well region, and the ninth first-type doping region is adjacent to the first floating gate and the second floating gate; as well as A third contact terminal is formed in the ninth first-type doping region, and the third contact terminal is connected to the coupling line.

6. The memory cell array layout structure according to claim 5, further comprising: A second second-type doping region is formed in the second first-type well region, and the second second-type doping region is adjacent to the first floating gate and the second floating gate; as well as A fourth contact terminal is formed in the second second-type doping region, and the fourth contact terminal is connected to the coupling line.

7. The memory cell array layout structure according to claim 6, further comprising: a tenth first-type doping region formed in the second first-type well region, and the tenth first-type doping region is adjacent to the first floating gate and the second floating gate; as well as A fifth contact terminal is formed in the tenth first-type doping region, and the fifth contact terminal is connected to the coupling line.

8. The memory cell array layout structure according to claim 3, further comprising: A second second-type doping region is formed in the second first-type well region, and the second second-type doping region is adjacent to the first floating gate and the second floating gate; as well as The third contact end is formed in the second second-type doping region, and the third contact end is connected to the coupling line.

9. The memory cell array layout structure according to claim 1, further comprising: a third second-type well region, wherein the first first-type well region is located between the first second-type well region and the third second-type well region; A third gate, a fourth gate and a second floating gate are formed on the surface of the third second-type well region; wherein the second floating gate extends from the third second-type well region through the first first-type well region and the first second-type well region to the second first-type well region, and the second floating gate is adjacent to the first second-type doped region; and The fifth first-type doping region, the sixth first-type doping region, the seventh first-type doping region and the eighth first-type doping region are formed on the surface of the third second-type well region; wherein the third gate is located on the surface between the fifth first-type doping region and the sixth first-type doping region, the second floating gate is located on the surface between the sixth first-type doping region and the seventh first-type doping region, and the fourth gate is located on the surface between the seventh first-type doping region and the eighth first-type doping region.

10. The memory cell array layout structure as described in claim 9, wherein the second floating gate and the second first-type well region form a second capacitor; the second floating gate, the first first-type well region, and the first second-type doping region form a second second-type transistor; the third gate, the fifth first-type doping region, and the sixth first-type doping region form a second selection transistor; the second floating gate, the sixth first-type doping region, and the seventh first-type doping region form a second floating gate transistor; the fourth gate, the seventh first-type doping region, and the eighth first-type doping region form a second switch transistor; and the second selection transistor, the second floating gate transistor, the second switch transistor, the second capacitor, and the second second-type transistor form a second memory cell.

11. The memory cell array layout structure according to claim 9, further comprising: a ninth first-type doping region formed in the second first-type well region, and the ninth first-type doping region is adjacent to the first floating gate and the second floating gate; as well as A third contact terminal is formed in the ninth first-type doping region, and the third contact terminal is connected to the coupling line.

12. The memory cell array layout structure according to claim 11, further comprising: A second second-type doping region is formed in the second first-type well region, and the second second-type doping region is adjacent to the first floating gate and the second floating gate; as well as A fourth contact terminal is formed in the second second-type doping region and is connected to the coupling line a tenth first-type doping region formed in the second first-type well region, and the tenth first-type doping region is adjacent to the first floating gate and the second floating gate; as well as A fifth contact terminal is formed in the tenth first-type doping region, and the fifth contact terminal is connected to the coupling line.

13. The memory cell array layout structure according to claim 9, further comprising: A second second-type doping region is formed in the second first-type well region, and the second second-type doping region is adjacent to the first floating gate and the second floating gate; as well as The third contact end is formed in the second second-type doping region, and the third contact end is connected to the coupling line. 14 . The memory cell array layout structure as claimed in claim 9 , wherein the first floating gate further extends to the third second-type well region, and the second floating gate further extends to the second second-type well region.

15. A storage cell array layout structure of a non-volatile memory, comprising: a first first-type well region, a second first-type well region, a first second-type well region, a second second-type well region, and a third second-type well region; wherein the second first-type well region is located between the first second-type well region and the second second-type well region, the first second-type well region is located between the first first-type well region and the second first-type well region, and the first first-type well region is located between the first second-type well region and the third second-type well region; A first gate, a second gate and a first floating gate are formed on the surface of the third second-type well region; wherein the first floating gate extends from the third second-type well region through the first first-type well region and the first second-type well region to the second first-type well region; A first first-type doping region, a second first-type doping region, a third first-type doping region and a fourth first-type doping region are formed on the surface of the third second-type well region; wherein the first gate is located on the surface between the first first-type doping region and the second first-type doping region, the first floating gate is located on the surface between the second first-type doping region and the third first-type doping region, and the second gate is located on the surface between the third first-type doping region and the fourth first-type doping region; A first second-type doping region is formed in the first first-type well region, and the first second-type doping region is adjacent to the first floating gate; A first contact terminal is formed in the first second-type doping region, and the first contact terminal is connected to an erase line; and The second contact end is formed in the second first-type well region, and the second contact end is connected to a coupling line.

16. A memory cell array layout structure as described in claim 15, wherein the first floating gate and the second first-type well region form a first capacitor; the first floating gate, the first first-type well region, and the first second-type doped region form a first second-type transistor; the first gate, the first first-type doped region, and the second first-type doped region form a first selection transistor; the first floating gate, the second first-type doped region, and the third first-type doped region form a first floating gate transistor; the second gate, the third first-type doped region, and the fourth first-type doped region form a first switch transistor; and the first selection transistor, the first floating gate transistor, the first switch transistor, the first capacitor, and the first second-type transistor form a first memory cell.

17. The memory cell array layout structure according to claim 15, further comprising: a fifth first-type doping region formed in the second first-type well region, and the fifth first-type doping region is adjacent to the first floating gate; as well as The third contact end is formed in the fifth first-type doping region, and the third contact end is connected to the coupling line.

18. The memory cell array layout structure according to claim 17, further comprising: A second second-type doping region is formed in the second first-type well region, and the second second-type doping region is adjacent to the first floating gate; A fourth contact terminal is formed in the second second-type doped region, and the fourth contact terminal is connected to the coupling line; a sixth first-type doping region formed in the second first-type well region, and the sixth first-type doping region is adjacent to the first floating gate; as well as A fifth contact terminal is formed in the sixth first-type doping region, and the fifth contact terminal is connected to the coupling line.

19. The memory cell array layout structure according to claim 15, further comprising: A second second-type doping region is formed in the second first-type well region, and the second second-type doping region is adjacent to the first floating gate; as well as The third contact end is formed in the second second-type doping region, and the third contact end is connected to the coupling line. 20 . The memory cell array layout structure as claimed in claim 15 , wherein the first floating gate further extends to the second second-type well region.

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