A ferroelectric tunnel junction memory device

Abstract

The present invention discloses a ferroelectric tunnel junction memory device, comprising a first dielectric layer (100) and an array of field effect tube monomers (1) arranged in an array thereon; a drain strip electrode (5), a second dielectric layer (200), a third dielectric layer (300), a ferroelectric tunnel junction first electrode (8), a ferroelectric dielectric tunneling layer (9), a ferroelectric tunnel junction second electrode (10) and a fourth dielectric layer (400) are sequentially arranged on the first dielectric layer (100). The fourth dielectric layer (400) is then used as the first dielectric layer (100) of the next device, and the operation is repeated to realize a multi-layer stacking of a three-dimensional ferroelectric tunnel junction, which has the advantages of low power consumption, easy reading, high-density integration, and good practicality.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, specifically to the field of information storage technology, and in particular to a ferroelectric tunnel junction memory device. Background Art

[0002] The information technology field has entered the era of big data, and the rapid development of technology has placed increasingly stringent demands on information storage and processing systems. The massive amount of data requires faster processing speeds, larger storage spaces, and lower unit energy consumption, creating an urgent need for non-volatile, ultra-fast, low-energy, and high-density memory devices. Ferroelectric tunnel junction memory, one of the emerging memory device principles, offers significant advantages in terms of non-volatility, high speed, and low power consumption due to its ferroelectric storage principle.

[0003] Existing information storage technologies, through structural design and cell size reduction, are gradually approaching their limits in terms of integration density and cell size for single-layer, two-dimensional planar memory. Furthermore, this scaling has placed higher demands on related micro-nanofabrication technologies, leading to increasingly expensive device manufacturing costs. Furthermore, with scaling, the low read current density of ferroelectric tunnel junctions hinders their optimal use in single-layer, planar, high-density storage. Therefore, there is an urgent need for ferroelectric tunnel junction memory devices that are low-power, easy to read, and capable of further high-density integration.

[0004] In view of this, the present invention is proposed. Summary of the Invention

[0005] The purpose of the present invention is to provide a ferroelectric tunnel junction memory device that can realize multi-layer stacking, has the advantages of low power consumption, easy reading and high-density integration, and has good practicality.

[0006] The object of the present invention is achieved through the following technical solutions:

[0007] A ferroelectric tunnel junction memory device comprises a first dielectric layer 100 and an array of field effect transistor monomers 1 arranged in an array on the first dielectric layer 100;

[0008] The field effect transistor monomer 1 includes a field effect transistor source 2, a field effect transistor gate 3 and a field effect transistor drain 4; the field effect transistor source 2 is arranged in a hexagonal close-packed array on the first dielectric layer 100;

[0009] The drain strip electrode 5 or the gate strip electrode 6 is provided on the first dielectric layer 100; the drain strip electrode 5 is connected to the drain electrode 4 of the field effect transistor monomer 1 in the same row or column; the gate strip electrode 6 is connected to the gate electrode 3 of the field effect transistor monomer 1 in the same row or column;

[0010] A second dielectric layer 200 is provided on the first dielectric layer 100 to cover the drain electrode 4 of the field effect transistor and the drain strip electrode 5 or the gate strip electrode 6;

[0011] A gate strip electrode 6 or a drain strip electrode 5 is further provided on the second dielectric layer 200; the gate strip electrode 6 is connected to the field effect transistor gate 3 of the field effect transistor monomer 1 in the same column or row; the drain strip electrode 5 is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same column or row;

[0012] The second dielectric layer 200 is further provided with a third dielectric layer 300 to cover the field effect transistor gate 3 and the gate strip electrode 6 or the drain strip electrode 5;

[0013] On the third dielectric layer 300, an array of ferroelectric tunnel junction first electrodes 8 connected to the source electrodes 2 of the field effect transistors are arranged upwards corresponding to the source electrodes 2 of the field effect transistors below; a ferroelectric dielectric tunnel layer 9 is further arranged on the surface of the first ferroelectric tunnel junction electrodes 8;

[0014] A ferroelectric tunnel junction second electrode 10 is disposed on the entire upper surface of the current device; and a fourth dielectric layer 400 is then entirely covered on the upper surface.

[0015] Preferably, the ferroelectric tunnel junction memory device is stacked in multiple layers; the fourth dielectric layer 400 of the ferroelectric tunnel junction memory device in the lower layer serves as the first dielectric layer 100 of the upper layer; and a field effect transistor monomer 1, a drain strip electrode 5 or a gate strip electrode 6, a second dielectric layer 200 of the upper layer, a gate strip electrode 6 or a drain strip electrode 5, a third dielectric layer 300 of the upper layer, a ferroelectric tunnel junction first electrode 8, a ferroelectric dielectric tunneling layer 9, a ferroelectric tunnel junction second electrode 10 and a fourth dielectric layer 400 of the upper layer are sequentially arranged thereon; forming a multi-layer stacked structure of a ferroelectric tunnel junction memory device of at least two layers.

[0016] Preferably, one or all of the length or width dimensions of the upper dielectric layer among the first dielectric layer 100, the second dielectric layer 200, the third dielectric layer 300 and the fourth dielectric layer 400 are smaller than those of the lower dielectric layer; a multi-layer stacked structure of a ferroelectric tunnel junction memory device with a terraced structure is formed; electrodes of each layer are exposed at the staggered layer edges for electrode leads.

[0017] Preferably, the ferroelectric tunnel junction first electrode 8 is a columnar electrode; comprising:

[0018] A single electrode, including a columnar electrode formed solely from the ferroelectric tunnel junction electrode material 801, or;

[0019] A double-layer electrode, comprising a columnar electrode core 802 and an electrode layer of a ferroelectric tunnel junction electrode material 801 covering the electrode core 802, forming a double-layer columnar electrode, or;

[0020] The three-layer electrode includes a columnar electrode core 802 , the columnar electrode core 802 is coated with a buffer electrode material layer 803 , and the electrode material layer 803 is coated with an electrode layer of a ferroelectric tunnel junction electrode material 801 , forming a three-layer columnar electrode.

[0021] Preferably, the ferroelectric dielectric tunneling layer 9 comprises:

[0022] a single ferroelectric layer 901, or;

[0023] A stacked structure of two or more layers consisting of at least one ferroelectric layer 901 and at least one dielectric layer 902 .

[0024] Preferably, the field effect transistor monomer 1 includes two field effect transistor sources 2, two field effect transistor gates 3 and a field effect transistor drain 4; the two field effect transistors forming a common drain constitute the strip-shaped field effect transistor monomer 1.

[0025] Preferably, the strip-shaped field effect transistor monomer 1 is tilted to form an angle of 30 to 75 degrees with the drain strip electrode 5 .

[0026] Preferably, the second dielectric layer 200 and the third dielectric layer 300 are etched away above the field effect transistor source 2 to form a through hole, and a conductor 7 made of conductive material is arranged in the through hole to connect the field effect transistor source 2 and the first electrode 8 of the ferroelectric tunnel junction.

[0027] A ferroelectric tunnel junction memory device comprises a first dielectric layer 100 and a top surface of which blind vias are etched in a hexagonal close-packed array; a second ferroelectric tunnel junction electrode 10 is integrally provided on the top surface and the inner surface of the blind vias;

[0028] A ferroelectric dielectric tunneling layer 9 is provided on the inner surface of the blind hole in the ferroelectric tunnel junction second electrode 10 in the blind hole groove; the upper surface of the ferroelectric dielectric tunneling layer 9 is flush with the ferroelectric tunnel junction second electrode 10;

[0029] A first ferroelectric tunnel junction electrode 8 is filled in a blind hole in the ferroelectric dielectric tunnel layer 9; the upper surface of the first ferroelectric tunnel junction electrode 8 is flush with the second ferroelectric tunnel junction electrode 10;

[0030] A second dielectric layer 200 is disposed on the entire upper surface of the current device;

[0031] An array of field effect transistor monomers 1 is arranged upwards from the second dielectric layer 200 corresponding to the first electrode 8 of the ferroelectric tunnel junction below;

[0032] The field effect transistor monomer 1 includes a field effect transistor source 2, a field effect transistor gate 3 and a field effect transistor drain 4; the ferroelectric tunnel junction first electrode 8 is respectively connected to the field effect transistor source 2; the field effect transistor source 2 is arranged in a hexagonal close-packed array on the second dielectric layer 200;

[0033] The second dielectric layer 200 is provided with a drain strip electrode 5 or a gate strip electrode 6; the drain strip electrode 5 is connected to the drain electrode 4 of the field effect transistor monomer 1 in the same row or column; the gate strip electrode 6 is connected to the gate electrode 3 of the field effect transistor monomer 1 in the same row or column;

[0034] A third dielectric layer 300 is provided on the second dielectric layer 200 to cover the drain electrode 4 of the field effect transistor and the drain strip electrode 5 or the gate strip electrode 6;

[0035] A gate strip electrode 6 or a drain strip electrode 5 is further provided on the third dielectric layer 300; the gate strip electrode 6 is connected to the field effect transistor gate 3 of the field effect transistor monomer 1 in the same column or row; the drain strip electrode 5 is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same column or row;

[0036] The third dielectric layer 300 is further provided with a fourth dielectric layer 400 to cover the field effect transistor gate 3 and the gate strip electrode 6 or the drain strip electrode 5 .

[0037] Preferably, the ferroelectric tunnel junction memory device is stacked in multiple layers; the fourth dielectric layer 400 of the ferroelectric tunnel junction memory device in the lower layer serves as the first dielectric layer 100 of the upper layer; the ferroelectric tunnel junction second electrode 10, the ferroelectric dielectric tunneling layer 9, the ferroelectric tunnel junction first electrode 8, the second dielectric layer 200 of the upper layer, the field effect transistor monomer 1, the drain strip electrode 5 or the gate strip electrode 6, the third dielectric layer 300 of the upper layer, the gate strip electrode 6 or the drain strip electrode 5 and the fourth dielectric layer 400 of the upper layer are arranged in sequence thereon; forming a multi-layer stacked structure of a ferroelectric tunnel junction memory device with at least two layers.

[0038] Preferably, one or all of the length or width dimensions of the upper dielectric layer among the first dielectric layer 100, the second dielectric layer 200, the third dielectric layer 300 and the fourth dielectric layer 400 are smaller than those of the lower dielectric layer; a multi-layer stacked structure of a ferroelectric tunnel junction memory device with a terraced structure is formed; electrodes of each layer are exposed at the staggered layer edges for electrode leads.

[0039] Preferably, the ferroelectric tunnel junction first electrode 8 is a columnar electrode; comprising:

[0040] A single electrode, including a columnar electrode formed solely from the ferroelectric tunnel junction electrode material 801, or;

[0041] A double-layer electrode, comprising a columnar electrode core 802 and an electrode layer of a ferroelectric tunnel junction electrode material 801 covering the electrode core 802, forming a columnar electrode, or;

[0042] The three-layer electrode includes a columnar electrode core 802 , the columnar electrode core 802 is coated with a buffer electrode material layer 803 , and the electrode material layer 803 is coated with an electrode layer of a ferroelectric tunnel junction electrode material 801 to form a columnar electrode.

[0043] Preferably, the ferroelectric dielectric tunneling layer 9 comprises:

[0044] a single ferroelectric layer 901, or;

[0045] A stacked structure of two or more layers consisting of at least one ferroelectric layer 901 and at least one dielectric layer 902 .

[0046] Preferably, the field effect transistor monomer 1 includes two field effect transistor sources 2, two field effect transistor gates 3 and a field effect transistor drain 4; the two field effect transistors forming a common drain constitute the strip-shaped field effect transistor monomer 1.

[0047] Preferably, the strip-shaped field effect transistor monomer 1 is tilted to form an angle of 10 to 75 degrees with the drain strip electrode 5 .

[0048] Preferably, the strip-shaped field effect transistor monomer 1 is tilted to form an angle of 60 degrees with the drain strip electrode 5 .

[0049] Preferably, the second dielectric layer 200 is etched away above the field effect transistor source 2 to form a through hole, and a conductor 7 made of a conductive material is arranged in the through hole to connect the field effect transistor source 2 and the first electrode 8 of the ferroelectric tunnel junction.

[0050] Based on the above scheme, the ferroelectric tunnel junction memory device provided by the present invention can realize a ferroelectric tunnel junction memory device structure with two or more layers of high-density stacking, and its beneficial effects include: the three-dimensional columnar ferroelectric tunnel junction increases the unit area within a limited surface, improves the read current, thereby realizing the miniaturization of the ferroelectric tunnel junction surface size and improving the storage density; utilizing the insulating barrier dielectric layer filled to isolate each information storage array layer and prevent device failure caused by series connection of devices, stacking integration is realized, thereby improving the storage density; the ferroelectric tunnel junctions in the same layer can be arranged in a hexagonal close-packed manner, thereby improving the storage density; the unit ferroelectric tunnel junction is an electrode / ferroelectric dielectric tunneling layer / electrode structure, and the ferroelectric dielectric tunneling layer includes at least one ferroelectric layer and an optional dielectric layer. The optional one or more dielectric layers can bring greater asymmetry to the entire ferroelectric tunnel junction device, which is conducive to achieving a high switching ratio and is beneficial to reducing the ferroelectric coercive field and operating voltage.

[0051] Compared with the prior art, the ferroelectric tunnel junction memory device provided by the present invention can realize multi-layer stacking, has the advantages of low power consumption, easy reading and high-density integration, and has good practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0053] Figure 1 A schematic diagram of a vertical cross-sectional structure of a ferroelectric tunnel junction memory device provided in the first embodiment of the present invention;

[0054] Figure 2 A schematic top view of the layout of multiple field effect transistors of a ferroelectric tunnel junction memory device is provided for the first embodiment of the present invention;

[0055] Figure 3 A schematic top view of the external circuits connected to the electrodes of a single-layer field effect transistor array of a ferroelectric tunnel junction memory device according to the first embodiment of the present invention is provided;

[0056] Figure 4 A schematic diagram of a rectangular array of field effect transistor units of a single-layer field effect transistor unit array of a ferroelectric tunnel junction memory device is provided for the first embodiment of the present invention;

[0057] Figure 5 A schematic diagram of a staggered rectangular array of field effect transistor units of a single-layer field effect transistor unit array of a ferroelectric tunnel junction memory device is provided for the first embodiment of the present invention;

[0058] Figure 6 A schematic diagram of a planar top view structure of a ferroelectric tunnel junction memory device is provided for the first embodiment of the present invention;

[0059] Figure 7 A schematic structural diagram of a first electrode of a ferroelectric tunnel junction of a ferroelectric tunnel junction memory device is provided for the first and second embodiments of the present invention;

[0060] Figure 8 A schematic structural diagram of a ferroelectric dielectric tunneling layer of a ferroelectric tunnel junction memory device is provided for an embodiment of the present invention;

[0061] Figure 9 A schematic diagram of a multi-layer stacked structure of a ferroelectric tunnel junction memory device provided in the second embodiment of the present invention;

[0062] Figure 10 A schematic diagram of a vertical cross-sectional structure of a ferroelectric tunnel junction memory device provided in a third embodiment of the present invention;

[0063] Figure 11 A schematic diagram of a multi-layer stacked structure of a ferroelectric tunnel junction memory device provided in the fourth embodiment of the present invention;

[0064] Figure 12 A schematic diagram of the structural principle of a ferroelectric tunnel junction memory device is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0065] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the specific content of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments, and do not constitute a limitation of the present invention. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0066] First, the following terms may be used in this article:

[0067] The term “and / or” means that either or both of them can be realized at the same time. For example, X and / or Y includes both “X” or “Y” and “X and Y”.

[0068] The terms "include," "comprises," "contains," "has," or other similar expressions should be interpreted as non-exclusive. For example, "including certain technical features (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products, or manufactured articles, etc.) should be interpreted as including not only the technical features explicitly listed, but also other technical features known in the art that are not explicitly listed.

[0069] The term "consisting of" excludes any technical features not explicitly listed. If used in a claim, this term renders the claim closed, excluding any technical features other than those explicitly listed, except for conventional impurities associated with them. If this term appears only in a clause of a claim, it limits only the elements explicitly listed in that clause; elements listed in other clauses are not excluded from the claim as a whole.

[0070] Unless otherwise specified or limited, the terms "mounted," "connected," "connect," and "fixed" should be interpreted broadly. For example, they can refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this document based on specific circumstances.

[0071] The terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings and are only for the convenience and simplification of description, and do not explicitly or implicitly indicate that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as a limitation to this document.

[0072] The technical solution provided by the present invention is described in detail below. The contents not described in detail in the embodiments of the present invention belong to the prior art known to professionals in this field. If specific conditions are not specified in the embodiments of the present invention, the conditions conventional in the art or the conditions recommended by the manufacturer are followed. If the manufacturer of the reagents or instruments used in the embodiments of the present invention is not specified, they are all conventional products that can be purchased commercially.

[0073] Example 1

[0074] like Figure 1 As shown, an embodiment of the present invention provides a ferroelectric tunnel junction memory device, which structurally includes a first dielectric layer 100; multiple field effect transistor monomers 1, a drain strip electrode 5, a second dielectric layer 200, a gate strip electrode 6, a third dielectric layer 300, a ferroelectric tunnel junction first electrode 8, a ferroelectric dielectric tunneling layer 9, a ferroelectric tunnel junction second electrode 10 and a fourth dielectric layer 400.

[0075] The material of the dielectric layer mainly plays an insulating role and can be a dielectric material with good insulation properties such as silicon oxide and aluminum oxide.

[0076] Specific examples Figure 2 and 3As shown, the first dielectric layer 100 serves as a substrate, upon which a plurality of field-effect transistor (FET) monomers 1 are arranged in an array. Here, a rectangular array of FET monomers 1 is grown on the substrate using a growth method. The term "growth" herein refers to the material growth and processing techniques used in integrated circuit manufacturing. Here, reference is made to the fabrication methods for FETs in integrated circuits, and the underlying principles will not be elaborated upon. Multiple FET monomers 1 form an array of FET monomers 1; each FET monomer 1 includes a FET source 2, a FET gate 3, and a FET drain 4. In this example, each FET monomer 1 includes two FET sources 2, two FET gates 3, and a FET drain 4; the two FETs sharing a drain form a strip-shaped FET monomer 1. Sharing a drain reduces overall size.

[0077] The array of field-effect transistor cells 1 can be either a rectangular array or a staggered rectangular array. It is essential that the field-effect transistor sources 2 are arranged in a hexagonal close-packed array on the first dielectric layer 100. Hexagonal close-packing refers to constructing an array in a hexagonal, close-packed manner, which fully utilizes the single-layer planar area and further increases integration density. This hexagonal close-packing arrangement, similar to the hexagonal shape of a honeycomb, fully utilizes the single-layer planar area.

[0078] like Figure 4 As shown, in this embodiment, the FET monomers 1 share a drain electrode. The FET monomers 1 are arranged as a "rectangular array" as a whole. The subsequent strip-shaped FET monomers 1 are tilted at a 60-degree angle to ensure that the FET sources 2 are arranged in a hexagonal close-packed array on the first dielectric layer 100. This further enables the multiple ferroelectric tunnel junction first electrodes 8 grown later to be arranged in a "hexagonal close-packed" arrangement. Figure 4 The five consecutive squares in the middle bar represent the field effect transistor monomers with a shared drain, while the solid black blocks are arranged in a "hexagonal close-packed" manner, expressing the "hexagonal close-packed" arrangement of the source 2 of the field effect transistor, and can be extended outward within the range allowed by the structural size.

[0079] like Figure 5 As shown, if the drain electrodes are not shared but individual field effect transistors, a staggered "rectangular array" arrangement is adopted. The field effect transistors in adjacent rows are staggered, while the field effect transistors in alternate rows are arranged in a "rectangular array," that is, two "rectangular arrays" are staggered to ensure that the field effect transistor sources 2 are arranged in a hexagonal close-packed array on the first dielectric layer 100. Figure 5 The three consecutive squares in the middle strip represent field-effect transistors that do not share a common drain. Adjacent rows are arranged in a staggered "rectangular array" and tilted at a 60-degree angle, ensuring that the source electrodes 2 of the field-effect transistors are arranged in a hexagonal close-packed array on the first dielectric layer 100 and facilitating the subsequent arrangement of strip electrodes.

[0080] Here, the drain strip electrodes 5 and gate strip electrodes 6 are grown on the first dielectric layer 100. This can be done by growing the drain strip electrodes 5 first and then the gate strip electrodes 6, or by growing the gate strip electrodes 6 first and then the drain strip electrodes 5. If the drain strip electrodes 5 are arranged on this layer, the gate strip electrodes 6 are then arranged on the second dielectric layer 200. Alternatively, the gate strip electrodes 6 are arranged on this layer and the drain strip electrodes 5 are then arranged on the second dielectric layer 200.

[0081] At the same time, reference Figure 3 In order to facilitate the subsequent growth of the drain strip electrode 5 or the gate strip electrode 6, the strip-shaped field effect transistor monomer 1 is tilted and arranged at an angle of 15 to 75 degrees to the drain strip electrode 5. Figure 3 Taking the drain strip electrode 5 as an example, since the drain strip electrode 5 has a certain width, the strip-shaped FET monomer 1 is tilted at a 60-degree angle to the drain strip electrode 5, placing the drain strip electrode 5 precisely between the two FET gates 3. Furthermore, this 60-degree angle allows the multiple ferroelectric tunnel junction first electrodes 8 to be arranged in a dense hexagonal pattern to form an array, fully utilizing the single-layer planar area and further increasing integration density. This "hexagonal close-packed" arrangement functions similarly to the hexagonal shape of a honeycomb, fully utilizing the single-layer planar area. The same principle applies to the gate strip electrode 6, except that it needs to be connected to the two FET gates 3 separately, avoiding the FET drain 4.

[0082] Of course, if the FET monomer 1 includes only one FET, there is no need to consider the angle issue, as long as the drain strip electrode 5 and the gate strip electrode 6 are staggered and do not contact each other.

[0083] The height of the field effect transistor gate 3 here should be greater than the sum of the heights of the field effect transistor drain 4 and the drain strip electrode 5, and the size greater than should ensure that no electrical breakdown occurs between the drain strip electrode 5 and the gate strip electrode 6. Under normal circumstances, the size greater than is more than 10nm.

[0084] In this example, the drain strip electrode 5 is first grown and then the gate strip electrode 6 is grown. After the strip-shaped field effect transistor monomer 1 is grown, the drain strip electrode 5 is provided on the first dielectric layer 100. Here, the drain strip electrode 5 is also grown on the first dielectric layer 100 by a growth method, and is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same row or column.

[0085] The electrode material of the drain strip electrode 5 can be, but is not limited to, heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or other electrode materials that have good conductivity and can form good contact with adjacent electrode materials.

[0086] refer to Figure 2 and 3 A second dielectric layer 200 is then disposed on the first dielectric layer 100. Here, the second dielectric layer 200 is also grown on the first dielectric layer 100. The second dielectric layer 200 needs to cover the field-effect transistor drain electrode 4 and the drain strip electrode 5. The height of the second dielectric layer 200 should not exceed the height of the field-effect transistor gate 3 to facilitate the subsequent arrangement of the gate strip electrode 6 for electrical connection to the field-effect transistor gate 3. Of course, if the height of the second dielectric layer 200 exceeds the height of the field-effect transistor gate 3, it is necessary to etch the second dielectric layer 200 at the position corresponding to the field-effect transistor gate 3 before arranging the gate strip electrode 6 to expose the field-effect transistor gate 3.

[0087] At the same time, at least one edge of the second dielectric layer 200 needs to leave a strip that does not cover the drain strip electrode 5 on the first dielectric layer 100. In other words, the second dielectric layer 200 should have one or both of its length and width smaller than the first dielectric layer 100. This facilitates connection of the drain strip electrode 5 to external circuits. If the second dielectric layer 200 is grown entirely on the first dielectric layer 100, the side parallel to the long side of the drain strip electrode 5 can be etched to be shorter than the drain strip electrode 5.

[0088] After the second dielectric layer 200 is completed, a chemical mechanical polishing process may be performed on the surface of the second dielectric layer 200 to form a flat surface, thereby providing a good base for subsequent structure growth.

[0089] refer to Figure 2 and 3 , a gate strip electrode 6 is further provided on the second dielectric layer 200. At this time, the drain strip electrode 5 is already provided on the corresponding first dielectric layer 100. Here, the gate strip electrode 6 is also grown on the second dielectric layer 200 by a growth method. The gate strip electrode 6 is connected to the field effect transistor gates 3 of the field effect transistor monomers 1 in the same column or row. The gate strip electrode 6 and the drain strip electrode 5 are generally intersected orthogonally.

[0090] The material selection requirements for the gate strip electrodes 6 are consistent with the material selection requirements for the drain strip electrodes 5 .

[0091] refer to Figure 2 and 3 After growing the gate strip electrodes 6, an insulating dielectric layer, namely a third dielectric layer 300, is required for isolation. Specifically, the third dielectric layer 300 is disposed on the second dielectric layer 200. Here, the third dielectric layer 300 is also grown on the second dielectric layer 200. The third dielectric layer 300 covers the field effect transistor gate 3 and the gate strip electrodes 6.

[0092] At the same time, at least one edge of the third dielectric layer 300 needs to leave a strip that does not cover the gate strip electrode 6 on the second dielectric layer 200. In other words, one or both of the length and width dimensions of the third dielectric layer 300 should be smaller than those of the second dielectric layer 200. This facilitates connection of the gate strip electrode 6 to external circuits. If the third dielectric layer 300 is grown entirely on the second dielectric layer 200, the length of the side parallel to the long side of the gate strip electrode 6 can be shortened by etching.

[0093] After the third dielectric layer 300 is completed, a chemical mechanical polishing process may be performed on the surface of the third dielectric layer 300 to form a flat surface, thereby providing a good base for subsequent structure growth.

[0094] Taking the example of first growing the gate strip electrode 6 and then growing the drain strip electrode 5, after the strip-shaped field effect transistor monomer 1 is grown, the gate strip electrode 6 is set on the first dielectric layer 100; here, the gate strip electrode 6 is also grown on the first dielectric layer 100 by a growth method to connect the field effect transistor gates 3 of the field effect transistor monomers 1 in the same row or column; the electrode material of the gate strip electrode 6 can be, but is not limited to, heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, and other electrode materials with good conductivity and capable of forming good contact with adjacent electrode materials.

[0095] refer to Figure 2 and 3 A second dielectric layer 200 is then disposed on the first dielectric layer 100. Here, the second dielectric layer 200 is also grown on the first dielectric layer 100. The second dielectric layer 200 needs to cover the field-effect transistor gate 3 and the gate strip electrode 6. The height of the second dielectric layer 200 should not exceed the height of the field-effect transistor drain 4, facilitating the subsequent arrangement of the drain strip electrode 5 for electrical connection to the field-effect transistor drain 4. Of course, if the height of the second dielectric layer 200 exceeds the height of the field-effect transistor drain 4, it is necessary to etch the second dielectric layer 200 at the location corresponding to the field-effect transistor drain 4 before arranging the gate strip electrode 6, exposing the field-effect transistor drain 4.

[0096] At the same time, at least one edge of the second dielectric layer 200 needs to leave a strip that does not cover the gate strip electrode 6 on the first dielectric layer 100. In other words, the second dielectric layer 200 should have one or both of its length and width smaller than the first dielectric layer 100 to facilitate connection of the gate strip electrode 6 to external circuits. If the second dielectric layer 200 is grown entirely on the first dielectric layer 100, the side parallel to the long side of the gate strip electrode 6 can be etched to be shorter than the gate strip electrode 6.

[0097] After the second dielectric layer 200 is completed, a chemical mechanical polishing process may be performed on the surface of the second dielectric layer 200 to form a flat surface, thereby providing a good base for subsequent structure growth.

[0098] refer to Figure 2 and 3 , a drain strip electrode 5 is further provided on the second dielectric layer 200 , and a gate strip electrode 6 is already provided on the corresponding first dielectric layer 100 ; here, the drain strip electrode 5 is also grown on the second dielectric layer 200 by a growth method, and the drain strip electrode 5 is connected to the drain electrodes 4 of the field effect transistors 1 of the same column or row; the drain strip electrode 5 and the gate strip electrode 6 are generally orthogonal to each other.

[0099] The material selection requirements for the drain strip electrode 5 are consistent with the material selection requirements for the gate strip electrode 6 .

[0100] refer to Figure 2 and 3 After growing the drain strip electrode 5, an insulating dielectric layer, namely a third dielectric layer 300, is required for corresponding isolation. Specifically, the third dielectric layer 300 is provided on the second dielectric layer 200. Here, the third dielectric layer 300 is also grown on the second dielectric layer 200. The third dielectric layer 300 covers the field effect transistor drain 4 and the drain strip electrode 5.

[0101] At the same time, at least one edge of the third dielectric layer 300 needs to leave a strip that does not cover the drain strip electrode 5 on the second dielectric layer 200. In other words, one or both of the length and width of the third dielectric layer 300 should be smaller than those of the second dielectric layer 200. This facilitates connection of the drain strip electrode 5 to external circuits. If the third dielectric layer 300 is grown entirely on the second dielectric layer 200, the length of the side parallel to the long side of the drain strip electrode 5 can be shortened by etching.

[0102] After the third dielectric layer 300 is completed, a chemical mechanical polishing process may be performed on the surface of the third dielectric layer 300 to form a flat surface, thereby providing a good base for subsequent structure growth.

[0103] refer to Figure 3 and 4An array of first ferroelectric tunnel junction electrodes 8 connected to the source electrodes 2 of the field-effect transistors is disposed upwardly on the third dielectric layer 300, corresponding to the source electrodes 2 of the field-effect transistors below. Here, the array of first ferroelectric tunnel junction electrodes 8 connected to the source electrodes 2 of the field-effect transistors is also grown upwardly on the third dielectric layer 300, corresponding to the source electrodes 2 of the field-effect transistors below. The thickness of the ferroelectric tunnel junction should be determined based on current process conditions. Given the current integration density, the allowable diameter of a single three-dimensional ferroelectric tunnel junction memory device is 50 nm. Therefore, the thickness (i.e., diameter) of the first ferroelectric tunnel junction electrode 8 should be approximately 20 to 30 nm to ensure conductivity and mechanical strength, while also leaving sufficient space for the ferroelectric dielectric tunnel layer 9 (generally less than 5 nm) and the second ferroelectric tunnel junction electrode 10 (generally 5 to 10 nm thick to ensure conductivity).

[0104] After forming the third dielectric layer 300, the source electrode 2 of the field-effect transistor needs to be exposed. This can be done by increasing the height of the source electrode 2 of the field-effect transistor. In this example, the second dielectric layer 200 and the third dielectric layer 300 are etched away above the source electrode 2 of the field-effect transistor to form a through hole. A conductor 7 made of a conductive material is grown within the through hole until it reaches the top surface of the third dielectric layer 300, exposing the conductor. The conductor 7 is used to connect the source electrode 2 of the field-effect transistor to the first electrode 8 of the ferroelectric tunnel junction.

[0105] The material of the conductor 7 is selected from but not limited to heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, titanium, cobalt, ruthenium, molybdenum, tantalum, alloys thereof and / or combinations thereof, which can form good contact.

[0106] refer to Figure 7 The first electrode 8 of the ferroelectric tunnel junction here is a columnar electrode; the specific shape of the columnar electrode can be selected as a rectangular parallelepiped, a cylinder, a hexagonal prism, an octagonal prism, etc., as long as it has a large aspect ratio structure. This can ensure that the electrode area of ​​a single ferroelectric tunnel junction device is increased as much as possible while occupying a certain area on the plane to increase the reading current. The material is selected as an electrode material with good conductivity and good mechanical strength, which can ensure that it can support itself when it forms a large aspect ratio material.

[0107] The ferroelectric tunnel junction first electrode 8 has but is not limited to the following three structural forms:

[0108] The first type, single electrode, reference Figure 7 In the two figures on the left, the first ferroelectric tunnel junction electrode 8 is a columnar electrode formed by a ferroelectric tunnel junction electrode material 801 alone; specifically, the ferroelectric tunnel junction electrode material 801 is grown on the entire surface of the third dielectric layer 300 to a required height, and then etched to form the first ferroelectric tunnel junction electrode 8, and finally formed as shown in FIG. Figure 6An array of arranged ferroelectric tunnel junction first electrodes 8 .

[0109] This growth process is relatively simple, but it also places high demands on the material of the ferroelectric tunnel junction electrode material 801. Under this structure, the electrode material must have high mechanical strength and a good process to etch it to form a flat surface. The material itself should also meet the requirements of the ferroelectric tunnel junction. For example, it should meet the requirements of the ferroelectric generation of the ferroelectric layer and the tunneling effect of the tunnel junction itself. If the ferroelectric properties of the ferroelectric layer place certain requirements on the electrode, the electrode material should also meet these requirements. For example, when the ferroelectric layer is selected to be a ferroelectric layer doped with hafnium oxide, the preferred electrode should be a material such as titanium nitride that can assist in the doping of hafnium oxide to produce a ferroelectric phase.

[0110] The second type, double-layer electrode, reference Figure 7 In the two figures above, the ferroelectric tunnel junction electrode material 801 includes a columnar electrode core 802 and an electrode layer of the ferroelectric tunnel junction electrode material 801 coated outside the electrode core 802, forming a double-layer columnar electrode.

[0111] Specifically, first, the electrode core material is grown on the entire surface of the third dielectric layer 300 to reach the required height, and then etched to form the electrode core 802, and finally formed as shown in FIG. Figure 5 An array of arranged electrode cores 802. The electrode cores 802 serve as internal supports and are required to have sufficient mechanical strength and be easy to etch and grow, including but not limited to polysilicon materials.

[0112] Then, a ferroelectric tunnel junction electrode material 801 is grown on the electrode core 802 to form an array of ferroelectric tunnel junction first electrodes 8. The ferroelectric tunnel junction electrode material 801 is made of titanium nitride, tungsten, ruthenium and other materials with excellent conductivity and suitable for process integration.

[0113] The third type, three-layer electrode, reference Figure 7 In the two figures on the right column, the ferroelectric tunnel junction electrode material 801 includes a columnar electrode core 802, the columnar electrode core 802 is coated with a buffer electrode material layer 803, and the electrode material layer 803 is coated with an electrode layer of the ferroelectric tunnel junction electrode material 801 to form a three-layer columnar electrode.

[0114] Specifically, first, the electrode core material is grown on the entire surface of the third dielectric layer 300 to reach the required height, and then etched to form the electrode core 802, and finally formed as shown in FIG. Figure 5 An array of arranged electrode cores 802. The electrode cores 802 serve as internal supports and are required to have sufficient mechanical strength and be easy to etch and grow, including but not limited to polysilicon materials.

[0115] A buffer electrode material layer 803 is then grown on the electrode core 802. This buffer layer can be made of a highly conductive metal or heavily doped polysilicon to reduce the negative effects of electrode resistance. This buffer layer is suitable for applications where the resistivity of the ferroelectric tunnel junction electrode material 801 itself is high in high-density integration.

[0116] Finally, a ferroelectric tunnel junction electrode material 801 is grown on the buffer electrode material layer 803 to form an array of ferroelectric tunnel junction first electrodes 8. The ferroelectric tunnel junction electrode material 801 is made of titanium nitride, tungsten, ruthenium and other materials with excellent conductivity and suitable for process integration.

[0117] It can be seen that the first electrode 8 of the ferroelectric tunnel junction can be a single material or a multi-layer material, such as a titanium nitride / heavily doped polysilicon double-layer material. If a multi-layer material is prepared, it is necessary to conformally grow the second layer of electrode material and etch it after the first layer of columnar electrode is etched.

[0118] refer to Figure 3 and 6 , a ferroelectric dielectric tunneling layer 9 is provided on the surface of the first ferroelectric tunnel junction electrode 8; here, the ferroelectric dielectric tunneling layer 9 is also grown on the first ferroelectric tunnel junction electrode 8 by a growth method.

[0119] refer to Figure 8 , in the upper left column, the ferroelectric dielectric tunneling layer 9 can be a single ferroelectric layer 901.

[0120] refer to Figure 8 Except for the left column of the figure, the ferroelectric dielectric tunneling layer 9 can be a stacked structure of two or more layers consisting of at least one ferroelectric layer 901 and at least one dielectric layer 902.

[0121] As can be seen, the structure of the ferroelectric dielectric tunneling layer 9 can be composed of a single ferroelectric layer 901 material. Alternatively, a low-k dielectric layer 902 material with a high bandgap can be introduced to form a ferroelectric tunneling layer. There is no clear relationship between the ferroelectric layer 901 and the dielectric layer 902, nor is there a clear relationship between the top and the bottom, or the number of layers. Alternatively, the number of ferroelectric layers 901 and dielectric layers 902 can be more than one layer. A ferroelectric layer 901 can be sandwiched between two dielectric layers 902, or the number of ferroelectric layers and dielectric layers can be increased to form an interlaced structure.

[0122] Among them, the material of the dielectric layer 902 is selected as an insulating dielectric material with a large band gap and a low dielectric constant, such as silicon oxide or aluminum oxide. The larger band gap ensures its good insulation and brings a larger switching ratio to the device, so as to facilitate the realization and reading of different discrete states. The lower dielectric constant is to reduce the delay effect of the capacitance on the entire circuit when the device is operated at high frequency.

[0123] The ferroelectric layer 901 is a ferroelectric material with stable and reversible electric polarization. Based on ferroelectric multi-domain switching, the ferroelectric layer can be in at least two stable directions to obtain at least two storage states. The ferroelectric material of the ferroelectric layer may include at least one material selected from the following: wurtzite-based ferroelectric nitride material, hafnium oxide, doped hafnium oxide (the doping element may be zirconium, yttrium, aluminum, silicon, gadolinium, strontium, lanthanum, nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium, gallium, calcium, carbon, but not limited to the above elements), barium titanate, colemanite, bismuth titanate, barium europium titanate, ferroelectric polymer, germanium telluride, anhydrous potassium magnesium sulfate, scandium lead tantalate, lead titanate, lead zirconate titanate, lithium niobate, polyvinylidene fluoride, potassium niobate, potassium sodium tartrate, potassium titanyl phosphate, sodium bismuth titanate, lithium tantalate, lanthanum lead titanate, lanthanum lead zirconate titanate, ammonium dihydrogen phosphate and potassium dihydrogen phosphate. Other suitable ferroelectric materials are within the expected scope of the present invention. The preferred ferroelectric material can form a continuous ferroelectric layer continuously and uniformly on the surface of the columnar electrode by atomic layer deposition technology.

[0124] In the ferroelectric dielectric tunneling layer 9, the sum of the thicknesses of the ferroelectric layer 901 and the dielectric layer 902 should be less than 5 nanometers to ensure that the main conductive mechanism is tunneling. This ensures that after the ferroelectric storage state of the storage device is changed in a non-volatile, stable, and low-power manner, the ferroelectric storage state can be directly and non-destructively read by reading the tunneling current.

[0125] refer to Figure 3 and 6 A second ferroelectric tunnel junction electrode 10 is disposed on the entire top surface of the device. This second ferroelectric tunnel junction electrode 10 is also grown on the top surface of the device. Considering the impact of the electrode material's conductivity on performance, after growing the second ferroelectric tunnel junction electrode 10, a conductive layer can be further grown to connect all individual devices, thereby reducing energy loss in the circuit. This conductive layer can be made of a material with good conductivity, such as copper.

[0126] The fourth dielectric layer 400 is then entirely covered on the upper surface. Here, the fourth dielectric layer 400 is also grown on the upper surface of the current device. Considering that the ferroelectric tunnel junction second electrode 10 needs to be fully covered here, it is necessary to provide insulation or a multi-layer arrangement.

[0127] At the same time, at least one edge of the fourth dielectric layer 400 must leave a strip that does not cover the ferroelectric tunnel junction second electrode 10 on the third dielectric layer 300. In other words, one or both of the length and width dimensions of the fourth dielectric layer 400 should be smaller than those of the third dielectric layer 300. The ferroelectric tunnel junction second electrode 10 is connected to an external circuit. If the fourth dielectric layer 400 is grown entirely on the third dielectric layer 300, one edge of the fourth dielectric layer 400 can be etched to a size smaller than that of the third dielectric layer 300.

[0128] In summary, after each insulating dielectric layer is covered, the material surface may be optionally subjected to chemical mechanical polishing to form a flat surface, thereby providing a good base for subsequent structure growth.

[0129] Example 2

[0130] like Figure 9 As shown, the ferroelectric tunnel junction memory device can be a multi-layer stack of ferroelectric tunnel junction memory devices; the fourth dielectric layer 400 of the lower ferroelectric tunnel junction memory device serves as the first dielectric layer 100 of the upper layer; thereon, in sequence, are grown a field effect transistor monomer 1, a drain strip electrode 5 or a gate strip electrode 6, a second dielectric layer 200 of the upper layer, a gate strip electrode 6 or a drain strip electrode 5, a third dielectric layer 300 of the upper layer, a ferroelectric tunnel junction first electrode 8, a ferroelectric dielectric tunneling layer 9, a ferroelectric tunnel junction second electrode 10, and a fourth dielectric layer 400 of the upper layer, forming a multi-layer stack structure of at least two layers of ferroelectric tunnel junction memory devices. Simultaneously, one or all of the length or width dimensions of the upper dielectric layer among the first dielectric layer 100, the second dielectric layer 200, the third dielectric layer 300, and the fourth dielectric layer 400 are smaller than those of the lower dielectric layer, forming a terraced structure of the ferroelectric tunnel junction memory device multi-layer stack; electrodes of each layer are exposed at the staggered layer edges for electrode leads.

[0131] Example 3

[0132] like Figure 10 As shown, a ferroelectric tunnel junction memory device structurally includes a first dielectric layer 100; multiple field effect transistor monomers 1, a drain strip electrode 5, a second dielectric layer 200, a gate strip electrode 6, a third dielectric layer 300, a ferroelectric tunnel junction first electrode 8, a ferroelectric dielectric tunneling layer 9, a ferroelectric tunnel junction second electrode 10 and a fourth dielectric layer 400.

[0133] You can refer to Figure 2 and 3 As shown, the first dielectric layer 100 serves as a substrate, and blind vias arranged in a hexagonal close-packed array are etched on the upper surface of the first dielectric layer 100. A ferroelectric tunnel junction second electrode 10 is then integrally arranged on the upper surface of the first dielectric layer 100 and the inner surface of the blind vias. Here, a layer of the ferroelectric tunnel junction second electrode 10 is also grown three-dimensionally and conformally on the upper surface of the first dielectric layer 100 and the inner surface of the blind vias. The ferroelectric tunnel junction second electrode 10 within the blind vias again forms an inner blind via of the ferroelectric tunnel junction second electrode 10. Three-dimensional conformal growth refers to growing the ferroelectric tunnel junction second electrode 10 on the surface of an existing product in a fully covered manner while maintaining the product's shape roughly unchanged.

[0134] The material and thickness of the second ferroelectric tunnel junction electrode 10 refer to the corresponding description in the first embodiment.

[0135] A ferroelectric dielectric tunneling layer 9 is disposed on the inner surface of the inner blind hole of the ferroelectric tunnel junction second electrode 10 formed within the blind hole trench; its upper surface is flush with the ferroelectric tunnel junction second electrode 10. Here, a layer of ferroelectric dielectric tunneling layer 9 is grown on the ferroelectric tunnel junction second electrode 10 using a three-dimensional conformal growth method. An inner blind hole of the ferroelectric dielectric tunneling layer 9 is again formed within the inner blind hole of the ferroelectric tunnel junction second electrode 10.

[0136] The structure and materials of the ferroelectric dielectric tunneling layer 9 refer to the corresponding description in the first reference embodiment.

[0137] The first ferroelectric tunnel junction electrode 8 is filled in the inner blind hole of the ferroelectric dielectric tunneling layer 9; the upper surface is flush with the second ferroelectric tunnel junction electrode 10; here, the first ferroelectric tunnel junction electrode 8 is grown in the inner blind hole of the ferroelectric dielectric tunneling layer 9 and filled.

[0138] refer to Figure 7 Here, the first ferroelectric tunnel junction electrode 8 is a columnar electrode; it can also be considered a slot-shaped electrode. The specific shape of the columnar electrode can be a rectangular parallelepiped, a cylinder, a hexagonal prism, an octagonal prism, etc., as long as it has a large aspect ratio structure. This ensures that the electrode area of ​​a single ferroelectric tunnel junction device is maximized while occupying a certain area on the plane, thereby improving the read current. The electrode material selected should have good conductivity and good mechanical strength to ensure that it can support itself when formed into a high-aspect-ratio material.

[0139] The ferroelectric tunnel junction first electrode 8 has but is not limited to the following three structural forms:

[0140] The first type, single electrode, reference Figure 7 In the two figures below, the first ferroelectric tunnel junction electrode 8 is a columnar electrode formed by a ferroelectric tunnel junction electrode material 801 alone; specifically, the first ferroelectric tunnel junction electrode 8 is grown in a blind hole inside the ferroelectric dielectric tunnel layer 9, and finally a reference is formed. Figure 5 An array of arranged ferroelectric tunnel junction first electrodes 8 .

[0141] This growth process is relatively simple, but it also places high demands on the material of the ferroelectric tunnel junction electrode material 801. In this structure, the electrode material must have high mechanical strength and a good process to etch it to form a flat surface. The material itself should also meet the requirements of the ferroelectric tunnel junction. For example, it should meet the requirements of the ferroelectric generation of the ferroelectric layer and the tunneling effect of the tunnel junction itself. If the ferroelectric properties of the ferroelectric layer place certain requirements on the electrode, the electrode material should also meet these requirements. For example, when the ferroelectric layer is selected to be a ferroelectric layer doped with hafnium oxide, the preferred electrode should be a material such as titanium nitride that can assist in the doping of hafnium oxide to produce a ferroelectric phase.

[0142] The second type, double-layer electrode, reference Figure 7 In the two figures below, the ferroelectric tunnel junction electrode material 801 includes a columnar electrode core 802 and an electrode layer of the ferroelectric tunnel junction electrode material 801 coated outside the electrode core 802, forming a double-layer columnar electrode.

[0143] Specifically, first, a layer of ferroelectric tunnel junction electrode material 801 is grown in the inner blind hole of the ferroelectric dielectric tunneling layer 9 to form an inner blind hole composed of the ferroelectric tunnel junction electrode material 801 .

[0144] Then, the electrode core 802 is grown and filled in the inner blind hole of the ferroelectric tunnel junction electrode material 801. The electrode core 802 serves as an inner support and is required to have sufficient mechanical strength and be easy to etch and grow, including but not limited to polysilicon materials.

[0145] The third type, three-layer electrode, reference Figure 7 In the two figures on the right column, the ferroelectric tunnel junction electrode material 801 includes a columnar electrode core 802, the columnar electrode core 802 is coated with a buffer electrode material layer 803, and the electrode material layer 803 is coated with an electrode layer of the ferroelectric tunnel junction electrode material 801 to form a three-layer columnar electrode.

[0146] Specifically, first, a layer of ferroelectric tunnel junction electrode material 801 is grown in the inner blind hole of the ferroelectric dielectric tunneling layer 9 to form an inner blind hole composed of the ferroelectric tunnel junction electrode material 801 .

[0147] A buffer electrode material layer 803 is then grown within the inner blind hole of the ferroelectric tunnel junction electrode material 801, forming an inner blind hole formed by the buffer electrode material layer 803. The buffer layer can be made of a highly conductive metal or heavily doped polysilicon to reduce the negative effects of electrode resistance. This buffer layer material is suitable for high-density integration applications where the ferroelectric tunnel junction electrode material 801 itself has a high resistivity.

[0148] Finally, the inner blind hole of the buffer electrode material layer 803 is filled with the electrode core 802. The electrode core 802 serves as an inner support and is required to have sufficient mechanical strength and be easy to etch and grow, including but not limited to polysilicon materials.

[0149] It can be seen that the first electrode 8 of the ferroelectric tunnel junction can be a single material or a multi-layer material, such as a titanium nitride / heavily doped polysilicon double-layer material. If a multi-layer material is prepared, it is necessary to conformally grow the second layer of electrode material and etch it after the first layer of columnar electrode is etched.

[0150] A second dielectric layer 200 is disposed on the entire upper surface of the current device; the second dielectric layer 200 is also grown in a growth manner, and the second dielectric layer 200 needs to cover the first ferroelectric tunnel junction electrode 8, the ferroelectric dielectric tunnel layer 9 and the second ferroelectric tunnel junction electrode 10;

[0151] At the same time, at least one edge of the second dielectric layer 200 needs to leave a strip that does not cover the ferroelectric tunnel junction second electrode 10 on the first dielectric layer 100. In other words, the second dielectric layer 200 should have one or both of its length and width smaller than the first dielectric layer 100. This facilitates connection of the ferroelectric tunnel junction second electrode 10 to an external circuit. If the second dielectric layer 200 is grown entirely on the first dielectric layer 100, etching can be used to expose the ferroelectric tunnel junction second electrode 10 on at least one edge.

[0152] After the second dielectric layer 200 is completed, a chemical mechanical polishing process may be performed on the surface of the second dielectric layer 200 to form a flat surface, thereby providing a good base for subsequent structure growth.

[0153] After forming the second dielectric layer 200, the first ferroelectric tunnel junction electrode 8 needs to be exposed. This can be done by increasing the height of the first ferroelectric tunnel junction electrode 8. In this example, the second dielectric layer 200 is etched away above the first ferroelectric tunnel junction electrode 8 to form a through hole. A conductor 7 made of a conductive material is grown within the through hole until it reaches the top surface of the second dielectric layer 200, exposing the conductor. The conductor 7 is used to connect the source electrode 2 of the field-effect transistor to the first ferroelectric tunnel junction electrode 8.

[0154] The material of the conductor 7 is selected from but not limited to heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, titanium, cobalt, ruthenium, molybdenum, tantalum, alloys thereof and / or combinations thereof, which can form good contact.

[0155] An array of field-effect transistor (FET) monomers 1 is positioned upward from the second dielectric layer 200, corresponding to the first ferroelectric tunnel junction electrode 8 below. Multiple FET monomers 1 are grown in a rectangular array on the second dielectric layer 200 using a growth method. The term "growth" herein can refer to electrode growth and processing techniques used in integrated circuit manufacturing, and the underlying principles are not elaborated here. Multiple FET monomers 1 constitute the array of FET monomers 1. Each FET monomer 1 includes a FET source 2, a FET gate 3, and a FET drain 4. In this example, each FET monomer 1 includes two FET sources 2, two FET gates 3, and a FET drain 4. The two FETs forming a shared drain form a strip-shaped FET monomer 1. The first ferroelectric tunnel junction electrodes 8 are each connected to the corresponding FET source 2.

[0156] The array of field-effect transistor cells 1 generated here can be either a "rectangular array" or a staggered "rectangular array." It is necessary to ensure that the field-effect transistor sources 2 are arranged in a "hexagonal close-packed" array on the second dielectric layer 200. Hexagonal close-packing refers to constructing an array in a hexagonal, close-packed manner, which fully utilizes the single-layer planar area and further increases the integration density. This "hexagonal close-packed" arrangement has the same function as the hexagonal shape of a honeycomb, fully utilizing the single-layer planar area.

[0157] like Figure 4 As shown, the generated field effect transistor monomers 1 share a drain electrode, and the field effect transistor monomers 1 are arranged as a "rectangular array" as a whole. The subsequent strip-shaped field effect transistor monomers 1 are tilted at a 60-degree angle to ensure that the field effect transistor sources 2 are arranged in a hexagonal close-packed array on the second dielectric layer 200. This also enables the multiple ferroelectric tunnel junction first electrodes 8 grown later to be arranged in a "hexagonal close-packed" array. Figure 4 The five consecutive squares in the middle bar represent the field effect transistor monomers with a shared drain, while the solid black blocks are arranged in a "hexagonal close-packed" manner, expressing the "hexagonal close-packed" arrangement of the source 2 of the field effect transistor, and can be extended outward within the range allowed by the structural size.

[0158] like Figure 5 As shown, if a separate field effect transistor is generated instead of a shared drain, an interlaced "rectangular array" arrangement is adopted, where the field effect transistors in adjacent rows are staggered and the field effect transistors in alternate rows are arranged in a "rectangular array", that is, two "rectangular arrays" are interlaced to ensure that the source electrodes 2 of the field effect transistors are arranged in a hexagonal close-packed array on the second dielectric layer 200. Figure 5 The three consecutive squares in the middle strip represent field-effect transistors that do not share a common drain. Adjacent rows are arranged in a staggered "rectangular array" and tilted at a 60-degree angle, ensuring that the source electrodes 2 of the field-effect transistors are arranged in a hexagonal close-packed array on the second dielectric layer 200 and facilitating the subsequent arrangement of strip electrodes.

[0159] Here, the drain strip electrodes 5 and gate strip electrodes 6 are grown on the second dielectric layer 200. This can be done by growing the drain strip electrodes 5 first and then the gate strip electrodes 6, or by growing the gate strip electrodes 6 first and then the drain strip electrodes 5. If the drain strip electrodes 5 are formed on this layer, the gate strip electrodes 6 are then formed on the third dielectric layer 300. Alternatively, the gate strip electrodes 6 are formed on this layer and the drain strip electrodes 5 are then formed on the third dielectric layer 300.

[0160] At the same time, you can refer to Figure 3 In order to facilitate the subsequent growth of the drain strip electrode 5 or the gate strip electrode 6, the strip-shaped field effect transistor monomer 1 is tilted to form an angle of 15 to 75 degrees with the drain strip electrode 5. This needs to be controlled when the blind hole trench array is generated in the early stage. Figure 3 Taking the drain strip electrode 5 as an example, since the drain strip electrode 5 has a certain width, the strip-shaped FET monomer 1 is tilted at a 60-degree angle to the drain strip electrode 5, placing the drain strip electrode 5 precisely between the two FET gates 3. Furthermore, this 60-degree angle allows the multiple ferroelectric tunnel junction first electrodes 8 to be arranged in a dense hexagonal pattern to form an array, fully utilizing the single-layer planar area and further increasing integration density. This "hexagonal close-packed" arrangement functions similarly to the hexagonal shape of a honeycomb, fully utilizing the single-layer planar area. The same principle applies to the gate strip electrode 6, except that it needs to be connected to the two FET gates 3 separately, avoiding the FET drain 4.

[0161] Of course, if the field effect transistor monomer 1 only includes one field effect transistor, there is no need to consider the angle problem, as long as the drain strip electrode 5 and the gate strip electrode 6 are staggered and do not touch each other. Usually, the larger size is more than 10 nm.

[0162] The height of the field effect transistor gate 3 here is greater than the sum of the heights of the field effect transistor drain 4 and the drain strip electrode 5, and the greater size is sufficient to ensure that no electrical breakdown occurs between the drain strip electrode 5 and the gate strip electrode 6.

[0163] In this example, the drain strip electrode 5 is first grown and then the gate strip electrode 6 is grown. After the strip-shaped field effect transistor monomer 1 is grown, the drain strip electrode 5 is provided on the second dielectric layer 200. Here, the drain strip electrode 5 is also grown on the second dielectric layer 200 by a growth method, and is connected to the field effect transistor drain 4 of the field effect transistor monomer 1 in the same row or column.

[0164] The electrode material of the drain strip electrode 5 can be, but is not limited to, heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or other electrode materials that have good conductivity and can form good contact with adjacent electrode materials.

[0165] A third dielectric layer 300 is disposed on the second dielectric layer 200. Here, the third dielectric layer 300 is also grown on the second dielectric layer 200. The third dielectric layer 300 needs to cover the field-effect transistor drain electrode 4 and the drain strip electrode 5. The height of the third dielectric layer 300 should not exceed the height of the field-effect transistor gate 3 to facilitate the subsequent arrangement of the gate strip electrode 6 for electrical connection to the field-effect transistor gate 3. Of course, if the height of the third dielectric layer 300 exceeds the height of the field-effect transistor gate 3, it is necessary to etch the third dielectric layer 300 at the location corresponding to the field-effect transistor gate 3 before arranging the gate strip electrode 6 to expose the field-effect transistor gate 3.

[0166] At the same time, at least one edge of the third dielectric layer 300 needs to leave a strip that does not cover the drain strip electrode 5 on the second dielectric layer 200. In other words, one or both of the length and width of the third dielectric layer 300 should be smaller than those of the second dielectric layer 200. This facilitates connection of the drain strip electrode 5 to external circuits. If the third dielectric layer 300 is grown entirely on the second dielectric layer 200, the length of the side parallel to the long side of the drain strip electrode 5 can be shortened by etching.

[0167] After the third dielectric layer 300 is completed, a chemical mechanical polishing process may be performed on the surface of the third dielectric layer 300 to form a flat surface, thereby providing a good base for subsequent structure growth.

[0168] A gate strip electrode 6 is further provided on the third dielectric layer 300; at this time, the drain strip electrode 5 is already provided on the corresponding second dielectric layer 200; here, the gate strip electrode 6 is also grown on the third dielectric layer 300 by a growth method, and the gate strip electrode 6 is connected to the field effect transistor gates 3 of the field effect transistor monomers 1 in the same column or row; the gate strip electrode 6 and the drain strip electrode 5 are intersected, generally in an orthogonal manner.

[0169] The material selection requirements for the gate strip electrodes 6 are consistent with the material selection requirements for the drain strip electrodes 5 .

[0170] After the gate strip electrodes 6 are grown, an insulating dielectric layer, namely a fourth dielectric layer 400, is added for isolation. Specifically, the fourth dielectric layer 400 is disposed on the third dielectric layer 300. Here, the fourth dielectric layer 400 is also grown on the third dielectric layer 300. The fourth dielectric layer 400 covers the field effect transistor gate 3 and the gate strip electrodes 6.

[0171] At the same time, at least one edge of the fourth dielectric layer 400 needs to leave a strip that does not cover the gate strip electrode 6 on the third dielectric layer 300. In other words, the fourth dielectric layer 400 should have one or both of its length and width smaller than the third dielectric layer 300 to facilitate connection of the gate strip electrode 6 to external circuits. If the fourth dielectric layer 400 is grown entirely on the third dielectric layer 300, the side parallel to the long side of the gate strip electrode 6 can be etched to be shorter than the gate strip electrode 6.

[0172] After the fourth dielectric layer 400 is completed, a chemical mechanical polishing process may be performed on the surface of the fourth dielectric layer 400 to form a flat surface, thereby providing a good base for subsequent structure growth.

[0173] In summary, after each insulating dielectric layer is covered, the material surface may be optionally subjected to chemical mechanical polishing to form a flat surface, thereby providing a good base for subsequent structure growth.

[0174] Taking the example of first growing the gate strip electrode 6 and then growing the drain strip electrode 5, after the strip-shaped field effect transistor monomer 1 is grown, the gate strip electrode 6 is provided on the second dielectric layer 200. Here, the gate strip electrode 6 is also grown on the second dielectric layer 200 by a growth method, and is connected to the field effect transistor gates 3 of the field effect transistor monomers 1 in the same row or column.

[0175] The electrode material of the gate strip electrode 6 can be, but is not limited to, heavily doped polysilicon, metal silicide, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or other electrode materials that have good conductivity and can form good contact with adjacent electrode materials.

[0176] A third dielectric layer 300 is disposed on the second dielectric layer 200. Here, the third dielectric layer 300 is also grown on the second dielectric layer 200. The third dielectric layer 300 needs to cover the field-effect transistor gate 3 and the gate strip electrode 6. The height of the third dielectric layer 300 should not exceed the height of the field-effect transistor drain 4, facilitating the subsequent arrangement of the drain strip electrode 5 for electrical connection to the field-effect transistor drain 4. Of course, if the height of the third dielectric layer 300 exceeds the height of the field-effect transistor drain 4, it is necessary to etch the third dielectric layer 300 at the location corresponding to the field-effect transistor drain 4 before arranging the drain strip electrode 5 to expose the field-effect transistor drain 4.

[0177] At the same time, at least one edge of the third dielectric layer 300 needs to leave a strip that does not cover the gate strip electrode 6 on the second dielectric layer 200. In other words, one or both of the length and width dimensions of the third dielectric layer 300 should be smaller than those of the second dielectric layer 200. This facilitates connection of the gate strip electrode 6 to external circuits. If the third dielectric layer 300 is grown entirely on the second dielectric layer 200, the length of the side parallel to the long side of the gate strip electrode 6 can be shortened by etching.

[0178] After the third dielectric layer 300 is completed, a chemical mechanical polishing process may be performed on the surface of the third dielectric layer 300 to form a flat surface, thereby providing a good base for subsequent structure growth.

[0179] A drain strip electrode 5 is further provided on the third dielectric layer 300 ; at this time, a gate strip electrode 6 is already provided on the corresponding second dielectric layer 200 ; here, the drain strip electrode 5 is also grown on the third dielectric layer 300 by a growth method, and the drain strip electrode 5 is connected to the drain electrodes 4 of the field effect transistor monomers 1 in the same column or row; the drain strip electrode 5 and the gate strip electrode 6 intersect, generally in an orthogonal manner.

[0180] The material selection requirements for the drain strip electrode 5 are consistent with the material selection requirements for the drain strip electrode 5 .

[0181] After growing the drain strip electrode 5, an insulating dielectric layer, namely a fourth dielectric layer 400, is added for isolation. Specifically, the fourth dielectric layer 400 is disposed on the third dielectric layer 300. Here, the fourth dielectric layer 400 is also grown on the third dielectric layer 300. The fourth dielectric layer 400 covers the field-effect transistor drain 4 and the drain strip electrode 5.

[0182] At the same time, at least one edge of the fourth dielectric layer 400 needs to leave a strip that does not cover the drain strip electrode 5 on the third dielectric layer 300. In other words, the fourth dielectric layer 400 should have one or both of its length and width smaller than the third dielectric layer 300. This facilitates connection of the drain strip electrode 5 to external circuits. If the fourth dielectric layer 400 is grown entirely on the third dielectric layer 300, the side parallel to the long side of the drain strip electrode 5 can be etched to be shorter than the drain strip electrode 5.

[0183] After the fourth dielectric layer 400 is completed, a chemical mechanical polishing process may be performed on the surface of the fourth dielectric layer 400 to form a flat surface, thereby providing a good base for subsequent structure growth.

[0184] In summary, after each insulating dielectric layer is covered, the material surface may be optionally subjected to chemical mechanical polishing to form a flat surface, thereby providing a good base for subsequent structure growth.

[0185] Example 4

[0186] You can refer to Figure 9 ,like Figure 11 As shown, the ferroelectric tunnel junction memory device can be a multi-layer stack of ferroelectric tunnel junction memory devices; the fourth dielectric layer 400 of the lower ferroelectric tunnel junction memory device serves as the first dielectric layer 100 of the upper layer; thereon, the ferroelectric tunnel junction second electrode 10, the ferroelectric dielectric tunneling layer 9, the ferroelectric tunnel junction first electrode 8, the upper second dielectric layer 200, the field effect transistor monomer 1, the drain strip electrode 5, the upper third dielectric layer 300, the gate strip electrode 6, and the upper fourth dielectric layer 400 are sequentially grown, forming a multi-layer stack structure of at least two layers of ferroelectric tunnel junction memory devices. At the same time, one or all of the length or width dimensions of the upper dielectric layer among the first dielectric layer 100, the second dielectric layer 200, the third dielectric layer 300, and the fourth dielectric layer 400 are smaller than the lower dielectric layer, forming a terraced structure of the ferroelectric tunnel junction memory device multi-layer stack structure; the electrodes of each layer are exposed at the staggered layer edges for electrode leads.

[0187] Figure 12 The figure shows the equivalent circuit diagram corresponding to a single-layer ferroelectric tunnel junction memory array. In this diagram, one end electrode of the ferroelectric tunnel junction memory devices in the same layer is connected via the ferroelectric tunnel junction second electrode 10. The other end electrode is open or connected via the field-effect transistor switch, preventing miswriting or misreading of information from different devices. The selection of a specific field-effect transistor and ferroelectric tunnel junction information unit can be uniquely determined by the row electrode (drain strip electrode 5) and the column electrode (gate strip electrode 6), enabling the selection of a specific memory device for read and write operations.

[0188] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art.

Claims

1. A ferroelectric tunnel junction memory device, characterized in that: It comprises a first dielectric layer (100) and an array of field effect tube monomers (1) arranged in an array thereon; The field effect transistor monomer (1) comprises a field effect transistor source (2), a field effect transistor gate (3) and a field effect transistor drain (4); the field effect transistor source (2) is arranged in a hexagonal close-packed array on the first dielectric layer (100); A drain strip electrode (5) or a gate strip electrode (6) is provided on the first dielectric layer (100); the drain strip electrode (5) is connected to the drain electrodes (4) of the field effect transistors (1) in the same row or column; and the gate strip electrode (6) is connected to the gate electrodes (3) of the field effect transistors (1) in the same row or column. A second dielectric layer (200) is provided on the first dielectric layer (100), covering the field effect transistor drain (4) and the drain strip electrode (5) or the gate strip electrode (6); A gate strip electrode (6) or a drain strip electrode (5) is further provided on the second dielectric layer (200); The gate strip electrode (6) is connected to the field effect transistor gates (3) of the field effect transistor monomers (1) in the same column or row; the drain strip electrode (5) is connected to the field effect transistor drains (4) of the field effect transistor monomers (1) in the same column or row; The second dielectric layer (200) is further provided with a third dielectric layer (300) to cover the field effect transistor gate (3) and the gate strip electrode (6) or the drain strip electrode (5); An array of ferroelectric tunnel junction first electrodes (8) connected to the source electrodes (2) of the field effect transistors is provided upwardly on the third dielectric layer (300) corresponding to the source electrodes (2) of the field effect transistors below; a ferroelectric dielectric tunnel layer (9) is further provided on the surface of the ferroelectric tunnel junction first electrodes (8); A ferroelectric tunnel junction second electrode (10) is entirely provided on the upper surface of the current device; and a fourth dielectric layer (400) is entirely covered on the upper surface.

2. The ferroelectric tunnel junction memory device according to claim 1, wherein: The ferroelectric tunnel junction memory device is multi-layered; The fourth dielectric layer (400) of the ferroelectric tunnel junction memory device in the lower layer serves as the first dielectric layer (100) of the upper layer; a field effect tube monomer (1), a drain strip electrode (5) or a gate strip electrode (6), a second dielectric layer (200) of the upper layer, a gate strip electrode (6) or a drain strip electrode (5), a third dielectric layer (300) of the upper layer, a ferroelectric tunnel junction first electrode (8), a ferroelectric dielectric tunneling layer (9), a ferroelectric tunnel junction second electrode (10) and a fourth dielectric layer (400) of the upper layer are sequentially arranged thereon; forming a multi-layer stacked structure of a ferroelectric tunnel junction memory device of at least two layers.

3. The ferroelectric tunnel junction memory device according to claim 2, wherein: Among the first dielectric layer (100), the second dielectric layer (200), the third dielectric layer (300) and the fourth dielectric layer (400), one or all of the length or width dimensions of the upper dielectric layer are smaller than those of the lower dielectric layer; a multi-layer stacked structure of a ferroelectric tunnel junction memory device with a terraced structure is formed; electrodes of each layer are exposed at the staggered layer edges for electrode leads.

4. The ferroelectric tunnel junction memory device according to claim 1, 2 or 3, wherein: The ferroelectric dielectric tunneling layer (9) comprises: a single ferroelectric layer (901), or; A two-layer or more stacked structure consisting of at least one ferroelectric layer (901) and at least one dielectric layer (902).

5. The ferroelectric tunnel junction memory device according to claim 1, 2 or 3, wherein: The field effect transistor monomer (1) comprises two field effect transistor source electrodes (2), two field effect transistor gate electrodes (3) and a field effect transistor drain electrode (4); A strip-shaped field effect tube monomer (1) is formed by two field effect tubes with a common drain.

6. A ferroelectric tunnel junction memory device, characterized in that: It comprises a first dielectric layer (100) and blind holes arranged in a hexagonal close-packed array are etched on the upper surface; and a ferroelectric tunnel junction second electrode (10) is integrally provided on the upper surface and the inner surface of the blind hole. A ferroelectric dielectric tunneling layer (9) is provided on the inner surface of the blind hole of the ferroelectric tunnel junction second electrode (10) in the blind hole groove; the upper surface is flush with the ferroelectric tunnel junction second electrode (10); A ferroelectric tunnel junction first electrode (8) is filled in a blind hole in a ferroelectric dielectric tunnel layer (9); the upper surface is flush with the ferroelectric tunnel junction second electrode (10); A second dielectric layer (200) is entirely provided on the upper surface of the current device; An array of field effect tube monomers (1) is arranged upwardly at a position corresponding to the first electrode (8) of the ferroelectric tunnel junction below the second dielectric layer (200); The field effect transistor monomer (1) comprises a field effect transistor source (2), a field effect transistor gate (3) and a field effect transistor drain (4); the first ferroelectric tunnel junction electrodes (8) are respectively connected to the field effect transistor source electrodes (2); the field effect transistor source electrodes (2) are arranged in a hexagonal close-packed array on the second dielectric layer (200); A drain strip electrode (5) or a gate strip electrode (6) is provided on the second dielectric layer (200); the drain strip electrode (5) is connected to the drain electrode (4) of the field effect transistor monomer (1) in the same row or column; the gate strip electrode (6) is connected to the gate electrode (3) of the field effect transistor monomer (1) in the same row or column; A third dielectric layer (300) is further provided on the second dielectric layer (200), covering the field effect transistor drain (4) and the drain strip electrode (5) or the gate strip electrode (6); A gate strip electrode (6) or a drain strip electrode (5) is further provided on the third dielectric layer (300); The gate strip electrode (6) is connected to the field effect transistor gates (3) of the field effect transistor monomers (1) in the same column or row; the pole strip electrode (5) is connected to the field effect transistor drains (4) of the field effect transistor monomers (1) in the same column or row; The third dielectric layer (300) is further provided with a fourth dielectric layer (400) to cover the field effect transistor gate (3) and the gate strip electrode (6) or the drain strip electrode (5).

7. The ferroelectric tunnel junction memory device according to claim 6, wherein: Multilayer stacking of ferroelectric tunnel junction memory devices; The fourth dielectric layer (400) of the ferroelectric tunnel junction memory device in the lower layer serves as the first dielectric layer (100) of the upper layer; a ferroelectric tunnel junction second electrode (10), a ferroelectric dielectric tunneling layer (9), a ferroelectric tunnel junction first electrode (8), a second dielectric layer (200) of the upper layer, a field effect transistor monomer (1), a drain strip electrode (5) or a gate strip electrode (6), a third dielectric layer (300) of the upper layer, a gate strip electrode (6) or a drain strip electrode (5), and a fourth dielectric layer (400) of the upper layer are sequentially arranged thereon; a multi-layer stacked structure of a ferroelectric tunnel junction memory device of at least two layers is formed.

8. The ferroelectric tunnel junction memory device according to claim 7, wherein: Among the first dielectric layer (100), the second dielectric layer (200), the third dielectric layer (300) and the fourth dielectric layer (400), one or all of the length or width dimensions of the upper dielectric layer are smaller than those of the lower dielectric layer; a multi-layer stacked structure of a ferroelectric tunnel junction memory device with a terraced structure is formed; electrodes of each layer are exposed at the staggered layer edges for electrode leads.

9. The ferroelectric tunnel junction memory device according to claim 6, 7 or 8, characterized in that: The ferroelectric dielectric tunneling layer (9) comprises: a single ferroelectric layer (901), or; A two-layer or more stacked structure consisting of at least one ferroelectric layer (901) and at least one dielectric layer (902).

10. The ferroelectric tunnel junction memory device according to claim 6, 7 or 8, characterized in that: The field effect transistor monomer (1) comprises two field effect transistor source electrodes (2), two field effect transistor gate electrodes (3) and a field effect transistor drain electrode (4); A strip-shaped field effect tube monomer (1) is formed by two field effect tubes with a common drain.

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