Array substrate and display device

Abstract

According to the array substrate and the display device, the first display area and the non-rectangular second display area are sequentially arranged in the first direction, and the frame area comprises the first frame area surrounding the first display area and the second frame area surrounding the second display area; the grid lines are arranged in the display area in the first direction and extend to the frame area in the second direction, and the second direction intersects with the first direction; the data lines and the grid lines are mutually insulated, and the data lines are arranged in the second direction in the display area, extend to the second frame area in the first direction and are wound in the second display area in the second frame area; the multiple anti-static structures are electrically connected with the multiple grid lines, the multiple anti-static structures comprise multiple first anti-static structures located in the first frame area and multiple second anti-static structures located in the second frame area, at least part of the first anti-static structures extend in the first direction, and at least part of the second anti-static structures extend in the second direction; at least part of the second anti-static structure extends in the winding direction of the data line.

Description

Array substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] With the rapid development of display technology, in addition to traditional functions such as information display, display panels are also facing increasing requirements for appearance in order to better adapt to the overall structure and usage requirements of the environment, resulting in the emergence of special-shaped display panels. Special-shaped display panels are specially shaped display panels modified from traditional display panels to better adapt the characteristics of the display panel to the overall structure and environment. Special-shaped display panels have been successfully applied to wearable electronic devices such as watches, glasses or smart bracelets, and common special-shaped display panels mainly include fan-shaped, arc-shaped, circular, cylindrical, polygonal and other shapes.

[0003] Summary of the Invention

[0004] The array substrate and display device provided by the embodiments of the present disclosure are specifically described as follows:

[0005] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0006] a base substrate, the base substrate comprising a display area and a frame area surrounding the display area, wherein the display area comprises a first display area and a second display area sequentially arranged along a first direction, the second display area being a non-rectangular display area; and the frame area comprises a first frame area surrounding the first display area and a second frame area surrounding the second display area;

[0007] a plurality of gate lines arranged along the first direction and extending along a second direction in the first display area and the second display area, wherein the gate lines in the first display area extend to the first frame area, and the gate lines in the second display area extend to the second frame area, and the second direction intersects the first direction;

[0008] a plurality of data lines, insulated from the plurality of gate lines, the plurality of data lines being arranged along the second direction in the first display area and the second display area and extending along the first direction, and the plurality of data lines extending to the second frame area and being arranged around the second display area in the second frame area;

[0009] Multiple anti-static structures are electrically connected to the multiple gate lines, and the multiple anti-static structures include multiple first anti-static structures located in the first border area and multiple second anti-static structures located in the second border area, wherein at least part of the first anti-static structures extend along the first direction, and at least part of the second anti-static structures extend along the winding direction of the data line.

[0010] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the anti-static structures electrically connected to two adjacent gate lines are located on both sides of the display area.

[0011] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a plurality of first floating anti-static structures and a plurality of second floating anti-static structures, wherein the plurality of first floating anti-static structures are electrically connected to the plurality of first anti-static structures in the first border area, and the plurality of first floating anti-static structures and the two first anti-static structures in the first border area that are farthest from the second border area are arranged side by side in the second direction; the second floating anti-static structure is electrically connected to the plurality of second anti-static structures in the second border area, and the plurality of second floating anti-static structures and the two second anti-static structures in the second border area that are farthest from the first border area are arranged side by side in the winding direction of the data line.

[0012] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a short-circuit ring, wherein the short-circuit ring is located in the first frame area and the second frame area;

[0013] The plurality of anti-static structures are electrically connected to the plurality of first floating anti-static structures and the plurality of second floating anti-static structures respectively through the short-circuit rings.

[0014] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a common electrode line and a common electrode, wherein the common electrode line is located in the first border area and the second border area, and the common electrode extends from the first display area and the second display area to the first border area and the second border area;

[0015] The plurality of first floating anti-static structures are electrically connected to the common electrode line, and the plurality of second floating anti-static structures are electrically connected to the common electrode.

[0016] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a first connecting line, which is in the same layer as the plurality of gate lines and connects the second floating anti-static structure and the common electrode.

[0017] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the short-circuit ring and the common electrode line are both in the same layer as the plurality of data lines.

[0018] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the second border area includes a binding area extending substantially along the second direction on a side of the second display area away from the first display area, a non-rectangular area connecting the binding area and the first border area, and a routing area located between the binding area and the second display area;

[0019] The array substrate also includes a second connecting line, which is on the same layer as the multiple gate lines. The second connecting line is connected between the common electrode line and the binding area. The second connecting line includes a widened portion, which is arranged adjacent to the connection between the routing area and the non-rectangular area, and the widened portion is a grid-like structure.

[0020] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, at least part of the gate lines are electrically connected to the anti-static structure after being bent in the first border area and the second border area.

[0021] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of gate leads, wherein the plurality of gate leads are electrically connected to the plurality of anti-static structures on a side of the plurality of anti-static structures away from the first display area and the second display area;

[0022] The plurality of gate leads include a plurality of first gate leads and a plurality of second gate leads. The plurality of first gate leads are in the same layer as the plurality of gate lines, and the plurality of second gate leads are in the same layer as the plurality of data lines.

[0023] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the anti-static structure includes a first transistor and a second transistor, wherein the gate of the first transistor is electrically connected to the gate line and the gate lead respectively, the first electrode of the first transistor is electrically connected to the gate of the first transistor, the second electrode of the first transistor is integrally arranged with the first electrode of the second transistor, the second electrode of the second transistor is integrally arranged with the first electrode of the first transistor, and the gate of the second transistor is electrically connected to the first electrode of the second transistor and the short-circuit ring.

[0024] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of first transfer electrodes and a plurality of second transfer electrodes, wherein the plurality of first transfer electrodes and the plurality of second transfer electrodes are arranged in the same layer on the layer where the plurality of gate lines are located and on a side of the layer where the plurality of data lines are located away from the base substrate;

[0025] The gate of the first transistor is electrically connected to the gate line and the gate lead respectively through the first switching electrode, and the gate of the second transistor is electrically connected to the first electrode of the second transistor and the short-circuit ring respectively through the second switching electrode.

[0026] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the second border area includes a binding area extending substantially along the second direction on a side of the second display area away from the first display area, a non-rectangular area connecting the binding area and the first border area, and a routing area located between the binding area and the second display area;

[0027] The gate lead includes a first gate lead section located in the non-rectangular area, a second gate lead section located in the routing area, and a third gate lead section connecting the first gate lead section and the second gate lead section; the sum of the line width of the first gate lead section and the line spacing of the first gate lead section adjacent to the same layer is a first distance, the sum of the line width of the second gate lead section and the line spacing of the second gate lead section adjacent to the same layer is a second distance, the sum of the line width of the third gate lead section and the line spacing of the third gate lead section adjacent to the same layer is a third distance, and the ratio of the first distance to the second distance is greater than 1 and less than or equal to 1.5.

[0028] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a grounding line, which is arranged in the same layer as the multiple gate lines and is located on a side of the multiple gate lines away from the multiple anti-static structures.

[0029] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of floating blocks, which are arranged in the same layer as the plurality of gate lines, and are roughly evenly distributed between the ground lines and the plurality of gate leads.

[0030] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of third connecting lines, wherein the plurality of third connecting lines are in the same layer as the plurality of gate lines;

[0031] The second border area includes a binding area extending substantially along a second direction on a side of the second display area away from the first display area, and a non-rectangular area connecting the binding area and the first border area;

[0032] The multiple data lines include first data lines and second data lines that are alternately arranged, the first data lines extend from the first display area and the second display area across the non-rectangular area and to the binding area, and the second data lines extend from the first display area and the second display area across the non-rectangular area and are connected to the binding area via the third connecting line.

[0033] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the orthographic projection of the third connection line on the base substrate at least partially overlaps with the orthographic projection of the adjacent first data line on the base substrate.

[0034] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of third transfer electrodes, a first insulating layer, and a second insulating layer, wherein the layer where the plurality of third transfer electrodes are located is located on a side of the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located, away from the base substrate, the first insulating layer is located between the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located, and the second insulating layer is located between the layer where the plurality of data lines are located and the layer where the plurality of third transfer electrodes are located;

[0035] The third transfer electrode is electrically connected to the third connection line through at least one first via hole penetrating the first insulating layer and the second insulating layer, and the third transfer electrode is electrically connected to the second data line through at least one second via hole penetrating the second insulating layer; the at least one first via hole and the at least one second via hole corresponding to the same third transfer electrode are arranged along the first direction.

[0036] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of fourth connecting lines and a plurality of fifth connecting lines, wherein the plurality of fourth connecting lines are in the same layer as the plurality of gate lines, and the plurality of fifth connecting lines are in the same layer as the plurality of data lines;

[0037] The second border area further includes a wiring area located between the binding area and the second display area;

[0038] The multiple data lines include a third data line and a fourth data line that are alternately arranged. The third data line extends from the first display area and the second display area to the routing area and is connected to the binding area via the fourth connecting line. The fourth data line extends from the first display area and the second display area to the routing area and is connected to the binding area via the fifth connecting line.

[0039] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the orthographic projection of the fourth connecting line on the base substrate at least partially overlaps with the orthographic projection of the fifth connecting line on the base substrate.

[0040] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of fourth transfer electrodes, a plurality of fifth transfer electrodes, a first insulating layer, and a second insulating layer, wherein the plurality of fourth transfer electrodes and the plurality of fifth transfer electrodes are arranged in the same layer on a side of the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located away from the base substrate, the first insulating layer is located between the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located, and the second insulating layer is located between the layer where the plurality of data lines are located and the layer where the plurality of fourth transfer electrodes are located;

[0041] The fourth transfer electrode is electrically connected to the fourth connection line through at least one third via hole penetrating the first insulating layer and the second insulating layer, and the fourth transfer electrode is electrically connected to the third data line through at least one fourth via hole penetrating the second insulating layer; the at least one third via hole and the at least one fourth via hole corresponding to the same fourth transfer electrode are respectively arranged along the second direction;

[0042] The fifth transfer electrode is electrically connected to the fifth connection line through at least one fifth via hole penetrating the second insulating layer, and the fifth transfer electrode is electrically connected to the fourth data line through at least one sixth via hole penetrating the second insulating layer; the at least one fifth via hole and the at least one sixth via hole corresponding to the same fifth transfer electrode are respectively arranged along the second direction.

[0043] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first data line includes a first data line section located in the non-rectangular area, and a second data line section located in the routing area, the sum of the line width of the first data line section and the line distance of the adjacent first data line section is the fourth distance, the sum of the line width of the second data line section and the line distance of the adjacent second data line section is the fifth distance, and the ratio of the first distance to the second distance is greater than 1 and less than or equal to 1.5.

[0044] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the second anti-static structure extends in a direction and has an acute angle with the first direction, or the second anti-static structure extends along an arc with an arc angle of 110° to 180°.

[0045] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first display area includes a first sub-display area disposed in contact with the second display area, and a second sub-display area located on a side of the first sub-display area away from the second display area;

[0046] The first frame area includes a first sub-frame area arranged side by side with the first sub-display area in the second direction, and a second sub-frame area arranged side by side with the second sub-display area in the second direction, and the second sub-frame area and the second sub-display area have a stepped boundary line;

[0047] The first anti-static structures in the first sub-frame area are arranged side by side along the first direction, and the first anti-static structures in the second sub-frame area are arranged at the steps of the stepped boundary line.

[0048] On the other hand, an embodiment of the present disclosure further provides a display device, the array substrate provided by the embodiment of the present disclosure, and a driving chip, wherein the driving chip is electrically connected to the plurality of gate lines and the plurality of data lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0050] FIG2 is another schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0051] FIG3 is another schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0052] FIG4 is an enlarged structural diagram of area a in FIG2 ;

[0053] FIG5 is an enlarged structural diagram of area b in FIG2 ;

[0054] FIG6 is an enlarged structural diagram of area c in FIG2 ;

[0055] FIG7 is a schematic diagram of an arrangement of a second anti-static structure provided in an embodiment of the present disclosure;

[0056] FIG8 is a schematic diagram of another arrangement of the second anti-static structure provided in an embodiment of the present disclosure;

[0057] FIG9 is a schematic diagram of the enlarged structure of area d in FIG2 ;

[0058] FIG10 is a schematic diagram of the enlarged structure of the region e in FIG2 ;

[0059] FIG11 is an enlarged structural diagram of the region f in FIG10 ;

[0060] FIG12 is a schematic diagram of the enlarged structure of the g area in FIG10;

[0061] FIG13 is a schematic diagram of the enlarged structure of the h area in FIG6;

[0062] FIG14 is an equivalent circuit diagram of an anti-static structure provided by an embodiment of the present disclosure;

[0063] FIG15a is a schematic diagram of an enlarged structure of area i in FIG10;

[0064] FIG15b is another enlarged structural diagram of the region i in FIG10;

[0065] FIG16a is a schematic diagram of an enlarged structure of region j in FIG10;

[0066] FIG16b is another enlarged structural diagram of the j region in FIG10;

[0067] FIG17a is a schematic diagram of an enlarged structure of the k region in FIG10;

[0068] FIG17b is another enlarged structural diagram of the k region in FIG10;

[0069] FIG18 is a schematic diagram of the enlarged structure of area 1 in FIG10;

[0070] FIG19 is a cross-sectional view along line I-II in FIG18;

[0071] FIG20 is a schematic diagram of the enlarged structure of the m region in FIG10 ;

[0072] FIG21 is a schematic diagram of the enlarged structure of the n region in FIG10;

[0073] FIG22 is a schematic diagram of the enlarged structure of the o area in FIG10;

[0074] FIG23 is a schematic diagram of the enlarged structure of the p region in FIG10;

[0075] FIG24 is a schematic diagram of the enlarged structure of the q region in FIG10;

[0076] FIG25 is a schematic diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0078] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0079] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0080] The display industry is developing rapidly and showing a trend of diversification. With the rise of various display products, the status of liquid crystal display (LCD) products has been challenged. To cope with this change, the LCD industry continues to push the boundaries of process technology. Small-size products have always been interested in narrow-frame, special-shaped structures, which poses a challenge to designers.

[0081] There are two gate line driving methods for liquid crystal display products: one is driven by a gate drive circuit (GOA) including multiple cascaded shift registers, specifically, the timing signal output by the driver chip (IC) is provided to each row of gate lines step by step through the gate drive circuit; the other is gate lead (Gateway) drive, in which the timing signal output by the driver chip is directly provided to each row of gate lines by different gate leads.

[0082] The gate lead drive scheme differs from the gate drive circuit scheme in that each shift register stage has the same structural dimensions in the gate drive circuit scheme, whereas in the gate lead drive scheme, the space occupied by the gate lead wiring increases as the distance from the driver chip decreases. Furthermore, in the rounded corners (R corners) near the driver chip in special-shaped display products, the required wiring space for the data lines increases the closer they are to the driver chip. Therefore, in special-shaped display products using the gateway drive scheme, the fanout lines occupy a large space in the rounded corners close to the driver chip, hindering the realization of a narrow bezel.

[0083] In order to improve the above technical problems existing in the related art, an array substrate provided in an embodiment of the present disclosure, as shown in FIG1 to FIG6 , includes:

[0084] A base substrate 101 includes a display area AA and a frame area BB surrounding the display area AA. The display area AA includes a first display area AA1 and a second display area AA2 sequentially arranged along a first direction Y, and the second display area AA2 is a non-rectangular display area. The frame area BB includes a first frame area BB1 surrounding the first display area AA1 and a second frame area BB2 surrounding the second display area AA2. In the present disclosure, "surrounding" can be understood as fully surrounding or partially surrounding, and is not specifically limited here.

[0085] A plurality of gate lines 102 are arranged along a first direction Y and extend along a second direction X in the first display area AA1 and the second display area AA2. The gate lines 102 in the first display area AA1 extend to the first border area BB1, and the gate lines 102 in the second display area AA2 extend to the second border area BB2. The second direction X intersects the first direction Y.

[0086] A plurality of data lines 103 are insulated from the plurality of gate lines 102. The plurality of data lines 103 are arranged along the second direction X and extend along the first direction Y within the first display area AA1 and the second display area AA2. The plurality of data lines 103 extend to the second border area BB2 and are disposed within the second border area BB2 around the second display area AA2.

[0087] Multiple anti-static structures 104 are electrically connected to multiple gate lines 102. The multiple anti-static structures 104 include multiple first anti-static structures 1041 located in the first border area BB1, and multiple second anti-static structures 1042 located in the second border area BB2, wherein at least part of the first anti-static structures 1041 extend along the first direction Y, and at least part of the second anti-static structures 1042 extend along the winding direction of the data line 103.

[0088] In the above-mentioned array substrate provided by the embodiment of the present disclosure, multiple data lines 103 extend to the second border area BB2 and are arranged around the second display area AA2 in the second border area BB2, making it more difficult to achieve a narrow border in the second border area BB2 compared to the first border area BB1. By extending at least part of the second anti-static structure 1042 in the second border area BB2 along the winding direction of the data line 103, it can be ensured that the space occupied by the second anti-static structure 1042 is small, thereby reducing the second border area BB2, which is conducive to achieving a narrow border design. At the same time, since the number of wirings in the first border area BB1 is small, there is sufficient space in the first border area BB1 for arranging the first anti-static structure 1041. Based on this, at least part of the first anti-static structure 1041 in the first border area BB1 can be extended along the first direction Y; when the first anti-static structure 1041 is extended in the first direction Y, it is easier to complete the design and production of the first anti-static structure 1041.

[0089] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the extension direction of the second anti-static structure 1042 may be substantially parallel (for example, within an angle range of 5°) or parallel to the winding direction of the data line 103. Exemplarily, as shown in FIG7 , the winding direction of the data line 103 forms an acute angle α with the first direction Y, and accordingly, the second anti-static structure 1042 extends in a direction and forms an acute angle α with the first direction Y; or, as shown in FIG8 , the winding direction of the data line 103 is an arc extension direction of 110° to 180°, and accordingly, the second anti-static structure 1042 extends along an arc with an arc angle β of 110° to 180°.

[0090] In some embodiments, in the above array substrate provided by the embodiment of the present disclosure, as shown in FIG. 1 to FIG. 3 , the first display area AA1 includes a first sub-display area AA2 that is disposed in contact with the second display area AA2. 11 , and located in the first sub-display area AA 11 The second sub-display area AA is away from the second display area AA2. 12 , the second sub-display area AA 12 The non-rectangular display area is symmetrical to the second display area AA2 about the symmetry axis MN extending along the second direction X of the display area AA. Optionally, the non-rectangular display area is located away from the first sub-display area AA. 11 In the direction of 12 The width along the second direction X gradually decreases; the first frame area BB1 includes the first sub-display area AA in the second direction X. 11 The first sub-border area BB is arranged side by side 11 , and in the second direction X with the second sub display area AA 12 The second sub-border area BB is set side by side 12, the second sub-border area BB 12 With the second sub display area AA 12 With a stepped boundary line. And referring to FIG3 to FIG5, it can be seen that in order to reduce the first sub-frame area BB 11 and the second sub-border area BB 12 The width of the first sub-border area BB 11 The first anti-static structures 1041 are arranged side by side along the first direction Y, and the second sub-frame area BB 12 The first anti-static structure 1041 is disposed at the step of the stepped boundary line.

[0091] Continuing to refer to FIG. 4 , it can be seen that in the second sub-display area AA 12 The second sub-border area BB on one side 12 The distances between two adjacent first anti-static structures 1041 in the first direction Y and the second direction X are d1 and d2, respectively. In some embodiments, the distance d1 between two adjacent first anti-static structures 1041 in the first direction Y may be approximately equal to (i.e., equal to or within a reasonable error range caused by factors such as manufacturing and measurement) the sum d3 of the lengths of the two pixels in the first direction Y (which may be equivalent to the sum of the lengths of the two pixel electrodes in the first direction Y), and the distance d2 between two adjacent first anti-static structures 1041 in the second direction X may be approximately equal to (i.e., equal to or within a reasonable error range caused by factors such as manufacturing and measurement) the sum d3 of the widths of the two pixels in the second direction X (which may be equivalent to the sum of the widths of the six pixel electrodes in the second direction X when a single pixel includes three sub-pixels).

[0092] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 4 to 6, at least part of the gate line 102 is electrically connected to the anti-static structure 104 after being bent in the first border area BB1 and the second border area BB2, so that the electrostatic current on the gate line 102 flows smoothly, thereby improving the anti-static capability.

[0093] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG3 , the anti-static structures 104 electrically connecting two adjacent gate lines 102 can be located on either side of the display area AA. Compared to a solution in which the anti-static structures 104 are located on the same side of the display area AA, by disposing the anti-static structures 104 electrically connecting two adjacent gate lines 102 on either side of the display area AA, the first border area BB1 on both sides of the display area AA can be made narrower, thereby facilitating a narrower border in the first border area BB1.

[0094] In some embodiments, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 3, 9 to 11, a plurality of first floating anti-static structures 106 and a plurality of second floating anti-static structures 107 may also be included, wherein the plurality of first floating anti-static structures 106 are electrically connected to the plurality of first anti-static structures 1041 in the first border area BB1, and the plurality of first floating anti-static structures 106 are electrically connected to the two first anti-static structures 1041 farthest from the second border area BB2 in the first border area BB1 (equivalent to the first anti-static structures 1041 in the direction from the first display area AA1 to the second display area AA2). The first anti-static structure 1041 electrically connected to the first two gate lines 102 is arranged side by side in the second direction X; the second floating anti-static structure 107 is electrically connected to multiple second anti-static structures 1042 in the second border area BB2, and the multiple second floating anti-static structures 107 and the two second anti-static structures 1042 farthest from the first border area BB1 in the second border area BB2 (equivalent to the second anti-static structures 1042 electrically connected to the last two gate lines 102 in the direction from the first display area AA1 to the second display area AA2) are arranged side by side in the winding direction of the data line 103. By setting the first floating anti-static structure 106 and the second floating anti-static structure 107, large current can be quickly evacuated when static electricity occurs, which has the effect of preventing static electricity from damaging the product; and since the first floating anti-static structure 106 and the second floating anti-static structure 107 are arranged in the second sub-display area AA 12 and the second sub-frame area BB with relatively large wiring space on the left and right sides of the second display area AA2. 12 Compared with setting the first floating anti-static structure 106 and the second floating anti-static structure 107 in the first sub-display area BB2, 11 The first sub-border area BB with relatively small wiring space on the left and right sides 11 It is more conducive to making the overall width of the border area BB smaller.

[0095] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 4 to 6 and Figures 9 to 11, a short-circuit ring 108 may also be included. The short-circuit ring 108 is located in the first border area BB1 and the second border area BB2, and can be set in the same layer as the data line 103; multiple anti-static structures 104 can be electrically connected to multiple first floating anti-static structures 106 and multiple second floating anti-static structures 107 through the short-circuit ring 108, so that static electricity is dispersed to the anti-static structure 104, the first floating anti-static structure 106 and the second floating anti-static structure 107 through the short-circuit ring 108, thereby improving the anti-static ability of the product.

[0096] It should be noted that in this disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for producing a specific pattern, and then using the same mask through a single patterning process. That is, one patterning process corresponds to one mask (also known as a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.

[0097] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 4 to 6 and Figures 9 to 11, the present disclosure further provides a common electrode line 109 and a common electrode 110, wherein the common electrode line 109 is located in the first frame area BB1 and the second frame area BB2, and can be attached to the boundary of the display area AA in the first frame area BB1 and the second frame area BB2. Optionally, the common electrode line 109 and the data line 103 are arranged in the same layer, and can optionally be of the same layer of material. In all embodiments of this case, the reference to the same layer includes the same layer and the same material, or different materials in the same layer, which is not limited here; the common electrode 110 is provided from the first frame area BB1 to the second frame area BB2. A display area AA1 and a second display area AA2 extend into the first frame area BB1 and the second frame area BB2 to be electrically connected to the common electrode line 109. Optionally, multiple first floating anti-static structures 106 are electrically connected to the common electrode line 109, and multiple second floating anti-static structures 107 are electrically connected to the common electrode 110, so that the anti-static structure 104 can be connected to the common electrode line 109 and the common electrode 110 through the first floating anti-static structure 106, the second floating anti-static structure 107 and the short-circuit ring 108. When static electricity occurs, a large current can be guided to flow to the common electrode line 109 and the common electrode 110, thereby preventing static electricity from damaging the product. Of course, in some embodiments, the short-circuit ring 108 can also be connected to the ground wire (GND) through the first floating anti-static structure 106 and the second floating anti-static structure 107, which is not limited here.

[0098] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 10 to 12, may further include a first connecting line 111, which is arranged on the same layer as the multiple gate lines 102, and the first connecting line 111 is used to connect the second floating anti-static structure 107 and the common electrode 110; optionally, the first connecting line 111 is arranged on the same layer and with the same material as the multiple gate lines 102.

[0099] In some embodiments, in the above array substrate provided by the embodiment of the present disclosure, as shown in FIG. 1 to FIG. 3 , the second border area BB2 includes a binding area BB extending substantially along the second direction X on a side of the second display area AA2 away from the first display area AA1. 21 , connect the binding area BB 21 The non-rectangular area BB of the first border area BB1 22 , and the binding area BB 21 The wiring area BB between the second display area AA2 23 , where the binding area BB 21 The function is to extend the signal lines of the display panel (such as gate lines 102, data lines 103, etc.) to the binding area BB 21 After being bound with the flexible circuit board or circuit, the display signal is provided to the signal line of the display panel; and as can be seen from FIG10, the array substrate further includes a second connecting line 112, the second connecting line 112 and the plurality of gate lines 102 are in the same layer (optionally the same layer and the same material), and the second connecting line 112 is connected between the common electrode line 109 and the binding area BB 21 The second connection line 112 is used to connect the bonding area BB 21 The common electrode signal output by the driving chip is provided to the common electrode line 109. Optionally, the second connecting line 112 includes a widened portion W, and the widened portion W is adjacent to the routing area BB. 23 and non-rectangular area BB 22 The widened portion W is provided at the connection of the frame sealant and the widened portion W is a grid structure. The widened portion W of the grid structure has good light transmittance, which is beneficial to enhancing the curing effect of light (such as ultraviolet light) on the frame sealant.

[0100] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 10, 15a, 15b, 16a, 16b, 17a and 17b, it may also include multiple gate leads 113, which are electrically connected to the multiple anti-static structures 104 on the side of the multiple anti-static structures 104 away from the first display area AA1 and the second display area AA2, and only part of the gate leads 113 extends from the second border area BB2 to the first border area BB1; optionally, the multiple gate leads 113 include multiple first gate leads 1131 and multiple second gate leads 1132, the multiple first gate leads 1131 are on the same layer as the multiple gate lines 102, and the multiple second gate leads 1132 are on the same layer as the multiple data lines 103, and the orthographic projection of the first gate leads 1131 on the base substrate 101 and the orthographic projection of the second gate leads 1132 on the base substrate 101 partially overlap. Since the signal on the gate lead 113 can be ±12V and the gate lead 113 is long, if the orthographic projection of the first gate lead 1131 overlaps with the orthographic projection of the second gate lead 1132, parasitic capacitance will be formed between the first gate lead 1131 and the second gate lead 1132, causing mutual interference. Therefore, in order to reduce the parasitic capacitance between the first gate lead 1131 and the second gate lead 1132 in the present disclosure, the orthographic projection of the first gate lead 1131 on the substrate 101 and the orthographic projection of the second gate lead 1132 on the substrate 101 are set to overlap at most; optionally, under the premise that the wiring space permits, the orthographic projection of the first gate lead 1131 on the substrate 101 and the orthographic projection of the second gate lead 1132 on the substrate 101 can be set not to overlap with each other (that is, staggered with each other), and the orthographic projection of the first gate lead 1131 on the substrate 101 and the orthographic projection of the second gate lead 1132 on the substrate 101 can be alternately set, as shown in Figures 15b, 16b and 17b.

[0101] In some embodiments, in the above array substrate provided by the embodiment of the present disclosure, as shown in FIG10, FIG11, FIG13 and FIG14, the anti-static structure 104 includes a first transistor T1 and a second transistor T2, wherein the gate G of the first transistor T1 T1 The first electrode S of the first transistor T1 is electrically connected to the gate line 102 and the gate lead 113. T1 The gate G of the first transistor T1 T1 Electrically connected, the second electrode D of the first transistor T1 T1 and the first electrode S of the second transistor T2 T2 The second electrode D of the second transistor T2 is integrated. T2 and the first electrode S of the first transistor T1 T1 The gate G of the second transistor T2 is integrated. T2 and the first electrode S of the second transistor T2 T2, and is electrically connected to the short-circuit ring 108. When there is a lot of static electricity on the gate line 102, the first transistor T1 is turned on, directing the static electricity to the short-circuit ring 108 and then outputting it to the common electrode line 109 for release; when there is a lot of static electricity on the short-circuit ring 108, on the one hand, the static electricity can be directly released to the common electrode line 109, and on the other hand, the second transistor T2 is turned on, dispersing the static electricity to the gate line 102 and the gate lead 113. In this way, the first transistor T1 and the second transistor T2 can effectively prevent excessive concentration of static electricity, thereby improving the anti-static effect.

[0102] It should be noted that, in the case where the anti-static structure 104 in the present disclosure includes the first transistor T1 and the second transistor T2, the extension direction of the anti-static structure 104 in the present disclosure can be understood as the extension direction of the active layer of the transistor (in the extension direction of the active layer, the length of the active layer is longer), that is, the first anti-static structure 1041 extending along the first direction Y is equivalent to the active layer A of the first transistor T1. T1 and the active layer A of the second transistor T2 T2 Extending along the first direction Y, the second anti-static structure 1042 extends along the winding direction of the data line 103 and is equivalent to the active layer A of the first transistor T1. T1 and the active layer A of the second transistor T2 T2 Extending along the winding direction of the data line 103. In addition, the first floating anti-static structure 106 and the second floating anti-static structure 107 in the present disclosure may also include a first transistor T1 and a second transistor T2, but the difference from the anti-static structure 104 is that in the first floating anti-static structure 106 and the second floating anti-static structure 107, the gate G of the first transistor T1 is T1 It is electrically connected to the common electrode line 109. In addition, in the present disclosure, the first transistor T1 and the second transistor T2 may be bottom-gate transistors, that is, the layer where the gate is located is located between the active layer and the base substrate 101; of course, in some embodiments, the first transistor T1 and the second transistor T2 may be top-gate transistors, that is, the active layer is located between the layer where the gate is located and the base substrate 101.

[0103] In some embodiments, the array substrate provided in the embodiment of the present disclosure may further include a plurality of first transfer electrodes 114 and a plurality of second transfer electrodes 115, as shown in FIG13. The plurality of first transfer electrodes 114 and the plurality of second transfer electrodes 115 are arranged in the same layer on the side away from the base substrate 101 in the layer where the plurality of gate lines 102 and the layer where the plurality of data lines 103 are located; the gate G of the first transistor T1 T1 The gate G of the second transistor T2 is electrically connected to the gate line 102 and the gate lead 113 through the first transfer electrode 114. T1 Through the second switching electrode 115 and the first electrode S of the second transistor T2T2 , and the short-circuit ring 108 are electrically connected. In some embodiments, the transfer electrode can have the same width as the gate of the transistor and be wider than the gate line 102 , for example, at least 1.5 times the width of the gate line 102 .

[0104] In some embodiments, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG10, FIG15a, FIG15b, FIG16a, FIG16b, FIG17a and FIG17b, the gate lead 113 includes a gate lead 113 located in the non-rectangular area BB. 22 The first gate lead section G1 is located in the routing area BB 23 a second gate lead division G2, and a third gate lead division G3 connecting the first gate lead division G1 and the second gate lead division G2; the sum of the line width of the first gate lead division G1 and the line spacing of the adjacent first gate lead division G1 on the same layer is a first distance P1, the sum of the line width of the second gate lead division G2 and the line spacing of the adjacent second gate lead division G2 on the same layer is a second distance P2, the sum of the line width of the third gate lead division G3 and the line spacing of the adjacent third gate lead division G3 on the same layer is a third distance P3, the ratio of the first distance P1 to the second distance P2 is greater than 1 and less than or equal to 1.5, optionally, the second distance P2 is substantially the same as the third distance P3, that is, the same or within an error range (for example, ±5%) caused by factors such as manufacturing and measurement. Optionally, the first distance P1 is 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, etc., and the second distance P2 is 6 μm, 6.1 μm, 6.2 μm, 6.3 μm, 6.4 μm, 6.5 μm, etc.

[0105] Since the gate leads 113 are located in the non-rectangular area BB 22 There are many wiring angles, and when the line width is small, compensation design is required to ensure that the line width uniformity of different gate leads 113 is better. When the compensation angles are large, compensation errors are prone to occur, resulting in short circuit (Short) or open circuit (Open) defects in the product. Considering that the second anti-static structure 1042 is provided in the present disclosure to extend along the winding direction of the data line 103, it is beneficial to reduce the space occupied by the second anti-static structure 1042. The saved space can be used to increase the wiring size (pitch), increase the process margin (Margin), and avoid defects. Based on this, the wiring size (i.e., the first distance P1) of the first gate lead division G1 is increased in the present disclosure. In some embodiments, the wiring size of the first gate lead section G1 can be increased by increasing the line width of the first gate lead section G1 and / or the line spacing between adjacent first gate lead sections G1 on the same layer; illustratively, the line width of the first gate lead section G1 is increased from 3.7 μm to 4.8 μm, and the line spacing between adjacent first gate lead sections G1 on the same layer is increased from 2.5 μm to 3.2 μm.

[0106] In some embodiments, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 10 and 18, a plurality of third connecting lines 116 may be further included, and the plurality of third connecting lines 116 are in the same layer as the plurality of gate lines 102; the plurality of data lines 103 include first data lines 1031 and second data lines 1032 arranged alternately, and the first data lines 1031 span the non-rectangular area BB from the first display area AA1 and the second display area AA2. 21 And extends to the binding area BB 21 The second data line 1032 extends from the first display area AA1 and the second display area AA2 across the non-rectangular area BB. 22 And connected to the binding area BB via the third connection line 116 21 The second data line 1032 is connected to the binding area BB by using the third connecting line 116 on the same layer as the gate line 102. 21 , reducing the total amount of wiring on the layer where the data line 103 is located, which is beneficial to the narrow frame design.

[0107] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in Figures 10 and 18 , the orthographic projection of the third connection line 116 on the base substrate 101 at least partially overlaps with the orthographic projection of the adjacent first data line 1031 on the base substrate 101. Because the signal on the data line 103 is relatively small, for example, ±5V, and the data line 103 is relatively short, even if the orthographic projection of the first data line 1031 overlaps with the orthographic projection of the third connection line 116, no significant parasitic capacitance is generated between the two. Based on this, in the present disclosure, the orthographic projection of the third connection line 116 on the base substrate 101 can be configured to at least partially overlap with the orthographic projection of the adjacent first data line 1031 on the base substrate 101.

[0108] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in Figures 18 and 19, further includes a plurality of third transfer electrodes 117, a first insulating layer 118, and a second insulating layer 119. The layer where the plurality of third transfer electrodes 117 are located is located on a side of the layer where the plurality of gate lines 102 are located and the layer where the plurality of data lines 103 are located, away from the base substrate 101. The first insulating layer 118 is located between the layer where the plurality of gate lines 102 are located and the layer where the plurality of data lines 103 are located. The second insulating layer 119 is located between the layer where the plurality of data lines 103 are located and the layer where the plurality of third transfer electrodes 117 are located. In addition, the third transfer electrode 117 is electrically connected to the third connection line 116 through at least one first via hole h1 penetrating the first insulating layer 118 and the second insulating layer 119. The third transfer electrode 117 is electrically connected to the second data line 1032 through at least one second via hole h2 penetrating the second insulating layer 119. The at least one first via hole h1 and the at least one second via hole h2 corresponding to the same third transfer electrode 117 are arranged along the first direction Y to save wiring space.

[0109] In some embodiments, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in Figures 10 and 20, it can also include multiple fourth connection lines 120 and multiple fifth connection lines 121, the multiple fourth connection lines 120 and the multiple gate lines 102 are on the same layer, and the multiple fifth connection lines 121 and the multiple data lines 103 are on the same layer; the multiple data lines 103 include third data lines 1033 and fourth data lines 1034 arranged alternately, and the third data lines 1033 extend from the first display area AA1 and the second display area AA2 to the routing area BB. 23 And connected to the binding area BB via the fourth connection line 120 21 The fourth data line 1034 extends from the first display area AA1 and the second display area AA2 to the routing area BB 23 And connected to the binding area BB via the fifth connection line 121 21 BB in the routing area 23 Therefore, the fourth connection line 120 and the fifth connection line 121 can be used to connect the third data line 1033 and the fourth data line 1034 to the binding area BB respectively. 21 And by using the fourth connecting line 120 on the same layer as the gate line 102, the third data line 1033 is transferred to the binding area BB 21 , reducing the total amount of wiring on the layer where the data line 103 is located, which is beneficial to the narrow frame design.

[0110] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in Figures 10 and 20 , the orthographic projection of the fourth connecting line 120 on the base substrate 101 at least partially overlaps the orthographic projection of the fifth connecting line 121 on the base substrate 101. Because both the fourth connecting line 120 and the fifth connecting line 121 transmit relatively small data signals, such as ±5V, and are relatively short, even if the orthographic projection of the fourth connecting line 120 and the orthographic projection of the fifth connecting line 121 overlap, they do not interfere with each other due to the large parasitic capacitance. Based on this, in the present disclosure, the orthographic projection of the fourth connecting line 120 on the base substrate 101 can be arranged to at least partially overlap the orthographic projection of the fifth connecting line 121 on the base substrate 101. Furthermore, since there are a large number of fourth connecting lines 120 and fifth connecting lines 121, overlapping them can reduce wiring space, facilitating a narrow bezel design.

[0111] In some embodiments, the array substrate provided in the embodiment of the present disclosure may further include a plurality of fourth transfer electrodes 122 and a plurality of fifth transfer electrodes 123, as shown in FIG20. The plurality of fourth transfer electrodes 122 and the plurality of fifth transfer electrodes 123 may be arranged in the same layer on the side away from the base substrate 101 of the layer where the plurality of gate lines 102 are located and the layer where the plurality of data lines 103 are located; the fourth transfer electrode 122 is electrically connected to the fourth connection line 120 through at least one third via hole h3 penetrating the first insulating layer 118 and the second insulating layer 119, and the fourth transfer electrode 122 is electrically connected to the third data line 1033 through at least one fourth via hole h4 penetrating the second insulating layer 119; and due to the routing area BB 23 There is sufficient wiring space, therefore, the at least one third via hole h3 and the at least one fourth via hole h4 corresponding to the same fourth transfer electrode 122 are respectively arranged along the second direction X; the fifth transfer electrode 123 is electrically connected to the fifth connection line 121 through at least one fifth via hole h5 penetrating the second insulating layer 119, and the fifth transfer electrode 123 is electrically connected to the fourth data line 1034 through at least one sixth via hole h6 penetrating the second insulating layer 119; and because the routing area BB 23 Therefore, the at least one fifth via hole h5 and the at least one sixth via hole h6 corresponding to the same fifth switching electrode 123 can be arranged along the second direction X, respectively.

[0112] In some embodiments, to reduce the number of film layers and save patterning times, the first transfer electrode 114, the second transfer electrode 115, the third transfer electrode 117, the fourth transfer electrode 122, and the fifth transfer electrode 123 in the present disclosure can be provided on the same layer. For example, each transfer electrode can be provided on the same layer as the common electrode 110. In addition, the first via h1 and the third via h3 penetrating the first insulating layer 118 and the second insulating layer 119, as well as the second via h2, the fourth via h4, the fifth via h5, and the sixth via h6 penetrating the second insulating layer 119, can be formed through a single patterning process.

[0113] In some embodiments, in the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 10 and FIG. 21 to FIG. 23 , the first data line 1031 includes a first data line 1031 located in the non-rectangular area BB. 22 The first data line segment S1 and the routing area BB 23The sum of the line width of the first data line section S1 and the line spacing between adjacent first data line sections S1 is a fourth distance P4, the sum of the line width of the second data line section S2 and the line spacing between adjacent second data line sections S2 is a fifth distance P5, and the ratio of the fourth distance P4 to the fifth distance P5 is greater than 1 and less than or equal to 1.5. Optionally, the fourth distance P4 is 6.5μm, 7μm, 7.5μm, 8μm, etc., and the fifth distance P5 is 6μm, 6.1μm, 6.2μm, 6.3μm, 6.4μm, etc.

[0114] Since the gate line 102 needs to be drawn out from the display area AA and cross the first data line division S1 to be connected to the anti-static structure 104, the first data line division S1 is distributed in oblique stripes, and the inclination directions of the first data line divisions S1 on the left and right sides of the second display area AA2 are exactly opposite. The line width and line spacing of each first data line division S1 balance each other. When the line spacing is small, short circuits are prone to occur, and when the line width is small, open circuits are prone to occur. Considering that the second anti-static structure 1042 is provided in the present disclosure to extend along the winding direction of the data line 103, it is beneficial to reduce the space occupied by the second anti-static structure 1042. The saved space can be used to increase the wiring size (pitch), increase the process margin (Margin), and avoid defects. Based on this, the wiring size of the first data line division S1 (i.e., the fourth distance P4) is increased in the present disclosure. In some embodiments, the wiring size of the first data line portion S1 can be increased by increasing the line width of the first data line portion S1 and / or the line spacing of the adjacent first gate lead portion G1 on the same layer; illustratively, the line width of the first data line portion S1 is increased from 3.3μm to 4.2μm, and the line spacing of adjacent first data line portions S1 is increased from 2.7μm to 2.8μm.

[0115] In some embodiments, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in FIG10 , a grounding line 124 may also be included. The grounding line 124 is provided in the same layer as the plurality of gate lines 102. The grounding line 124 is located on the side of the plurality of gate leads 113 away from the plurality of anti-static structures 104, and a blank is provided on the side of the grounding line 124 away from the plurality of gate leads 113. In other words, the grounding line 124 is wired at the outermost periphery of the frame area BB. In the related art, a common electrode line is also provided in addition to the grounding line 124. The present disclosure saves this common electrode line, which can ensure that the frame sealant wraps all the wirings in the frame area BB in consideration of process fluctuations, thereby achieving better protection for all the wirings in the frame area BB and avoiding oxidation and other defects of all the wirings in the frame area BB. In addition, the grounding line 124 can also prevent external static electricity from entering the display area AA, thereby achieving an anti-static effect.

[0116] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure, as shown in Figures 4 and 5, further includes a plurality of floating blocks 125, and the plurality of floating blocks 125 are arranged on the same layer as the plurality of gate lines 102, and the plurality of floating blocks 125 are roughly evenly distributed between the ground line 124 and the plurality of gate leads 113, that is, the distribution density of the plurality of floating blocks 125 in the area between the ground line 124 and the plurality of gate leads 113 is the same or within a reasonable error range caused by factors such as manufacturing and measurement. Since the distance between the grounding wire 124 and the nearest gate lead 113 is greater than the distance between two adjacent gate leads 113, the support effect of the frame sealant in the area between the grounding wire 124 and the multiple gate leads 113 will be reduced; and since the number of wirings in the first border area BB1 is less than the number of wirings in the second border area BB2, the support effect of the frame sealant in the first border area BB1 is not ideal. In the present disclosure, by evenly arranging floating blocks 125 in the area between the grounding wire 124 and the multiple gate leads 113, the frame sealant can be effectively supported, and the floating blocks 125 can also play a certain anti-static role.

[0117] In some embodiments, the array substrate provided in the embodiments of the present disclosure, as shown in FIG24 , may further include a pixel electrode 126 located in the display area AA, a switching transistor 127 connecting the pixel electrode 126 to the data line 103, and the like. Optionally, the pixel electrode 126 is a block electrode located in the pixel opening region, and the common electrode 110 has a slit in the pixel opening region. Optionally, the pixel electrode 126 is located between the first insulating layer 118 and the second insulating layer 119, and the common electrode 110 is located on the side of the second insulating layer 119 away from the base substrate 101. Other essential components of the array substrate are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0118] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in FIG25 , comprising the above-mentioned array substrate 001 provided in an embodiment of the present disclosure, and a driver chip 002, wherein the driver chip 002 can be electrically connected to a plurality of gate lines 102 and a plurality of data lines 103. In some embodiments, the driver chip 002 is also electrically connected to the flexible circuit board 003. Optionally, the number of driver chips 002 can be one or more, which is not limited here. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned array substrate, the implementation of the display device can refer to the embodiment of the above-mentioned array substrate, and the repeated parts will not be repeated.

[0119] In some embodiments, the display device provided by the embodiments of the present disclosure may be a liquid crystal display screen. The liquid crystal display screen may include a backlight module and a display panel located on the light-emitting side of the backlight module. The display panel includes a display substrate and an opposing substrate disposed opposite to each other, a liquid crystal layer located between the display substrate and the opposing substrate, a sealant surrounding the liquid crystal layer between the display substrate and the opposing substrate, a first polarizer located on the side of the display substrate away from the liquid crystal layer, and a second polarizer located on the side of the opposing substrate away from the liquid crystal layer; wherein the polarization direction of the first polarizer is perpendicular to the polarization direction of the second polarizer; the backlight module may be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism assembly, etc., wherein the light bar is located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, wherein the reflective sheet includes openings arranged directly opposite to the positions of the individual lamp beads in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0120] Submillimeter or even micron-scale micro-LEDs are self-luminous devices, just like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. And when micro-LEDs are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving screen brightness and contrast, they can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0121] In some embodiments, the above-mentioned display device provided by the embodiments of the present disclosure may be any product or component with a display function, such as a smart watch, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a fitness wristband, a personal digital assistant, etc. The display device may include, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0122] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0123] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: a base substrate, the base substrate comprising a display area and a frame area surrounding the display area, wherein the display area comprises a first display area and a second display area sequentially arranged along a first direction, the second display area being a non-rectangular display area; and the frame area comprises a first frame area surrounding the first display area and a second frame area surrounding the second display area; a plurality of gate lines arranged along the first direction and extending along a second direction in the first display area and the second display area, wherein the gate lines in the first display area extend to the first frame area, and the gate lines in the second display area extend to the second frame area, and the second direction intersects the first direction; a plurality of data lines, insulated from the plurality of gate lines, the plurality of data lines being arranged along the second direction in the first display area and the second display area and extending along the first direction, and the plurality of data lines extending to the second frame area and being arranged around the second display area in the second frame area; Multiple anti-static structures are electrically connected to the multiple gate lines, and the multiple anti-static structures include multiple first anti-static structures located in the first border area and multiple second anti-static structures located in the second border area, wherein at least part of the first anti-static structures extend along the first direction, and at least part of the second anti-static structures extend along the winding direction of the data line.

2. The array substrate according to claim 1, wherein: The anti-static structures electrically connected to two adjacent gate lines are located on both sides of the display area.

3. The array substrate according to claim 2, wherein: It also includes multiple first floating anti-static structures and multiple second floating anti-static structures, wherein the multiple first floating anti-static structures are electrically connected to the multiple first anti-static structures in the first border area, and the multiple first floating anti-static structures and the two first anti-static structures in the first border area that are farthest from the second border area are arranged side by side in the second direction; the second floating anti-static structure is electrically connected to the multiple second anti-static structures in the second border area, and the multiple second floating anti-static structures and the two second anti-static structures in the second border area that are farthest from the first border area are arranged side by side in the winding direction of the data line.

4. The array substrate according to claim 3, wherein: It also includes a short-circuit ring, which is located in the first frame area and the second frame area; The plurality of anti-static structures are electrically connected to the plurality of first floating anti-static structures and the plurality of second floating anti-static structures respectively through the short-circuit rings.

5. The array substrate according to claim 4, wherein: It also includes a common electrode line and a common electrode, wherein the common electrode line is located in the first frame area and the second frame area, and the common electrode extends from the first display area and the second display area to the first frame area and the second frame area; The plurality of first floating anti-static structures are electrically connected to the common electrode line, and the plurality of second floating anti-static structures are electrically connected to the common electrode.

6. The array substrate according to claim 5, wherein: It also includes a first connecting line, which is in the same layer as the plurality of gate lines, and connects the second floating anti-static structure and the common electrode.

7. The array substrate according to claim 5 or 6, wherein: The short-circuit ring and the common electrode line are both in the same layer as the plurality of data lines.

8. The array substrate according to any one of claims 5 to 7, wherein: The second border area includes a binding area extending substantially along a second direction on a side of the second display area away from the first display area, a non-rectangular area connecting the binding area and the first border area, and a routing area located between the binding area and the second display area; The array substrate also includes a second connecting line, which is on the same layer as the multiple gate lines. The second connecting line is connected between the common electrode line and the binding area. The second connecting line includes a widened portion, which is arranged adjacent to the connection between the routing area and the non-rectangular area, and the widened portion is a grid-like structure.

9. The array substrate according to any one of claims 1 to 8, wherein: At least part of the gate lines are electrically connected to the anti-static structure after being bent in the first frame area and the second frame area.

10. The array substrate according to any one of claims 4 to 8, wherein: Also included are a plurality of gate leads electrically connected to the plurality of anti-static structures on a side of the plurality of anti-static structures away from the first display area and the second display area; The plurality of gate leads include a plurality of first gate leads and a plurality of second gate leads. The plurality of first gate leads are in the same layer as the plurality of gate lines, and the plurality of second gate leads are in the same layer as the plurality of data lines.

11. The array substrate according to claim 10, wherein: The anti-static structure includes a first transistor and a second transistor, wherein the gate of the first transistor is electrically connected to the gate line and the gate lead respectively, the first electrode of the first transistor is electrically connected to the gate of the first transistor, the second electrode of the first transistor is integrally arranged with the first electrode of the second transistor, the second electrode of the second transistor is integrally arranged with the first electrode of the first transistor, and the gate of the second transistor is electrically connected to the first electrode of the second transistor and the short-circuit ring.

12. The array substrate according to claim 11, wherein: It also includes a plurality of first transfer electrodes and a plurality of second transfer electrodes, wherein the plurality of first transfer electrodes and the plurality of second transfer electrodes are arranged in the same layer on the layer where the plurality of gate lines are located and on a side of the layer where the plurality of data lines are located away from the base substrate; The gate of the first transistor is electrically connected to the gate line and the gate lead respectively through the first switching electrode, and the gate of the second transistor is electrically connected to the first electrode of the second transistor and the short-circuit ring respectively through the second switching electrode.

13. The array substrate according to any one of claims 10 to 12, wherein: The second border area includes a binding area extending substantially along a second direction on a side of the second display area away from the first display area, and a non-rectangular area connecting the binding area and the first border area; The gate lead includes a first gate lead portion located in the non-rectangular area, a second gate lead portion located between the binding area and the second display area, and a third gate lead portion connecting the first gate lead portion and the second gate lead portion; the sum of the line width of the first gate lead portion and the line spacing of the first gate lead portion adjacent to the same layer is a first distance, the sum of the line width of the second gate lead portion and the line spacing of the second gate lead portion adjacent to the same layer is a second distance, the sum of the line width of the third gate lead portion and the line spacing of the third gate lead portion adjacent to the same layer is a third distance, and the ratio of the first distance to the second distance is greater than 1 and less than or equal to 1.

5.

14. The array substrate according to any one of claims 10 to 13, wherein: It also includes a grounding line, which is arranged in the same layer as the multiple gate lines and is located on a side of the multiple gate lines away from the multiple anti-static structures.

15. The array substrate according to claim 14, wherein: The system further comprises a plurality of floating blocks, which are arranged in the same layer as the plurality of gate lines and are substantially evenly distributed between the ground line and the plurality of gate leads.

16. The array substrate according to any one of claims 1 to 15, wherein: Also comprising a plurality of third connecting lines, wherein the plurality of third connecting lines and the plurality of gate lines are in the same layer; The second border area includes a binding area extending substantially along a second direction on a side of the second display area away from the first display area, and a non-rectangular area connecting the binding area and the first border area; The multiple data lines include first data lines and second data lines that are alternately arranged, the first data lines extend from the first display area and the second display area across the non-rectangular area and to the binding area, and the second data lines extend from the first display area and the second display area across the non-rectangular area and are connected to the binding area via the third connecting line.

17. The array substrate according to claim 16, wherein: An orthographic projection of the third connecting line on the base substrate at least partially overlaps with an orthographic projection of the adjacent first data line on the base substrate.

18. The array substrate according to claim 16 or 17, wherein: The present invention also includes a plurality of third transfer electrodes, a first insulating layer and a second insulating layer, wherein the layer where the plurality of third transfer electrodes are located is located on a side of the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located away from the base substrate, the first insulating layer is located between the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located, and the second insulating layer is located between the layer where the plurality of data lines are located and the layer where the plurality of third transfer electrodes are located; The third transfer electrode is electrically connected to the third connection line through at least one first via hole penetrating the first insulating layer and the second insulating layer, and the third transfer electrode is electrically connected to the second data line through at least one second via hole penetrating the second insulating layer; the at least one first via hole and the at least one second via hole corresponding to the same third transfer electrode are arranged along the first direction.

19. The array substrate according to any one of claims 16 to 18, wherein: Also comprising a plurality of fourth connecting lines and a plurality of fifth connecting lines, wherein the plurality of fourth connecting lines are in the same layer as the plurality of gate lines, and the plurality of fifth connecting lines are in the same layer as the plurality of data lines; The second border area further includes a wiring area connecting the binding area and the second display area; The multiple data lines include a third data line and a fourth data line that are alternately arranged. The third data line extends from the first display area and the second display area to the routing area and is connected to the binding area via the fourth connecting line. The fourth data line extends from the first display area and the second display area to the routing area and is connected to the binding area via the fifth connecting line.

20. The array substrate according to claim 19, wherein: An orthographic projection of the fourth connecting line on the base substrate at least partially overlaps with an orthographic projection of the fifth connecting line on the base substrate.

21. The array substrate according to claim 19 or 20, wherein: The present invention also includes a plurality of fourth transfer electrodes, a plurality of fifth transfer electrodes, a first insulating layer and a second insulating layer, wherein the plurality of fourth transfer electrodes and the plurality of fifth transfer electrodes are arranged in the same layer on a side away from the base substrate and a layer where the plurality of gate lines are located and a layer where the plurality of data lines are located, the first insulating layer is located between the layer where the plurality of gate lines are located and the layer where the plurality of data lines are located, and the second insulating layer is located between the layer where the plurality of data lines are located and the layer where the plurality of fourth transfer electrodes are located; The fourth transfer electrode is electrically connected to the fourth connection line through at least one third via hole penetrating the first insulating layer and the second insulating layer, and the fourth transfer electrode is electrically connected to the third data line through at least one fourth via hole penetrating the second insulating layer; the at least one third via hole and the at least one fourth via hole corresponding to the same fourth transfer electrode are respectively arranged along the second direction; The fifth transfer electrode is electrically connected to the fifth connection line through at least one fifth via hole penetrating the second insulating layer, and the fifth transfer electrode is electrically connected to the fourth data line through at least one sixth via hole penetrating the second insulating layer; the at least one fifth via hole and the at least one sixth via hole corresponding to the same fifth transfer electrode are respectively arranged along the second direction.

22. The array substrate according to any one of claims 19 to 21, wherein: The first data line includes a first data line section located in the non-rectangular area and a second data line section located in the routing area. The sum of the line width of the first data line section and the line distance between adjacent first data line sections is a fourth distance. The sum of the line width of the second data line section and the line distance between adjacent second data line sections is a fifth distance. The ratio of the first distance to the second distance is greater than 1 and less than or equal to 1.

5.

23. The array substrate according to any one of claims 1 to 22, wherein: The second anti-static structure extends in a direction and forms an acute angle with the first direction, or the second anti-static structure extends along an arc with an angle of 110° to 180°.

24. The array substrate according to any one of claims 1 to 23, wherein: The first display area includes a first sub-display area arranged in contact with the second display area, and a second sub-display area located on a side of the first sub-display area away from the second display area; The first frame area includes a first sub-frame area arranged side by side with the first sub-display area in the second direction, and a second sub-frame area arranged side by side with the second sub-display area in the second direction, and the second sub-frame area and the second sub-display area have a stepped boundary line; The first anti-static structures in the first sub-frame area are arranged side by side along the first direction, and the first anti-static structures in the second sub-frame area are arranged at the steps of the stepped boundary line.

25. A display device, wherein: The invention comprises the array substrate according to any one of claims 1 to 24, and a driving chip, wherein the driving chip is electrically connected to the plurality of gate lines and the plurality of data lines.

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