Techniques for handling data elements stored in array storage devices

Abstract

In one embodiment, an apparatus is provided, the apparatus comprising: processing circuitry to perform an operation; instruction decoder circuitry to decode an instruction to control the processing circuitry to perform the operation specified by the instruction; and an array storage device including storage elements to store the data elements. The array storage device is arranged to store at least one two-dimensional array data element, the processing circuitry being accessible to the data element when the operation is performed, each two-dimensional array data element comprising a plurality of data element vectors, where each vector is one-dimensional. The instruction decoder circuitry is arranged to control the processing circuitry in response to a movement of one or more data element vectors identifying a given two-dimensional array data element within the array storage and a zero instruction, and a controller to move the data element of one or more identified vectors from the array storage device to a destination storage device, and to set the storage element of the array storage device to store the data element of the one or more identified vectors to a logical zero value.

Description

Background Art

[0001] The present technology relates to the field of data processing, and more particularly to manipulating data elements stored in array storage devices.

[0002] Some modern data processing systems may provide array storage devices for storing one or more two-dimensional array data elements, which may be accessed by processing circuitry of the data processing system when performing data processing operations. This may provide an efficient mechanism for performing a variety of different types of operations, such as operations involving accumulation functions, where the accumulation output may be maintained within the two-dimensional array data elements.

[0003] However, in order to fully exploit the efficiency gains that may be realized from using such array storage devices, it is beneficial to provide an efficient mechanism for transferring data elements out of the array storage device in a manner that frees up resources of the array storage device for use in connection with subsequent operations. Summary of the invention

[0004] In one exemplary arrangement, a device is provided, the device comprising: processing circuitry to perform an operation; instruction decoder circuitry to decode an instruction to thereby control the processing circuitry to perform the operation specified by the instruction; and an array storage device, the array storage device comprising storage elements to store data elements, the array storage device being arranged to store at least one two-dimensional array data element that is accessible to the processing circuitry when performing the operation, each two-dimensional array data element comprising a plurality of data element vectors, wherein each vector is one-dimensional; wherein the instruction decoder circuitry is arranged to control the processing circuitry in response to a move and zero instruction identifying one or more data element vectors of a given two-dimensional array data element within the array storage device to move the data elements of the one or more identified vectors from the array storage device to a destination storage device and set the storage elements of the array storage device storing the data elements of the one or more identified vectors to a logic zero value.

[0005] In another exemplary arrangement, a method for handling data elements within an array storage device of an apparatus is provided, the method comprising: utilizing a processing circuit system to perform an operation; utilizing an instruction decoder circuit system to decode an instruction to control the processing circuit system to perform the operation specified by the instruction; providing storage elements in the array storage device to store data elements, the array storage device being arranged to store at least one two-dimensional array data element, the data elements being accessible to the processing circuit system when performing the operation, each two-dimensional array data element comprising a plurality of data element vectors, wherein each vector is one-dimensional; and utilizing the instruction decoder circuit system to control the processing circuit system in response to a move and zero instruction identifying one or more data element vectors of a given two-dimensional array data element within the array storage device to move the data elements of the one or more identified vectors from the array storage device to a destination storage device, and to set the storage elements of the array storage device used to store the data elements of the one or more identified vectors to a logical zero value.

[0006] In a further exemplary arrangement, a computer program for controlling a host data processing apparatus to provide an instruction execution environment is provided, the computer program comprising: a processing program logic, the processing program logic being configured to perform an operation; an instruction decoding program logic, the instruction decoding program logic being configured to decode an instruction, thereby controlling the processing program logic to perform the operation specified by the instruction; and an array storage device emulation program logic, the array storage device emulation program logic being configured to emulate an array storage device comprising storage elements for storing data elements, the array storage device being arranged to store at least one two-dimensional array data element, the data elements being accessible to the processing program logic when performing the operation, each two-dimensional array data element comprising a plurality of data element vectors, wherein each vector is one-dimensional; wherein the instruction decoding program logic is arranged to control the processing program logic in response to a move and zero instruction identifying one or more data element vectors of a given two-dimensional array data element within the array storage device to move the data elements of the one or more identified vectors from the array storage device to a destination storage device, and to set the storage elements of the array storage device for storing the data elements of the one or more identified vectors to a logic zero value. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present technology will be further described, by way of illustration only, with reference to examples thereof as shown in the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of a device according to an exemplary implementation;

[0009] Figure 2showing examples of architectural registers that may be provided within a device, the architectural registers including vector registers for storing vector operands and array registers for storing 2D array data elements, the array registers including examples of physical implementations of the array registers;

[0010] Figure 3A and Figure 3B shows examples where a given 2D array data element may be non-square or square;

[0011] Figure 4A and Figure 4B schematically illustrates how to perform access to a square 2D array within an array storage device according to an exemplary implementation;

[0012] Figure 5A schematically illustrates fields provided within a move and zero instruction according to one exemplary implementation, and Figure 5B schematically illustrates subfields of a vector identification field that may be used in one particular exemplary implementation to implement move and zero instructions;

[0013] Figure 6 A flowchart illustrating how move and zero instructions may be handled according to one exemplary implementation;

[0014] Figure 7 An exemplary instruction sequence that may operate on data elements provided within an array storage device is shown, wherein the instruction sequence includes several instances of the move and zero instructions described herein;

[0015] Figure 8 Schematically illustrating a finite impulse response (FIR) filtering operation that can be performed;

[0016] 9A to 9D illustrates how an array storage device may be used when performing a 2D image filtering operation according to an exemplary implementation;

[0017] Fig.10 An alternative exemplary instruction sequence that may operate on data elements provided within an array storage device is shown, wherein the instruction sequence includes several instances of the move and zero instructions described herein;

[0018] Fig.11 A flowchart illustrating how a zero vector instruction may be handled according to one exemplary implementation;

[0019] Fig.12 schematically illustrates fields that may be provided within a zero vector instruction according to one exemplary implementation;

[0020] Fig.13 is a flowchart illustrating how a zero vector instruction may be handled according to an alternative exemplary implementation; and

[0021] Fig.14 A simulator implementation that can be used is shown. DETAILED DESCRIPTION

[0022] In an exemplary arrangement, a device is provided, the device having: a processing circuit system, the processing circuit system for performing an operation; and an instruction decoder circuit system, the instruction decoder circuit system for decoding an instruction to control the processing circuit system to perform the operation specified by the instruction. An array storage device is also provided, the array storage device comprising storage elements for storing data elements. The array storage device is arranged to store at least one two-dimensional array data element, the processing circuit system can access the data element when performing the operation, each two-dimensional array data element comprising a plurality of data element vectors, wherein each vector is one-dimensional.

[0023] As previously mentioned, the use of array storage devices can provide a very efficient mechanism for performing certain types of operations, such as accumulation operations. An accumulation operation may simply perform an accumulation function, but alternatively, may incorporate additional processing in addition to the accumulation function (purely by way of example, an accumulation operation may perform a multiply-accumulate function of the form A=A+B*C). In order to yield the greatest potential achievable efficiency advantage, it may be desirable to have an efficient mechanism for moving data elements out of the array storage device when the data elements are no longer subject to an operation performed using the array storage device, and also an efficient mechanism for freeing up the associated storage elements of the array storage device so that they are available for use in association with subsequent operations.

[0024] According to an exemplary implementation, a move and zero instruction is provided that can achieve a significant improvement in the efficiency of such a process. Specifically, in an exemplary implementation, the instruction decoder circuitry can be arranged to control the processing circuitry in response to a move and zero instruction that identifies one or more data element vectors of a given two-dimensional array data element within the array storage device to move the data elements of the one or more identified vectors from the array storage device to a destination storage device and set the storage elements of the array storage device used to store the data elements of the one or more identified vectors to a logical zero value.

[0025] Thus, in accordance with the above-described techniques, a single instruction may be specified which, when executed, causes data elements in one or more identified data element vectors within a given two-dimensional array to be shifted out of the array storage device and, additionally, causes the associated storage element of the array storage device used to store the data element to be cleared to a logic-zero value, thereby preparing the storage element for use in a subsequent operation.

[0026] This can significantly improve performance. Specifically, the act of moving the data element out of the array storage device and preparing the associated storage element for reuse does not itself perform useful operations, and therefore can be considered a load associated with the use of the array storage device. By allowing a single instruction to cause both the data element to be moved and the associated storage element to be cleared to a logical zero value, this can significantly reduce the load.

[0027] Specifically, the prior known technology would require the execution of at least one move instruction to move the desired data element from the array storage device to the specified destination storage device, and thereafter would require one or more additional move instructions to move one or more vectors of logical zero values ​​from one or more source vector registers to the associated storage element of the array storage device. This therefore establishes a sequence of dependent instructions that must be executed one by one. For example, considering only the simple case where a first move instruction is used to move the one or more vectors of data elements from the array storage device, and then a second move instruction is used to move the vector of logical zero values ​​from the specified source vector register to the associated storage element of the array storage device, there are clearly two dependent move instructions that need to be executed one by one, and this instruction dependency is removed by using the new move and zero instruction.

[0028] Further, it has been found that in some implementations, the hardware cost associated with performing a combined move and zeroing operation can be the same as the hardware cost associated with simply performing a standard move operation to move the data element vector out of the array storage device, and thus zeroing of the associated storage element can be efficiently achieved without additional hardware load. Further, in an exemplary implementation, it has been found that the performance (execution speed) of the combined move and zeroing operation is the same as performing only a single move operation.

[0029] Additionally, use of the present technique avoids storing logic zero values ​​within vector registers that would otherwise be needed as source operands for move instructions used to move the logic zero values ​​to the array storage device, thereby freeing up one or more vector registers within the vector register file.

[0030] In addition, performance may be seen to be improved since no separate move instructions are required to perform the zeroing functionality.

[0031] Such methods have been found to be highly beneficial for many exemplary use cases of array storage devices. For example, array storage devices are often used to accumulate results produced when performing several iterations of accumulation operations, and when a final accumulation result is produced, the final accumulation result is typically moved out of the array storage device, such as by moving to one or more vector registers provided within the device. When the array storage device is being used for the execution of an accumulation operation, it is only possible to reuse the storage element that is storing the final accumulation result for a new series of accumulation operations if the storage element is first set to a logical zero value, and the use of move and zero instructions as described herein can enable this to be efficiently achieved.

[0032] Thus, in an exemplary implementation, the processing circuit system may be arranged to perform multiple iterations of the accumulation operation and use the given two-dimensional array data element to maintain the accumulation results produced when performing the accumulation operation, wherein after a given iteration of the accumulation operation, at least one given vector of data elements in the given two-dimensional array data element is arranged to store a final accumulation result, while the remaining vectors of data elements in the given two-dimensional array data element are arranged to store intermediate accumulation results. In such implementations, the move and zero instruction may be arranged to identify the at least one given vector of data elements and may be executed after the given iteration of the accumulation operation to cause the processing circuit system to move the final accumulation result of the at least one given vector from the array storage device to the destination storage device and clear the storage element of the array storage device used to store the final accumulation result of the at least one given vector to free the storage element for use in a subsequent accumulation operation.

[0033] It should be noted that the accumulation operation mentioned above may simply perform an accumulation function (e.g., of the form A=A+B), but more generally may also involve some additional processing operations in addition to the accumulation function. Thus, the accumulation operation may include a processing operation that is performed to produce a processing operation result value, which is then accumulated with an existing data element value in an associated storage element of the array storage device to establish a new data element value to be stored in the associated storage element of the array storage device. Purely by way of example, the accumulation operation mentioned above may be a multiply-accumulate operation (e.g., of the form A=A+B*C).

[0034] There are various types of data processing operations that may use the accumulation functionality mentioned above, and for which the use of an array storage device may provide efficient specific implementation techniques. In a particular exemplary use case, the multiple iterations of the accumulation operation are processing and accumulation operations for performing a finite impulse response (FIR) filtering operation on input data elements of an array, and the given two-dimensional array data element within the array storage device may be used to hold output data elements of the array generated during performance of the FIR filtering operation. The processing circuitry may be arranged to process a single vector of input data elements during each iteration of the accumulation operation and generate output data elements for accumulation within multiple vectors of output data elements of the array.

[0035] The correspondence between input data elements and output data elements may vary depending on the implementation. For example, one vector of input data elements may be associated with multiple vectors of output data elements. In addition, the multiple vectors of output data elements may be arranged in either or both of the horizontal and vertical directions within the array storage device (to support implementations in which the vectors can be accessed in both the horizontal and vertical directions, the two-dimensional array data elements will generally be two-dimensional square array data elements). Further, the input data elements and the output data elements may be different sizes.

[0036] Such techniques as described above may utilize an outer product method to operate FIR filtering implemented by a sliding window technique using square array data elements. Such techniques generally result in some vectors of the square array output data elements being completed before other vectors of output data elements, and thus using the move and zero instructions described above may result in the completed vectors of output data elements being moved out of the array storage device, wherein the associated storage elements are freed for use in association with other vectors of output data elements.

[0037] The array input data elements may take a variety of forms, but in one exemplary implementation may represent array pixel values. However, the techniques described herein are equally applicable to other array data elements that may not, for example, represent image data.

[0038] In some exemplary implementations, the plurality of vectors of output data elements generated by processing a row of input data elements may be referred to as a plurality of "rows" of output data elements. However, as mentioned above, it should be noted that the accumulated output data elements of the row within a given square 2D array of data elements of output data elements (such square 2D arrays may also be referred to herein as square sub-arrays) may be stored in any desired orientation within the array storage device. For example, a row may be stored as a horizontal vector within a square sub-array or as a vertical vector within a square sub-array, and thus, herein, the term "row" should not be viewed as indicating any particular orientation of data elements within the array storage device.

[0039] In an exemplary arrangement, the given two-dimensional array data element is a square two-dimensional array data element, the plurality of vectors forming the square two-dimensional array data element comprises a first plurality of vectors arranged in a first array direction and a second plurality of vectors arranged in a second array direction, the second array direction being orthogonal to the first array direction, and each instance of the move and zero instruction is arranged to identify one or more data element vectors extending either entirely in the first array direction or entirely in the second array direction. This therefore provides a great deal of flexibility in how to identify various data element vectors to be moved out of the array storage device.

[0040] Depending on the implementation, the one or more two-dimensional array data elements stored in the array storage device may take a variety of forms. In one particular exemplary implementation, the processing circuitry is arranged to perform processing operations on the square two-dimensional array data elements during which the processing circuitry is enabled to access data element vectors in both the first array direction and the second array direction.

[0041] In an exemplary implementation, the array storage device may be configured to include a plurality of array vector registers extending in a first array direction. The processing circuit system may be arranged to perform one or more accumulation operations, wherein each accumulation operation is arranged to produce output data for accumulation in a plurality of array vector registers of a group of the array storage device. Therefore, in such implementations, the array storage device is regarded as including a plurality of separately addressable array vector registers extending in a single direction, and a given two-dimensional array data element referred to above may be regarded as comprising data elements stored in the plurality of array vector registers of the group referred to above.

[0042] In such exemplary implementations, the move and zero instruction may be executed to cause the processing circuit system to move the data elements of the one or more identified vectors from the array storage device to the destination storage device and to set each array vector register within the plurality of array vector registers used to store the group of data elements of the one or more identified vectors to a logical zero value when execution of the one or more accumulate operations has resulted in final result data being present in the one or more identified vectors identified by the move and zero instruction.

[0043] In one particular exemplary implementation, when the processing circuitry has completed execution of the one or more accumulate operations, final result data is present in each of the plurality of array vector registers of the group. Execution of the move and zero instruction may then cause the final result data to be moved from the plurality of array vector registers of the group to the destination storage device, and each of the plurality of array vector registers of the group to be cleared to zero. This then enables the processing circuitry to reuse one or more array vector registers from the group of array vector registers for any desired subsequent processing operation (so for example execution of a subsequent accumulate instruction using any or all of the array vector registers will cause a non-accumulate variant to be executed due to the contents of the array vector registers being cleared to zero).

[0044] The destination storage device designated for the move and zero instruction may take a variety of forms. In an exemplary implementation, the device may further provide a vector register file including a plurality of vector registers, and the move and zero instruction may be arranged to indicate one or more vector registers within the vector register file as the destination storage device. There are various ways in which the move and zero instruction may be arranged to identify the one or more vector registers. For example, in the case of a single vector register in which a single vector of data elements is moved out of the array storage device, the move and zero instruction may provide an identifier for determining the single vector register. For the case of multiple vector registers in which multiple vectors of data elements are moved out of the array storage device, separate identifier information for each of the vector registers may be used to explicitly identify the multiple vector registers, or alternatively, a vector register may be identified by the instruction, wherein other vector registers in the multiple vector registers are implicit. For example, the multiple vector registers may be a sequence of adjacent vector registers starting with the vector register that has been explicitly identified, or the multiple vector registers may be separated by a constant stride value.

[0045] However, in an alternative implementation, if desired, the move and zero instruction may be arranged to indicate one or more locations in a memory where the data elements of the one or more identified vectors are to be stored as the destination storage device. In this case, the move and zero instruction may alternatively be referred to as a store and zero instruction.

[0046] There are various ways in which the move and zero instruction can be arranged to identify the memory location to which the one or more data element vectors are to be moved. For example, considering the single vector case in which only a single data element vector is moved to memory, the move and zero instruction can be arranged to identify a location in memory, where the data element vector is then written to a continuous memory address identified by the location (in this case, the location may, for example, be the memory address of the first data element). If multiple vectors are to be moved, multiple discrete locations in memory may be identified by the instruction, where each of the data element vectors is moved to a sequence of memory addresses identified by one of the specified locations. Alternatively, one location may be specified by the instruction, and the other location may be implicit (e.g., identifying the location at a memory address at a fixed stride / offset from the identified location).

[0047] Depending on the direction of the array being accessed and the nature of the data elements of the stored vector held within the array, it may also be necessary to store individual elements of a single vector to discrete memory locations. However, where individual data elements within a single vector need to be stored to discrete memory locations, it will generally be the case that the data element vector is first moved to a vector register before being transferred to memory where appropriate.

[0048] There are several methods in which the one or more data element vectors to be moved can be identified by the move and zero instruction. In an exemplary implementation, the move and zero instruction may include a vector identification field to identify the one or more data element vectors of the given two-dimensional array data element within the array storage device. For example, when a single data element vector is to be moved, an identifier sufficient to identify the single vector may be provided. When multiple data element vectors are to be moved, then the vector identification field may be used to provide sufficient information to explicitly identify each of the multiple vectors, or alternatively, one data element vector may be explicitly identified, while the other vectors are then implicit, such as adjacent vectors or regularly spaced vectors (commonly referred to as stride access). In this latter case, a number may be provided by the vector identification field to identify the number of vectors to be moved.

[0049] In the aforementioned method where access can be performed in either array direction, the vector identification field can then be used to provide sufficient information to identify the array direction being accessed. For example, in one implementation, the vector identification field may include: a first subfield, the first subfield is used to identify the square two-dimensional array; and a second subfield, the second subfield provides one or more row identifiers and an array direction indication for identifying the one or more vectors.

[0050] In an exemplary implementation, the move and zero instruction may include a prediction field to identify prediction information to identify which data elements of the one or more identified vectors are to be moved from the array storage device to the destination storage device and have their associated storage elements set to the logical zero value. This may provide additional flexibility by enabling functionality to be restricted to specific data elements within a specific vector.

[0051] In some implementations using prediction, the data element size may vary, and in this case, the move and zero instruction may include a size field to identify the size of each data element within the one or more identified vectors. By enabling the instruction to provide this additional information, it is possible to allow the instruction to be used for a variety of different data element sizes processed in the system while enabling the move and zero operation to be performed on a subset of the total data elements within the one or more identified vectors.

[0052] According to another technique described herein, an additional new form of instruction is provided that can also be used to zero a vector of data elements within the array storage device and provide performance improvements when performing accumulation operations using such array storage devices. According to this technique, a device is provided, the device having: a processing circuit system, the processing circuit system for performing an operation; an instruction decoder circuit system, the instruction decoder circuit system for decoding an instruction to control the processing circuit system to perform the operation specified by the instruction; and an array storage device, the array storage device including storage elements for storing data elements. As with the previously described techniques, the array storage device is arranged to store at least one two-dimensional array data element, the processing circuit system can access the data element when performing the operation, each two-dimensional array data element includes a plurality of data element vectors, wherein each vector is one-dimensional. According to this additional technique, the instruction decoder circuitry is arranged to, in response to decoding a zero-vector instruction identifying a plurality of vectors of data elements for a given two-dimensional array data element within the array storage device, also decode a subsequent accumulate instruction arranged to operate on the identified plurality of vectors of data elements, and control the processing circuitry to perform a non-accumulate variant of the accumulate operation specified by the accumulate instruction to produce result data elements for storage in the identified plurality of vectors within the array storage device.

[0053] By using the above method, the zero vector instruction can be fused / merged with a subsequent accumulation instruction when decoded by the instruction decoder circuit system to actually establish a non-accumulation variant of the accumulation instruction, and the subsequent accumulation instruction specifies the same multiple data element vectors specified by the zero vector instruction. It has been found that it may be desirable because the instruction encoding space is generally quite limited, such methods may be highly beneficial, and provide several different accumulation instructions for performing accumulation operations on multiple vectors in the array storage device at the same time, it may be undesirable because the amount of instruction encoding space will be consumed by providing the non-accumulation variant, seeking to also provide the non-accumulation variant of the instruction. By using the present technology, it is not necessary to provide the non-accumulation variant of the instruction, and alternatively, they can be simulated by combining the zero vector instruction with the subsequent accumulation instruction to cause the processing circuit system to perform the non-accumulation variant.

[0054] In an exemplary implementation, the array storage device may include a plurality of array vector registers extending in a first array direction, and the identified plurality of vectors within the array storage device are provided by a plurality of array vector registers of a group of the array storage device. In such a configuration, the given two-dimensional array data element may include the data element stored in the plurality of array vector registers of the group. Further, the subsequent accumulate instruction may specify a processing operation including an accumulate operation to be performed on the identified plurality of data element vectors (i.e., on the same plurality of array vectors of the group as specified by the zero vector instruction), and the zero vector instruction may be used in combination with the subsequent accumulate instruction to implement a non-accumulate variant of the processing operation performed by the processing circuit system.

[0055] In an exemplary implementation, the zero vector instruction may include a vector identification field for identifying the plurality of data element vectors for the given two-dimensional array data element within the array storage device.

[0056] As with the previously discussed move and zero instructions, if desired, the zero vector instruction may include a prediction field to identify prediction information to identify which storage elements within the plurality of identified vectors are to be set to the logical zero value. Such an approach may actually allow some data elements to be subjected to non-accumulative variants of subsequent accumulation instructions, while other data elements are subjected to true accumulation variants. Furthermore, if desired, the zero vector instruction may include a size field to identify the size of each data element within the plurality of identified vectors.

[0057] Certain exemplary implementations will now be discussed with reference to the drawings.

[0058] Figure 1A data processing system 10 is schematically shown and includes a processor 20 coupled to a memory 30 storing data values ​​32 and program instructions 34. The processor 20 includes an instruction fetch unit 40 for fetching program instructions 34 from the memory 30 and supplying the fetched program instructions to instruction decoder circuitry 50. The decoder circuitry 50 decodes the fetched program instructions and generates control signals to control the processing circuitry 60 to perform processing operations on data values ​​held in storage elements of a register storage device 65 as specified by the decoded vector instruction. Figure 1 As shown, register storage device 65 may be formed of a plurality of different blocks. For example, a scalar register file 70 may be provided, which includes a plurality of scalar registers that may be specified by instructions, and similarly, a vector register file 80 may be provided, which includes a plurality of vector registers that may be specified by instructions.

[0059] like Figure 1 As shown, the processor 20 can access the array storage device 90. Figure 1 In the example shown, array storage device 90 is provided as part of processor 20, but this is not required. In various examples, the array storage device can be implemented as any one or more of the following: architecturally addressable registers; non-architecturally addressable registers; high-speed scratchpad memory; and cache memory.

[0060] In an exemplary implementation, the processing circuit system 60 may include both vector processing circuit systems and scalar processing circuit systems. The general difference between scalar processing and vector processing is as follows. Vector processing may involve applying a single vector processing instruction to a data element of a data vector, which has multiple data elements at corresponding positions in the data vector. According to the present technology, the processing circuit system may also perform vector processing to perform operations on multiple vectors in a two-dimensional array of data elements (which may also be referred to as subarrays) stored in the array storage device 90. Scalar processing effectively operates on a single data element, but not on a data vector. Vector processing can be used in instances where processing operations are performed on many different instances of data to be processed. In a vector processing arrangement, a single instruction can be applied to multiple data elements (of a data vector) simultaneously. Compared to scalar processing, this can improve the efficiency and output of data processing.

[0061] The processor 20 may be arranged to process two-dimensional array data elements stored in the array storage device 90. In at least some examples, the two-dimensional array may be accessed in multiple directions as one-dimensional vector data elements. In an exemplary implementation, the array storage device 90 may be arranged to store one or more two-dimensional array data elements, and each two-dimensional array data element may form a square array portion of a larger or even higher dimensional array data element in memory.

[0062] Figure 2 An example of architectural registers 65 of processor 20 that may be provided in an exemplary implementation is shown. The architectural registers (as defined in an instruction set architecture (ISA)) may include a set of scalar integer registers 100 that function as general purpose registers for processing operations performed by scalar processing circuitry within processing circuitry 60. For example, there may be a number of general purpose registers 100, such as 31 registers X0 to X30 provided in this example (the 32nd encoding of the scalar register field may not correspond to a register provided in hardware, as it may be considered by default to indicate a value such as zero, or may be used to indicate a special type of register that is not a general purpose register). Accessing scalar registers of different sizes mapped to the same physical storage device is possible. For example, register tags X0 to X30 may refer to 64-bit registers, but the same registers may also be accessed as 32-bit registers (e.g., using the lower 32 bits of each 64-bit register provided in hardware for access), in which case register tags W0 to W30 may be used in assembler code to refer to the same registers.

[0063] Furthermore, the architectural registers selectable by program instructions in the ISA supported by decoder 50 may include a number of vector registers 105 (labeled Z0 to Z31 in this example). Figure 2 The number of scalar / vector registers shown in is not necessary, and other examples may provide different numbers of registers that may be specified by program instructions. Each vector register may store a vector operand including a variable number of data elements, each of which may represent an independent data value. In response to a vector processing (SIMD) instruction, the processing circuit system may perform vector processing on the vector operands stored in the register to produce a result. For example, vector processing may include channel-by-channel operations, wherein the corresponding operation is performed on each element channel in one or more operand vectors to produce the corresponding result of the element of the result vector. When performing vector or SIMD processing, each vector register may have a certain vector length VL, wherein the vector length refers to the number of bits in a given vector register. The vector length VL used in the vector processing mode may be fixed or variable for a given hardware implementation. The ISA supported by the processor 20 may support variable vector lengths, so that different processors may be selected to implement vector registers of different sizes, but the ISA is independent of the vector length, so that the instruction is designed so that the program code can function correctly regardless of the specific vector length implemented on the given CPU that executes the program.

[0064] Vector registers Z0 to Z31 may also function as operand registers for storing vector operands which provide input to processing and accumulation operations performed by processing circuitry 60 on two-dimensional array data elements stored in array storage device 90. When a vector register is used to provide input to such an operation, the vector register has a vector length MVL, which may be the same as the vector length VL used for the vector operation, or may be a different vector length.

[0065] like Figure 2 As shown, the architecture registers also include the array storage device 90 (ZA0 to ZA0N) mentioned above. A -1)) a certain number N A Array registers 110 may be used to store a single 2D array data element (e.g., the result of a process and accumulate operation). However, process and accumulate operations may not be the only operations that may use array registers. Array registers may also be used to store square arrays while performing a row / column transposition of the array structure in memory. When a program instruction refers to one of the array registers 110, it is referenced as a single entity using the array identifier ZAi, but some types of instructions (e.g., data transfer instructions) may also select a sub-portion of the array (e.g., a horizontal / vertical group of elements) by defining an index value that selects a portion of the array.

[0066] In practice, the physical implementation of the register storage device corresponding to the array register may include a certain number N R There are array vector registers ZAR0 to ZAR(N R -1), such as Figure 2 As shown. The array vector registers ZAR forming the array register storage device 110 may be a set of registers different from the vector registers Z0 to Z31 used for SIMD processing and vector input to array processing. Each of the array vector registers ZAR may have a vector length MVL, so each array vector register ZAR may store a 1D vector of length MVL, which may be logically divided into a variable number of data elements. For example, if MVL is 512 bits, this may be a set of 64 8-bit elements, 32 16-bit elements, 16 32-bit elements, 8 64-bit elements, or 4 128-bit elements. It should be understood that not all of these options need to be supported in a given implementation. By supporting variable element sizes, this provides flexibility in handling calculations involving data structures of different precisions. In order to represent 2D array data, a group of array vector registers ZAR0 to ZAR(N R -1) can be logically viewed as assigning array register identifiers ZA0 to ZA(N A-1) such that a 2D array is formed with elements extending within a single vector register corresponding to one dimension of the array, and elements in the other dimension of the array striped across multiple vector registers.

[0067] It may be useful (although not necessary) to arrange the array registers ZA so that they store square array data, where the number of elements in the horizontal direction is equal to the number of elements in the vertical direction. This may help support real-time transposition of the array, where by providing support for reading / writing the array registers 110 in either the horizontal or vertical direction, the row / column dimensions of the array structure in memory may be swapped when transferring the array structure between the array registers 110 and the memory. By providing support for writing / reading data to / from a 2D array register in either the horizontal or vertical direction, this may allow data loaded from memory in one direction (e.g., row by row) to be written back to memory in the opposite direction (e.g., column by column), potentially faster than using several gather / scatter load / store or permute operations to transfer data between memory and the vector registers.

[0068] As mentioned above, given 2D array data elements may form a square array in some exemplary implementations, but this is not necessary. Figure 3A As shown in , in one exemplary implementation, a given 2D array data element 115 may form a non-square array. Alternatively, Figure 3B As shown, a given 2D array of data elements 120 may form a square array. Figure 3A and Figure 3B In each of the examples, individual boxes represent data elements, and in some implementations, the data element size may vary. In any example, the two-dimensional array data elements may be specified in a variety of ways, but in an exemplary implementation, such as Figure 3A and Figure 3B As shown, a given 2D array data element may be specified by a sequence of array vector registers (ZAR).

[0069] As discussed above, processing circuitry 60 is arranged to access scalar registers 70, vector registers 80, and / or array storage 90 under the control of instructions decoded by decoder circuitry 50. Figure 4A Further details of this latter arrangement are described, which merely provides one illustrative example of how an array storage device may be accessed, particularly considering accessing a square 2D array within the array storage device.

[0070] In the illustrated example, the square 2D array within the array storage device 90 is arranged as an array 205 of nxn storage elements / locations 200, where n is an integer greater than 1. In this example, n is 16, which means that the granularity of access to the storage locations 200 is 1 / 16 of the total storage in either the horizontal or vertical array direction.

[0071] From the perspective of the processing circuitry, the array of nxn locations is accessible as n linear (one-dimensional) vectors in a first direction (e.g., the horizontal direction as shown) and n linear vectors in a second array direction (e.g., the vertical direction as shown). Thus, from the perspective of the processing circuitry 60, the nxn storage locations are arranged or at least accessible as 2n linear vectors, each having n data elements.

[0072] Array of storage locations 200 is accessible by access circuitry 210 , 220 , column select circuitry 230 , and row select circuitry 240 under the control of control circuitry 250 in communication with at least processing circuitry 60 and optionally decoder circuitry 50 .

[0073] refer to Figure 4B In the case of an exemplary square 2D array designated as "A1" (note that more than one such 2D array may be provided within array storage device 90, such as A0, A1, A2, and so on, as discussed below), the n linear vectors in a first direction (the horizontal or "H" direction as shown) may each have 16 data elements 0...F (in hexadecimal notation) and may be referred to in this example as A1H0...A1H15. Stored in Figure 4B The same basic data in the 256 items (16 x 16 items) of array storage device 90A1 may alternatively be referenced in a second direction (vertical or "V" direction as shown) as A1V0 ... A1V15. Note that, for example, data element 260 is referenced as item F of A1H0, rather than item 0 of A1V15. Note that the use of "H" and "V" does not indicate any spatial or physical layout requirements regarding the storage of the data elements making up array storage device 90, nor does it have any relevance as to whether the 2D array within the array storage device stores row data or column data in any exemplary application.

[0074] As previously discussed, the use of array storage device 90 can significantly improve performance for certain types of operations, such as accumulation operations, where multiple iterations of such accumulation operations may be performed on a given two-dimensional array data element within array storage device 90, where the two-dimensional array data element is used to accumulate results while performing the accumulation operation. However, when the accumulation operation is complete, an efficient mechanism for moving the resulting data element vectors out of the array storage device and preparing the associated storage elements within the array storage device so that they can be used for subsequent accumulation operations would be desirable.

[0075] As previously discussed, in one exemplary implementation, this is achieved through the use of a move and zero instruction that identifies one or more data element vectors of a given two-dimensional array of data elements within array storage device 90. When this move and zero instruction is decoded, then processing circuitry 60 is controlled to move the data elements of the one or more identified vectors from the array storage device to a destination storage device (which may be, for example, one or more vector registers within vector register file 80), and also to set the storage elements of the array storage device used to store the data elements of the one or more identified vectors to a logic zero value.

[0076] Figure 5A The fields that may be provided within the move and zero instruction according to one exemplary implementation are schematically illustrated. An opcode field 305 is used to identify the instruction as a move and zero instruction. In some exemplary implementations, there may be different variants of the move and zero instruction provided, and thus there may be more than one different opcode that may identify the move and zero instruction. As a specific example, when the move and zero instruction is used to move the identified vector within the array storage device to a destination vector register within the vector register file 80, there may be one variant defined for the move and zero instruction, and when one or more vectors within the array storage device are moved to memory, different variants may be provided (in this latter case, the instruction may, for example, be referred to as a store and zero instruction).

[0077] A vector identification field 310 is also provided for identifying one or more vectors within the array storage device to be subject to a move operation. In some instances, only a single vector may be identified, but in other instances, multiple vectors may be identified by this field. In the latter case, in one exemplary implementation, all of the multiple vectors may be identified independently, but in another exemplary implementation, the multiple vectors may be inferred, for example, from an indication of the first vector and an indication of the number of vectors to be moved.

[0078] like Figure 5AAs shown, a destination storage device identification field 315 is also provided within the move and zero instruction to identify the destination storage device to which the (the) vector should be moved. In one exemplary implementation, this field is used to identify one or more vector registers in the vector register file 80, and in examples where multiple such vector registers are identified, they can be identified in a similar manner to the identification of multiple vectors by the vector identification field (for example, a first vector register can be identified, and then other vector registers are implicit based on the knowledge of the number of vector registers required to form the destination storage device). In an alternative implementation, one or more vectors are to be moved to memory within the array storage device, and then the information provided in the destination storage device identification field 315 can be arranged to identify the location in memory to which the data elements of the one or more vectors are to be stored. This may, for example, involve identifying one or more registers whose contents are used to identify the required location in memory.

[0079] If desired, one or more optional additional fields 320 may be provided within the instruction 300. For example, a prediction field may be used to identify prediction information that is used to control which data elements of the one or more identified vectors are to be subjected to the move and zero operations. This provides flexibility by allowing operations to be applied to certain data elements but not to other data elements. As another example, a data element size indication may be provided within the instruction, thereby allowing the instruction to be applied to vectors whose data element size is not fixed.

[0080] In one exemplary implementation, the move and zero instructions may be arranged to operate on array vector registers extending in a first array direction, and in this implementation, it is not necessary to enable both horizontal and vertical directions to be encoded in the vector identification field 310. However, in examples where a 2D array within the array storage device 90 is accessible in either a horizontal or vertical direction (in one such implementation, the 2D array is a square array), then the vector identification field may take the form Figure 5B . Specifically, this vector identification field 310' may include a first subfield 312 for identifying a given square 2D array to be accessed within the array storage device 90, and a second subfield formed by two parts 313 and 314. The first part 313 provides one or more row identifiers for identifying one or more rows of data elements within the square 2D array, and the second part 314 provides an array direction indication, thereby enabling determination of whether the row of data elements identified by the row identifier extends in the horizontal direction or the vertical direction. It should be understood that the combination of the first part 313 and the second part 314 enables identification of one or more vectors within the square 2D array.

[0081] Figure 6Flowchart showing the operation of a move and zero instruction. At step 350, when it is determined that the decoder circuit system 50 has encountered a move and zero instruction, then at step 355, one or more data element vectors within the array storage device are identified from the information provided in the vector identification field 310 of the move and zero instruction. Further, at step 360, the destination storage device to be used is identified from the destination storage device identification field 315 of the move and zero instruction. As mentioned above, this step may generally cause one or more vector registers in the vector register file 80 to be identified as the destination of the data element to be moved out of the array storage device, but alternatively, in some specific implementations, this may be the case where the identified destination storage device takes the form of one or more locations in a memory. In an exemplary specific implementation, steps 355 and 360 may be performed by the decoder circuit system 50, but in an alternative specific implementation, the processing circuit system 60 may perform the determination step based on information provided by the decoder circuit system 50.

[0082] At step 365, the processing circuitry 60 is operative to move each identified data element vector to the destination storage device and then set the associated storage element of the array storage device (ie, the storage element used to store the data element now moved to the destination storage device) to zero.

[0083] Figure 7 An exemplary instruction sequence that can be used to operate the array storage device 90 in an exemplary implementation is shown. Figure 7 As shown in the example of , a series of data processing instructions (in this example, three instructions) can be executed to perform processing and accumulation operations within a given 2D array provided within the array storage device. During the execution of these multiple instructions, the results are accumulated within the given 2D array.

[0084] In this example, it is assumed that when the third data processing instruction has been completed, the first vertical vector in the given 2D array then stores the final accumulation result, while at this stage, the other vertical vectors in the given 2D array only store intermediate accumulation results. Given that the first vertical vector stores the final accumulation result, it would be useful to move the result out of the array storage device to free up the storage element of the first vertical vector for use in subsequent processing and accumulation operations.

[0085] like Figure 7 As shown, this is accomplished by executing a move and zero instruction, identifying a vertical vector 1, and defining a destination vector register to which the contents of the vertical vector should be moved, which in this example is referred to as register Z. iExecution of this instruction causes the final accumulated result in vertical vector 1 to be moved into the identified vector register and the associated storage element in the given 2D array (i.e., that implementing vertical vector 1) to be cleared to a logical zero value. As a result of executing this single instruction, not only has the final accumulated result been moved out of the array storage device, but the basic storage elements have also been prepared so that they are immediately available for reuse in subsequent processing and accumulation operations. In particular, by clearing their contents to zero, they can immediately begin to be designated as the destination for new accumulated results generated by subsequent instructions.

[0086] Therefore, if Figure 7 As shown, when subsequent data processing instructions 4 are executed, this can be accumulated into the 2D array and vertical vector 1 can be reused if necessary. When the data processing instructions have been executed, it is assumed that vertical vector 2 now holds the final accumulated result and additional move and zero instructions can be executed accordingly to move the contents of vertical vector 2 within the given 2D array out of the array storage device and into the destination vector register (in this example, register Z). i+x ). Again, execution of this instruction causes the contents of the identified vector to be shifted out of the array storage device and the corresponding storage element to be cleared to a logical zero value, thereby freeing the storage element for use in subsequent processing and accumulation operations. Figure 7 As shown, subsequent iterations of the data processing instructions may then be executed and vertical column 2 may be reused if necessary.

[0087] There are various types of operations that can be performed using a given 2D array within array storage device 90 to accumulate results, where not all vectors within the given 2D array will necessarily hold the final accumulated result at the same time. Figure 7 The method schematically shown in exemplarily in can be useful to free up resources in a 2D array for reuse. An exemplary use case of such a method is when performing 2D finite impulse response (FIR) filtering using a sliding window approach. Figure 8 Such a method is schematically shown in , where an input image 400 is considered. Specifically, a FIR filtering operation is applied to the input image to produce a corresponding output image 430, where each pixel 415, 420 in the output image 430 is produced as a result of a corresponding filtering operation 407, 412. For each of the filtering operations, a plurality of input pixels are considered, and filtering coefficients are applied to the plurality of input pixels to produce a value for the output pixel.

[0088] exist Figure 8In the example shown, it is assumed that each output pixel is produced by considering a 3x3 array of input pixels. Thus, the input pixels 405 of the first 3x3 array are provided to a filtering operation 407, where filtering is performed using the filter coefficients of the corresponding array to produce an output value for pixel 415. Similarly, the input pixels 410 of the second 3x3 array are subjected to a filtering operation 412 using a set of corresponding filter coefficients to produce a value for output pixel 420. It will be appreciated that array 410 is shifted one pixel position to the right relative to array 405, and as the process described above is repeated, a sliding window of 3x3 pixels can be retrieved to serve as input to each filtering operation. When the end of a row is reached, the process can return to the left side of the input image, but starting from a row below in the image and again proceeding from left to right of the image. Therefore, it will be appreciated that in Figure 8 In the arrangement shown, there is effectively a sliding window that moves first in the "horizontal" direction, which moves across the input image to retrieve a 3x3 array of input image pixels to use in operating on each output image pixel.

[0089] 9A to 9D It is shown how such a 2D image filtering operation can be efficiently performed using a square 2D array within array storage device 90 and by performing outer accumulation and addition operations on the data held in the 2D array. 9A to 9D In the example shown in , the sliding window will first move in the "vertical" direction, that is, in a direction orthogonal to Figure 8 directions shown in the example. Therefore, 9A to 9D The input image 440 shown in FIG. 4 may be viewed on its side relative to its normal viewing direction.

[0090] like 9A to 9D As shown, one column (or portion of an image) of the input image 440 is processed at a time and subjected to a filtering operation using a filter coefficient vector. Each block within the filter coefficient vector (see, e.g. Fig.9A Block 465 in ) represents three filter coefficients from the 3x3 array of coefficients. The padding elements (see e.g. Fig.9A The element 467 in corresponds to a zero or undefined value and is only an artifact of the illustrated implementation. Specifically, in the illustrated implementation, the instructions used may perform four multiplications and accumulations per result, but only three multiplications and accumulations need to be performed in the illustrated exemplary implementation.

[0091] In the example, four sets of coefficients are shown (see e.g. Fig.9AThe four blocks 468 in FIG. 460 , the four sets of coefficients are taken from one row of the four sets of 3x3 coefficients) are used as input to operate four output vectors for the provided input vector (each of the four multiplication operations used to produce the four output vectors produces a set of (3+1) coefficients). In addition, 9A to 9D The process shown in uses only three coefficients from one column of each 3x3 array of coefficients, and therefore, takes three instructions to produce the final accumulation result within any particular group of four vectors.

[0092] When the process is underway and in a stable state, then as will be referred to later Fig. 9C and Fig.9D Discussion, this process simultaneously performs four output vectors of three groups (see e.g. Fig. 9C The operation is performed using the three sets of output vectors 475, 485, 495) shown in FIG.

[0093] like Fig.9A As shown, when the first column 470 of the input image 440 is processed using the coefficient vector 460, this causes the accumulated results to be stored in four vectors 475. Fig. 9B As shown, when the second column 480 of the input image 440 is processed using the coefficient vector 482, the accumulated results are filled in both the four vectors 475 and the four vectors 485. Then, as Fig. 9C As shown, when the third column 490 is processed using coefficient vector 492, this causes the accumulated results to be filled in four vectors 475, four vectors 485, and four vectors 495. Figure 8 Based on the above discussion, it should be understood that at this point, all pixels within the first three columns of the input image will have been processed, and accordingly, the contents of the four horizontal vectors 475 will represent the final accumulation results of the output image of the first column group. Fig. 9C As shown, the contents of the four registers 475 may be subjected to the move and zero instructions described above to move the contents to a destination storage device (e.g., four vector registers within the vector register file 80) and to clear the storage elements forming the four vectors 475 within the 2D array 450 so that they are available for subsequent accumulation operations.

[0094] So, for example, Fig.9D As shown, when the fourth column 500 of the input image 440 is processed using the coefficient vector 460, this may cause the accumulated results to be filled into four vectors 485, four vectors 495, and four vectors 475 (which may now be reused since the storage elements within the vectors have been cleared to logical zero values ​​by the previous move and zero instructions). Fig.9DAs shown, the four vectors 485 will now store the final accumulation results representing the output image of the second column group (because at this point, each of the second input column, the third input column, and the fourth input column will have been processed). Accordingly, the data elements stored in the four horizontal vectors 485 can be shifted out of the array into vector registers of the vector register file, and then the basic storage elements are cleared to allow them to be reused in subsequent accumulation operations.

[0095] Although in 9A to 9D , any vector that has been moved and zeroed is immediately reused (as this may result in easier programming), but there is no requirement that a cleared vector be immediately reused, and instead processing may continue to consume vectors below the group of vectors 475, 485, 495, if necessary, simply returning to the beginning when the bottom of the array 450 is reached.

[0096] In one exemplary implementation, a given square 2D array within array storage device 90 may be accessed in either the horizontal or vertical direction. However, in some implementations, there are certain processing operations that may be performed using a 2D array within array storage device 90 where vectors are accessed in only one of the directions. Thus, for example, returning to reference to the previously discussed Figure 2 , there may be some processing instructions that specifically identify array vector registers ZAR that extend across the array in a first array direction. These instructions may allow certain processing and accumulation operations to be performed efficiently by specifying a plurality of ZAR registers on which associated processing and accumulation operations are to be performed. However, when a series of such instructions have been executed, then all of the identified array vector registers ZAR will generally contain the final accumulation result, but the use of such registers for subsequent processing and accumulation operations will not be feasible until such result has been shifted out of the array storage means and the present contents of the storage elements forming the array vector registers have been cleared to a logical zero value.

[0097] Fig.10 Schematically illustrates how the move and zero instructions described above can be used to significantly increase performance in such situations. Specifically, Fig.10As shown, it is assumed that three array vector registers ZAR2, ZAR3 and ZAR4 are initialized to 0, and then a series of data processing instructions of the above type are executed to perform processing and accumulation operations, wherein the accumulated results are maintained in the above three array vector registers. When the required series of data processing instructions have been completed (in this example, it is assumed that there are two such data processing instructions executed), all of the above three array vector registers will store the final accumulated results. The move and zero instructions mentioned above can therefore be used to specify the three array vector registers as vectors whose data elements should be moved to the destination storage device, and can also identify the storage device to be used as the destination storage device. In this example, it is assumed that three adjacent vector registers within the vector register file 80 are used. Therefore, executing the move and zero instruction will cause all of the accumulated results to be moved out of the array storage device and into the identified vector register of the vector register file, and also cause the storage elements forming the three array vector registers to be cleared to logical zero values. Therefore, as Fig.10 As shown, the process may then immediately continue to execute a sequence of subsequent data processing instructions which will also accumulate into the same series of array vector registers ZAR2, ZAR3 and ZAR4. This provides a highly efficient implementation.

[0098] According to another technique described herein, an additional new form of instruction (referred to herein as a zero vector instruction) is provided which can also be used to zero a vector of data elements within the array storage device and provide a performance improvement when performing an accumulation operation when performing an accumulation operation using such an array storage device (when compared to a specific implementation that requires the use of a move instruction to move zeros from one or more vector registers to a desired vector of the array storage device and requires the retention of one or more vector registers to hold the zero value). According to this additional technique, the instruction decoder circuitry 50 is arranged to, in response to decoding this zero vector instruction (which is arranged to identify a plurality of data element vectors of a given two-dimensional array data element within the array storage device), also decode a subsequent accumulation instruction arranged to operate on the identified plurality of data element vectors. Then, the processing circuitry is caused to set the storage elements of the array storage device used to store the data elements of the identified plurality of vectors to a logical zero value, and then perform the accumulation operation specified by the accumulation instruction to produce result data elements for storage in the identified plurality of vectors within the array storage device.

[0099] By using the above method, the zero-vector instruction, when decoded by the instruction decoder circuitry, can be merged with a subsequent accumulate instruction to effectively create a non-accumulate variant of the accumulate instruction, the subsequent accumulate instruction specifying the same plurality of data element vectors as specified by the zero-vector instruction. This can be highly beneficial because instruction encoding space is typically high premium, and specifying non-accumulate variants of various accumulate instructions that may be defined to operate on a plurality of data element vectors within the array storage device may not be feasible.

[0100] Fig.11 Flowchart showing the handling of such a zero vector instruction according to an exemplary implementation. When the decoder circuit system 50 encounters a zero vector instruction at step 520, then at step 525, a plurality of data element vectors within the array storage device are identified with reference to the vector identification field of the zero vector instruction. For example, a plurality of array vector registers ZAR may be identified in the vector identification field. Then, at step 530, the decoder circuit system determines whether the next instruction to be decoded is an accumulation instruction that operates on the same vector as identified by the zero vector instruction.

[0101] If not, then at step 535 the processing circuitry is controlled to set the storage elements of the array storage device determined at step 525 for storing the data elements of the identified plurality of vectors to logic zero values ​​and processing thereafter continues with execution of the next instruction only.

[0102] However, at step 530, if it is determined that the next instruction is an accumulate instruction that operates on the same vector as identified by the zero vector instruction, the decoder effectively fuses the two instructions and, at step 540, controls the processing circuitry to perform a non-accumulate variant of the accumulate operation specified by the accumulate instruction (generally, this involves both a processing operation and a subsequent accumulation) to produce a result for storage in each of the identified plurality of vectors. As previously mentioned, by such an approach, there is no need to specifically encode a non-accumulate variant of any accumulate instruction that is arranged to operate on a plurality of vectors within the array storage device, as such a non-accumulate variant may be effectively implemented by the above-described fusion process via use of a zero vector instruction followed by use of the desired accumulate instruction (thereby implementing the processing operation defined by the accumulate instruction, but wherein the accumulate function is effectively nullified).

[0103] Fig.12FIG. 5 is a diagram schematically illustrating fields that may be provided within a zero vector instruction in an exemplary implementation. Specifically, a zero vector instruction 550 includes an opcode field 555 for identifying that the instruction is in fact a zero vector instruction. Further, a vector identification field 560 is provided for identifying a plurality of vectors in an array storage device. The information in this field is generally the same as described above in the description of Figure 5A The vector identification field 310 of the move and zero instruction 300 is discussed in the form, although in an exemplary embodiment, subsequent accumulate instructions are arranged to operate on array vector registers extending in a first array direction, and therefore it is generally not necessary to have both the horizontal and vertical directions encoded in the vector identification field 560.

[0104] If desired, as shown at block 565, certain optional additional fields may be provided, such as a prediction information field and a data element size field as discussed above with reference to the move and zero instruction example.

[0105] Fig.13 Flowchart showing the handling of a zero vector instruction according to another exemplary implementation. When the decoder circuit system 50 encounters a zero vector instruction at step 570, then at step 575, a plurality of data element vectors within the array storage device are identified with reference to the vector identification field of the zero vector instruction. For example, a plurality of array vector registers ZAR may be identified in the vector identification field.

[0106] Next at step 580, the processing circuitry is controlled to set the storage elements of the array storage device determined at step 575 for storing the data elements of the identified plurality of vectors to logic zero values, and processing thereafter continues with execution of the next instruction only.

[0107] Even in this implementation, when fusion does not occur to combine the zero vector instruction with the subsequent accumulate instruction, significant benefits can still be achieved. Specifically, there is no need to execute multiple move instructions, each of which moves a zero vector from a vector register of the vector register file to an identified vector of the array storage device. Further, such zeroing functionality is simpler and cheaper to implement in hardware than having to implement (zero) move vector functionality. In addition, there is additional savings because one or more vector registers in the vector register file do not need to be retained to hold a logical zero value (which would be required in the above implementation based on the move instructions utilized).

[0108] Fig.14The simulator that can be used is shown to be implemented. Although the examples described previously implement the present invention with the apparatus and method for operating the specific processing hardware supporting the technology of interest, it is also possible to provide an instruction execution environment according to the examples described herein, which is implemented via the use of a computer program. Such computer programs are often referred to as simulators because they provide a software-based implementation of a hardware architecture. The types of simulator computer programs include emulators, virtual machines, models, and binary translators (including dynamic binary translators). In general, the simulator is implemented to run on a host processor 615 that optionally runs a host operating system 610 and supports a simulator program 605. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, a powerful processor has been required to provide a simulator implementation that is executed at a reasonable speed, but this method may be justified in some cases, such as when it is necessary to execute another processor native program code because of compatibility or reuse reasons. For example, the simulator implementation may provide an instruction execution environment with additional functionality that is not supported by the host processor hardware, or provide an instruction execution environment that is generally associated with different hardware architectures. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques" (Robert Bedichek, Winter 1990 USENIX Conference, pages 53-63).

[0109] Where implementations have been previously described with reference to specific hardware architectures or features, in simulated implementations, equivalent functionality may be provided by suitable software architectures or features. For example, specific circuitry may be provided as computer program logic in simulated implementations. Similarly, memory hardware (such as registers or caches) may be provided as software data structures in simulated implementations. Furthermore, the physical address space used to access memory 30 in hardware device 10 may be simulated as a simulated address space mapped to a virtual address space used by host operating system 610 by simulator 605. In the previously described examples, one or more of the hardware elements mentioned are present in an arrangement on host hardware (e.g., host processor 615), and some simulated implementations may utilize host hardware (where appropriate).

[0110] The simulator program 605 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provide a virtual hardware interface (instruction execution environment) to the target code 600 (which may include an application, an operating system, and a hypervisor) that is the same as the hardware interface of the hardware architecture modeled by the simulator program 605. Therefore, the program instructions of the target code 600 may be executed within the instruction execution environment using the simulator program 605, so that a host computer 615 that does not actually have the hardware features of the device 10 discussed above can simulate the features. The simulator program may include: a processing program logic 620 that simulates the behavior of the processing circuit system 60; an instruction decoding program logic 625 that simulates the behavior of the instruction decoder circuit system 50; and an array storage device simulation program logic 622 that maintains data structures to simulate the array storage device 90. Therefore, the technology described herein is Fig.14 In the example, the simulator program 605 can be executed in software.

[0111] In this application, the term "configured to..." is used to mean that the elements of a device have a configuration that can perform the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have special-purpose hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0112] Although illustrative examples have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to this precise example and that various changes, additions and modifications may be implemented therein by a person skilled in the art without departing from the scope and spirit of the invention as defined in the accompanying claims. For example, various combinations of features of the independent claims with features of the dependent claims may be made without departing from the scope of the invention.

Claims

1. A device, comprising: a processing circuit system for performing an operation; an instruction decoder circuit system, the instruction decoder circuit system being used to decode an instruction so as to control the processing circuit system to perform the operation specified by the instruction; and an array storage device comprising storage elements for storing data elements, the array storage device being arranged to store at least one two-dimensional array data element accessible to the processing circuitry when performing the operation, each two-dimensional array data element comprising a plurality of data element vectors, wherein each vector is one-dimensional; wherein the instruction decoder circuitry is arranged to control the processing circuitry in response to a move-and-zero instruction identifying one or more data element vectors of a given two-dimensional array data element within the array storage device to move the data elements of the one or more identified vectors from the array storage device to a destination storage device and to set storage elements of the array storage device used to store the data elements of the one or more identified vectors to logic-zero values.

2. The apparatus according to claim 1, wherein: the processing circuitry being arranged to perform a plurality of iterations of an accumulation operation and to use the given two-dimensional array data elements to maintain accumulation results produced when performing the accumulation operation, wherein after a given iteration of the accumulation operation at least one given vector of data elements in the given two-dimensional array data elements is arranged to store a final accumulation result while remaining vectors of data elements in the given two-dimensional array data elements are arranged to store intermediate accumulation results; and The move and zero instructions are arranged to identify the at least one given vector of data elements and to be executed after the given iteration of the accumulate operation to cause the processing circuitry to move the final accumulated result of the at least one given vector from the array storage device to the destination storage device and to clear the storage elements of the array storage device used to store the final accumulated result of the at least one given vector to free those storage elements for use in a subsequent accumulate operation.

3. The apparatus according to claim 2, wherein: the plurality of iterations of accumulation operations are process and accumulation operations for performing a finite impulse response (FIR) filtering operation on input data elements of an array, and the given two-dimensional array data element within the array storage device is used to hold output data elements of the array produced during performance of the FIR filtering operation; and The processing circuitry is arranged to process a single vector of input data elements during each iteration of the accumulation operation and produce output data elements for accumulation within a plurality of vectors of output data elements of the array.

4. An apparatus according to any preceding claim, wherein the given two-dimensional array data element is a square two-dimensional array data element, the plurality of vectors forming the square two-dimensional array data element comprises a first plurality of vectors arranged in a first array direction and a second plurality of vectors arranged in a second array direction, the second array direction being orthogonal to the first array direction, and each instance of the move and zero instruction is arranged to identify one or more data element vectors extending entirely in the first array direction or entirely in the second array direction.

5. The apparatus according to claim 4, wherein: The processing circuitry is arranged to perform processing operations on the square two-dimensional array of data elements, during which the processing circuitry is enabled to access data element vectors in both the first array direction and the second array direction.

6. Apparatus according to any preceding claim, wherein: the array storage device comprises a plurality of array vector registers extending in a first array direction, and the processing circuitry is arranged to perform one or more accumulation operations, wherein each accumulation operation is arranged to produce output data for accumulation within the plurality of array vector registers of a group of the array storage device; said given two-dimensional array data element comprises said data elements stored within a plurality of array vector registers of said group; and The move and zero instruction, upon execution, causes the processing circuit system to move the data elements of the one or more identified vectors from the array storage device to the destination storage device and to set each array vector register within a plurality of array vector registers used to store the group of data elements of the one or more identified vectors to a logical zero value when execution of the one or more accumulate operations has resulted in final result data being present in the one or more identified vectors identified by the move and zero instruction.

7. An apparatus according to claim 6, wherein when the processing circuit system has completed execution of the one or more accumulate operations, final result data is present in each array vector register within the group of multiple array vector registers, and executing the move and zero instruction causes the final result data to be moved from the group of multiple array vector registers to the destination storage device and clears each array vector register in the group of multiple array vector registers to zero.

8. The apparatus of any preceding claim, further comprising: a vector register file, the vector register file comprising a plurality of vector registers; and The move and zero instructions are arranged to indicate one or more vector registers within the vector register file as the destination storage.

9. Apparatus according to any one of claims 1 to 7, wherein the move and zero instructions are arranged to indicate one or more locations in a memory where the data elements of the one or more identified vectors are to be stored as the destination storage means.

10. Apparatus according to any preceding claim, wherein the move and zero instruction comprises a vector identification field to identify the one or more data element vectors for the given two-dimensional array data element within the array storage device.

11. A device according to claim 10, when dependent on claim 4, wherein the vector identification field includes a first subfield and a second subfield, wherein the first subfield is used to identify the square two-dimensional array, and the second subfield provides one or more row identifiers and array direction indications for identifying the one or more vectors.

12. An apparatus according to any preceding claim, wherein the move and zero instruction includes a prediction field for identifying prediction information, the prediction information being used to identify which data elements of the one or more identified vectors are to be moved from the array storage device to the destination storage device and have their associated storage elements set to the logical zero value.

13. The apparatus of claim 12, wherein the move and zero instruction further comprises a size field to identify a size of each data element within the one or more identified vectors.

14. A method of handling data elements in an array storage device of an apparatus, the method comprising: performing operations using a processing circuit system; decoding the instruction using instruction decoder circuitry to control the processing circuitry to perform the operation specified by the instruction; providing storage elements within the array storage device to store data elements, the array storage device being arranged to store at least one two-dimensional array data element accessible to the processing circuitry when performing the operation, each two-dimensional array data element comprising a plurality of data element vectors, wherein each vector is one-dimensional; as well as The instruction decoder circuitry is utilized to control the processing circuitry in response to a move and zero instruction identifying one or more data element vectors of a given two-dimensional array data element within the array storage device to move the data elements of the one or more identified vectors from the array storage device to a destination storage device and to set storage elements of the array storage device used to store the data elements of the one or more identified vectors to logic-zero values.

15. A computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising: Processing program logic, the processing program logic is used to perform operations; Instruction decoding program logic, the instruction decoding program logic is used to decode instructions, thereby controlling the processing program logic to perform the operation specified by the instruction; and an array storage device emulation program logic, the array storage device emulation program logic being used to emulate an array storage device including storage elements for storing data elements, the array storage device being arranged to store at least one two-dimensional array data element, the processing program logic being able to access the data elements when performing the operation, each two-dimensional array data element comprising a plurality of data element vectors, wherein each vector is one-dimensional; wherein the instruction decode program logic is arranged to control the processing program logic in response to a move and zero instruction identifying one or more data element vectors of a given two-dimensional array data element within the array storage device to move the data elements of the one or more identified vectors from the array storage device to a destination storage device and to set the storage elements of the array storage device used to store the data elements of the one or more identified vectors to logic zero values.

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